US20130099357A1 - Strain compensated reo buffer for iii-n on silicon - Google Patents

Strain compensated reo buffer for iii-n on silicon Download PDF

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US20130099357A1
US20130099357A1 US13/278,952 US201113278952A US2013099357A1 US 20130099357 A1 US20130099357 A1 US 20130099357A1 US 201113278952 A US201113278952 A US 201113278952A US 2013099357 A1 US2013099357 A1 US 2013099357A1
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rare earth
earth oxide
oxide structure
single crystal
interface
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Rytis Dargis
Erdem Arkun
Radek Roucka
Andrew Clark
Michael Lebby
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System

Definitions

  • This invention relates in general to the deposition of III-N on silicon wafers.
  • III-N materials are a desirable semiconductor material in many electronic and photonic applications.
  • the III-N semiconductor material must be provided as a crystalline or single crystal formation for the most efficient and useful bases for the fabrication of various electronic and photonic devices therein.
  • the single crystal III-N semiconductor material is most conveniently formed on single crystal silicon wafers because of the extensive background and technology developed in the silicon semiconductor industry.
  • efforts to grow III-N on silicon wafers have resulted in substantially bowed wafers due to tensile strain in the III-N material.
  • a preferred method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material.
  • the layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure.
  • the rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
  • a rare earth oxide buffered III-N on silicon wafer including a crystalline silicon substrate with a rare earth oxide structure deposited on the silicon substrate and including one or more layers of single crystal rare earth oxide and a layer of single crystal III-N material deposited on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material.
  • the layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure.
  • the thickness of the rare earth oxide structure is grown to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
  • FIG. 1 is a simplified layer diagram of a strain compensated rare earth oxide (REO) buffered III-N on silicon wafer, in accordance with the present invention
  • FIG. 2 illustrates in a semi-graphic representation the relative strains between REO and III-N materials
  • FIG. 3 ( FIGS. 3 a - 3 c ) is a graphical representation of the relative strains in GaN and REO with varying thicknesses grown on a 100 mm wafer.
  • Wafer 10 includes a single crystal silicon substrate 12 which, it will be understood, is or may be a standard well know single crystal silicon wafer or portion thereof generally known and used in the semiconductor industry.
  • Single crystal silicon substrate 12 it will be understood, is not limited to any specific crystal orientation but could include ⁇ 111> silicon, ⁇ 110> silicon, ⁇ 100> silicon or any other orientation or variation known and used in the art.
  • a rare earth oxide (REO) structure 14 is grown directly on the surface of substrate 12 using any of the well known growth methods, such as MBE, MOCVD, PLD (pulsed laser deposition), sputtering, ALD (atomic layer deposition), or any other known growth method for thin films. Further, the growth method used will generally be used for all additional layers and may conveniently be employed to grow the entire structure in a continuous process sometimes referred to herein as performed within a one wafer single epitaxial process.
  • REO structure 14 may be considered one or more single crystal or crystalline layers or a single layer of single crystal or crystalline material with a plurality of sub-layers, either of which will be referred to herein for convenience of understanding as an “REO structure”.
  • REO structure 14 may vary from the bottom to the top (as described in more detail below) and/or within each layer either linearly or in a step by step process. In any case, REO structure 14 is positioned between the surface of substrate 12 and the lower surface of a single crystal layer of III-N material 16 .
  • rare earth materials are generally defined as any of the lanthanides as well as scandium and yttrium.
  • III-N materials are generally defined as nitrides of any of the III materials from the periodic table of elements.
  • the rare earth oxide of structure 14 may be either a binary or a ternary alloy and may include two or more layers of different compositions to form an intermediate buffer between substrate 12 and III-N material 16 .
  • different REOs may be included in REO structure 14 to perform different functions.
  • the rare earth oxide of structure 14 will produce a compressive strain at the interface with III-N material 16 .
  • the amount of compressive strain at the interface is increased. That is, the compressive stress in structure 16 is substantially zero at the interface with substrate 12 and increases generally linearly (or at some predetermined rate) up to the interface with III-N material 16 . As illustrated in FIG.
  • FIG. 3 a a graphical representation of the relative strains in GaN and REO with varying thicknesses grown on a 100 mm wafer is illustrated.
  • Initial testing performed on 100 mm silicon wafers and using GaN as the III-N material showed that increasing the thickness of REO structure 14 increased the positive bowing, as graphically represented by bars 30 , 32 , and 34 .
  • the thinner REO, represented by bar 30 produced a positive bowing of approximately 10 ⁇ m while the thickest REO, represented by bar 34 , produced a bowing of approximately 30 ⁇ m.
  • FIG. 3 b a pictorial represents the resulting negative bowing of the wafer caused by the tensile stress of the III-N material, represented by bar 36 , being substantially larger than the compressive stress of the REO structure, represented by bar 30 .
  • FIG. 3 b pictorial represents the resulting positive bowing of the wafer caused by the tensile stress of the III-N material, represented by bar 38 , being substantially smaller than the compressive stress of the REO structure, represented by bar 34 .
  • III-N materials with tensile stresses are the primary target for this invention, it should also be noted that the concept is useful for the growth of other semiconductor materials, some of which have compressive stresses, which are traditionally difficult to grow on silicon substrates.
  • a typical example of such semiconductor material is germanium (Ge) which in combination with a silicon substrate or wafer produces a compressive stress.
  • germanium (Ge) which in combination with a silicon substrate or wafer produces a compressive stress.
  • rare earth materials with crystalline structures both larger than silicon (or a multiple thereof) and smaller than silicon (or a multiple thereof) are available.
  • a buffer layer of REO can be grown that will compensate for a semiconductor that creates either a tensile of a compressive stress.
  • any semiconductor material that results in either a tensile stress or a compressive stress can be compensated by REO structures with a thickness sufficient to produce approximately equal and opposite amounts of either compressive stress or tensile stress.
  • new and improved structure and methods of growing III-N and other semiconductor materials on silicon substrates have been disclosed.
  • the new and improved methods provide large diameter, high yield epitaxial wafers of III-N nitrides on silicon with substantially flat surfaces.
  • the tensile and compressive stresses are specifically engineered to prevent or overcome any bowing in the III-n or other semiconductor layer.
  • the high yield epitaxial wafers of III-N or other semiconductor on silicon can be grown within a one wafer single epitaxial process.

Abstract

A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.

Description

    FIELD OF THE INVENTION
  • This invention relates in general to the deposition of III-N on silicon wafers.
    • BACKGROUND OF THE INVENTION
  • It has been found that III-N materials are a desirable semiconductor material in many electronic and photonic applications. As understood in the art, the III-N semiconductor material must be provided as a crystalline or single crystal formation for the most efficient and useful bases for the fabrication of various electronic and photonic devices therein. Further, the single crystal III-N semiconductor material is most conveniently formed on single crystal silicon wafers because of the extensive background and technology developed in the silicon semiconductor industry. However, efforts to grow III-N on silicon wafers have resulted in substantially bowed wafers due to tensile strain in the III-N material.
  • It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
  • Accordingly, it is an object of the present invention to provide new and improved methods of growing III-N on silicon substrates that are strain compensated.
  • It is another object of the present invention to provide new and improved substantially flat or unbowed, large diameter, high yield epitaxial wafers of III-N on silicon.
  • It is another object of the present invention to provide new and improved methods of providing substantially flat, large diameter, high yield epitaxial wafers of III-N on silicon.
    • SUMMARY OF THE INVENTION
  • Briefly, the desired objects and aspects of the instant invention are achieved in accordance with a preferred method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
  • The desired objects and aspects of the instant invention are further realized in accordance with a preferred embodiment of a rare earth oxide buffered III-N on silicon wafer including a crystalline silicon substrate with a rare earth oxide structure deposited on the silicon substrate and including one or more layers of single crystal rare earth oxide and a layer of single crystal III-N material deposited on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The thickness of the rare earth oxide structure is grown to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the drawings, in which:
  • FIG. 1 is a simplified layer diagram of a strain compensated rare earth oxide (REO) buffered III-N on silicon wafer, in accordance with the present invention;
  • FIG. 2 illustrates in a semi-graphic representation the relative strains between REO and III-N materials; and
  • FIG. 3 (FIGS. 3 a-3 c) is a graphical representation of the relative strains in GaN and REO with varying thicknesses grown on a 100 mm wafer.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • It has been found that any attempted growth of a III-N layer directly on silicon, or even in some cases on a rare earth oxide intermediate layer, results in substantial tensile stress in the III-N layer which results in excessive bowing of the wafer. This bowing of the wafer can make the wafer impractical for further processing, resulting in substantial amounts of wasted material and effort.
  • Referring to FIG. 1, a simplified layer diagram is illustrated of a high yield epitaxial wafer 10 including III-N on silicon in accordance with the present invention. Wafer 10 includes a single crystal silicon substrate 12 which, it will be understood, is or may be a standard well know single crystal silicon wafer or portion thereof generally known and used in the semiconductor industry. Single crystal silicon substrate 12, it will be understood, is not limited to any specific crystal orientation but could include <111> silicon, <110> silicon, <100> silicon or any other orientation or variation known and used in the art.
  • A rare earth oxide (REO) structure 14 is grown directly on the surface of substrate 12 using any of the well known growth methods, such as MBE, MOCVD, PLD (pulsed laser deposition), sputtering, ALD (atomic layer deposition), or any other known growth method for thin films. Further, the growth method used will generally be used for all additional layers and may conveniently be employed to grow the entire structure in a continuous process sometimes referred to herein as performed within a one wafer single epitaxial process. REO structure 14 may be considered one or more single crystal or crystalline layers or a single layer of single crystal or crystalline material with a plurality of sub-layers, either of which will be referred to herein for convenience of understanding as an “REO structure”.
  • Further, REO structure 14 may vary from the bottom to the top (as described in more detail below) and/or within each layer either linearly or in a step by step process. In any case, REO structure 14 is positioned between the surface of substrate 12 and the lower surface of a single crystal layer of III-N material 16. Throughout this disclosure whenever rare earth materials are mentioned it will be understood that “rare earth” materials are generally defined as any of the lanthanides as well as scandium and yttrium. Also, whenever III-N materials are mentioned it will be understood that “III-N” materials are generally defined as nitrides of any of the III materials from the periodic table of elements.
  • Generally, the rare earth oxide of structure 14 may be either a binary or a ternary alloy and may include two or more layers of different compositions to form an intermediate buffer between substrate 12 and III-N material 16. For example, in different applications different REOs may be included in REO structure 14 to perform different functions. The rare earth oxide of structure 14 will produce a compressive strain at the interface with III-N material 16. Further, by increasing the thickness of structure 14 the amount of compressive strain at the interface is increased. That is, the compressive stress in structure 16 is substantially zero at the interface with substrate 12 and increases generally linearly (or at some predetermined rate) up to the interface with III-N material 16. As illustrated in FIG. 2 a, when the compressive stress of the rare earth oxide of structure 14 is less than the tensile stress of the III-N material 16 a wafer with a negative bow at the surface is produced. However, as illustrated in FIG. 2 b, when the compressive stress of the rare earth oxide of structure 14 is equal to the tensile stress of the III-N material 16 a wafer with a flat or unbowed surface is produced.
  • Referring additionally to FIG. 3 a, a graphical representation of the relative strains in GaN and REO with varying thicknesses grown on a 100 mm wafer is illustrated. Initial testing performed on 100 mm silicon wafers and using GaN as the III-N material showed that increasing the thickness of REO structure 14 increased the positive bowing, as graphically represented by bars 30, 32, and 34. The thinner REO, represented by bar 30, produced a positive bowing of approximately 10 μm while the thickest REO, represented by bar 34, produced a bowing of approximately 30 μm.
  • Referring additionally to FIG. 3 b, a pictorial represents the resulting negative bowing of the wafer caused by the tensile stress of the III-N material, represented by bar 36, being substantially larger than the compressive stress of the REO structure, represented by bar 30. Conversely, FIG. 3 b pictorial represents the resulting positive bowing of the wafer caused by the tensile stress of the III-N material, represented by bar 38, being substantially smaller than the compressive stress of the REO structure, represented by bar 34. Thus, it can be seen that when the compressive stress of the rare earth oxide of structure 14 is equal to the tensile stress of the III-N material 16 a wafer with a flat or unbowed surface is produced.
  • It should be understood that slightly different amounts of compressive stress may be produced by different REO structures but generally the thickness of the REO structure determines the total compressive stress at the interface with the III-N material. Also, the ultimate thickness of the III-N material can result in different amounts of tensile stress so that, as a general rule, thicker layers of III-N material produce greater tensile stress and require thicker REO structures that produce greater compressive stress.
  • While III-N materials with tensile stresses are the primary target for this invention, it should also be noted that the concept is useful for the growth of other semiconductor materials, some of which have compressive stresses, which are traditionally difficult to grow on silicon substrates. A typical example of such semiconductor material is germanium (Ge) which in combination with a silicon substrate or wafer produces a compressive stress. It should be understood that rare earth materials with crystalline structures both larger than silicon (or a multiple thereof) and smaller than silicon (or a multiple thereof) are available. Thus, a buffer layer of REO can be grown that will compensate for a semiconductor that creates either a tensile of a compressive stress. Thus, any semiconductor material that results in either a tensile stress or a compressive stress can be compensated by REO structures with a thickness sufficient to produce approximately equal and opposite amounts of either compressive stress or tensile stress.
  • Thus, new and improved structure and methods of growing III-N and other semiconductor materials on silicon substrates have been disclosed. The new and improved methods provide large diameter, high yield epitaxial wafers of III-N nitrides on silicon with substantially flat surfaces. The tensile and compressive stresses are specifically engineered to prevent or overcome any bowing in the III-n or other semiconductor layer. Also, the high yield epitaxial wafers of III-N or other semiconductor on silicon can be grown within a one wafer single epitaxial process.
  • Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.

Claims (20)

Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:
1. A method of fabricating a rare earth oxide buffered semiconductor on silicon wafer comprising the steps of:
providing a crystalline silicon substrate;
depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide;
depositing a layer of single crystal semiconductor material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal semiconductor material, the layer of single crystal semiconductor material producing one of a tensile stress and a compressive stress at the interface and the rare earth oxide structure having an opposite one of a compressive stress and a tensile stress at the interface dependent upon a thickness of the rare earth oxide structure; and
growing the thickness of the rare earth oxide structure to provide the one of compressive stress and tensile stress offsetting at least a portion of the one of tensile stress and compressive stress at the interface to substantially reduce bowing in the wafer.
2. A method as claimed in claim 1 wherein the rare earth oxide structure is grown with a thickness that provides the opposite one of compressive stress and tensile stress approximately equal to the one of tensile stress and compressive stress of the layer of single crystal semiconductor material at the interface, whereby bowing of the silicon wafer is substantially eliminated.
3. A method as claimed in claim 1 wherein the step of depositing the rare earth oxide structure includes depositing one of a binary alloy and a ternary alloy.
4. A method as claimed in claim 1 wherein the step of depositing the rare earth oxide structure includes depositing two or more layers of different compositions.
5. A method as claimed in claim 1 wherein the step of depositing the semiconductor material includes depositing a material including germanium.
6. A method of fabricating a rare earth oxide buffered III-N on silicon wafer comprising the steps of:
providing a crystalline silicon substrate;
depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide;
depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material, the layer of single crystal III-N material producing a tensile stress at the interface and the rare earth oxide structure having a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure; and
growing the thickness of the rare earth oxide structure to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
7. A method as claimed in claim 6 wherein the rare earth oxide structure is grown with a thickness that provides a compressive stress approximately equal to the tensile stress of the layer of single crystal III-N material at the interface, whereby bowing of the silicon wafer is substantially eliminated.
8. A method as claimed in claim 6 wherein the step of depositing the rare earth oxide structure includes depositing one of a binary alloy and a ternary alloy.
9. A method as claimed in claim 6 wherein the step of depositing the rare earth oxide structure includes depositing two or more layers of different compositions.
10. A method of fabricating a rare earth oxide buffered III-N on silicon wafer comprising the steps of:
providing a crystalline silicon substrate;
depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and at least one of the one or more layers including one of a binary alloy and a ternary alloy;
depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material, the layer of single crystal III-N material producing a tensile stress at the interface and the rare earth oxide structure having a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure; and
growing the rare earth oxide structure with a thickness that provides a compressive stress approximately equal to the tensile stress of the layer of single crystal III-N material at the interface, whereby bowing of the silicon wafer is substantially eliminated.
11. A method as claimed in claim 10 wherein the step of depositing the rare earth oxide structure includes depositing two or more layers of different compositions.
12. Rare earth oxide buffered III-N on silicon wafer comprising:
a crystalline silicon substrate;
a rare earth oxide structure deposited on the silicon substrate and including one or more layers of single crystal rare earth oxide;
a layer of single crystal III-N material deposited on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material, and the layer of single crystal III-N material producing a tensile stress at the interface; and
the rare earth oxide structure having a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure, and the thickness of the rare earth oxide structure providing a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.
13. A rare earth oxide buffered III-N on silicon wafer as claimed in claim 12 wherein the thickness of the rare earth oxide structure provides a compressive stress approximately equal to the tensile stress of the layer of single crystal III-N material at the interface whereby bowing of the silicon wafer is substantially eliminated.
14. A rare earth oxide buffered III-N on silicon wafer as claimed in claim 12 wherein the rare earth oxide structure includes one of a binary alloy and a ternary alloy.
15. A rare earth oxide buffered III-N on silicon wafer as claimed in claim 12 wherein the rare earth oxide structure include two or more layers of different compositions.
16. Rare earth oxide buffered semiconductor on silicon wafer comprising:
a crystalline silicon substrate;
a rare earth oxide structure deposited on the silicon substrate and including one or more layers of single crystal rare earth oxide;
a layer of single crystal semiconductor material deposited on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal semiconductor material, and the layer of single crystal semiconductor material producing one of a tensile stress and a compressive stress at the interface; and
the rare earth oxide structure having an opposite one of a compressive stress and a tensile stress at the interface dependent upon a thickness of the rare earth oxide structure, and the thickness of the rare earth oxide structure providing the opposite one of a compressive stress and a tensile stress offsetting at least a portion of the one of tensile stress and compressive stress at the interface to substantially reduce bowing in the wafer.
17. A rare earth oxide buffered semiconductor on silicon wafer as claimed in claim 16 wherein the thickness of the rare earth oxide structure provides the opposite one of a compressive stress and a tensile stress approximately equal to the one of tensile stress and compressive stress of the layer of single crystal semiconductor material at the interface whereby bowing of the silicon wafer is substantially eliminated.
18. A rare earth oxide buffered semiconductor on silicon wafer as claimed in claim 16 wherein the rare earth oxide structure includes one of a binary alloy and a ternary alloy.
19. A rare earth oxide buffered semiconductor on silicon wafer as claimed in claim 16 wherein the rare earth oxide structure include two or more layers of different compositions.
20. A method as claimed in claim 16 wherein the layer of single crystal semiconductor material includes germanium.
US13/278,952 2011-10-21 2011-10-21 Strain compensated reo buffer for iii-n on silicon Abandoned US20130099357A1 (en)

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US20130248853A1 (en) * 2012-03-20 2013-09-26 Erdem Arkun Nucleation of iii-n on reo templates
CN106057643A (en) * 2016-05-27 2016-10-26 清华大学 Semiconductor structure and method for preparing semiconductor structure
US20160343903A1 (en) * 2015-05-20 2016-11-24 Sharp Kabushiki Kaisha Nitride semiconductor light-emitting device and method for producing the same
US9520696B2 (en) 2014-03-04 2016-12-13 Princeton Optronics Inc. Processes for making reliable VCSEL devices and VCSEL arrays
JP2017503334A (en) * 2013-11-19 2017-01-26 トランスルーセント インコーポレイテッドＴｒａｎｓｌｕｃｅｎｔ， Ｉｎｃ． Amorphous SiO2 interlayer to relieve stress
US9761539B2 (en) 2015-06-29 2017-09-12 Globalfoundries Inc. Wafer rigidity with reinforcement structure
EP3105795A4 (en) * 2014-02-12 2017-09-27 Translucent, Inc. Iii-n semiconductor layer on si substrate
US10205303B1 (en) 2017-10-18 2019-02-12 Lumentum Operations Llc Vertical-cavity surface-emitting laser thin wafer bowing control
WO2024056424A1 (en) * 2022-09-12 2024-03-21 Iqe Plc A semiconductor structure

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130248853A1 (en) * 2012-03-20 2013-09-26 Erdem Arkun Nucleation of iii-n on reo templates
US9496132B2 (en) * 2012-03-20 2016-11-15 Translucent, Inc. Nucleation of III-N on REO templates
JP2017503334A (en) * 2013-11-19 2017-01-26 トランスルーセント インコーポレイテッドＴｒａｎｓｌｕｃｅｎｔ， Ｉｎｃ． Amorphous SiO2 interlayer to relieve stress
EP3105795A4 (en) * 2014-02-12 2017-09-27 Translucent, Inc. Iii-n semiconductor layer on si substrate
US9520696B2 (en) 2014-03-04 2016-12-13 Princeton Optronics Inc. Processes for making reliable VCSEL devices and VCSEL arrays
US20160343903A1 (en) * 2015-05-20 2016-11-24 Sharp Kabushiki Kaisha Nitride semiconductor light-emitting device and method for producing the same
US10026869B2 (en) * 2015-05-20 2018-07-17 Sharp Kabushiki Kaisha Nitride semiconductor light-emitting device and method for producing the same
US9761539B2 (en) 2015-06-29 2017-09-12 Globalfoundries Inc. Wafer rigidity with reinforcement structure
US10325862B2 (en) 2015-06-29 2019-06-18 Globalfoundries Inc. Wafer rigidity with reinforcement structure
CN106057643A (en) * 2016-05-27 2016-10-26 清华大学 Semiconductor structure and method for preparing semiconductor structure
US10205303B1 (en) 2017-10-18 2019-02-12 Lumentum Operations Llc Vertical-cavity surface-emitting laser thin wafer bowing control
WO2024056424A1 (en) * 2022-09-12 2024-03-21 Iqe Plc A semiconductor structure

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