US20120324154A1 - Data programming methods and devices - Google Patents
Data programming methods and devices Download PDFInfo
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- US20120324154A1 US20120324154A1 US13/596,697 US201213596697A US2012324154A1 US 20120324154 A1 US20120324154 A1 US 20120324154A1 US 201213596697 A US201213596697 A US 201213596697A US 2012324154 A1 US2012324154 A1 US 2012324154A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 12/244,131, filed on Oct. 2, 2008, which claims the benefit of Taiwan application Serial No. 97126262 filed Jul. 11, 2008, the subject matter of which is incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to a data programming method, and more particularly to a data programming method for reducing the time it takes for programming.
- 2. Description of the Related Art
-
FIG. 1 is a diagram of a conventional memory structure. A non-volatile memory, such as a flash memory, comprises at least onememory unit 100, and thememory unit 100 comprises 1024 memory blocks Block0-Block1023. Each memory block comprises 64 pages, and each page comprises four sectors. As shown inFIG. 1 , the memory block BlockM comprises 64 pages Page0-Page63, and the page PageN comprises four sectors Sector0-Sector3, wherein M is a positive integer from 0 to 1023, and N is a positive integer from 0 to 63. Each sector has 512-byte storage space, and one page is a unit for data programming. - It is assumed that a conventional memory unit desires to program two data in the same page. The memory unit first receives first data to be programmed into the page Page0 of the memory block BlockM. If the page Page0 is empty, the memory unit programs the first data into the page Page0. After, when the memory unit receives second data to be programmed into the page Page0, the data of the other pages (such as Page1-Page63) are backed up into volatile memory (not shown in
FIG. 1 ) or other memory blocks, and then the entire memory block BlockM is erased. Finally, the second data is programmed into the page Page0 of the memory block BlockM, and the un-changed data is programmed back into the memory block BlockM from the volatile memory (not shown inFIG. 1 ) or the other memory blocks. Since the time period taken by the memory unit to erase data is longest and next longest time period taken is the time period taken by the memory unit to program data, the time it takes for erasing data from the pages and programming data into pages can be decreased for shortening the time period for data programming. - An exemplary embodiment of a data programming method comprises the steps: (A) determining whether data exceeds one page; (B) if the data exceeds one page, programming a first portion of the data into a non-volatile memory and storing a second portion of the data, which is insufficient for one page, into a volatile memory; (C) if the data does not exceed one page, storing the data insufficient for one page into the volatile memory; (D) determining whether a next data is programmed into the same page as the data; (E) if the next data is programmed into the same page as the data, performing the step (A); and (F) if the next data is not programmed into the same page as the data, programming the second portion of data into the non-volatile memory and performing the step (A).
- An exemplary embodiment of a data programming device comprises a non-volatile memory, a volatile memory, and a memory control unit. The non-volatile memory is arranged for programming data. The volatile memory is arranged for temporarily storing data. The memory control unit is arranged for receiving data and determining whether the data is programmed into the non-volatile memory or stored into the volatile memory. If the data exceeds one page, the memory control unit programs a first portion of the data into the non-volatile memory and stores a second portion of the data, which is insufficient for one page, into the volatile memory.
- A detailed description is given in the following embodiments with reference to the accompanying drawings.
- The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
-
FIG. 1 is a diagram of a conventional memory structure; -
FIG. 2 shows an exemplary embodiment of a data programming device; -
FIG. 3 is a flow chart of an exemplary embodiment of a data programming method. - The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
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FIG. 2 shows an exemplary embodiment of adata programming device 200. Thedata programming device 200 comprises amemory control unit 210 and amemory unit 220. Thememory control unit 210 comprises anon-volatile memory 230 and avolatile memory 240. In an embodiment, thevolatile memory 240 is implemented by a cache memory, and thenon-volatile memory 230 is implemented by a NAND flash memory. In another embodiment, thenon-volatile memory 230 comprises at least one single-level cell (SLC), at least one multi-level cell (MLC), or a combination of at least one SLC and at least one MLC. Thedata programming device 200 can be a solid state drive (SSD) or a memory card device. According to memory specifications, if the number of programs (NOP) is equal to 1, each page of a memory programs data once after the page has been erased. Since the time period for erasing data is longest and the next longest time period is the time period for programming data for pages of a non-volatile memory, decreasing the times of erasing data or programming data for pages of a non-volatile is an objective of the present invention. - In one embodiment, the
memory control unit 210 receives data and a logic address from a host (not shown inFIG. 2 ) and determines the data to be stored into thecache memory 240 or programmed into theflash memory 230 according to the logic address and the data length. If the data length exceeds one page, thememory control unit 210 programs the data into theflash memory 230. In other words, the data of at least one page is programmed into theflash memory 230, and the remaining data which is insufficient for one page is programmed into thecache memory 240. If data is insufficient for one page, thememory control unit 210 stores the data insufficient for one page into thecache memory 240 and then determines whether the next data is to be programmed into the same page as the data already programmed into thecache memory 240. If the next data is not determined to be suitable for programming into the same page as the data already stored in thecache memory 240, thememory control unit 210 switches the data of thecache memory 240 to be programmed into theflash memory 230 and determines whether the next data exceeds one page to determine whether the next data should be programmed into to theflash memory 230. If the next data is determined to be programmed into the same page as the data already programmed into thecache memory 240, thememory control unit 210 determines whether the remaining data (in the cache memory 240) plus the next data exceeds one page to determine whether the remaining data plus the next data is programmed into to theflash memory 230. Moreover, if the time period when thememory control unit 210 is waiting to program data exceeds a predetermined time period, thememory control unit 210 directly programs the remaining data of thecache memory 240 into theflash memory 230. A data programming method in the memory is described in detail by the following embodiments. -
FIG. 3 is a flow chart of an exemplary embodiment of a data programming method. When the time period when thememory control unit 210 is waiting to program data exceeds a predetermined time period (step S310), thememory control unit 210 finishes the data programming process. If thememory control unit 210 receives data in the predetermined time period, thememory control unit 210 determines that all data exceeds one page (step S320). If all the data exceeds one page, the data of N pages is programmed into the flash memory 230 (step S330), and the remaining data which is insufficient for one page is stored into the cache memory 240 (step S340). If all the data is insufficient for one page, thememory control unit 210 stores the data insufficient for one page into the cache memory 240 (step S340). Next, thememory control unit 210 waits for a next data. If the time for waiting for a next data exceeds the predetermined time period (step S350), thememory control unit 210 programs the data of thecache memory 240 into the flash memory 230 (step S360). If thememory control unit 210 receives the next data in the predetermined time period, thememory control unit 210 determines whether the next data is determined to be programmed into the same page as the remaining data already stored into the cache memory 240 (step S370). If the next data should be programmed into the same page as the data of thecache memory 240, the process proceeds to the step S320 to determine whether the remaining data plus the next data exceeds one page or not. If the next data should not programmed into the same page as the data of thecache memory 240, thememory control unit 210 programs the remaining data of thecache memory 240 into the flash memory 230 (step S380), and the process proceeds to the step S320 to determined whether all the data exceeds one page. - According to the embodiments, the data insufficient for one page is stored into the
cache memory 240, and then, when all the data exceeds one page, the data of the cache memory is programmed into theflash memory 230. Thus, the time period for programming and erasing data of theflash memory 230 is decreased, resulting in a shortened time period for programming data of thememory unit 100. - While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (3)
Priority Applications (1)
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US13/596,697 US8856432B2 (en) | 2008-07-11 | 2012-08-28 | Data programming methods and devices for programming data into memories |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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TW97126262A | 2008-07-11 | ||
TW97126262 | 2008-07-11 | ||
TW97126262A TWI363272B (en) | 2008-07-11 | 2008-07-11 | Data programming method and device |
US12/244,131 US8281063B2 (en) | 2008-07-11 | 2008-10-02 | Data programming methods and devices for programming data into memories |
US13/596,697 US8856432B2 (en) | 2008-07-11 | 2012-08-28 | Data programming methods and devices for programming data into memories |
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Application Number | Title | Priority Date | Filing Date |
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US12/244,131 Continuation US8281063B2 (en) | 2008-07-11 | 2008-10-02 | Data programming methods and devices for programming data into memories |
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US20120324154A1 true US20120324154A1 (en) | 2012-12-20 |
US8856432B2 US8856432B2 (en) | 2014-10-07 |
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US12/244,131 Active 2031-02-28 US8281063B2 (en) | 2008-07-11 | 2008-10-02 | Data programming methods and devices for programming data into memories |
US13/596,697 Active US8856432B2 (en) | 2008-07-11 | 2012-08-28 | Data programming methods and devices for programming data into memories |
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US12/244,131 Active 2031-02-28 US8281063B2 (en) | 2008-07-11 | 2008-10-02 | Data programming methods and devices for programming data into memories |
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US20120117303A1 (en) * | 2010-11-04 | 2012-05-10 | Numonyx B.V. | Metadata storage associated with flash translation layer |
TWI470432B (en) * | 2011-11-21 | 2015-01-21 | Mstar Semiconductor Inc | Electronic system and flash memory managing method thereof |
US9262316B2 (en) | 2013-12-09 | 2016-02-16 | International Business Machines Corporation | Recording dwell time in a non-volatile memory system |
US9390003B2 (en) | 2013-12-09 | 2016-07-12 | International Business Machines Corporation | Retirement of physical memory based on dwell time |
WO2019112907A1 (en) | 2017-12-06 | 2019-06-13 | Rambus Inc. | Error-correction-detection coding for hybrid memory module |
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US6897976B2 (en) | 1998-07-17 | 2005-05-24 | Canon Kabushiki Kaisha | Record control apparatus and recording apparatus |
US20080320209A1 (en) * | 2000-01-06 | 2008-12-25 | Super Talent Electronics, Inc. | High Performance and Endurance Non-volatile Memory Based Storage Systems |
US7058784B2 (en) | 2003-07-04 | 2006-06-06 | Solid State System Co., Ltd. | Method for managing access operation on nonvolatile memory and block structure thereof |
CN100543702C (en) * | 2003-11-18 | 2009-09-23 | 松下电器产业株式会社 | File recording device and control method thereof and manner of execution |
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- 2008-07-11 TW TW97126262A patent/TWI363272B/en active
- 2008-10-02 US US12/244,131 patent/US8281063B2/en active Active
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US20080250195A1 (en) * | 2000-01-06 | 2008-10-09 | Super Talent Electronics Inc. | Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear |
US20080183949A1 (en) * | 2007-01-26 | 2008-07-31 | Micron Technology, Inc. | Flash storage partial page caching |
US7930487B1 (en) * | 2007-09-13 | 2011-04-19 | Emc Corporation | System and method for providing access control to raw shared devices |
US20100030999A1 (en) * | 2008-08-01 | 2010-02-04 | Torsten Hinz | Process and Method for Logical-to-Physical Address Mapping in Solid Sate Disks |
US20140143489A1 (en) * | 2012-11-16 | 2014-05-22 | Avalanche Technology, Inc. | Controller management of memory array of storage device using magnetic random access memory (mram) |
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TW201003395A (en) | 2010-01-16 |
US8281063B2 (en) | 2012-10-02 |
TWI363272B (en) | 2012-05-01 |
US20100011152A1 (en) | 2010-01-14 |
US8856432B2 (en) | 2014-10-07 |
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