US20120319231A1

US20120319231A1 - Microelectronic Device Including Shallow Trench Isolation Structures Having Rounded Bottom Surfaces

Info

Publication number: US20120319231A1
Application number: US13/584,518
Authority: US
Inventors: Albert Wu; Runzi Chang
Original assignee: Marvell World Trade Ltd
Current assignee: Marvell World Trade Ltd
Priority date: 2007-07-13
Filing date: 2012-08-13
Publication date: 2012-12-20
Also published as: US9142445B2; US8241993B2; TWI400769B; US20090017593A1; TW200926353A; US20140080285A1; WO2009012122A1

Abstract

Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of, and claims priority to, U.S. patent application Ser. No. 12/171,173, filed on Jul. 10, 2008, entitled “Method for Shallow Trench Isolation,” which claims priority to U.S. Provisional Patent Application No. 60/949,648, filed Jul. 13, 2007, the entire disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

Embodiments of the present invention relate to the field of microelectronic devices, in particular, to methods for rounding the bottom corners of shallow trench isolation structures.

BACKGROUND

Device integration has been, and will continue to be, an important design factor in the integrated circuit manufacturing industry. As the degree of device integration continues to increase, so too does the importance of device isolation. Device isolation ensures that devices are adequately isolated from each other as needed. Shallow trench isolation (STI) is a commonly-used isolation technique as it may allow for the formation of isolation structures in smaller dimensions and may also avoid bird's beak encroachment and other problems sometimes associated with local oxidation of silicon (LOCOS) and other isolation techniques.

SUMMARY OF THE INVENTION

In view of the problems in the state of the art, embodiments of the invention are directed to methods for forming trenches with rounded bottom corners. More specifically, with the foregoing and other items in view, there is provided, in accordance with various embodiments of the invention, a method comprising forming a first masking layer on a sidewall of an opening in a substrate; removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein; forming a second masking layer on the first masking layer in the opening; and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein, wherein the second depth is greater than the first depth.
In various embodiments, the first masking layer may be formed over the sidewall and over the bottom surface of an opening in a substrate. In various ones of these embodiments, removing of the first portion of the substrate may include removing a bottom portion of the first masking layer, the bottom portion being over the bottom surface of the opening. Removing of the bottom portion of the first masking layer may include leaving the first masking layer on the sidewall. Removing of the bottom portion of the first masking layer may include anisotropically etching the first masking layer so as to remove the bottom portion of the first masking layer without removing the first masking layer on the sidewall.
In various embodiments, the second masking layer may be formed over the bottom surface of the opening and over the first masking layer on the sidewall. Removing of the second portion of the substrate may include removing a bottom portion of the second masking layer, the bottom portion being over the bottom surface of the opening.
In various embodiments, the second portion of the substrate may be narrower than the first portion of the substrate. The removing of the first portion and the removing of the second portion may result in the bottom surface having a rounded shape.
In various embodiments, at least one of the first masking layer and the second masking layer is a polymer material. The polymer material may be a fluorohydrocarbon polymer.
In various embodiments, the first and second masking layers may be removed from the sidewall after removing of the second portion of the substrate. Oxide may be formed in the opening after removing of the first and second masking layers from the sidewall. The forming of the oxide may include forming a liner oxide layer in the opening using an in-situ steam generation (ISSG) operation. The ISSG operation may be performed at a temperature greater than 1000° Celsius (C) for about 30 seconds.
Other features that are considered as characteristic for embodiments of the invention are set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

FIG. 1 illustrates a cross-sectional side view of a related art microelectronic device.

FIG. 2 illustrates a cross-sectional side view of an exemplary microelectronic device including shallow trench isolation structures with rounded bottom corners in accordance with various embodiments of the present invention.

FIGS. 3-13 illustrate various stages of a method for forming shallow trench isolation structures with rounded bottom corners in accordance with various embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments in accordance with the present invention is defined by the appended claims and their equivalents.
The description may use the phrases “in an embodiment,” “in embodiments,” or “in various embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present invention, are synonymous. The phrase “NB” means A or B. For the purposes of the present invention, the phrase “A and/or B” means “(A), (B), or (A and B).” The phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).” The phrase “(A)B” means “(B) or (AB),” that is, A is an optional element.
The terms chip, die, integrated circuit, monolithic device, semiconductor device, and microelectronic device are often used interchangeably in the microelectronics field. The present invention is applicable to all of the above as they are generally understood in the field.
Various embodiments of the present invention are directed to methods for rounding the bottom corners of substrate openings such as, for example, shallow trench isolation (STI) structures. Rounding the bottom corners of these structures may result in reduced stress at the corners relative to bottom corners of substrate openings in the related art.
A cross-sectional side view of an exemplary related art microelectronic device 100 is illustrated at FIG. 1. As illustrated, device 100 includes a device component such as, for example, transistor 102. Transistor 102 is bounded by two STI structures 104 a, 104 b. STI structures 104 a, 104 b are formed in substrate 106 and may be lined with a liner oxide 108 a, 108 b and filled with a trench oxide 110 a, 110 b.
STI structures 104 a, 104 b have flat bottom surfaces 112 a, 112 b and sharp corners 114 a, 114 b. Sharp corners 114 a, 114 b may lead to increased stress for the layers formed thereover (e.g., liner oxide 108 a, 108 b), which may result in undesirable electrical breakdown and leakage. This stress may be due, in some cases, to the thermal oxidation process used for forming liner oxide 108 a, 108 b. As the thermal oxide is grown from the surface silicon atoms of substrate 106, the silicon oxide molecules become crowded in corners 114 a, 114 b due to the size difference between silicon oxide molecules and silicon atoms (a silicon oxide molecule may be approximately 2.17 times greater in size than a silicon atom).
In order to reduce the stress associated with sharp corners 114 a, 114 b, an anneal operation is sometimes performed after the thermal oxidation operation for forming liner oxide 108 a, 108 b. Although annealing may be capable of reducing the amount of stress present in corners 114 a, 114 b, it is a rather time- and thermal-budget-consuming operation. In some operations, for example, the anneal operation may take more than 30 minutes to perform on top of the more than 30 minutes it may take to perform the liner oxidation itself. Moreover, the anneal and/or liner oxidation operation may be performed at temperatures exceeding 1000° Celsius (C).
Illustrated at FIG. 2 is an exemplary microelectronic device 200 including STI structures 204 a, 204 b with rounded bottom surfaces 212 a, 212 b formed using methods in accordance with various embodiments of the present invention. As illustrated, device 200 includes a device component such as, for example, transistor 202. STI structures 204 a, 204 b are formed in substrate 206 and may be lined with liner oxide 208 a, 208 b and filled with a trench oxide 210 a, 210 b.
Rounding of bottom surfaces 212 a, 212 b may result in a minimization of the stress experienced by the liner oxide 208 a, 208 b relative to that of various related art STI structures such as, for example, STI structures 104 a, 104 b of device 100 illustrated at FIG. 1. This may be due, at least in part, to the reduction or elimination of the sharp corners of the STI structure. As noted above, stress may be increased due to the confined space of sharp corners, which may result in silicon oxide molecules being crowded in the corners. In contrast, the sloped bottom of STI structures 204 a, 204 b may allow for more room for the molecules of liner oxide 208 a, 208 b.
An exemplary method for forming STI structures with rounded bottom corners is illustrated at FIGS. 3-13 as cross-sectional views of a microelectronic device after various operations of the method.
As illustrated at FIG. 3, a hardmask 316 is provided over a substrate 306. Hardmask 316 may be formed to cover the surface of substrate 306 except for those areas at which an STI structure is to be formed, as illustrated. Hardmask 316 may comprise any material or apparatus known in the art and suitable for protecting those areas of substrate 306 which are not to receive subsequent etching. In some embodiments, hardmask 316 may comprise a silicon nitride material deposited over the surface of substrate 306. Intermediate layers (not illustrated) may be formed between hardmask 316 and substrate 306 including, for example, a pad oxide layer.
Those areas of substrate 306 not protected by hardmask 316 may be etched as illustrated at FIG. 4 to form openings 318 in substrate 306. In order to form openings 318 with vertical sidewalls 320 and a generally flat bottom surface 322, substrate 306 may be anisotropically etched. The depth of openings 318 may be governed, at least in part, by the desired ultimate depth of the STI structure to be formed as will become more evident in the discussion to follow. In general, the depth of STI structures should be suitable to provide adequate device isolation. In some embodiments, for example, the depth of openings 318 is between approximately 100 nanometers and 800 nanometers.
A masking layer 324 may be formed over hardmask 316 and sidewalls 320 and bottom surfaces 322 of openings 318 as illustrated at FIG. 5. Masking layer 324 may be formed conformally as illustrated.
Masking layer 324 may comprise any material suitable for purposes described herein. In some embodiments, for example, masking layer 324 may comprise a dielectric material. Exemplary dielectric materials may include one comprising a hydrocarbon, a fluorocarbon, or a fluorohydrocarbon. In various embodiments, for example, masking layer 324 comprises a fluorohydrocarbon polymer material.
In various embodiments, hardmask 316 and masking layer 324 may be formed in the same piece of equipment, but in other embodiments, separate pieces of equipment may be used. Certain efficiencies may be evident, however, in forming hardmask 316 and masking layer 324 in the same piece of equipment including, for example, increased throughput due to elimination of transfer time.
Portions of masking layer 324 may then be etched as illustrated at FIG. 6. As illustrated, the portions of masking layer 324 over sidewalls 320 of openings 318 are not etched away during this operation, but rather, remain on sidewalls 318. In order to achieve this, an anisotropic etch process may be used. Because anisotropic etching is a highly-directional etch operation, horizontal portions of masking layer 324 may be etched away, as illustrated, while vertical portions remain.
During the etch operation for etching portions of masking layer 324, some of bottom surfaces 322 of substrate 306 may also be etched. As illustrated, a thickness 326 of substrate 306 is etched such that the etched portion of openings 318 has a greater overall depth relative to its starting depth (compare, e.g., to FIG. 4). The portions of bottom surfaces 322 adjacent to masking layer 324 remaining on sidewalls 320 may be lightly etched or not etched at all, however. Accordingly, a center portion of openings 318 is slightly deeper than the edge portion.
The operations described herein with reference to FIG. 5 and FIG. 6 may be repeated a plurality of times for forming rounded bottom surfaces 322 of openings 318. Each iteration may etch deeper into center portions of bottom surfaces 322 of openings 318, until a substantially rounded shape is achieved. It is noted that as used herein, a “bottom surface having a rounded shape” may include any configuration in which a transition from the sidewall to a bottom surface occurs in a graduated (or incremental) manner.
In a second iteration, for example, another masking layer 328 may be formed over hardmask 316 and also over masking layer 324 remaining on sidewalls 320 of openings 318 and over bottom surfaces 322 as illustrated at FIG. 7. In various embodiments, masking layer 328 may be formed using the same material and same general process as for forming masking layer 324. In other embodiments, however, the iterations may be tuned as needed.
Portions of masking layer 328 may then be etched as illustrated at FIG. 8. As illustrated, the portions of masking layer 328 over masking layer 324 on sidewalls 320 of openings 318 are not etched away during this operation, but rather, remain on masking layer 324. In order to achieve this, an anisotropic etch process may be used, etching horizontal portions of masking layer 328 while allowing vertical portions to remain.
During the etch operation for etching portions of masking layer 328, some of bottom surfaces 322 of substrate 306 may also be etched as described above. As illustrated, another thickness 330 of substrate 306 is etched such that the etched portion of openings 318 has a greater overall depth relative to its depth in a preceding iteration (compare, e.g., to FIG. 6). The portions of bottom surfaces 322 adjacent to masking layer 328 may be lightly etched or not etched at all, however.
After a desired number of iterations of forming and etching of the masking layers is performed, a plurality of masking layers 332 may remain on sidewalls 320 of openings 318 as illustrated at FIG. 9. As illustrated, bottom surfaces 322 of openings 318 are tapered. Although the illustrated structure depicts bottom surface 322 having a stepped shaped, in various embodiments the masking layers and etch operations may be adjusted to fine-tune the curve of bottom surfaces 322. For example, using thinner masking layers may result in a more gradually curved, smoother surface.
The remaining masking layers 332 may be etched to expose bottom surfaces 322 and sidewalls 320 of openings 318 as illustrated at FIG. 10. Any suitable etch operation may be used for removing masking layers 332. In various embodiments, an isotropic etch may be suitable for removing masking layers 332, as directionality may not be required.
Turning now to FIG. 11, a liner oxide 334 may be formed in openings 318 having rounded bottom surfaces 322. Liner oxide 334 may be formed using any method suitable for the purpose. In some embodiments, liner oxide 334 may be formed using a wet oxidation process including, for example, in-situ steam generation (ISSG). In various embodiments, an anneal operation may not be necessary after forming liner oxide 334 due at least in part to the rounded bottom surfaces 322 resulting in liner oxide 334 having less stress relative to oxide formed in openings having squared-off bottom corners. Moreover, in various embodiments, formation of liner oxide 334 may be performed in much less time relative to related art methods. For example, in some embodiments, liner oxide 334 may be formed in less than about a minute due to this low-stress condition (compared to 30 minutes or more in some related art methods). In an exemplary embodiment, liner oxide 334 is formed using ISSG at about 1050° C. for about 30 seconds. Other methods may be similarly suitable.
Openings 318 may be filled with a trench oxide 336 as illustrated at FIG. 12. A chemical-mechanical planarization operation may be performed to remove the remaining hardmask 316 and any excess trench oxide 336 as illustrated at FIG. 13.
STI structures 304 may be formed before, after, or during formation of device components such as, for example, transistors (see, e.g., transistor 202 at FIG. 2). In any event, formation of STI structures 304 having rounded bottom surfaces 322 may provide for reduced leakage, and thus, higher reliability devices relative to various related art devices due at least part to reduction or elimination of high stress bottom corners. Moreover, thermal cycling of the device may be reduced according to various embodiments, which may also affect performance of the device.
Although STI structures formed in accordance with various embodiments of the present invention may be suitable for different types of devices, high-transistor-density devices may find these embodiments particularly beneficial. Memory devices, for example, may include dense arrays of transistors isolated by shallow trench isolation structures.
Although certain embodiments have been illustrated and described herein for purposes of description of a preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present invention. Those with skill in the art will readily appreciate that embodiments in accordance with the present invention may be implemented in a very wide variety of ways. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments in accordance with the present invention be limited only by the claims and the equivalents thereof.

Claims

1. A microelectronic device comprising:

a substrate;

a first shallow trench isolation structure defined within the substrate, wherein the first shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a first liner oxide is formed within the first shallow trench isolation structure;

a second shallow trench isolation structure defined within the substrate, wherein the second shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a second liner oxide is formed within the second shallow trench isolation structure; and

a device component located (i) on the surface of the substrate and (ii) between the top of the first shallow trench isolation structure and the top of the second shallow trench isolation structure,

wherein each of the rounded bottom surface of the first shallow trench isolation structure and the rounded bottom surface of the second shallow trench isolation structure respectively reduce stress associated with formation of the first liner oxide within the first shallow trench isolation structure and formation of the second liner oxide within the second shallow trench isolation structure.

2. The microelectronic device of claim 1, wherein each of the first shallow trench isolation structure and the second shallow trench isolation structure is filled with a trench oxide.

3. The microelectronic device of claim 1, wherein the device component comprises a transistor.

4. The microelectronic device of claim 1, wherein the microelectronic device comprises a memory device.

5. The microelectronic device of claim 1, wherein:

the microelectronic device comprises a plurality of shallow trench isolation structures defined within the substrate, wherein the plurality of shallow trench isolation structures includes the first shallow trench isolation structure and the second shallow trench isolation structure, and wherein each of the plurality of shallow trench isolation structures includes (i) a top located at the surface of the substrate and (ii) a bottom surface that has a rounded shape; and

a plurality of device components, wherein each device component of the plurality of device components is located (i) on the surface of the substrate and (ii) between corresponding tops of a corresponding two of the plurality of shallow trench isolation structures,

wherein each of the rounded bottom surfaces of the plurality of shallow trench isolation structures respectively reduce stress associated with formation of the liner oxides within the plurality of shallow trench isolation structures.

6. The microelectronic device of claim 5, wherein each of the plurality of shallow trench isolation structures is filled with a trench oxide.

7. The microelectronic device of claim 6, wherein the plurality of device components comprise a plurality of transistors.

8. The microelectronic device of claim 7, wherein the microelectronic device comprises a memory device.

9. A method of making a microelectronic device, the method comprising:

providing a substrate;

forming a first shallow trench isolation structure within the substrate, wherein the first shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a first liner oxide is formed within the first shallow trench isolation structure;

forming a second shallow trench isolation structure within the substrate, wherein the second shallow trench isolation structure includes (i) a top located at a surface of the substrate, and (ii) a bottom surface having a rounded shape, and wherein a second liner oxide is formed within the second shallow trench isolation structure; and

forming a device component located (i) on the surface of the substrate and (ii) between the top of the first shallow trench isolation structure and the top of the second shallow trench isolation structure,

10. The method of claim 9, wherein forming a first shallow trench isolation structure and forming a second shallow trench isolation structure within the substrate comprises:

forming two openings within the substrate; and

filling each of the two openings with a trench oxide.

11. The method of claim 9, wherein forming a device component comprises forming a transistor.

12. The method of claim 9, wherein the microelectronic device comprises a memory device.

13. A method of making a microelectronic device, the method comprising:

providing a substrate;

forming a plurality of shallow trench isolation structures within the substrate, each of the plurality of shallow trench isolation structures including (i) a top located at a surface of the substrate and (ii) a bottom surface that has a rounded shape, wherein a liner oxide is formed within each shallow trench isolation structure; and

forming a plurality of device components located (i) on the surface of the substrate and (ii) between corresponding tops of a corresponding two of the plurality of shallow trench isolation structures,

14. The method of claim 13, wherein forming a plurality of shallow trench isolation structures within the substrate comprises:

forming a plurality of openings within the substrate; and

filling each of the plurality of openings with a trench oxide.

15. The method of claim 14, wherein forming a plurality of device components comprises forming a plurality of transistors.

16. The method of claim 15, wherein the microelectronic device comprises a memory device.