US20120313166A1 - Semiconductor Device Having A Modified Shallow Trench Isolation (STI) Region And A Modified Well Region - Google Patents
Semiconductor Device Having A Modified Shallow Trench Isolation (STI) Region And A Modified Well Region Download PDFInfo
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- US20120313166A1 US20120313166A1 US13/567,524 US201213567524A US2012313166A1 US 20120313166 A1 US20120313166 A1 US 20120313166A1 US 201213567524 A US201213567524 A US 201213567524A US 2012313166 A1 US2012313166 A1 US 2012313166A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Definitions
- the present invention generally relates to semiconductors. More specifically, the invention relates to increasing a breakdown voltage of a semiconductor device.
- auxiliary devices are devices used in conjunction with integrated circuits and may include printers, scanners, disk drives, tape drives, microphones, speakers, and cameras to provide some examples.
- Auxiliary devices may operate at voltages above the breakdown voltage of the transistors contained within the integrated circuit. As the operating voltage applied to a transistor increases, the transistor will eventually breakdown allowing an uncontrollable increase in current to pass through the junction. Breakdown voltage is the voltage level where this uncontrollable increase in current occurs. Examples of breakdown may include punch-through, avalanche breakdown, and gate oxide breakdown to provide some examples. Operating above the breakdown voltage for a significant duration reduces the lifetime of the transistor.
- Techniques are currently available to increase the voltage at which breakdown occurs. These techniques may include the separate design of input-output circuits using a high voltage process, double diffused drain or other extended chain techniques, or the cascading of two individual transistors to provide some examples. These techniques often increase the fabrication cost by requiring additional process steps along with additional substrate masking.
- MOSFET metal oxide semiconductor field effect transistor
- FIG. 1A illustrates a cross-sectional view of a conventional n-type laterally diffused metal oxide semiconductor (LDMOS) fabricated using a conventional complementary metal oxide semiconductor (CMOS) logic foundry technology.
- LDMOS laterally diffused metal oxide semiconductor
- FIG. 1B illustrates a doping profile of an n-well region formed within the conventional n-type LDMOS.
- FIG. 1C illustrates a cross-sectional view of a drain to source resistance of the conventional n-type LDMOS.
- FIG. 1D illustrates a voltage potential profile of the conventional n-type LDMOS.
- FIG. 2A illustrates a cross-sectional view of a first n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a first exemplary embodiment.
- FIG. 2B illustrates a cross-sectional view of a drain to source resistance of the first n-type LDMOS structure according to an exemplary embodiment of the present invention.
- FIG. 2C illustrates a voltage potential profile of the first n-type LDMOS structure according to an exemplary embodiment of the present invention.
- FIG. 3A illustrates a cross-sectional view of a second n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a second exemplary embodiment.
- FIG. 3B illustrates a first doping profile of a modified n-well region formed within the n-type LDMOS structure according a first exemplary embodiment of the present invention.
- FIG. 3C illustrates a second doping profile of a modified n-well region formed within the n-type LDMOS structure according to a second exemplary embodiment of the present invention.
- FIG. 3D illustrates a cross-sectional view of a drain to source resistance of the second n-type LDMOS structure according to an exemplary embodiment of the present invention.
- FIG. 3E illustrates a voltage potential profile of the second n-type LDMOS structure according to an exemplary embodiment of the present invention.
- references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- FIG. 1A illustrates a cross-sectional view of a conventional n-type laterally diffused metal oxide semiconductor (LDMOS) fabricated using a conventional complementary metal oxide semiconductor (CMOS) logic foundry technology.
- the conventional CMOS logic foundry technology fabricates a conventional LDMOS structure 100 onto a substrate 102 of one conductivity type.
- the substrate 102 represents a physical material on which the conventional CMOS logic foundry technology fabricates the conventional LDMOS structure 100 .
- the conventional CMOS logic foundry technology fabricates the conventional LDMOS structure 100 onto the substrate 102 composed with a p-type material.
- the p-type material includes impurity atoms of an acceptor type, such as, but not limited to, boron or aluminum to provide some examples, that are capable of accepting an electron. Doping the substrate 102 with the p-type material causes a carrier hole density in the substrate 102 to exceed a carrier electron density.
- a first heavily doped region of opposite conductivity as the substrate 102 represents a source region 104 of the conventional LDMOS structure 100 .
- the source region 104 may optionally include a lightly doped region, often referred to as an LDD region 106 .
- the LDD region 106 is of substantially similar conductivity as the source region 104 with a lesser doping density when compared to a doping density of the source region 104 .
- a second heavily doped region of opposite conductivity as the substrate 102 represents a drain region 108 of the conventional LDMOS structure 100 .
- the conventional CMOS logic foundry technology implants the source region 104 and the drain region 108 with N+ material to form a first N+ region and a second N+ region corresponding to the source region 104 and the drain region 108 , respectively.
- the “+” indicates that the region is implanted with a higher carrier concentration than a region not designated by a “+.” For instance, an N+ region generally has a greater number of excess carrier electrons than an n-type region.
- a P+ region typically has a greater number of excess carrier holes than a p-type substrate.
- the conventional CMOS logic foundry may optionally implant the LDD region 106 with n-type material having a doping density less than a doping density of the first N+ region and/or the second N+ region.
- the n-type material includes impurity atoms of a donor type, such as, but not limited to, phosphorus, arsenic, or antimony to provide some examples, that are capable of donating an electron.
- Implanting the source region 104 and/or the drain region 108 with the n-type material causes the carrier electron density in the source region 104 and/or the drain region 108 to exceed a carrier hole density.
- a third heavily doped region of opposite conductivity as the substrate 102 represents a gate region 110 of the conventional LDMOS structure 100 .
- the conventional CMOS logic foundry technology heavily implants polycrystalline silicon with the opposite conductivity as the substrate 102 to form the gate region 110 .
- the conventional CMOS logic foundry technology implants the polycrystalline silicon with the N+ material to form an N+ poly region corresponding to the gate region 110 .
- the conventional LDMOS structure 100 may form a part of an interconnected array of active and passive elements integrated with or deposited on the substrate 102 by a continuous series of compatible processes known as an integrated circuit.
- the conventional LDMOS structure 100 includes shallow trench isolation (STD regions to provide isolation and/or protection for the conventional LDMOS structure 100 from neighboring active and passive elements integrated with or deposited on the substrate 102 .
- a first STI region 116 and a second STI region 120 provides isolation and protection for the conventional LDMOS structure 100 .
- the first STI region 116 is adjacent to a first side of the source region 104 .
- the second STI region 120 is adjacent to a first side of the drain region 108 .
- the first STI region 116 and/or the second STI region 120 contact their respective sides of the source region 104 and/or the drain region 108 .
- the conventional LDMOS structure 100 further includes a breakdown STI region 118 to increase a breakdown voltage of the conventional LDMOS structure 100 when compared to a similar LDMOS structure that does not include the breakdown STI region 118 .
- the conventional CMOS logic foundry technology uses a dielectric material such as SiO 2 , though any suitable material may be used, to fabricate the first STI region 116 , the breakdown STI region 118 , and/or the second STI region 120 .
- the conventional LDMOS structure 100 additionally includes spacers to provide isolation and/or protection between the source region 104 , the drain region 108 , and/or a gate region 110 .
- the conventional LDMOS structure 100 includes a first spacer 126 between the source region 104 and the gate region 110 to isolate and/or protect the source region 104 and the gate region 110 .
- the conventional LDMOS structure 100 includes a second spacer 128 between a top side of the drain region 108 and a second side of the gate region 110 .
- the first spacer 126 and/or the second spacer 128 contact the respective sides of the source region 104 and/or the drain region 108 .
- the conventional CMOS logic foundry technology fabricates the second spacer 128 and/or the first spacer 126 using a dielectric material, such as SiO 2 , though any suitable material may be used.
- the conventional CMOS logic foundry technology accommodates a minimum size, such as a length, width, and/or height for at least some of the regions of the conventional LDMOS structure 100 and/or a minimum distance between two or more of the regions of the conventional LDMOS structure 100 as defined by one or more minimum design rules (MDRs), such a minimum space interval or a minimum overlap area to provide some examples.
- MDRs minimum design rules
- These minimum design rules represent limits a resolution of photolithographic processing used by the conventional CMOS logic foundry technology between one or more masks used to manufacture the conventional LDMOS structure 100 .
- the breakdown STI region 118 includes a minimum width 130 and a minimum height 132 .
- the minimum width 130 represents a smallest horizontal distance, i.e., width, of the breakdown STI region 118 that the conventional CMOS logic foundry technology may accommodate.
- the minimum height 132 represents a smallest vertical distance, i.e., height, of the breakdown STI region 118 that the conventional CMOS logic foundry technology may accommodate.
- the minimum width 130 is approximately 0.11 ⁇ m for a 65 nm minimum design rule foundry technology and the minimum height 132 varies from approximately 0.2 ⁇ m to approximately 0.25 ⁇ m from one 65 nm minimum design rule foundry technology to another.
- LDMOS structure 100 is described in further detail in U.S. patent application Ser. No. 12/155,628, filed Jun. 6, 2008, entitled “Shallow Trench Isolation (STI) Based Laterally Diffused Metal Oxide Semiconductor (LDMOS)” which is incorporated herein by reference in its entirety.
- STI Trench Isolation
- LDMOS Laterally Diffused Metal Oxide Semiconductor
- Applying a first potential, such as a positive direct current (DC) voltage to provide an example, to the gate region 110 and applying a second potential, such as a ground potential to provide an example, to the source region 104 causes a voltage to appear between the gate region 110 and the source region 104 .
- the first potential on the gate region 110 repels the positively charged carrier holes from a bottom side of the gate region 110 forming a channel region 112 .
- the channel region 112 represents a carrier-depletion region populated by a negative charge formed at a bottom side of a gate oxide 114 by an electric field. This electric field also attracts carrier electrons from the source region 104 and the drain region 108 into the channel region 112 .
- An n-type region connecting the source region 104 to the drain region 108 forms after a sufficient number of carrier electrons have accumulated in the channel region 112 allowing a current to pass through the channel region 112 .
- Specially implanted regions may increase the number of carrier holes and/or carrier electrons located in the substrate 102 .
- increasing the number of carrier holes in the substrate 102 requires a greater number of carrier electrons to form the depletion region.
- a specially implanted p-type region known as a p-well 122 , is adjacent to a bottom side of the source region 104 , the gate region 110 , and the first STI region 116 .
- the p-well 122 extends from a first side located under the first STI region 116 to a second side located under the gate region 110 .
- the conventional CMOS logic foundry technology may implant the substrate 102 with the p-type material to fabricate the p-well 122 .
- n-well region 124 a specially implanted n-type region, known as an n-well region 124 , is located below the drain region 106 , the gate region 110 , and the second STI region 120 .
- the n-well region 124 extends from a first side located under the second STI region 120 to a second side located under the gate region 110 .
- the conventional CMOS logic foundry technology may implant the substrate 102 with the n-type material to fabricate the n-well region 124 .
- the second side of the p-well 122 may contact the second side of the n-well region 124 .
- FIG. 1B illustrates a doping profile of an n-well region formed within the conventional n-type LDMOS.
- FIG. 1B illustrates the doping profile of the n-well region 124 along a cross section of the conventional n-type LDMOS structure designated by the broken line A-A′.
- the broken line A-A′ passes through the gate region 110 , the gate oxide 114 , a first region 176 of the n-well region 124 , a second region 178 of the n-well region 124 , a third region 180 of the n-well region 124 , and the substrate 102 .
- the first region 176 represents a portion of the n-well region 124 extending from the bottom of the gate oxide 114 until substantially horizontally aligned with the bottom side of the channel region 112 .
- the second region 178 extends from the first region 176 until substantially horizontally aligned with the bottom side of the breakdown STI region 118 .
- the third region 180 extends from the second region 178 to a bottom side of the n-well region 124 .
- the conventional CMOS logic foundry technology may lightly implant the substrate 102 with a high energy implant having a doping density between approximately
- the conventional CMOS logic foundry technology may concentrate the high energy implant into the third region 180 during formation of the n-well region 124 such that the doping destiny of the first region 176 and/or the second region 178 is less than the doping destiny of the third region 180 with the first region 176 having the lightest doping density.
- a drain to source resistance of the conventional LDMOS structure 100 namely a resistance from the drain region 108 to the source region 104 , influences the breakdown voltage.
- the breakdown voltage of a semiconductor device having a higher drain to source resistance is larger when compared to a substantially similar semiconductor device having a lower drain to source resistance.
- FIG. 1C illustrates a cross-sectional view of a drain to source resistance of the conventional n-type LDMOS. More specifically, FIG. 1C illustrates the cross-sectional view of a drain to source resistance 160 of the conventional LDMOS structure 100 in an on-state, namely after the sufficient number of carrier electrons have accumulated in the channel region 112 allowing the current to pass through the channel region 112 .
- the drain to source resistance 160 may be represented by multiple serial drain to source resistances.
- a first drain to source resistance 162 extends substantially horizontally from the source region 104 , or the from the LDD region 106 , to the n-well region 124 .
- the first drain to source resistance 162 includes the channel region 112 .
- a second drain to source resistance 164 extends substantially vertically from the first drain to source resistance 162 to a third drain to source resistance 166 .
- the second drain to source resistance 164 represents a drain to source resistance of the n-well region 124 along a first vertical side 168 of the breakdown STI region 118 .
- the third drain to source resistance 166 extends substantially horizontally from the second drain to source resistance 164 to a fourth drain to source resistance 170 .
- the third drain to source resistance 166 represents a drain to source resistance of the n-well region 124 along a first horizontal side 172 of the breakdown STI region 118 .
- the fourth drain to source resistance 170 extends substantially vertically from the third drain to source resistance 166 to the drain region 108 .
- the fourth drain to source resistance 170 represents a drain to source resistance of the n-well region 124 along a second vertical side 174 of the breakdown STI region 118 .
- FIG. 1D illustrates a voltage potential profile of the conventional n-type LDMOS. More specifically, FIG. 1D illustrates a voltage potential profile 180 of the conventional LDMOS structure 100 as a function of position and voltage.
- the voltage potential profile 180 represents a voltage dissipated by the drain to source resistance 160 along the depletion region extending from the source region 104 to the drain region 108 .
- the first drain to source resistance 162 dissipates from approximately zero volts to approximately a first voltage VDD.
- the second drain to source resistance 164 through the fourth drain to source resistance 170 dissipate from approximately the first voltage V DD to approximately a first high voltage HV V DD1 , the first high voltage HV V DD1 being greater than the first voltage V DD .
- the voltage potential profile of the first drain to source resistance 162 increases at a first rate m 1 as a function of position such that the voltage potential at the source region 104 , or at the LDD region 106 , is less than the voltage potential at the second drain to source resistance 164 .
- the first rate m 1 represents a rate of increase of the voltage potential of the first drain to source resistance 162 along the depletion region extending from the source region 104 to the second drain to source resistance 164 .
- the voltage potential profile of the second drain to source resistance 164 increases at a second rate m 2 as a function of position such that the voltage potential at the second drain to source resistance 164 is less than the voltage potential at the third drain to source resistance 166 .
- the second rate m 2 represents a rate of increase of the voltage potential of the second drain to source resistance 164 along the depletion region extending from the first drain to source resistance 162 to the third drain to source resistance 166 .
- the second rate m 2 may include a first portion m 2A and a second portion m 2B .
- the first portion m 2A represents a rate of increase of the voltage potential of the second drain to source resistance 164 along the depletion region extending from the gate oxide 114 , along a first vertical side 168 of the breakdown STI region 118 , until substantially horizontally aligned with a bottom side of the channel region 112 .
- the second portion m 2B represents a rate of increase of the voltage potential of the second drain to source resistance 164 along the depletion region extending from the first portion m 2A , along the first vertical side 168 , to the third drain to source resistance 166 .
- the second portion m 2B extends substantially vertically from the first portion m 2A , along the first horizontal side 172 , to the third drain to source resistance 166 .
- the voltage potential profile of the third drain to source resistance 166 increases at a third rate m 3 as a function of position such that the voltage potential at the third drain to source resistance 166 is less than the voltage potential at the fourth drain to source resistance 168 .
- the third rate m 3 represents a rate of increase of a voltage potential of the third drain to source resistance 166 along the depletion region extending from the second drain to source resistance 164 , along the first horizontal side 172 , to the fourth drain to source resistance 170 .
- the voltage potential profile of the fourth drain to source resistance 170 increases at a fourth rate m 4 as a function of position such that the voltage potential at the fourth drain to source resistance 170 is less than the voltage potential at the drain region 108 .
- the fourth rate m 4 represents a rate of increase of a voltage potential of the fourth drain to source resistance 170 along the depletion region extending from the third drain to source resistance 166 , along a second vertical side 174 of the breakdown STI region 118 , to the drain region 108 .
- FIG. 2A illustrates a cross-sectional view of a first n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a first exemplary embodiment.
- a LDMOS structure 200 may be characterized as including a lesser drain to source resistance when compared to the drain to source resistance of the conventional LDMOS structure 100 .
- the LDMOS structure 200 includes a modified breakdown STI region to effectively reduce the drain to source resistance of the LDMOS structure 200 when compared to the conventional LDMOS structure 100 . This decrease in the drain to source resistance of the LDMOS structure 200 further increases the breakdown voltage of the LDMOS structure 200 when compared to the conventional LDMOS structure 100 .
- the breakdown STI region 118 of the conventional LDMOS structure 100 increases the drain to source resistance of the conventional LDMOS structure 100 , thereby increasing the breakdown voltage of the conventional LDMOS structure 100 .
- the breakdown STI region 118 restricts the current passing from the source region to the drain region.
- the modified breakdown STI region in FIG. 2A reduces this restriction from the breakdown STI region 118 while maintaining the benefits of the increase in breakdown voltage. As a result, more current may pass from the source region to the drain region of the LDMOS structure 200 , thereby further increasing the break down voltage of the LDMOS structure 200 from that of the conventional LDMOS structure 100 .
- CMOS logic foundry technology fabricates the LDMOS structure 200 in a substantially similar manner as the conventional LDMOS structure 100 as described above. Therefore, only differences between the LDMOS structure 200 and the conventional LDMOS structure 100 are to be described in further detail.
- the LDMOS structure 200 includes a modified breakdown STI region 202 to decrease the drain to source resistance of the LDMOS structure 200 when compared to the drain to source resistance of the conventional LDMOS structure 100 while further increasing the breakdown voltage when compared to the conventional LDMOS structure 100 as described above.
- the CMOS logic foundry technology fabricates the modified breakdown STI region 202 between the source region 104 and the drain region 108 within the n-well region 124 .
- the CMOS logic foundry technology fabricates the modified breakdown STI region 202 adjacent to the drain region 108 whereby at least some of the modified breakdown STI region 202 is positioned below the second spacer 128 .
- the modified breakdown STI region 202 includes a top edge 206 , a bottom edge 208 , a first slanted edge 210 , and a second slanted edge 212 .
- the top edge 206 , the bottom edge 208 , the first slanted edge 210 , and the second slanted edge 212 are configured to form a quadrilateral, such as a trapezoid to provide an example.
- quadrilaterals such as a trapezium, a parallelogram, a rhombus, or a kite to provide some are examples, are possible without departing from the spirit and scope of the present invention.
- the top edge 206 is characterized as having a horizontal length 214 of approximately 0.08 ⁇ m and the bottom edge 208 is characterized as having a horizontal length 216 of approximately 0.06 ⁇ m.
- the first slanted edge 210 and the second slanted edge 212 are configured and arranged such that a vertical length 218 of the modified breakdown STI region 202 is between approximately 0.30 ⁇ m and approximately 0.35 ⁇ m.
- the bottom edge 208 is characterized as having a horizontal length 216 of approximately 0 ⁇ m.
- the top edge 206 , the bottom edge 208 , the first slanted edge 210 , and the second slanted edge 212 are configured and arranged to form a triangle.
- the first slanted edge 210 connects a first end of the top edge 206 to a first end of the bottom edge 208
- the second slanted edge 212 connects a second end of the top edge 206 to a second end of the bottom edge 208
- the first slanted edge 210 and the second slanted edge 212 may each be characterized as having a slope m 1 and m 2 , respectively, greater than zero.
- This slope of the first slanted edge 210 and the second slanted edge 212 allows for more current to pass from the source region 104 to the drain region 108 , thereby reducing the drain to source resistance of the LDMOS structure 200 when compared to the conventional LDMOS structure 100 .
- the breakdown voltage of the LDMOS structure 200 is increased when compared to the breakdown voltage of the conventional LDMOS structure 100 .
- FIG. 2B illustrates a cross-sectional view of a drain to source resistance of the first n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically, FIG. 2B illustrates the cross-sectional view of a drain to source resistance 220 of the LDMOS structure 200 in an on-state, namely after the sufficient number of carrier electrons have accumulated in the channel region 112 allowing the current to pass through the channel region 112 .
- the drain to source resistance 220 may be represented by multiple serial drain to source resistances.
- a first drain to source resistance 222 extends substantially horizontally from the source region 104 , or the from the LDD region 106 , to the n-well region 124 .
- the first drain to source resistance 222 includes the channel region 112 .
- a second drain to source resistance 224 extends substantially vertically from the first drain to source resistance 222 to a third drain to source resistance 226 .
- the second drain to source resistance 224 represents a drain to source resistance of the n-well region 124 along the first slanted edge 210 of the modified breakdown STI region 202 .
- the third drain to source resistance 226 extends substantially horizontally from the second drain to source resistance 224 to a fourth drain to source resistance 228 .
- the third drain to source resistance 226 represents a drain to source resistance of the n-well region 124 along the bottom edge 208 of the modified breakdown STI region 202 .
- the fourth drain to source resistance 228 extends substantially vertically from the third drain to source resistance 226 to the drain region 108 .
- the fourth drain to source resistance 228 represents a drain to source resistance of the n-well region 124 along the second slanted edge 212 of the modified breakdown STI region 202 .
- FIG. 2C illustrates a voltage potential profile of the first n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically, FIG. 2C illustrates a voltage potential profile 230 of the LDMOS structure 200 as a function of position and voltage.
- the voltage potential profile 230 represents a voltage dissipated by the drain to source resistance 220 along the depletion region extending from the source region 104 to the drain region 108 .
- the first drain to source resistance 222 dissipates from approximately zero volts to approximately a first voltage VDD.
- the second drain to source resistance 224 through the fourth drain to source resistance 228 dissipate from approximately the first voltage V DD to approximately a second high voltage HV V DD2 , the second high voltage HV V DD2 being greater than the first high voltage HV V DD1 .
- the voltage potential profile of the first drain to source resistance 222 increases at a first rate m 11 as a function of position such that the voltage potential at the source region 104 , or at the LDD region 106 , is less than the voltage potential at the second drain to source resistance 224 .
- the first rate m 11 represents a rate of increase of the voltage potential of the first drain to source resistance 222 along the depletion region extending from the source region 104 to the second drain to source resistance 224 .
- the voltage potential profile of the second drain to source resistance 224 increases at a second rate m 2 as a function of position such that the voltage potential at the second drain to source resistance 224 is less than the voltage potential at the third drain to source resistance 226 .
- the second rate m 22 represents a rate of increase of the voltage potential of the second drain to source resistance 224 along the depletion region extending from the first drain to source resistance 222 to the third drain to source resistance 226 .
- the second rate m 22 may include a first portion m 22A and a second portion m 22B .
- the first portion m 22A represents a rate of increase of the voltage potential of the second drain to source resistance 224 along the depletion region extending from the gate oxide 114 , along the first slanted edge 210 , until substantially horizontally aligned with a bottom side of the channel region 112 .
- the first portion m 22A is less than the first portion m 2A as described in FIG. 1D .
- the first slanted edge 210 allows for more current to pass from the source region 104 to the drain region 108 , thereby reducing the drain to source resistance of the LDMOS structure 200 when compared to the conventional LDMOS structure 100 .
- the voltage potential of the second drain to source resistance 224 along the depletion region in this region within the n-well region 124 increases at a rate that is less than a similar region with the n-well region 124 of the conventional LDMOS structure 100 .
- the second portion m 22B represents a rate of increase of the voltage potential of the second drain to source resistance 224 along the depletion region extending from the first portion m 22A , along the first slanted edge 210 , to the third drain to source resistance 226 .
- the second portion m 22B extends substantially vertically from the first portion m 22A , along the first slanted edge 210 , to the third drain to source resistance 226 .
- the voltage potential profile of the third drain to source resistance 226 increases at a third rate m 33 as a function of position such that the voltage potential at the third drain to source resistance 226 is less than the voltage potential at the fourth drain to source resistance 228 .
- the third rate m 33 represents a rate of increase of a voltage potential of the third drain to source resistance 226 along the depletion region extending from the second drain to source resistance 224 , along the bottom edge 208 , to the fourth drain to source resistance 228 .
- the voltage potential profile of the fourth drain to source resistance 228 increases at a fourth rate m 44 as a function of position such that the voltage potential at the fourth drain to source resistance 228 is less than the voltage potential at the drain region 108 .
- the fourth rate m 4 represents a rate of increase of a voltage potential of the fourth drain to source resistance 228 along the depletion region extending from the third drain to source resistance 226 , along the second horizontal side 174 , to the drain region 108 .
- FIG. 3A illustrates a cross-sectional view of a second n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a second exemplary embodiment.
- a LDMOS structure 300 may be characterized by a lower drain to source resistance when compared to the drain to source resistance of the LDMOS structure 200 .
- the LDMOS structure 300 includes a modified well region to effectively reduce a drain to source resistance of the LDMOS structure 300 when compared to the LDMOS structure 200 .
- the modified well region further increases the breakdown voltage of the LDMOS structure 300 when compared to the LDMOS structure 200 .
- the modified breakdown STI region 202 of the LDMOS structure 200 decreases the drain to source resistance of the LDMOS structure 200 , thereby increasing the breakdown voltage of the LDMOS structure 200 .
- the n-well region 124 restricts the current passing from the source region to the drain region.
- the modified well region reduces this restriction from the n-well region 124 while maintaining the benefits of the increase in breakdown voltage.
- more current may pass from the source region to the drain region of the LDMOS structure 300 , thereby further increasing the break down voltage of the LDMOS structure 300 from that of the LDMOS structure 200 .
- the CMOS logic foundry technology fabricates the LDMOS structure 300 in a substantially similar manner as the LDMOS structure 200 described above. Therefore, only differences between the LDMOS structure 300 and the LDMOS structure 200 are to be described in further detail.
- the LDMOS structure 300 includes a modified breakdown STI region 302 and a modified n-well region 304 to decrease a drain to source resistance of the LDMOS structure 300 when compared to the drain to source resistance of the LDMOS structure 200 while further increasing the breakdown voltage as compared to the LDMOS structure 200 as described above.
- the modified breakdown STI region 302 is substantially similar to the modified breakdown STI region 202 as described above.
- the modified n-well region 304 includes a first heavily doped region of substantially similar conductivity as the modified n-well region 304 to form a heavily doped well region 306 .
- the CMOS logic foundry technology fabricates the heavily doped well region 306 between the modified breakdown STI region 302 and the source region 104 below the gate region 110 within the modified n-well region 304 .
- the CMOS logic foundry technology may implant the heavily doped well region 306 with N+ material to form an N+ region.
- the CMOS logic foundry may optionally include a second lightly doped region of substantially similar conductivity as the modified n-well region 304 to form an optional lightly doped well region 308 .
- the CMOS logic foundry technology fabricates the optional lightly doped well region 308 between the modified breakdown STI region 302 and the source region 104 below the gate region 110 within the modified n-well region 304 .
- the CMOS logic foundry technology may form the optional lightly doped well region 308 to have a horizontal length that is greater than a horizontal length of the heavily doped well region 306 as shown in FIG. 3A .
- the CMOS logic foundry technology may form the optional lightly doped well region 308 to have the horizontal length that is less than or equal to the horizontal length of the heavily doped well region 306 .
- the CMOS logic foundry may optionally implant the optional lightly doped well region 308 with n-type material having a doping density less than a doping density of the first heavily doped well region 306 .
- Implanting the modified n-well region 304 with the heavily doped well region 306 and/or the optional lightly doped well region 308 increases the number of carrier electrons located in the modified n-well region 304 when compared to the n-well region 124 . This reduces the drain to source resistance of the LDMOS structure 300 when compared to the LDMOS structure 200 , thereby increasing the breakdown voltage of the LDMOS structure 300 when compared to the breakdown voltage of the conventional LDMOS structure 200 .
- FIG. 3B illustrates a first doping profile of a modified n-well region formed within the n-type LDMOS structure according a first exemplary embodiment of the present invention.
- FIG. 3B illustrates the doping profile of the modified n-well region 304 without the optional lightly doped well region 308 along a cross section of the n-type LDMOS structure 300 as designated by the broken line A-A′.
- A-A′ As shown in FIG.
- the broken line A-A′ passes through the gate region 110 , the gate oxide 114 , a first region 312 of the modified n-well region 304 , a second region 314 of the modified n-well region 304 , a third region 316 of the modified n-well region 304 , and the substrate 102 .
- the first region 312 represents a portion of the modified n-well region 304 extending from the bottom of the gate oxide 114 until substantially horizontally aligned with a bottom side of the heavily doped well region 306 .
- the second region 314 extends from the first region 312 until substantially horizontally aligned with the bottom side of the modified breakdown STI region 302 .
- the third region 316 extends from the second region 314 to a bottom side of the modified n-well region 304 .
- the second region 314 and the third region 316 are substantially similar to the second region 178 and the third region 180 , respectively, as described above. Therefore, only the first region 312 is to be described in further detail below.
- the CMOS logic foundry technology may heavily implant the modified n-well region 304 with a high energy implant having a doping density of approximately
- the CMOS logic foundry technology may concentrate the high energy implant into the first region 312 during formation of the modified n-well region 304 such that the doping destiny of the first region 312 is greater than the second region 314 and the third region 316 .
- FIG. 3C illustrates a second doping profile of a modified n-well region formed within the n-type LDMOS structure according to a second exemplary embodiment of the present invention.
- FIG. 3C illustrates the doping profile of the modified n-well region 304 including the optional lightly doped well region 308 along a cross section of the n-type LDMOS structure 300 as designated by the broken line A-A′. As shown in FIG.
- the broken line A-A′ passes through the gate region 110 , the gate oxide 114 , a first region 318 of the modified n-well region 304 , a second region 314 of the modified n-well region 304 , a third region 316 of the modified n-well region 304 , and the substrate 102 .
- the first region 318 represents a portion of the modified n-well region 304 extending from the bottom of the gate oxide 114 until substantially horizontally aligned with a bottom side of the heavily doped well region 306 .
- the second region 314 extends from the first region 318 until substantially horizontally aligned with the bottom side of the modified breakdown STI region 302 .
- the third region 316 extends from the second region 314 to a bottom side of the modified n-well region 304 .
- the second region 314 and the third region 316 are substantially similar to the second region 178 and the third region 180 , respectively, as described above. Therefore, only the first region 318 is to be described in further detail below.
- the CMOS logic foundry technology may heavily implant the modified n-well region 304 with the high energy implant to form the heavily doped well region 306 in a substantially similar manner as described above in FIG. 3B .
- the CMOS logic foundry technology may implant the modified n-well region 304 with a second high energy implant having a doping density of approximately
- Implanting the modified n-well region 304 with the optional lightly doped well region 308 in this manner increases the doping density of the modified n-well region 304 from approximately
- the optional lightly doped well region 308 increases the breakdown voltage LDMOS structure 300 when compared to the breakdown voltage of the LDMOS structure 300 without the optional lightly doped well region 308 .
- FIG. 3D illustrates a cross-sectional view of a drain to source resistance of the second n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically, FIG. 3D illustrates the cross-sectional view of a drain to source resistance 320 of the LDMOS structure 300 in an on-state, namely after the sufficient number of carrier electrons have accumulated in the channel region 112 allowing the current to pass through the channel region 112 .
- the drain to source resistance 320 may be represented by multiple serial drain to source resistances.
- a first drain to source resistance 322 extends substantially horizontally from the source region 104 , or the from the LDD region 106 , to the modified n-well region 304 .
- the first drain to source resistance 322 includes the channel region 112 .
- a second drain to source resistance 324 extends substantially vertically from the first drain to source resistance 322 to a third drain to source resistance 326 .
- the second drain to source resistance 324 represents a drain to source resistance of the modified n-well region 304 along a first slanted edge of the modified breakdown STI region 302 .
- the third drain to source resistance 326 extends substantially horizontally from the second drain to source resistance 324 to a fourth drain to source resistance 328 .
- the third drain to source resistance 326 represents a drain to source resistance of the modified n-well region 304 along a bottom edge of the modified breakdown STI region 302 .
- the fourth drain to source resistance 328 extends substantially vertically from the third drain to source resistance 326 to the drain region 108 .
- the fourth drain to source resistance 328 represents a drain to source resistance of the modified n-well region 304 along the second slanted edge 212 of the modified breakdown STI region 302 .
- FIG. 3E illustrates a voltage potential profile of the second n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically, FIG. 3E illustrates a voltage potential profile 330 of the LDMOS structure 300 as a function of position and voltage.
- the voltage potential profile 330 represents a voltage dissipated by the drain to source resistance 320 along the depletion region extending from the source region 104 to the drain region 108 .
- the first drain to source resistance 322 dissipates from approximately zero volts to approximately a first voltage VDD.
- the second drain to source resistance 324 through the fourth drain to source resistance 328 dissipate from approximately the first voltage V DD to approximately a third high voltage HV V DD3 , the third high voltage HV V DD3 being greater than the second high voltage HV V DD2 .
- the voltage potential profile of the first drain to source resistance 322 increases at a first rate m 111 as a function of position such that the voltage potential at the source region 104 , or at the LDD region 106 , is less than the voltage potential at the second drain to source resistance 324 .
- the first rate m 111 represents a rate of increase of the voltage potential of the first drain to source resistance 322 along the depletion region extending from the source region 104 to the second drain to source resistance 324 .
- the voltage potential profile of the second drain to source resistance 324 increases at a second rate m 222 as a function of position such that the voltage potential at the second drain to source resistance 324 is less than the voltage potential at the third drain to source resistance 326 .
- the second rate m 222 represents a rate of increase of the voltage potential of the second drain to source resistance 324 along the depletion region extending from the first drain to source resistance 322 to the third drain to source resistance 326 .
- the second rate m 222 may include a first portion m 222A and a second portion m 222B .
- the first portion m 222A represents a rate of increase of the voltage potential of the second drain to source resistance 324 along the depletion region extending from the gate oxide 114 , along the first slanted edge 210 , until substantially horizontally aligned with a bottom side of the channel region 112 .
- the first portion m 222A is less than the first portion M 22A , as described in FIG. 2C .
- the heavily doped well region 306 allows for more current to pass from the source region 104 to the drain region 108 , thereby further reducing the drain to source resistance of the LDMOS structure 300 when compared to the LDMOS structure 200 .
- the voltage potential of the second drain to source resistance 324 along the depletion region in this region within the modified breakdown STI region 302 increases at a rate that is less than a similar region with the modified breakdown STI region 202 of the LDMOS structure 200 .
- the first portion m 222A may be decreased even further by including the optional lightly doped well region 308 .
- the optional lightly doped well region 308 further allows for more current to pass from the source region 104 to the drain region 108 , thereby further reducing the drain to source resistance of the LDMOS structure 300 when compared to the LDMOS structure 200 .
- the second portion m 222B represents a rate of increase of the voltage potential of the second drain to source resistance 324 along the depletion region extending from the first portion m 222A , along the first slanted edge of the modified breakdown STI region 302 , to the third drain to source resistance 326 .
- the second portion m 222B extends substantially vertically from the first portion m 222A , along the first slanted edge of the modified breakdown STI region 302 , to the third drain to source resistance 326 .
- the voltage potential profile of the third drain to source resistance 326 increases at a third rate m 333 as a function of position such that the voltage potential at the third drain to source resistance 326 is less than the voltage potential at the fourth drain to source resistance 328 .
- the third rate m 333 represents a rate of increase of a voltage potential of the third drain to source resistance 326 along the depletion region extending from the second drain to source resistance 324 , along the bottom edge of the LDMOS structure 300 , to the fourth drain to source resistance 328 .
- the voltage potential profile of the fourth drain to source resistance 328 increases at a fourth rate m 444 as a function of position such that the voltage potential at the fourth drain to source resistance 328 is less than the voltage potential at the drain region 108 .
- the fourth rate m 4 represents a rate of increase of a voltage potential of the fourth drain to source resistance 328 along the depletion region extending from the third drain to source resistance 326 , along a slanted edge of the modified breakdown STI region 302 , to the drain region 108 .
- LDMOS structures of the present invention have been described as n-type structures those skilled in the relevant art(s) will recognize that p-type structures may be similarly formed by using p-type material instead of n-type materiel without departing from the spirit and scope of the present invention. These p-type structures may be implanted into a deep n-well region formed within a p-type semiconductor substrate and/or directly implanted into an n-type semiconductor substrate. Additionally, those skilled in the relevant art(s) will recognize that the substrate as described herein may be composed of n-type material without departing from the spirit and scope of the present invention. In this situation, the LDMOS structures of the present invention may be implanted into a deep p-well region formed within the n-type semiconductor substrate.
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Abstract
Description
- The present application is a continuation of U.S. patent application Ser. No. 12/656,054, filed Jan. 14, 2010, which is incorporated herein by reference in its entirety.
- The present invention generally relates to semiconductors. More specifically, the invention relates to increasing a breakdown voltage of a semiconductor device.
- Silicon semiconductor processing has evolved sophisticated operations for fabricating integrated circuits. As advancement in fabrication process technology continues, the operating voltage of the integrated circuits has decreased, but the operating voltage of auxiliary devices remains the same. Auxiliary devices are devices used in conjunction with integrated circuits and may include printers, scanners, disk drives, tape drives, microphones, speakers, and cameras to provide some examples.
- Auxiliary devices may operate at voltages above the breakdown voltage of the transistors contained within the integrated circuit. As the operating voltage applied to a transistor increases, the transistor will eventually breakdown allowing an uncontrollable increase in current to pass through the junction. Breakdown voltage is the voltage level where this uncontrollable increase in current occurs. Examples of breakdown may include punch-through, avalanche breakdown, and gate oxide breakdown to provide some examples. Operating above the breakdown voltage for a significant duration reduces the lifetime of the transistor.
- Techniques are currently available to increase the voltage at which breakdown occurs. These techniques may include the separate design of input-output circuits using a high voltage process, double diffused drain or other extended chain techniques, or the cascading of two individual transistors to provide some examples. These techniques often increase the fabrication cost by requiring additional process steps along with additional substrate masking.
- What is needed is a metal oxide semiconductor field effect transistor (MOSFET) device that addresses one or more of the aforementioned shortcomings of conventional MOSFET devices.
- The accompanying drawings illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable one skilled in the pertinent art to make and use the invention.
-
FIG. 1A illustrates a cross-sectional view of a conventional n-type laterally diffused metal oxide semiconductor (LDMOS) fabricated using a conventional complementary metal oxide semiconductor (CMOS) logic foundry technology. -
FIG. 1B illustrates a doping profile of an n-well region formed within the conventional n-type LDMOS. -
FIG. 1C illustrates a cross-sectional view of a drain to source resistance of the conventional n-type LDMOS. -
FIG. 1D illustrates a voltage potential profile of the conventional n-type LDMOS. -
FIG. 2A illustrates a cross-sectional view of a first n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a first exemplary embodiment. -
FIG. 2B illustrates a cross-sectional view of a drain to source resistance of the first n-type LDMOS structure according to an exemplary embodiment of the present invention. -
FIG. 2C illustrates a voltage potential profile of the first n-type LDMOS structure according to an exemplary embodiment of the present invention. -
FIG. 3A illustrates a cross-sectional view of a second n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a second exemplary embodiment. -
FIG. 3B illustrates a first doping profile of a modified n-well region formed within the n-type LDMOS structure according a first exemplary embodiment of the present invention. -
FIG. 3C illustrates a second doping profile of a modified n-well region formed within the n-type LDMOS structure according to a second exemplary embodiment of the present invention. -
FIG. 3D illustrates a cross-sectional view of a drain to source resistance of the second n-type LDMOS structure according to an exemplary embodiment of the present invention. -
FIG. 3E illustrates a voltage potential profile of the second n-type LDMOS structure according to an exemplary embodiment of the present invention. - The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.
- The following detailed description of the present invention refers to the accompanying drawings that illustrate exemplary embodiments consistent with this invention. Other embodiments are possible, and modifications may be made to the embodiments within the spirit and scope of the invention. Therefore, the detailed description is not meant to limit the invention. Rather, the scope of the invention is defined by the appended claims.
- References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
- Furthermore, it should be understood that spatial descriptions (e.g., “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein may be spatially arranged in any orientation or manner. Likewise, particular bit values of “0” or “1” (and representative voltage values) are used in illustrative examples provided herein to represent information for purposes of illustration only. Information described herein may be represented by either bit value (and by alternative voltage values), and embodiments described herein may be configured to operate on either bit value (and any representative voltage value), as would be understood by persons skilled in the relevant art(s). It should be understood that relative spatial descriptions between one or more particular features, structures, or characteristics (e.g., “vertically aligned,” “contact,” etc.) used herein are for purposes of illustration only, and that practical implementations of the structures described herein may include fabrication and/or misalignment tolerances without departing from the spirit and scope of the present invention.
- The example embodiments described herein are provided for illustrative purposes, and are not limiting. Further structural and operational embodiments, including modifications/alterations, will become apparent to persons skilled in the relevant art(s) from the teachings herein.
- Fabrication of a Conventional Laterally Diffused Metal Oxide Semiconductor (LDMOS) Structure
-
FIG. 1A illustrates a cross-sectional view of a conventional n-type laterally diffused metal oxide semiconductor (LDMOS) fabricated using a conventional complementary metal oxide semiconductor (CMOS) logic foundry technology. The conventional CMOS logic foundry technology fabricates aconventional LDMOS structure 100 onto asubstrate 102 of one conductivity type. Thesubstrate 102 represents a physical material on which the conventional CMOS logic foundry technology fabricates theconventional LDMOS structure 100. For example, in the exemplary embodiment ofFIG. 1A , the conventional CMOS logic foundry technology fabricates theconventional LDMOS structure 100 onto thesubstrate 102 composed with a p-type material. The p-type material includes impurity atoms of an acceptor type, such as, but not limited to, boron or aluminum to provide some examples, that are capable of accepting an electron. Doping thesubstrate 102 with the p-type material causes a carrier hole density in thesubstrate 102 to exceed a carrier electron density. - A first heavily doped region of opposite conductivity as the
substrate 102 represents asource region 104 of theconventional LDMOS structure 100. Generally, implanting a comparatively small number of atoms, approximately -
- refers to an implanting that is low or light. Similarly, implanting a comparatively large number of atoms, approximately
-
- refers to an implanting that is high or heavy. The
source region 104 may optionally include a lightly doped region, often referred to as anLDD region 106. TheLDD region 106 is of substantially similar conductivity as thesource region 104 with a lesser doping density when compared to a doping density of thesource region 104. - A second heavily doped region of opposite conductivity as the
substrate 102 represents adrain region 108 of theconventional LDMOS structure 100. The conventional CMOS logic foundry technology implants thesource region 104 and thedrain region 108 with N+ material to form a first N+ region and a second N+ region corresponding to thesource region 104 and thedrain region 108, respectively. The “+” indicates that the region is implanted with a higher carrier concentration than a region not designated by a “+.” For instance, an N+ region generally has a greater number of excess carrier electrons than an n-type region. A P+ region typically has a greater number of excess carrier holes than a p-type substrate. The conventional CMOS logic foundry may optionally implant theLDD region 106 with n-type material having a doping density less than a doping density of the first N+ region and/or the second N+ region. The n-type material includes impurity atoms of a donor type, such as, but not limited to, phosphorus, arsenic, or antimony to provide some examples, that are capable of donating an electron. Implanting thesource region 104 and/or thedrain region 108 with the n-type material causes the carrier electron density in thesource region 104 and/or thedrain region 108 to exceed a carrier hole density. - A third heavily doped region of opposite conductivity as the
substrate 102 represents agate region 110 of theconventional LDMOS structure 100. The conventional CMOS logic foundry technology heavily implants polycrystalline silicon with the opposite conductivity as thesubstrate 102 to form thegate region 110. For example, the conventional CMOS logic foundry technology implants the polycrystalline silicon with the N+ material to form an N+ poly region corresponding to thegate region 110. - The
conventional LDMOS structure 100 may form a part of an interconnected array of active and passive elements integrated with or deposited on thesubstrate 102 by a continuous series of compatible processes known as an integrated circuit. Theconventional LDMOS structure 100 includes shallow trench isolation (STD regions to provide isolation and/or protection for theconventional LDMOS structure 100 from neighboring active and passive elements integrated with or deposited on thesubstrate 102. Afirst STI region 116 and asecond STI region 120 provides isolation and protection for theconventional LDMOS structure 100. Thefirst STI region 116 is adjacent to a first side of thesource region 104. Likewise, thesecond STI region 120 is adjacent to a first side of thedrain region 108. Thefirst STI region 116 and/or thesecond STI region 120 contact their respective sides of thesource region 104 and/or thedrain region 108. Theconventional LDMOS structure 100 further includes abreakdown STI region 118 to increase a breakdown voltage of theconventional LDMOS structure 100 when compared to a similar LDMOS structure that does not include thebreakdown STI region 118. The conventional CMOS logic foundry technology uses a dielectric material such as SiO2, though any suitable material may be used, to fabricate thefirst STI region 116, thebreakdown STI region 118, and/or thesecond STI region 120. - The
conventional LDMOS structure 100 additionally includes spacers to provide isolation and/or protection between thesource region 104, thedrain region 108, and/or agate region 110. Theconventional LDMOS structure 100 includes afirst spacer 126 between thesource region 104 and thegate region 110 to isolate and/or protect thesource region 104 and thegate region 110. Likewise, theconventional LDMOS structure 100 includes asecond spacer 128 between a top side of thedrain region 108 and a second side of thegate region 110. Thefirst spacer 126 and/or thesecond spacer 128 contact the respective sides of thesource region 104 and/or thedrain region 108. The conventional CMOS logic foundry technology fabricates thesecond spacer 128 and/or thefirst spacer 126 using a dielectric material, such as SiO2, though any suitable material may be used. - The conventional CMOS logic foundry technology accommodates a minimum size, such as a length, width, and/or height for at least some of the regions of the
conventional LDMOS structure 100 and/or a minimum distance between two or more of the regions of theconventional LDMOS structure 100 as defined by one or more minimum design rules (MDRs), such a minimum space interval or a minimum overlap area to provide some examples. These minimum design rules represent limits a resolution of photolithographic processing used by the conventional CMOS logic foundry technology between one or more masks used to manufacture theconventional LDMOS structure 100. For example, as shown inFIG. 1A , thebreakdown STI region 118 includes aminimum width 130 and aminimum height 132. Theminimum width 130 represents a smallest horizontal distance, i.e., width, of thebreakdown STI region 118 that the conventional CMOS logic foundry technology may accommodate. Theminimum height 132 represents a smallest vertical distance, i.e., height, of thebreakdown STI region 118 that the conventional CMOS logic foundry technology may accommodate. For example, theminimum width 130 is approximately 0.11 μm for a 65 nm minimum design rule foundry technology and theminimum height 132 varies from approximately 0.2 μm to approximately 0.25 μm from one 65 nm minimum design rule foundry technology to another. - The
conventional LDMOS structure 100 is described in further detail in U.S. patent application Ser. No. 12/155,628, filed Jun. 6, 2008, entitled “Shallow Trench Isolation (STI) Based Laterally Diffused Metal Oxide Semiconductor (LDMOS)” which is incorporated herein by reference in its entirety. - Operation of the Conventional LDMOS Structure
- Applying a first potential, such as a positive direct current (DC) voltage to provide an example, to the
gate region 110 and applying a second potential, such as a ground potential to provide an example, to thesource region 104 causes a voltage to appear between thegate region 110 and thesource region 104. The first potential on thegate region 110 repels the positively charged carrier holes from a bottom side of thegate region 110 forming achannel region 112. Thechannel region 112 represents a carrier-depletion region populated by a negative charge formed at a bottom side of agate oxide 114 by an electric field. This electric field also attracts carrier electrons from thesource region 104 and thedrain region 108 into thechannel region 112. An n-type region connecting thesource region 104 to thedrain region 108 forms after a sufficient number of carrier electrons have accumulated in thechannel region 112 allowing a current to pass through thechannel region 112. - Specially implanted regions, known as wells, may increase the number of carrier holes and/or carrier electrons located in the
substrate 102. For example, increasing the number of carrier holes in thesubstrate 102 requires a greater number of carrier electrons to form the depletion region. A specially implanted p-type region, known as a p-well 122, is adjacent to a bottom side of thesource region 104, thegate region 110, and thefirst STI region 116. The p-well 122 extends from a first side located under thefirst STI region 116 to a second side located under thegate region 110. The conventional CMOS logic foundry technology may implant thesubstrate 102 with the p-type material to fabricate the p-well 122. Likewise, a specially implanted n-type region, known as an n-well region 124, is located below thedrain region 106, thegate region 110, and thesecond STI region 120. The n-well region 124 extends from a first side located under thesecond STI region 120 to a second side located under thegate region 110. The conventional CMOS logic foundry technology may implant thesubstrate 102 with the n-type material to fabricate the n-well region 124. The second side of the p-well 122 may contact the second side of the n-well region 124. - Doping Profile of the N-Well Region
-
FIG. 1B illustrates a doping profile of an n-well region formed within the conventional n-type LDMOS. In particular,FIG. 1B illustrates the doping profile of the n-well region 124 along a cross section of the conventional n-type LDMOS structure designated by the broken line A-A′. As shown inFIG. 1B , the broken line A-A′ passes through thegate region 110, thegate oxide 114, afirst region 176 of the n-well region 124, asecond region 178 of the n-well region 124, athird region 180 of the n-well region 124, and thesubstrate 102. Thefirst region 176 represents a portion of the n-well region 124 extending from the bottom of thegate oxide 114 until substantially horizontally aligned with the bottom side of thechannel region 112. Thesecond region 178 extends from thefirst region 176 until substantially horizontally aligned with the bottom side of thebreakdown STI region 118. Thethird region 180 extends from thesecond region 178 to a bottom side of the n-well region 124. - As further shown in
FIG. 1B , the conventional CMOS logic foundry technology may lightly implant thesubstrate 102 with a high energy implant having a doping density between approximately -
- and approximately
-
- to form the n-
well region 124. The conventional CMOS logic foundry technology may concentrate the high energy implant into thethird region 180 during formation of the n-well region 124 such that the doping destiny of thefirst region 176 and/or thesecond region 178 is less than the doping destiny of thethird region 180 with thefirst region 176 having the lightest doping density. - Breakdown Voltage of the Conventional LDMOS Structures
- There is a point, known as the breakdown voltage, where the current passing through the
channel region 112 increases uncontrollably resulting in breakdown of theconventional LDMOS structure 100. Examples of breakdown may include avalanche breakdown, punch-through, and/or gate oxide breakdown to provide some examples. A drain to source resistance of theconventional LDMOS structure 100, namely a resistance from thedrain region 108 to thesource region 104, influences the breakdown voltage. For example, the breakdown voltage of a semiconductor device having a higher drain to source resistance is larger when compared to a substantially similar semiconductor device having a lower drain to source resistance. -
FIG. 1C illustrates a cross-sectional view of a drain to source resistance of the conventional n-type LDMOS. More specifically,FIG. 1C illustrates the cross-sectional view of a drain to sourceresistance 160 of theconventional LDMOS structure 100 in an on-state, namely after the sufficient number of carrier electrons have accumulated in thechannel region 112 allowing the current to pass through thechannel region 112. - As illustrated in
FIG. 1C the drain to sourceresistance 160 may be represented by multiple serial drain to source resistances. A first drain to sourceresistance 162 extends substantially horizontally from thesource region 104, or the from theLDD region 106, to the n-well region 124. The first drain to sourceresistance 162 includes thechannel region 112. A second drain to sourceresistance 164 extends substantially vertically from the first drain to sourceresistance 162 to a third drain to sourceresistance 166. The second drain to sourceresistance 164 represents a drain to source resistance of the n-well region 124 along a firstvertical side 168 of thebreakdown STI region 118. The third drain to sourceresistance 166 extends substantially horizontally from the second drain to sourceresistance 164 to a fourth drain to sourceresistance 170. The third drain to sourceresistance 166 represents a drain to source resistance of the n-well region 124 along a firsthorizontal side 172 of thebreakdown STI region 118. The fourth drain to sourceresistance 170 extends substantially vertically from the third drain to sourceresistance 166 to thedrain region 108. The fourth drain to sourceresistance 170 represents a drain to source resistance of the n-well region 124 along a secondvertical side 174 of thebreakdown STI region 118. - Voltage Potential Profile of the Conventional LDMOS Structure
-
FIG. 1D illustrates a voltage potential profile of the conventional n-type LDMOS. More specifically,FIG. 1D illustrates a voltagepotential profile 180 of theconventional LDMOS structure 100 as a function of position and voltage. The voltagepotential profile 180 represents a voltage dissipated by the drain to sourceresistance 160 along the depletion region extending from thesource region 104 to thedrain region 108. The first drain to sourceresistance 162 dissipates from approximately zero volts to approximately a first voltage VDD. The second drain to sourceresistance 164 through the fourth drain to sourceresistance 170 dissipate from approximately the first voltage VDD to approximately a first high voltage HV VDD1, the first high voltage HV VDD1 being greater than the first voltage VDD. - The voltage potential profile of the first drain to source
resistance 162 increases at a first rate m1 as a function of position such that the voltage potential at thesource region 104, or at theLDD region 106, is less than the voltage potential at the second drain to sourceresistance 164. The first rate m1 represents a rate of increase of the voltage potential of the first drain to sourceresistance 162 along the depletion region extending from thesource region 104 to the second drain to sourceresistance 164. - The voltage potential profile of the second drain to source
resistance 164 increases at a second rate m2 as a function of position such that the voltage potential at the second drain to sourceresistance 164 is less than the voltage potential at the third drain to sourceresistance 166. The second rate m2 represents a rate of increase of the voltage potential of the second drain to sourceresistance 164 along the depletion region extending from the first drain to sourceresistance 162 to the third drain to sourceresistance 166. - As shown in
FIG. 1D , the second rate m2 may include a first portion m2A and a second portion m2B. The first portion m2A represents a rate of increase of the voltage potential of the second drain to sourceresistance 164 along the depletion region extending from thegate oxide 114, along a firstvertical side 168 of thebreakdown STI region 118, until substantially horizontally aligned with a bottom side of thechannel region 112. The second portion m2B represents a rate of increase of the voltage potential of the second drain to sourceresistance 164 along the depletion region extending from the first portion m2A, along the firstvertical side 168, to the third drain to sourceresistance 166. The second portion m2B extends substantially vertically from the first portion m2A, along the firsthorizontal side 172, to the third drain to sourceresistance 166. - The voltage potential profile of the third drain to source
resistance 166 increases at a third rate m3 as a function of position such that the voltage potential at the third drain to sourceresistance 166 is less than the voltage potential at the fourth drain to sourceresistance 168. The third rate m3 represents a rate of increase of a voltage potential of the third drain to sourceresistance 166 along the depletion region extending from the second drain to sourceresistance 164, along the firsthorizontal side 172, to the fourth drain to sourceresistance 170. - The voltage potential profile of the fourth drain to source
resistance 170 increases at a fourth rate m4 as a function of position such that the voltage potential at the fourth drain to sourceresistance 170 is less than the voltage potential at thedrain region 108. The fourth rate m4 represents a rate of increase of a voltage potential of the fourth drain to sourceresistance 170 along the depletion region extending from the third drain to sourceresistance 166, along a secondvertical side 174 of thebreakdown STI region 118, to thedrain region 108. - Fabrication of a First Laterally Diffused Metal Oxide Semiconductor (LDMOS) Structure According to a First Exemplary Embodiment
-
FIG. 2A illustrates a cross-sectional view of a first n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a first exemplary embodiment. ALDMOS structure 200 may be characterized as including a lesser drain to source resistance when compared to the drain to source resistance of theconventional LDMOS structure 100. TheLDMOS structure 200 includes a modified breakdown STI region to effectively reduce the drain to source resistance of theLDMOS structure 200 when compared to theconventional LDMOS structure 100. This decrease in the drain to source resistance of theLDMOS structure 200 further increases the breakdown voltage of theLDMOS structure 200 when compared to theconventional LDMOS structure 100. More specifically, thebreakdown STI region 118 of theconventional LDMOS structure 100 increases the drain to source resistance of theconventional LDMOS structure 100, thereby increasing the breakdown voltage of theconventional LDMOS structure 100. Thebreakdown STI region 118, however, restricts the current passing from the source region to the drain region. The modified breakdown STI region inFIG. 2A reduces this restriction from thebreakdown STI region 118 while maintaining the benefits of the increase in breakdown voltage. As a result, more current may pass from the source region to the drain region of theLDMOS structure 200, thereby further increasing the break down voltage of theLDMOS structure 200 from that of theconventional LDMOS structure 100. A metal oxide semiconductor (CMOS) logic foundry technology fabricates theLDMOS structure 200 in a substantially similar manner as theconventional LDMOS structure 100 as described above. Therefore, only differences between theLDMOS structure 200 and theconventional LDMOS structure 100 are to be described in further detail. - The
LDMOS structure 200 includes a modifiedbreakdown STI region 202 to decrease the drain to source resistance of theLDMOS structure 200 when compared to the drain to source resistance of theconventional LDMOS structure 100 while further increasing the breakdown voltage when compared to theconventional LDMOS structure 100 as described above. The CMOS logic foundry technology fabricates the modifiedbreakdown STI region 202 between thesource region 104 and thedrain region 108 within the n-well region 124. In particular, the CMOS logic foundry technology fabricates the modifiedbreakdown STI region 202 adjacent to thedrain region 108 whereby at least some of the modifiedbreakdown STI region 202 is positioned below thesecond spacer 128. - As shown in an exploded
view 204 ofFIG. 2A , the modifiedbreakdown STI region 202 includes atop edge 206, abottom edge 208, a firstslanted edge 210, and a secondslanted edge 212. Thetop edge 206, thebottom edge 208, the firstslanted edge 210, and the secondslanted edge 212 are configured to form a quadrilateral, such as a trapezoid to provide an example. However, those skilled in the relevant art(s) will recognize that other quadrilaterals such as a trapezium, a parallelogram, a rhombus, or a kite to provide some are examples, are possible without departing from the spirit and scope of the present invention. In an exemplary embodiment, thetop edge 206 is characterized as having ahorizontal length 214 of approximately 0.08 μm and thebottom edge 208 is characterized as having ahorizontal length 216 of approximately 0.06 μm. In this exemplary embodiment, the firstslanted edge 210 and the secondslanted edge 212 are configured and arranged such that avertical length 218 of the modifiedbreakdown STI region 202 is between approximately 0.30 μm and approximately 0.35 μm. In another exemplary embodiment, thebottom edge 208 is characterized as having ahorizontal length 216 of approximately 0 μm. In this exemplary embodiment, thetop edge 206, thebottom edge 208, the firstslanted edge 210, and the secondslanted edge 212 are configured and arranged to form a triangle. - As further shown in exploded
view 204, the firstslanted edge 210 connects a first end of thetop edge 206 to a first end of thebottom edge 208, whereas the secondslanted edge 212 connects a second end of thetop edge 206 to a second end of thebottom edge 208. As a result of thehorizontal length 214 of thetop edge 206 being greater than thehorizontal length 216 of thebottom edge 208, the firstslanted edge 210 and the secondslanted edge 212 may each be characterized as having a slope m1 and m2, respectively, greater than zero. This slope of the firstslanted edge 210 and the secondslanted edge 212 allows for more current to pass from thesource region 104 to thedrain region 108, thereby reducing the drain to source resistance of theLDMOS structure 200 when compared to theconventional LDMOS structure 100. As a result, the breakdown voltage of theLDMOS structure 200 is increased when compared to the breakdown voltage of theconventional LDMOS structure 100. - Breakdown Voltage of the First LDMOS Structure
-
FIG. 2B illustrates a cross-sectional view of a drain to source resistance of the first n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically,FIG. 2B illustrates the cross-sectional view of a drain to sourceresistance 220 of theLDMOS structure 200 in an on-state, namely after the sufficient number of carrier electrons have accumulated in thechannel region 112 allowing the current to pass through thechannel region 112. - As illustrated in
FIG. 2B , the drain to sourceresistance 220 may be represented by multiple serial drain to source resistances. A first drain to sourceresistance 222 extends substantially horizontally from thesource region 104, or the from theLDD region 106, to the n-well region 124. The first drain to sourceresistance 222 includes thechannel region 112. A second drain to sourceresistance 224 extends substantially vertically from the first drain to sourceresistance 222 to a third drain to sourceresistance 226. The second drain to sourceresistance 224 represents a drain to source resistance of the n-well region 124 along the firstslanted edge 210 of the modifiedbreakdown STI region 202. The third drain to sourceresistance 226 extends substantially horizontally from the second drain to sourceresistance 224 to a fourth drain to sourceresistance 228. The third drain to sourceresistance 226 represents a drain to source resistance of the n-well region 124 along thebottom edge 208 of the modifiedbreakdown STI region 202. The fourth drain to sourceresistance 228 extends substantially vertically from the third drain to sourceresistance 226 to thedrain region 108. The fourth drain to sourceresistance 228 represents a drain to source resistance of the n-well region 124 along the secondslanted edge 212 of the modifiedbreakdown STI region 202. - Voltage Potential Profile of the First LDMOS Structure
-
FIG. 2C illustrates a voltage potential profile of the first n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically,FIG. 2C illustrates a voltagepotential profile 230 of theLDMOS structure 200 as a function of position and voltage. The voltagepotential profile 230 represents a voltage dissipated by the drain to sourceresistance 220 along the depletion region extending from thesource region 104 to thedrain region 108. The first drain to sourceresistance 222 dissipates from approximately zero volts to approximately a first voltage VDD. The second drain to sourceresistance 224 through the fourth drain to sourceresistance 228 dissipate from approximately the first voltage VDD to approximately a second high voltage HV VDD2, the second high voltage HV VDD2 being greater than the first high voltage HV VDD1. - The voltage potential profile of the first drain to source
resistance 222 increases at a first rate m11 as a function of position such that the voltage potential at thesource region 104, or at theLDD region 106, is less than the voltage potential at the second drain to sourceresistance 224. The first rate m11 represents a rate of increase of the voltage potential of the first drain to sourceresistance 222 along the depletion region extending from thesource region 104 to the second drain to sourceresistance 224. - The voltage potential profile of the second drain to source
resistance 224 increases at a second rate m2 as a function of position such that the voltage potential at the second drain to sourceresistance 224 is less than the voltage potential at the third drain to sourceresistance 226. The second rate m22 represents a rate of increase of the voltage potential of the second drain to sourceresistance 224 along the depletion region extending from the first drain to sourceresistance 222 to the third drain to sourceresistance 226. - As shown in
FIG. 2C , the second rate m22 may include a first portion m22A and a second portion m22B. The first portion m22A represents a rate of increase of the voltage potential of the second drain to sourceresistance 224 along the depletion region extending from thegate oxide 114, along the firstslanted edge 210, until substantially horizontally aligned with a bottom side of thechannel region 112. The first portion m22A is less than the first portion m2A as described inFIG. 1D . More specifically, the firstslanted edge 210 allows for more current to pass from thesource region 104 to thedrain region 108, thereby reducing the drain to source resistance of theLDMOS structure 200 when compared to theconventional LDMOS structure 100. As a result, the voltage potential of the second drain to sourceresistance 224 along the depletion region in this region within the n-well region 124 increases at a rate that is less than a similar region with the n-well region 124 of theconventional LDMOS structure 100. - The second portion m22B represents a rate of increase of the voltage potential of the second drain to source
resistance 224 along the depletion region extending from the first portion m22A, along the firstslanted edge 210, to the third drain to sourceresistance 226. The second portion m22B extends substantially vertically from the first portion m22A, along the firstslanted edge 210, to the third drain to sourceresistance 226. - The voltage potential profile of the third drain to source
resistance 226 increases at a third rate m33 as a function of position such that the voltage potential at the third drain to sourceresistance 226 is less than the voltage potential at the fourth drain to sourceresistance 228. The third rate m33 represents a rate of increase of a voltage potential of the third drain to sourceresistance 226 along the depletion region extending from the second drain to sourceresistance 224, along thebottom edge 208, to the fourth drain to sourceresistance 228. - The voltage potential profile of the fourth drain to source
resistance 228 increases at a fourth rate m44 as a function of position such that the voltage potential at the fourth drain to sourceresistance 228 is less than the voltage potential at thedrain region 108. The fourth rate m4 represents a rate of increase of a voltage potential of the fourth drain to sourceresistance 228 along the depletion region extending from the third drain to sourceresistance 226, along the secondhorizontal side 174, to thedrain region 108. - Fabrication of a Second Laterally Diffused Metal Oxide Semiconductor (LDMOS) Structure According to a Second Exemplary Embodiment
-
FIG. 3A illustrates a cross-sectional view of a second n-type LDMOS structure fabricated using a CMOS logic foundry technology according to a second exemplary embodiment. ALDMOS structure 300 may be characterized by a lower drain to source resistance when compared to the drain to source resistance of theLDMOS structure 200. In addition to the modified breakdown STI region as described above, theLDMOS structure 300 includes a modified well region to effectively reduce a drain to source resistance of theLDMOS structure 300 when compared to theLDMOS structure 200. The modified well region further increases the breakdown voltage of theLDMOS structure 300 when compared to theLDMOS structure 200. More specifically, the modifiedbreakdown STI region 202 of theLDMOS structure 200 decreases the drain to source resistance of theLDMOS structure 200, thereby increasing the breakdown voltage of theLDMOS structure 200. The n-well region 124, however, restricts the current passing from the source region to the drain region. The modified well region reduces this restriction from the n-well region 124 while maintaining the benefits of the increase in breakdown voltage. As a result, more current may pass from the source region to the drain region of theLDMOS structure 300, thereby further increasing the break down voltage of theLDMOS structure 300 from that of theLDMOS structure 200. The CMOS logic foundry technology fabricates theLDMOS structure 300 in a substantially similar manner as theLDMOS structure 200 described above. Therefore, only differences between theLDMOS structure 300 and theLDMOS structure 200 are to be described in further detail. - The
LDMOS structure 300 includes a modifiedbreakdown STI region 302 and a modified n-well region 304 to decrease a drain to source resistance of theLDMOS structure 300 when compared to the drain to source resistance of theLDMOS structure 200 while further increasing the breakdown voltage as compared to theLDMOS structure 200 as described above. The modifiedbreakdown STI region 302 is substantially similar to the modifiedbreakdown STI region 202 as described above. - As shown in exploded
view 310, the modified n-well region 304 includes a first heavily doped region of substantially similar conductivity as the modified n-well region 304 to form a heavily dopedwell region 306. The CMOS logic foundry technology fabricates the heavily dopedwell region 306 between the modifiedbreakdown STI region 302 and thesource region 104 below thegate region 110 within the modified n-well region 304. The CMOS logic foundry technology may implant the heavily dopedwell region 306 with N+ material to form an N+ region. The CMOS logic foundry may optionally include a second lightly doped region of substantially similar conductivity as the modified n-well region 304 to form an optional lightlydoped well region 308. The CMOS logic foundry technology fabricates the optional lightlydoped well region 308 between the modifiedbreakdown STI region 302 and thesource region 104 below thegate region 110 within the modified n-well region 304. The CMOS logic foundry technology may form the optional lightlydoped well region 308 to have a horizontal length that is greater than a horizontal length of the heavily dopedwell region 306 as shown inFIG. 3A . Alternatively, the CMOS logic foundry technology may form the optional lightlydoped well region 308 to have the horizontal length that is less than or equal to the horizontal length of the heavily dopedwell region 306. The CMOS logic foundry may optionally implant the optional lightlydoped well region 308 with n-type material having a doping density less than a doping density of the first heavily dopedwell region 306. Implanting the modified n-well region 304 with the heavily dopedwell region 306 and/or the optional lightlydoped well region 308 increases the number of carrier electrons located in the modified n-well region 304 when compared to the n-well region 124. This reduces the drain to source resistance of theLDMOS structure 300 when compared to theLDMOS structure 200, thereby increasing the breakdown voltage of theLDMOS structure 300 when compared to the breakdown voltage of theconventional LDMOS structure 200. - Doping Profile of the Modified N-Well Region
-
FIG. 3B illustrates a first doping profile of a modified n-well region formed within the n-type LDMOS structure according a first exemplary embodiment of the present invention. In particular,FIG. 3B illustrates the doping profile of the modified n-well region 304 without the optional lightlydoped well region 308 along a cross section of the n-type LDMOS structure 300 as designated by the broken line A-A′. As shown inFIG. 3B , the broken line A-A′ passes through thegate region 110, thegate oxide 114, afirst region 312 of the modified n-well region 304, asecond region 314 of the modified n-well region 304, athird region 316 of the modified n-well region 304, and thesubstrate 102. Thefirst region 312 represents a portion of the modified n-well region 304 extending from the bottom of thegate oxide 114 until substantially horizontally aligned with a bottom side of the heavily dopedwell region 306. Thesecond region 314 extends from thefirst region 312 until substantially horizontally aligned with the bottom side of the modifiedbreakdown STI region 302. Thethird region 316 extends from thesecond region 314 to a bottom side of the modified n-well region 304. Thesecond region 314 and thethird region 316 are substantially similar to thesecond region 178 and thethird region 180, respectively, as described above. Therefore, only thefirst region 312 is to be described in further detail below. - As further shown in
FIG. 3B , the CMOS logic foundry technology may heavily implant the modified n-well region 304 with a high energy implant having a doping density of approximately -
- to form the heavily doped
well region 306. The CMOS logic foundry technology may concentrate the high energy implant into thefirst region 312 during formation of the modified n-well region 304 such that the doping destiny of thefirst region 312 is greater than thesecond region 314 and thethird region 316. -
FIG. 3C illustrates a second doping profile of a modified n-well region formed within the n-type LDMOS structure according to a second exemplary embodiment of the present invention. In particular,FIG. 3C illustrates the doping profile of the modified n-well region 304 including the optional lightlydoped well region 308 along a cross section of the n-type LDMOS structure 300 as designated by the broken line A-A′. As shown inFIG. 3C , the broken line A-A′ passes through thegate region 110, thegate oxide 114, afirst region 318 of the modified n-well region 304, asecond region 314 of the modified n-well region 304, athird region 316 of the modified n-well region 304, and thesubstrate 102. Thefirst region 318 represents a portion of the modified n-well region 304 extending from the bottom of thegate oxide 114 until substantially horizontally aligned with a bottom side of the heavily dopedwell region 306. Thesecond region 314 extends from thefirst region 318 until substantially horizontally aligned with the bottom side of the modifiedbreakdown STI region 302. Thethird region 316 extends from thesecond region 314 to a bottom side of the modified n-well region 304. Thesecond region 314 and thethird region 316 are substantially similar to thesecond region 178 and thethird region 180, respectively, as described above. Therefore, only thefirst region 318 is to be described in further detail below. - As further shown in
FIG. 3C , the CMOS logic foundry technology may heavily implant the modified n-well region 304 with the high energy implant to form the heavily dopedwell region 306 in a substantially similar manner as described above inFIG. 3B . The CMOS logic foundry technology may implant the modified n-well region 304 with a second high energy implant having a doping density of approximately -
- to form the optional lightly
doped well region 308. Implanting the modified n-well region 304 with the optional lightlydoped well region 308 in this manner increases the doping density of the modified n-well region 304 from approximately -
- as described in
FIG. 3B , to approximately -
- at an interface between the bottom side of a
gate oxide 114 and thefirst region 318. As a result, the optional lightlydoped well region 308 increases the breakdownvoltage LDMOS structure 300 when compared to the breakdown voltage of theLDMOS structure 300 without the optional lightlydoped well region 308. - Breakdown Voltage of the First LDMOS Structure
-
FIG. 3D illustrates a cross-sectional view of a drain to source resistance of the second n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically,FIG. 3D illustrates the cross-sectional view of a drain to sourceresistance 320 of theLDMOS structure 300 in an on-state, namely after the sufficient number of carrier electrons have accumulated in thechannel region 112 allowing the current to pass through thechannel region 112. - As illustrated in
FIG. 3D , the drain to sourceresistance 320 may be represented by multiple serial drain to source resistances. A first drain to sourceresistance 322 extends substantially horizontally from thesource region 104, or the from theLDD region 106, to the modified n-well region 304. The first drain to sourceresistance 322 includes thechannel region 112. A second drain to sourceresistance 324 extends substantially vertically from the first drain to sourceresistance 322 to a third drain to sourceresistance 326. The second drain to sourceresistance 324 represents a drain to source resistance of the modified n-well region 304 along a first slanted edge of the modifiedbreakdown STI region 302. The third drain to sourceresistance 326 extends substantially horizontally from the second drain to sourceresistance 324 to a fourth drain to sourceresistance 328. The third drain to sourceresistance 326 represents a drain to source resistance of the modified n-well region 304 along a bottom edge of the modifiedbreakdown STI region 302. The fourth drain to sourceresistance 328 extends substantially vertically from the third drain to sourceresistance 326 to thedrain region 108. The fourth drain to sourceresistance 328 represents a drain to source resistance of the modified n-well region 304 along the secondslanted edge 212 of the modifiedbreakdown STI region 302. - Voltage Potential Profile of the First LDMOS Structure
-
FIG. 3E illustrates a voltage potential profile of the second n-type LDMOS structure according to an exemplary embodiment of the present invention. More specifically,FIG. 3E illustrates a voltagepotential profile 330 of theLDMOS structure 300 as a function of position and voltage. The voltagepotential profile 330 represents a voltage dissipated by the drain to sourceresistance 320 along the depletion region extending from thesource region 104 to thedrain region 108. The first drain to sourceresistance 322 dissipates from approximately zero volts to approximately a first voltage VDD. The second drain to sourceresistance 324 through the fourth drain to sourceresistance 328 dissipate from approximately the first voltage VDD to approximately a third high voltage HV VDD3, the third high voltage HV VDD3 being greater than the second high voltage HV VDD2. - The voltage potential profile of the first drain to source
resistance 322 increases at a first rate m111 as a function of position such that the voltage potential at thesource region 104, or at theLDD region 106, is less than the voltage potential at the second drain to sourceresistance 324. The first rate m111 represents a rate of increase of the voltage potential of the first drain to sourceresistance 322 along the depletion region extending from thesource region 104 to the second drain to sourceresistance 324. - The voltage potential profile of the second drain to source
resistance 324 increases at a second rate m222 as a function of position such that the voltage potential at the second drain to sourceresistance 324 is less than the voltage potential at the third drain to sourceresistance 326. The second rate m222 represents a rate of increase of the voltage potential of the second drain to sourceresistance 324 along the depletion region extending from the first drain to sourceresistance 322 to the third drain to sourceresistance 326. - As shown in
FIG. 3E , the second rate m222 may include a first portion m222A and a second portion m222B. The first portion m222A represents a rate of increase of the voltage potential of the second drain to sourceresistance 324 along the depletion region extending from thegate oxide 114, along the firstslanted edge 210, until substantially horizontally aligned with a bottom side of thechannel region 112. The first portion m222A is less than the first portion M22A, as described inFIG. 2C . More specifically, the heavily dopedwell region 306 allows for more current to pass from thesource region 104 to thedrain region 108, thereby further reducing the drain to source resistance of theLDMOS structure 300 when compared to theLDMOS structure 200. As a result, the voltage potential of the second drain to sourceresistance 324 along the depletion region in this region within the modifiedbreakdown STI region 302 increases at a rate that is less than a similar region with the modifiedbreakdown STI region 202 of theLDMOS structure 200. The first portion m222A may be decreased even further by including the optional lightlydoped well region 308. The optional lightlydoped well region 308 further allows for more current to pass from thesource region 104 to thedrain region 108, thereby further reducing the drain to source resistance of theLDMOS structure 300 when compared to theLDMOS structure 200. - The second portion m222B represents a rate of increase of the voltage potential of the second drain to source
resistance 324 along the depletion region extending from the first portion m222A, along the first slanted edge of the modifiedbreakdown STI region 302, to the third drain to sourceresistance 326. The second portion m222B extends substantially vertically from the first portion m222A, along the first slanted edge of the modifiedbreakdown STI region 302, to the third drain to sourceresistance 326. - The voltage potential profile of the third drain to source
resistance 326 increases at a third rate m333 as a function of position such that the voltage potential at the third drain to sourceresistance 326 is less than the voltage potential at the fourth drain to sourceresistance 328. The third rate m333 represents a rate of increase of a voltage potential of the third drain to sourceresistance 326 along the depletion region extending from the second drain to sourceresistance 324, along the bottom edge of theLDMOS structure 300, to the fourth drain to sourceresistance 328. - The voltage potential profile of the fourth drain to source
resistance 328 increases at a fourth rate m444 as a function of position such that the voltage potential at the fourth drain to sourceresistance 328 is less than the voltage potential at thedrain region 108. The fourth rate m4 represents a rate of increase of a voltage potential of the fourth drain to sourceresistance 328 along the depletion region extending from the third drain to sourceresistance 326, along a slanted edge of the modifiedbreakdown STI region 302, to thedrain region 108. - Although the LDMOS structures of the present invention have been described as n-type structures those skilled in the relevant art(s) will recognize that p-type structures may be similarly formed by using p-type material instead of n-type materiel without departing from the spirit and scope of the present invention. These p-type structures may be implanted into a deep n-well region formed within a p-type semiconductor substrate and/or directly implanted into an n-type semiconductor substrate. Additionally, those skilled in the relevant art(s) will recognize that the substrate as described herein may be composed of n-type material without departing from the spirit and scope of the present invention. In this situation, the LDMOS structures of the present invention may be implanted into a deep p-well region formed within the n-type semiconductor substrate.
- While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant art(s) that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. Thus the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (20)
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US8994103B2 (en) | 2013-07-10 | 2015-03-31 | United Microelectronics Corp. | High voltage metal-oxide-semiconductor transistor device and manufacturing method thereof |
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