US20120280356A1 - Uniformly aligned well and isolation regions in a substrate and resulting structure - Google Patents
Uniformly aligned well and isolation regions in a substrate and resulting structure Download PDFInfo
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- US20120280356A1 US20120280356A1 US13/552,695 US201213552695A US2012280356A1 US 20120280356 A1 US20120280356 A1 US 20120280356A1 US 201213552695 A US201213552695 A US 201213552695A US 2012280356 A1 US2012280356 A1 US 2012280356A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Definitions
- This invention generally relates to a semiconductor structure, and more specifically to a semiconductor structure having no edge placement variation of well implants relative to the isolation structure.
- CMOS technologies continue scale smaller and smaller. As a result parasitic bipolar leakages become harder to control.
- well implants are defined using purely lithographics definition done independently from lithographic steps used for defining physical isolation structures. This independence creates inherent variability.
- the following describes a structure and method for alleviating parasitic bipolar leakages in scaled semiconductor technologies.
- the structure has no edge (or boundary) placement variation for edges of implants under shallow trench isolation (STI) areas, in other words, the distance between the edges of the STI and the corresponding edges or boundaries of implanted wells beneath a given STI are substantially equal.
- STI shallow trench isolation
- FIG. 1 is a diagram showing the problem to be solved
- FIG. 2 is demonstrates the various types of parasitic devices which are inadvertently formed
- FIG. 3 is an illustration of the problem and shows advantages offered by the solution
- FIGS. 4A and 4B are each a view of simulation of electrical properties using the prior art solution
- FIG. 5A is a view of an embodiment at a step in a process where a second layer is deposited onto a first substrate.
- FIG. 5B is a top view of an embodiment of the invention at that step in the process, showing second layer after deposition;
- FIG. 6A is a view of an embodiment at another step in the process where a third layer is deposited over the second layer on the substrate.
- FIG. 6B is a top view of this embodiment of the invention and shows the third layer overlaying the second layer on the substrate;
- FIG. 7A illustrates a side view of a structure which has had portions of the top substrate removed using a chemical etch process or other process which provides similar results;
- FIG. 7B illustrates the result from the top view;
- FIG. 8A illustrates a side view of a structure having implants (e.g. n-well, p-well) and an annealing process. The edges or boundaries of the implants are located at a predetermined distances from the planned STI placement;
- FIG. 8B shows a top view of the structure;
- FIG. 9A illustrates a step of depositing a fourth substrate (e.g. nitride) over the second substrate and adjacent to the third substrate and performing a polishing process.
- FIG. 9B illustrates an example top view of the results of the depositing step;
- FIG. 10A illustrates a side view of the structure after removing the third substrate (e.g. Polysilicon).
- FIG. 10B illustrates a top view of the structure.
- the third substrate e.g. Polysilicon
- FIG. 11A shows the structure after an etch process to remove a portion of the first and second substrates (e.g. silicon and oxide);
- FIG. 11B shows a top view of the structure;
- FIG. 12A shows the structure having a fifth film deposited in the shallow trench isolation (STI) areas.
- FIG. 12B shows a top view of the structure at this step in the process;
- FIG. 13A illustrates an example of the structure having a similar distance between a first implant (or doped) region and an STI and a second implant (or doped) region on the other side of the STI;
- FIG. 13B shows a top view of the structure shown in FIG. 13A ;
- FIG. 14 illustrates a flow diagram of an example process used to make the structure
- FIG. 1 illustrates a problematic parasitic effect shown as NPN device 130 in structure 100 .
- NPN device 130 represents a function that occurs when the boundaries between two (or more) implanted (or doped) regions (e.g. Pwell 125 , Nwell 120 , and N+ region 115 ) are touching or very nearly touching.
- the parasitic effect varies depending on the distance between the adjacent doped regions.
- a parasitic effect is created beneath a shallow trench isolation (STI) region 105 at the Nwell 120 and Pwell 125 junction.
- STI shallow trench isolation
- FIG. 3 shows a prior art solution to the parasitics problem as structure 300 .
- Structure 300 is a hyper-abrupt junction varactor having p+-n junctions 315 , cathode contact 335 , anode contact 330 , an N cathode implant region 320 , Nwells 325 a and 325 b , n+ regions 310 a and 310 b , and STIs 305 a - d .
- This figure demonstrates the size of the structure required to avoid generation of the variable parasitic devices.
- FIG. 3A shows “n+ii”, “P&Nii”, and “n+ii” ion implants, which extend into the STI walls 305 for each device.
- the small geometries result in narrow anode widths as shown in FIG. 3A .
- Degradation of an ideality factor is significant for small geometry diodes such as P-n diodes bounded by STIs having implant penetration.
- An ideality factor is a constant adjustment factor used to correct for discrepancies between an ideal PN junction equation and a measured device.
- FIG. 4A shows a simulated degradation of the ideality factor as a function of width.
- Simulated device 1 shown in FIG. 3 has a width of 1 um resulting in an ideality factor of 1.16 or greater.
- Device 2 has a width of 0.5 um and a corresponding ideality factor of between 1.13 and 1.15.
- device 3 has a width of 0.25 um and an ideality factor of less than 1.13. The decreasing widths directly correlate with decreasing ideality factors.
- FIG. 4B shows a simulation plot for a percent capacitance degradation after 25 hours of stress (reverse bias mode) at 4.5V and 140° C. As the varactor width (in um) increases the percent capacitance change approaches 0% after 25 hours of stress. The reliability degradation of the varactor capacitance is directly proportional to the degradation of the ideality factor.
- FIG. 5A shows a side view of a structure 500 having a substrate 510 (for example a layer of silicon such as one used for a wafer), and a film 505 is deposited over substrate 510 (for example a layer of oxide);
- FIG. 5B shows a top view of structure 500 , which shows film 505 deposited over substrate 510 .
- FIG. 7A shows a structure 700 after patterning.
- the process may include, for example a photolithography step and a subsequent etching step.
- the process generates structure 700 which shows a patterned film 610 ;
- FIG. 7B illustrates an example of a top view of structure 700 having the patterned film 610 and the exposed film 505 beneath.
- FIG. 8A shows a side view of a structure 800 having been through processing that includes, for example, a well implant step (e.g. ion implant or doping step) and an annealing step.
- Wells 810 a and 810 b are formed in substrate 510 through, for example, the use of a photomask (not shown) followed by ion implantation, thermal activation, and annealing, and may be, for example, n-wells ( 810 a ) or p-wells ( 810 b ).
- Substrate 510 directly beneath film 610 (and corresponding photomasks) is shielded from the implants.
- the implanting step is followed by an annealing process.
- FIG. 9A shows structure 900 after several processing steps, for example, a nitride deposition step, and a planarization step such as by chemical mechanical planarization (CMP).
- Structures 910 e.g. a nitride
- CMP chemical mechanical planarization
- FIG. 9B shows a top view of structure 900 having structures 910 and film 610 visible.
- FIG. 10A shows structure 1000 after film 610 has been removed.
- the patterned film 610 may be removed using a stripping process, for example;
- FIG. 10B shows a top view of structure 1000 having structures 910 and film 505 .
- FIG. 11A shows a side view of structure 1100 where film 505 and substrate 510 have undergone a stripping and/or etching process (for example a reactive ion etching (RIE) process known to those of ordinary skill in the semiconductor manufacturing field) to generate trenches 1110 a and 1110 b (or depressions, channels, etc.).
- RIE reactive ion etching
- FIG. 11B shows a top view of structure 1100 with exposed substrate 510 , implant areas 810 , and structures 910 .
- FIG. 12A shows a side view of a structure 1200 having a material 1210 a and 1210 b , such as an isolation material (e.g. oxide) for example, deposited over structure 1200 to fill-in trenches 1110 a and 1110 b respectively, thereby creating a shallow trench isolation area.
- a subsequent polishing step e.g. a CMP
- FIG. 12B shows a top view of structure 1200 having structures 910 and the isolation materials 1210 in trenches 1110 visible from the top.
- One edge of trench 1110 b is shown as edge or boundary 1220
- a second boundary of trench 1110 b is shown as boundary 1230 .
- a first and second boundary of trench 1110 a is shown as boundaries 1240 and 1250 respectively.
- FIG. 13B shows a top view of structure 1300 which includes a substrate 510 having the material 1210 a and b (e.g. oxide to create an STI) and at least a first region (e.g. a doped or ion implanted region 810 a ); the trench 1110 a having the first edge or first boundary 1220 (e.g. the side wall or bottom of the trench 1110 b or material 1210 b ); the first region 810 a having a boundary 1320 (e.g. the edge or boundary of the doped region 810 a where it connects to an adjacent substance such as oxide material of 1210 b ); the first region (e.g. the doped region 810 a ) being coupled to (e.g.
- first portion of the trench 1110 b e.g. the bottom and/or side of the trench 1110 b or material 1210 b
- a portion of the boundary 1320 of the first region 810 a is at a predetermined distance W 1 from the first edge 1220 of trench 1110 b (e.g. with respect to the side of the trench and doped regions as shown as W 1 between elements 810 a and 1210 ).
- FIGS. 13A and 13B also show the structure 1300 , having a second region 810 b (e.g. another doped region); the second region 810 b having a second boundary 1330 (e.g. edge) coupled to at least a second portion 1230 of the material 1210 b (e.g. a sidewall and/or bottom of trench 1110 b ) such that a second portion of the second boundary 1330 (e.g. a portion of the boundary around second region 801 b ) is at a second predetermined distance (W 2 ) from a second edge boundary 1230 of trench 1110 b .
- the predetermined distance, W 1 , and the second predetermined distance W 2 are substantially similar (e.g. W 1 is about equal to W 2 ).
- FIGS. 13A and 13B show: the second trench 1110 a having a material 1210 a , a boundary 1240 of trench 1110 a , and a doped region 810 b having a boundary 1340 and adjacent to material 1210 a .
- the distance between boundaries 1240 and 1340 is shown as W 3 .
- Region 810 a further has a second boundary 1350 adjacent to a second boundary 1350 of material 1210 a .
- the distance between boundary 1250 and boundary 1350 is shown as W 4 . Where W 3 and W 4 are substantially equal.
- the predetermined distance from the first edge (W 1 ) and the second predetermined distance (W 2 ), may be within, for example, about 10 nm, 10 nm should not be construed as a limitation however. Likewise, the predetermined distance (W 3 ) is equivalent to within 10 nm of the distance (W 4 ).
- FIG. 14 shows a flow diagram of a method 1400 of making structure 1300 .
- Step 1410 deposit a material film 505 such as a thin oxide for example, over a substrate 510 such as a silicon wafer.
- Step 1420 perform photolithography using a reticle and photoresist, which will shield substrate 510 from unwanted implantation and guide self-alignment of the wells 810 to the STIs 1210 ;
- Step 1425 perform an etch process to remove film 610 where any implants 810 are desired;
- Step 1430 implant in the exposed film 505 to generate implant areas or wells 810 ;
- Step 1435 anneal the subsequent structure to evenly expand areas 810 under film 610 ;
- Step 1440 deposit a structure 910 (e.g. nitride) over film 505 ;
- a structure 910 e.g. nitride
- Step 1445 perform a CMP process to even the thickness of structure 910 with film 610 ;
- Step 1450 remove film 610 (e.g. Polysilicon) using a stripping process
- Step 1455 perform an RIE step on the exposed substrate 510 and film 505 (e.g. oxide and silicon);
- film 505 e.g. oxide and silicon
- Step 1460 optionally, perform additional implants into exposed substrate 510 ;
- Step 1465 deposit a film such as an oxide to generate isolation regions (STIs) 1210 ;
- Step 1470 perform a CMP process to remove overfill of trenches
- Step 1475 remove structures 910 (e.g. nitride).
- Step 1480 perform the process of record (POR). For example, forming FETs and wires to create a functional IC.
- FIGS. 15A and 15B show a side and top view of structure 1500 , respectively.
- Structure 1500 includes a substrate 510 having the material 1210 a and b (e.g. oxide to create an STI) and at least a first region (e.g. a doped or ion implanted region 810 a ); the trench 1110 b having the first edge or first boundary 1220 (e.g. the side wall or bottom of the trench 1110 b or material 1210 b ); the first region 810 a having a boundary 1530 (e.g. the edge or boundary of the doped region 810 a where it connects to an adjacent substance such as oxide material of 1210 b ); the first region (e.g.
- the doped region 810 a being coupled to (e.g. touching) at least a first portion of the trench 1110 b (e.g. the bottom and/or side of the trench 1110 b or material 1210 b ) such that a portion of the boundary 1530 of the first region 810 a is at a predetermined distance W 8 from the first edge 1220 of trench 1110 b (e.g. with respect to the side of the trench and doped regions as shown as W 8 between elements 810 a and 1210 ).
- FIGS. 15A and 15B also show the structure 1500 , having a second region 810 b (e.g. another doped region); the second region 810 b having the same boundary 1530 (e.g. edge) as doped region 810 a and coupled to at least a second portion 1230 of the material 1210 b (e.g. a sidewall and/or bottom of trench 1110 b ) such that a second portion of the boundary 1530 (e.g. a portion of the boundary around second region 801 b ) is at a second predetermined distance (W 7 ) from a second edge boundary 1230 of trench 1110 b .
- the predetermined distance, W 7 , and the second predetermined distance W 8 are substantially similar and coupled (e.g. W 7 is about equal to W 8 ).
- FIGS. 15A and 15B show the second trench 1110 a having a material 1210 a , a boundary 1240 of trench 1110 a , and a doped region 810 b having a boundary 1550 and adjacent to material 1210 a .
- the distance between boundaries 1240 and 1550 is shown as W 6 .
- Region 810 a further has boundary 1550 adjacent and coupled to a boundary 1250 of material 1210 a .
- the distance between boundary 1250 and boundary 1550 is shown as W 5 . Where W 5 and W 6 are substantially equal.
Abstract
Description
- The present application is a divisional application of co-pending U.S. application Ser. No. 12/570,415, filed on Sep. 30, 2009, the contents of which are incorporated by reference in their entirety herein.
- 1. Field of the Invention
- This invention generally relates to a semiconductor structure, and more specifically to a semiconductor structure having no edge placement variation of well implants relative to the isolation structure.
- 2. Background of the Invention
- CMOS technologies continue scale smaller and smaller. As a result parasitic bipolar leakages become harder to control. In traditional process flows, well implants are defined using purely lithographics definition done independently from lithographic steps used for defining physical isolation structures. This independence creates inherent variability.
- The following describes a structure and method for alleviating parasitic bipolar leakages in scaled semiconductor technologies. The structure has no edge (or boundary) placement variation for edges of implants under shallow trench isolation (STI) areas, in other words, the distance between the edges of the STI and the corresponding edges or boundaries of implanted wells beneath a given STI are substantially equal.
-
FIG. 1 is a diagram showing the problem to be solved; -
FIG. 2 is demonstrates the various types of parasitic devices which are inadvertently formed; -
FIG. 3 is an illustration of the problem and shows advantages offered by the solution; -
FIGS. 4A and 4B are each a view of simulation of electrical properties using the prior art solution; -
FIG. 5A is a view of an embodiment at a step in a process where a second layer is deposited onto a first substrate.FIG. 5B is a top view of an embodiment of the invention at that step in the process, showing second layer after deposition; -
FIG. 6A is a view of an embodiment at another step in the process where a third layer is deposited over the second layer on the substrate.FIG. 6B is a top view of this embodiment of the invention and shows the third layer overlaying the second layer on the substrate; -
FIG. 7A illustrates a side view of a structure which has had portions of the top substrate removed using a chemical etch process or other process which provides similar results;FIG. 7B illustrates the result from the top view; -
FIG. 8A illustrates a side view of a structure having implants (e.g. n-well, p-well) and an annealing process. The edges or boundaries of the implants are located at a predetermined distances from the planned STI placement;FIG. 8B shows a top view of the structure; -
FIG. 9A illustrates a step of depositing a fourth substrate (e.g. nitride) over the second substrate and adjacent to the third substrate and performing a polishing process.FIG. 9B illustrates an example top view of the results of the depositing step; -
FIG. 10A illustrates a side view of the structure after removing the third substrate (e.g. Polysilicon).FIG. 10B illustrates a top view of the structure. -
FIG. 11A shows the structure after an etch process to remove a portion of the first and second substrates (e.g. silicon and oxide);FIG. 11B shows a top view of the structure; -
FIG. 12A shows the structure having a fifth film deposited in the shallow trench isolation (STI) areas.FIG. 12B shows a top view of the structure at this step in the process; -
FIG. 13A illustrates an example of the structure having a similar distance between a first implant (or doped) region and an STI and a second implant (or doped) region on the other side of the STI;FIG. 13B shows a top view of the structure shown inFIG. 13A ; -
FIG. 14 illustrates a flow diagram of an example process used to make the structure; and -
FIG. 15A illustrates an example of the structure having a similar distance and coupled between a first implant (or doped) region and an STI and a second implant (or doped) region on the other side of the STI;FIG. 15B shows a top view of the structure shown inFIG. 15A . -
FIG. 1 illustrates a problematic parasitic effect shown asNPN device 130 instructure 100.NPN device 130 represents a function that occurs when the boundaries between two (or more) implanted (or doped) regions (e.g. Pwell 125, Nwell 120, and N+ region 115) are touching or very nearly touching. The parasitic effect varies depending on the distance between the adjacent doped regions. In this example, a parasitic effect is created beneath a shallow trench isolation (STI)region 105 at theNwell 120 andPwell 125 junction. -
FIG. 2 represents the growing complexity of the problem as more devices are manufactured within smaller areas on a wafer (e.g. scaling semiconductor technologies to become smaller and smaller).Structure 200 shows two parasitic devices (npn and pnp) created between anN+ region 225,Pwell 205 andNwell 210; andP+ region 230,Nwell 210 andPwell 205 respectively. -
FIG. 3 shows a prior art solution to the parasitics problem asstructure 300.Structure 300 is a hyper-abrupt junction varactor having p+-n junctions 315,cathode contact 335,anode contact 330, an Ncathode implant region 320,Nwells n+ regions - In conventional processing, STI is defined prior to well implants. In some cases, the implants penetrate the side walls of one or more of STIs 305.
FIG. 3A shows “n+ii”, “P&Nii”, and “n+ii” ion implants, which extend into the STI walls 305 for each device. The small geometries result in narrow anode widths as shown inFIG. 3A . Degradation of an ideality factor is significant for small geometry diodes such as P-n diodes bounded by STIs having implant penetration. An ideality factor is a constant adjustment factor used to correct for discrepancies between an ideal PN junction equation and a measured device. -
FIG. 4A shows a simulated degradation of the ideality factor as a function of width.Simulated device 1 shown inFIG. 3 has a width of 1 um resulting in an ideality factor of 1.16 or greater. Device 2 has a width of 0.5 um and a corresponding ideality factor of between 1.13 and 1.15. Likewise,device 3 has a width of 0.25 um and an ideality factor of less than 1.13. The decreasing widths directly correlate with decreasing ideality factors. -
FIG. 4B shows a simulation plot for a percent capacitance degradation after 25 hours of stress (reverse bias mode) at 4.5V and 140° C. As the varactor width (in um) increases the percent capacitance change approaches 0% after 25 hours of stress. The reliability degradation of the varactor capacitance is directly proportional to the degradation of the ideality factor. -
FIG. 5A shows a side view of astructure 500 having a substrate 510 (for example a layer of silicon such as one used for a wafer), and afilm 505 is deposited over substrate 510 (for example a layer of oxide);FIG. 5B shows a top view ofstructure 500, which showsfilm 505 deposited oversubstrate 510. -
FIG. 6A shows a side view of astructure 600 having a third film 610 (for example a Polysilicon layer) deposited oversubstrate 510;FIG. 6B shows the top view ofstructure 600 having the top layer offilm 610. -
FIG. 7A shows astructure 700 after patterning. The process may include, for example a photolithography step and a subsequent etching step. The process generatesstructure 700 which shows apatterned film 610;FIG. 7B illustrates an example of a top view ofstructure 700 having the patternedfilm 610 and the exposedfilm 505 beneath. -
FIG. 8A shows a side view of astructure 800 having been through processing that includes, for example, a well implant step (e.g. ion implant or doping step) and an annealing step.Wells substrate 510 through, for example, the use of a photomask (not shown) followed by ion implantation, thermal activation, and annealing, and may be, for example, n-wells (810 a) or p-wells (810 b).Substrate 510, directly beneath film 610 (and corresponding photomasks) is shielded from the implants. The implanting step is followed by an annealing process. In this example implant areas 810 expand during the annealing process such that their edges (or boundaries) are located a predetermined distance from the edges offilm 610;FIG. 8B shows a top view ofstructure 800, which showsfilms film 505 and their boundaries are shown as dottedlines film 610 shown by way of illustration as W1, W2, W3, and W4. -
FIG. 9A showsstructure 900 after several processing steps, for example, a nitride deposition step, and a planarization step such as by chemical mechanical planarization (CMP). Structures 910 (e.g. a nitride) is deposited overfilm 505 then a step such as a planarization step for example, is used to polishstructures 910 to be nearly even with the top offilm 610;FIG. 9B shows a top view ofstructure 900 havingstructures 910 andfilm 610 visible. -
FIG. 10A showsstructure 1000 afterfilm 610 has been removed. The patternedfilm 610 may be removed using a stripping process, for example;FIG. 10B shows a top view ofstructure 1000 havingstructures 910 andfilm 505. -
FIG. 11A shows a side view ofstructure 1100 wherefilm 505 andsubstrate 510 have undergone a stripping and/or etching process (for example a reactive ion etching (RIE) process known to those of ordinary skill in the semiconductor manufacturing field) to generatetrenches FIG. 11B shows a top view ofstructure 1100 with exposedsubstrate 510, implant areas 810, andstructures 910. -
FIG. 12A shows a side view of astructure 1200 having a material 1210 a and 1210 b, such as an isolation material (e.g. oxide) for example, deposited overstructure 1200 to fill-intrenches FIG. 12B shows a top view ofstructure 1200 havingstructures 910 and the isolation materials 1210 in trenches 1110 visible from the top. One edge oftrench 1110 b is shown as edge orboundary 1220, a second boundary oftrench 1110 b is shown asboundary 1230. A first and second boundary oftrench 1110 a is shown asboundaries -
FIG. 13B shows a top view ofstructure 1300 which includes asubstrate 510 having the material 1210 a and b (e.g. oxide to create an STI) and at least a first region (e.g. a doped or ion implantedregion 810 a); thetrench 1110 a having the first edge or first boundary 1220 (e.g. the side wall or bottom of thetrench 1110 b ormaterial 1210 b); thefirst region 810 a having a boundary 1320 (e.g. the edge or boundary of the dopedregion 810 a where it connects to an adjacent substance such as oxide material of 1210 b); the first region (e.g. the dopedregion 810 a) being coupled to (e.g. touching) at least a first portion of thetrench 1110 b (e.g. the bottom and/or side of thetrench 1110 b ormaterial 1210 b) such that a portion of theboundary 1320 of thefirst region 810 a is at a predetermined distance W1 from thefirst edge 1220 oftrench 1110 b (e.g. with respect to the side of the trench and doped regions as shown as W1 betweenelements 810 a and 1210). -
FIGS. 13A and 13B also show thestructure 1300, having asecond region 810 b (e.g. another doped region); thesecond region 810 b having a second boundary 1330 (e.g. edge) coupled to at least asecond portion 1230 of thematerial 1210 b (e.g. a sidewall and/or bottom oftrench 1110 b) such that a second portion of the second boundary 1330 (e.g. a portion of the boundary around second region 801 b) is at a second predetermined distance (W2) from asecond edge boundary 1230 oftrench 1110 b. The predetermined distance, W1, and the second predetermined distance W2, are substantially similar (e.g. W1 is about equal to W2). - Likewise,
FIGS. 13A and 13B show: thesecond trench 1110 a having a material 1210 a, aboundary 1240 oftrench 1110 a, and a dopedregion 810 b having aboundary 1340 and adjacent to material 1210 a. The distance betweenboundaries Region 810 a further has asecond boundary 1350 adjacent to asecond boundary 1350 of material 1210 a. The distance betweenboundary 1250 andboundary 1350 is shown as W4. Where W3 and W4 are substantially equal. - The predetermined distance from the first edge (W1) and the second predetermined distance (W2), may be within, for example, about 10 nm, 10 nm should not be construed as a limitation however. Likewise, the predetermined distance (W3) is equivalent to within 10 nm of the distance (W4).
-
FIG. 14 shows a flow diagram of amethod 1400 of makingstructure 1300. Step 1410: deposit amaterial film 505 such as a thin oxide for example, over asubstrate 510 such as a silicon wafer. - Step 1415: deposit a
second film 610, such as Polysilicon, adjacent to film 505; - Step 1420: perform photolithography using a reticle and photoresist, which will shield
substrate 510 from unwanted implantation and guide self-alignment of the wells 810 to the STIs 1210; - Step 1425: perform an etch process to remove
film 610 where any implants 810 are desired; - Step 1430: implant in the exposed
film 505 to generate implant areas or wells 810; - Step 1435: anneal the subsequent structure to evenly expand areas 810 under
film 610; - Step 1440: deposit a structure 910 (e.g. nitride) over
film 505; - Step 1445: perform a CMP process to even the thickness of
structure 910 withfilm 610; - Step 1450: remove film 610 (e.g. Polysilicon) using a stripping process;
- Step 1455: perform an RIE step on the exposed
substrate 510 and film 505 (e.g. oxide and silicon); - Step 1460: optionally, perform additional implants into exposed
substrate 510; - Step 1465: deposit a film such as an oxide to generate isolation regions (STIs) 1210;
- Step 1470: perform a CMP process to remove overfill of trenches;
- Step 1475: remove structures 910 (e.g. nitride); and
- Step 1480: perform the process of record (POR). For example, forming FETs and wires to create a functional IC.
-
FIGS. 15A and 15B show a side and top view ofstructure 1500, respectively.Structure 1500 includes asubstrate 510 having the material 1210 a and b (e.g. oxide to create an STI) and at least a first region (e.g. a doped or ion implantedregion 810 a); thetrench 1110 b having the first edge or first boundary 1220 (e.g. the side wall or bottom of thetrench 1110 b ormaterial 1210 b); thefirst region 810 a having a boundary 1530 (e.g. the edge or boundary of the dopedregion 810 a where it connects to an adjacent substance such as oxide material of 1210 b); the first region (e.g. the dopedregion 810 a) being coupled to (e.g. touching) at least a first portion of thetrench 1110 b (e.g. the bottom and/or side of thetrench 1110 b ormaterial 1210 b) such that a portion of theboundary 1530 of thefirst region 810 a is at a predetermined distance W8 from thefirst edge 1220 oftrench 1110 b (e.g. with respect to the side of the trench and doped regions as shown as W8 betweenelements 810 a and 1210). -
FIGS. 15A and 15B also show thestructure 1500, having asecond region 810 b (e.g. another doped region); thesecond region 810 b having the same boundary 1530 (e.g. edge) as dopedregion 810 a and coupled to at least asecond portion 1230 of thematerial 1210 b (e.g. a sidewall and/or bottom oftrench 1110 b) such that a second portion of the boundary 1530 (e.g. a portion of the boundary around second region 801 b) is at a second predetermined distance (W7) from asecond edge boundary 1230 oftrench 1110 b. The predetermined distance, W7, and the second predetermined distance W8, are substantially similar and coupled (e.g. W7 is about equal to W8). - Likewise,
FIGS. 15A and 15B show thesecond trench 1110 a having a material 1210 a, aboundary 1240 oftrench 1110 a, and a dopedregion 810 b having aboundary 1550 and adjacent to material 1210 a. The distance betweenboundaries Region 810 a further hasboundary 1550 adjacent and coupled to aboundary 1250 of material 1210 a. The distance betweenboundary 1250 andboundary 1550 is shown as W5. Where W5 and W6 are substantially equal. - It should be apparent to one of ordinary skill in the art that the foregoing description and drawings are meant to provide an illustrative example of developing regions that are self-aligned with edges such as edges of shallow trenches and changes to the structure and process may be modified without departing from the spirit and scope of the invention.
Claims (8)
Priority Applications (1)
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US13/552,695 US20120280356A1 (en) | 2009-09-30 | 2012-07-19 | Uniformly aligned well and isolation regions in a substrate and resulting structure |
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US12/570,415 US8232177B2 (en) | 2009-09-30 | 2009-09-30 | Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure |
US13/552,695 US20120280356A1 (en) | 2009-09-30 | 2012-07-19 | Uniformly aligned well and isolation regions in a substrate and resulting structure |
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US12/570,415 Division US8232177B2 (en) | 2009-09-30 | 2009-09-30 | Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure |
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US20120280356A1 true US20120280356A1 (en) | 2012-11-08 |
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US12/570,415 Expired - Fee Related US8232177B2 (en) | 2009-09-30 | 2009-09-30 | Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure |
US13/552,695 Abandoned US20120280356A1 (en) | 2009-09-30 | 2012-07-19 | Uniformly aligned well and isolation regions in a substrate and resulting structure |
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US12/570,415 Expired - Fee Related US8232177B2 (en) | 2009-09-30 | 2009-09-30 | Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure |
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
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US6323103B1 (en) * | 1998-10-20 | 2001-11-27 | Siemens Aktiengesellschaft | Method for fabricating transistors |
JP2002158278A (en) * | 2000-11-20 | 2002-05-31 | Hitachi Ltd | Semiconductor device and manufacturing method and design method thereof |
KR100606935B1 (en) * | 2004-08-23 | 2006-08-01 | 동부일렉트로닉스 주식회사 | method for fabrication Semiconductor device |
US20070293016A1 (en) * | 2006-06-14 | 2007-12-20 | International Business Machines Corporation | Semiconductor structure including isolation region with variable linewidth and method for fabrication therof |
US8125044B2 (en) * | 2007-10-26 | 2012-02-28 | Hvvi Semiconductors, Inc. | Semiconductor structure having a unidirectional and a bidirectional device and method of manufacture |
-
2009
- 2009-09-30 US US12/570,415 patent/US8232177B2/en not_active Expired - Fee Related
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2012
- 2012-07-19 US US13/552,695 patent/US20120280356A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
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US20110073985A1 (en) | 2011-03-31 |
US8232177B2 (en) | 2012-07-31 |
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