US20120256270A1

US20120256270A1 - Dual metal gates using one metal to alter work function of another metal

Info

Publication number: US20120256270A1
Application number: US13/525,840
Authority: US
Inventors: Byoung H. Lee; Sang Ho Bae; Kisik Choi; Rino Choi; Craig Huffman; Prashant Majhi; Jong Hoan Sim; Seung-Chul Song; Zhibo Zhang
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 2008-05-30
Filing date: 2012-06-18
Publication date: 2012-10-11
Also published as: US20090294867A1; US8236686B2

Abstract

Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of currently pending U.S. patent application Ser. No. 12/129,984, filed May 30, 2008. The application identified above is incorporated herein by reference in its entirety for all that it contains in order to provide continuity of disclosure.

BACKGROUND OF THE INVENTION

1. Technical Field
The invention relates generally to semiconductor device fabrication, and more particularly, to methods of forming and a resulting dual metal gate using one metal to alter a work function of another metal.
2. Background Art
Recently, there has been substantial interest in replacing polysilicon gate conductors with metal gate electrodes, so that the gate conductor is a metal in both n-type and p-type metal oxide semiconductor (NMOS and PMOS) devices. In order to provide appropriate threshold voltages in the two types of devices, two different metals are typically needed. In addition, the NMOS and PMOS devices require metals with different work functions. The “work function” of a material is a measurement of how much energy is required to extract an electron from the material by moving the electron in the solid from the Fermi level to the vacuum level, i.e., to outside of the solid.
Conventionally, the two metals used are selected based on their work function and ease of integration in terms of wet and dry etching depending on the method of implementation. There are several different integration schemes used to realize two different metal layers on the same wafer to form dual metal gates. Referring to FIGS. 1A-1E, one of the most simple and well accepted schemes is illustrated. As shown, in a first step, a first metal layer 10 is deposited over a gate dielectric layer 12. Both layers 10, 12 are over a substrate 14 having an NMOS region 20 separated from a PMOS region 22 by a trench isolation 24. First metal layer 10 can be an NMOS metal or a PMOS metal, primarily depending on the ease of removal possible without damaging an underlying gate dielectric layer 12. Usually the NMOS metal (e.g., tantalum silicon nitride (TaSiN), titanium nitride (TiN), tantalum nitride (TaN)) has a work function close to the silicon conduction band and exhibits a tendency towards dissolution in common wet chemistries such as a sulfuric peroxide mixture (SPM), SC1 (NH₄OH:H₂O₂:H₂O mixture) or hydrogen peroxide (H₂0₂). On the other hand, PMOS metals (e.g., ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt)) have work functions close to the silicon valence band and are more inert and difficult to etch in wet chemistries that are typically used in normal microelectronic fabrication. Due to the ease of wet etching, the NMOS metal is usually used as first metal layer 10. The following description is based on that assumption.
Next, as shown in FIGS. 1A-1D, first metal 10 is selectively etched away over a region 20 or 22 (PMOS region 22 as shown) to gate dielectric layer 12. Since the metal removal process attacks typical photo resist materials, a lithography process is used to open PMOS region 20 using (hard) masking material 30 such as an amorphous silicon layer. In particular, a masking material 30 is deposited and a photoresist 32 is patterned and etched, as shown in FIG. 1A. Further, etching patterns masking material 30, as shown in FIG. 1B. As shown in FIG. 1C, masking material 30 is then used to etch first metal 10 over PMOS region 22. Masking material 30 has a high wet etch selectivity with respect to first metal 10 and gate dielectric layer 12. FIG. 1D shows first metal 10 remains over NMOS region 20, but is removed over PMOS region 22 selective to gate dielectric layer 12. As also shown in FIG. 1D, masking material 30 is removed. As shown in FIG. 1E, depositing a second, PMOS metal 40, a capping layer 42 and a polysilicon 44 are next. Conventionally, as shown in FIG. 1E, second metal 40 is deposited both on PMOS region 22 and NMOS region 20, and does not have to be removed over NMOS region 20 because first metal 10 is contacting gate dielectric layer 12 where the work function is primarily determined. Subsequent processing (not shown) patterns the gates from this material.
A number of challenges are presented by these processes. As shown in FIGS. 1C-1D, first metal 10 needs to be selectively removed from PMOS region 22 without damaging the underlying gate dielectric layer 12. Conventional photoresists, however, cannot be used for masking material 30 because first metal 10 etch chemistries, e.g., SPM, SC1, H₂0₂, etc., tend to etch masking material 30 with too high of an etch rate. In addition, when the photoresist masking material 30 is removed using wet etching, it is difficult to preserve first metal 10. Furthermore, as shown in FIG. 1D, gate dielectric layer 12 is continuously exposed to the wet chemical during masking material 30 removal, which may remove significant amounts of gate dielectric layer 12, especially if it contains silicon oxide. As photoresists cannot serve as masking material 30 during first metal 10 etch, other materials such as silicon oxide or silicon nitride have been used with some success. However, removing silicon oxide or silicon nitride based masking materials from gate dielectric layer 12, which may contain the same materials, without damaging layer 12 and first metal 10 is problematic. For example, hydrofluoric (HF) acid is typically used for etching a silicon oxide based mask because it has good selectivity with first metal 10. However, depending on gate dielectric layer 12 material, HF acid could significantly etch gate dielectric layer 12. Silicon nitride based masks have similar problems. It is possible to prevent over etching of gate dielectric layer 12 by using masking material 30 that has a high wet etch selectivity compared to the materials of gate dielectric layer 12 (e.g., silicon oxide or hafnium silicate). However, exposing gate dielectric layer 12 to wet chemicals also can cause various other problems, such as surface roughening, impurity absorption and gate work function modification. Accordingly, it is desirable not to expose gate dielectric layer 12 to the wet chemical during the integration.
The structure as illustrated in FIG. 1E also presents challenges relative to gate formation in subsequent steps (not shown). In particular, the heterogeneous metals (i.e., first metal layer 10 and second metal 40, on the single wafer poses a significant challenge for the gate stack dry etch stopping on gate dielectric layer 12. Since second metal 40 is different on NMOS region 20 and PMOS region 22, the dry etch chemistry has to be different. In order to remove both metals and stop on gate dielectric layer 12, sequential removal of the two metals has to be implemented in the dry etch recipe. This process is particularly difficult because gate dielectric layer 12 on one side of the wafer will be exposed to a dry etch ambient during etching of second metal 40. As a result, penetration of gate dielectric layer 12 is highly likely, leading to recessing of substrate 14. In order to avoid this situation, it is desirable to have the same metal contact gate dielectric layer 12 in both NMOS region 20 and PMOS region 22.
In view of the foregoing, there is a need in the art for a solution to the problems of the related art.

SUMMARY OF THE INVENTION

Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may then remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to damage from the metal etch process.
A first aspect of the invention provides a method of forming dual metal gates, the method comprising: forming a first metal layer on a gate dielectric layer and a second metal layer on the first metal layer, wherein the second metal layer alters a work function of the first metal layer; removing a portion of the second metal layer to expose the first metal layer in a first region; forming a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and forming the dual metal gates in the first and second regions.
A second aspect of the invention provides a method of forming dual metal gates, the method comprising: forming a first metal layer on a gate dielectric layer; forming a second metal layer on the first metal layer, wherein the second metal layer alters a work function of the first metal layer; and forming the dual metal gates without exposing the gate dielectric layer using the first metal layer and the second metal layer.
A third aspect of the invention provides a set of dual metal gates comprising: a first gate including a first metal having a first work function; a second gate including the first metal and a second metal, the second metal altering the first work function to a second work function for the second gate; and a gate dielectric layer under the first gate and the second gate, wherein only the first metal contacts the gate dielectric layer.
The illustrative aspects of the present invention are designed to solve the problems herein described and/or other problems not discussed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:

FIGS. 1A-E show a conventional dual metal gate forming process.

FIGS. 2A-F show a method of forming dual metal gates according to one embodiment of the invention.

It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.

DETAILED DESCRIPTION

Turning to the drawings, FIGS. 2A-2F show one embodiment of a method of forming dual metal gates 100A, 100B (FIG. 2F) (shown without spacers or interconnects). FIG. 1A shows forming a first metal layer 110 on a gate dielectric layer 112 and a second metal layer 140 on first metal layer 110. Both layers are positioned over a gate dielectric layer 112, which is positioned over a substrate 114 having an n-type metal oxide semiconductor (NMOS) region 120 and a p-type metal oxide semiconductor (PMOS) region 122. Regions 120, 122 may be simply designated as for a particular type device, and may not have any structural differences. A trench isolation 124, e.g., of silicon oxide (SiO₂) separates regions 120, 122. Gate dielectric layer 112 may include, for example, hafnium silicate (HfSi), hafnium oxide (HfO₂), zirconium silicate (ZrSiO_x), zirconium oxide (ZrO₂), silicon oxide (SiO₂) or any other material(s) used as a gate dielectric. Layers 110, 112 may be formed using any now known or later developed deposition technique such as chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), atomic layer deposition (ALD), etc.
First metal layer 110 and second metal layer 140 are selected such that second metal layer 140 alters a work function of first metal layer 110. That is, elements from second metal layer 140 are mixed with first metal layer 110 during the subsequent semiconductor device processing, primarily during a high temperature anneal and the final work function of first metal layer is altered from that of the material of first metal layer 110. The effect of changing work functions may be attributed to, for example, the changes in material composition, crystalline structure, interfacial reaction with underlying dielectrics, impurity concentration, and oxygen concentration. As illustrated, first metal layer 110 is ultimately used as a gate material for an NMOS device 100A (FIG. 2F) and second metal layer 140 with first metal layer 110 are used as a gate material for a PMOS device 100B (FIG. 2F). In this situation, first metal layer 110 may include material having a work function within an acceptable range of that typically used for an NMOS device 100A (FIG. 2F). For example, first metal layer 110 may include tantalum carbon (TaC), titanium nitride (TiN), hafnium silicide (HfSi), tantalum (Ta) or tantalum carbon nitride (TaCN). Similarly, second metal layer 140 may include material that when combined with first metal layer 110 has a work function within an acceptable range of that typically used for a PMOS device 100B (FIG. 2F). For example, second metal layer 140 may include: tantalum carbon nitride (TaCN), titanium nitride (TiN) or ruthenium (Ru). Illustrative combinations of first metal layer 110 and second metal layer 140, respectively, may include: titanium nitride (TiN) and tantalum carbon nitride (TaCN), hafnium silicide (HfSi) and titanium silicon nitride (TiSiN), tantalum (Ta) and ruthenium (Ru), tantalum carbon nitride (TaCN) and titanium nitride (TiN). Other combinations may exist and are considered within the scope of the invention. It should also be recognized that the material that constitutes first metal layer 110 may be switched. That is, first metal layer 110 may be used to form PMOS device 100B (FIG. 2F), and second metal layer 140 with first metal layer 110 may be used to form NMOS device 100A (FIG. 2F).
Continuing with the processing, FIGS. 2B-D show a step of removing a portion 150 of second metal layer 140 to expose first metal layer 110 in a first region 152 (FIG. 2D). As illustrated, first region 152 is over NMOS region 120. The removing may include, as shown in FIG. 2B, depositing a masking material 130 and patterning masking material 130 using a photoresist 132. Masking material 130 and photoresist 132 may include any now known or later developed materials compatible for etching second metal layer 140. For example, masking material 130 may include silicon oxide (SiO₂) deposited using tetraethyl orthosilicate (Si(OC₂H₅)₄) (TEOS), armorphous silicon, or other common hard mask material. FIG. 2C shows etching 154 second metal layer 140 to remove portion 150 (FIG. 2B). FIG. 2D shows removing masking material 130 (FIG. 2C), leaving second metal layer 140 over first metal layer 110 over PMOS region 122. Notice that gate dielectric layer 112 is never exposed during this process, i.e., first metal layer 110 remains intact during removal of second metal layer 140.
FIG. 2E shows forming a silicon layer 144 on exposed first metal layer 110 in first region 152 and on second metal layer 140 in a second region 156. Silicon layer 144 may include any type of silicon material typically used for gate stacks, e.g., polysilicon, polysilicon germanium, etc. Silicon layer 144 may be formed using any now known or later developed technique, e.g., CVD.
FIG. 2F shows forming of dual metal gates 100A, 100B in first and second regions. For example, gates 100A, 100B may be patterned and etched. During this process, gate dielectric layer 112 is never exposed to a dry etch ambient during etching of second metal layer 140. Hence, damage to gate dielectric layer 112 and substrate 114 is avoided. That is, dual metal gates 100A, 100B may be formed using first metal layer 110 and second metal layer 140 without exposing gate dielectric layer 112.
One example of implementation is as follows: deposition of 100 Angstroms (Å) ALD of first metal layer 110 (FIG. 2A) in the form of tantalum carbon nitride (TaCN) on 20 Å of gate dielectric layer 112 in the form of hafnium silicate (HfSiO_x). Next, deposition of 100 Å CVD of second metal layer 140 (FIG. 2A) in the form of titanium nitride. Next, deposition of 400 Å of silicon oxide (SiO₂) deposited with tetraethyl orthosilicate (Si(OC₂H₅)₄) (TEOS) masking material 130 (FIG. 2B). Lithography and selective etch of masking material 130 (FIG. 2B) to open it in first region 152 is next, as shown in FIG. 2B, followed by etching second metal layer 140 in first region 152 over NMOS region 120. Masking material 130 (FIG. 2C) is then removed, as shown in FIG. 2D. Conventional processing to form set of dual metal gates 100A, 100B completes the illustrative implementation.
FIG. 2F shows the resulting set of dual metal gates 100A, 100B including a first gate 100A including first metal 110 having a first work function, a second gate 100B including first metal 110 and second metal 140, and gate dielectric layer 112 under first gate 100A and second gate 100B. Here, only first metal 110 contacts gate dielectric layer 112. Second metal 140 alters the first work function of first metal 110 to a second work function usable for second gate 100B.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.

Claims

1. A set of dual metal gates comprising:

a first gate including a first metal having a first work function;

a second gate including the first metal and a second metal, the second metal structured to alter the first work function to a second work function for the second gate; and

a gate dielectric layer under the first gate and the second gate, wherein only the first metal contacts the gate dielectric layer.

2. The dual metal gates of claim 1, wherein one of the dual metal gates is for an n-type metal oxide semiconductor (NMOS) device and the other dual metal gate is for a p-type metal oxide semiconductor (PMOS).

3. The dual metal gates of claim 1, wherein a combination of the first metal and the second metal, respectively, are selected from the group consisting of: titanium nitride (TiN) and tantalum carbon nitride (TaCN), hafnium silicide (HfSi) and titanium silicon nitride (TiSiN), tantalum (Ta) and ruthenium (Ru), tantalum carbon nitride (TaCN) and titanium nitride (TiN).

4. The dual metal gates of claim 1, wherein the first metal includes one of: titanium nitride (TiN), hafnium silicide (HfSi), tantalum (Ta) and tantalum carbon nitride (TaCN), and the second metal includes one of: tantalum carbon nitride (TaCN), titanium nitride (TiN) and ruthenium (Ru).

5. The dual metal gates of claim 1, wherein the gate dielectric layer includes one of: hafnium silicate (HfSiO_x), hafnium oxide (HfO₂), zirconium silicate (ZrSiO_x), zirconium oxide (ZrO₂) and silicon oxide (SiO₂).

6. The dual metal gates of claim 1, wherein the first gate is for an n-type metal oxide semiconductor (NMOS) device.

7. The dual metal gates of claim 6, wherein the second gate is for a p-type metal oxide semiconductor (PMOS) device.

8. The dual metal gates of claim 7, wherein the NMOS device and the PMOS device are separated by a trench isolation region.

9. The dual metal gates of claim 1, further comprising a silicon layer over the first gate and the second gate.

10. The dual metal gates of claim 9, wherein the silicon layer directly contacts the first metal layer in the first gate, and the silicon layer is prevented from contacting the first metal layer in the second gate by the second metal layer.

11. The dual metal gates of claim 10, wherein the silicon layer directly contacts the second metal layer in the second gate.

12. A set of dual metal gates comprising:

a first gate including a first metal having a first work function;

a second gate including the first metal and a second metal, the second metal structured to alter the first work function to a second work function for the second gate;

a gate dielectric layer under the first gate and the second gate, wherein only the first metal contacts the gate dielectric layer; and

a silicon layer over the first gate and the second gate, wherein the silicon layer directly contacts the first metal layer in the first gate, and the silicon layer is prevented from contacting the first metal layer in the second gate by the second metal layer.

13. The dual metal gates of claim 12, wherein one of the dual metal gates is for an n-type metal oxide semiconductor (NMOS) device and the other dual metal gate is for a p-type metal oxide semiconductor (PMOS).

14. The dual metal gates of claim 12, wherein a combination of the first metal and the second metal, respectively, are selected from the group consisting of: titanium nitride (TiN) and tantalum carbon nitride (TaCN), hafnium silicide (HfSi) and titanium silicon nitride (TiSiN), tantalum (Ta) and ruthenium (Ru), tantalum carbon nitride (TaCN) and titanium nitride (TiN).

15. The dual metal gates of claim 12, wherein the first metal includes one of: titanium nitride (TiN), hafnium silicide (HfSi), tantalum (Ta) and tantalum carbon nitride (TaCN), and the second metal includes one of: tantalum carbon nitride (TaCN), titanium nitride (TiN) and ruthenium (Ru).

16. The dual metal gates of claim 12, wherein the gate dielectric layer includes one of: hafnium silicate (HfSiO_x), hafnium oxide (HfO₂), zirconium silicate (ZrSiO_x), zirconium oxide (ZrO₂) and silicon oxide (SiO₂).

17. The dual metal gates of claim 12, wherein the first gate is for an n-type metal oxide semiconductor (NMOS) device.

18. The dual metal gates of claim 17, wherein the second gate is for a p-type metal oxide semiconductor (PMOS) device.

19. The dual metal gates of claim 18, wherein the NMOS device and the PMOS device are separated by a trench isolation region.

20. The dual metal gates of claim 12, wherein the silicon layer directly contacts the second metal layer in the second gate.