US20120254584A1

US20120254584A1 - System and method for identifying tlb entries associated with a physical address of a specified range

Info

Publication number: US20120254584A1
Application number: US13/493,810
Authority: US
Inventors: Guillermo Rozas; Alexander Klaiber; H. Peter Anvin; David Dunn
Original assignee: Individual
Current assignee: Individual
Priority date: 2003-07-10
Filing date: 2012-06-11
Publication date: 2012-10-04
Also published as: US8239656B2; US20080294868A1; US7913058B2; US20050010739A1; US7149872B2; US7380096B1; US20120072697A1

Abstract

A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of and claims priority to U.S. patent application Ser. No. 13/053,955, filed on Mar. 22, 2011, which is a Continuation of and claims priority to U.S. patent application Ser. No. 12/127,768, filed on May 27, 2008 and now issued as U.S. Pat. 7,913,058, which is a Continuation of and claims priority to U.S. patent application Ser. No. 11/449,950, filed on Jun. 8, 2006 and now issued as U.S. Pat. No. 7,380,096, which is a Continuation of and claims priority to U.S. patent application Ser. No. 10/629,031, filed on Jul. 28, 2003 and now issued as U.S. Pat. No. 7,149,872, which claims the benefit of and priority to U.S. Provisional Application No. 60/486,629, filed on Jul. 10, 2003, which are hereby incorporated by reference in their entirety.

FIELD

Embodiments relate to the field of memory management. Specifically, embodiments relate to a system and method for creating TLB entries.

BACKGROUND

SUMMARY

What is needed is a system and method for identifying translation lookaside buffer (TLB) entries that contain a physical address that resides within a predetermined address range. What is also needed is a system and method for allowing the modification of a tentative TLB entry such that the physical address and/or TLB entry attributes (e.g., cacheability) may be altered before the entry is stored in the TLB.
Embodiments may be used within circuitry that is responsible for TLB entry generation and storage. Specifically, there are a number of cases, wherein it is desirable to identify tentative TLB entries that have a physical address falling within a predetermined memory range and take some action in response thereto.
A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. A computer system is also described in accordance with the above described method embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments, together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a logical block diagram of an exemplary embedded computer system in accordance with embodiments.

FIG. 2 is a block diagram of an exemplary tentative TLB entry, a TLB and a plurality of range registers in accordance with an embodiment.

FIG. 3 is a block diagram of an exemplary circuit for creating a TLB entry in a TLB in accordance with an embodiment.

FIG. 4 is a block diagram of an exemplary tentative TLB entry and a modified TLB entry in accordance with an embodiment.

FIG. 5 is a flow diagram of an exemplary process for determining if a tentative TLB has a physical address that falls within an address range specified by a finite number of range registers in accordance with an embodiment.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding. However, it will be recognized by one of ordinary skill in the art that embodiments may be practiced without these specific details.
A system and method for identifying tentative TLB entries comprising a physical address within a specified range is disclosed. Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications, and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims.
Furthermore in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. In other instances, well-known components, circuits, methods, materials, and procedures have not been described in detail so as not to unnecessarily obscure aspects of the disclosure. Embodiments are discussed primarily in the context of a method for identifying TLB entries that have a physical address within a specified address range.
Certain portions of the detailed descriptions of embodiments, which follow, are presented in terms of processes and methods (e.g., processes 500 of FIG. 5). Although specific steps are disclosed herein describing the operations of these processes and methods, such steps are exemplary. That is, embodiments are well suited to performing various other steps or variations of the steps and/or order of steps recited in the flowcharts of the figures herein.
In one embodiment, such processes are carried out by processors and electrical/electronic components under the control of computer readable and computer executable instructions comprising code contained in a computer usable medium. The computer readable and computer executable instructions reside, for example, in code within a computer usable medium and used in the processor, data storage features, memory, registers and other components of a computer system performing the method for maintaining sufficient bandwidth on a network link during failures. However, the computer readable and computer executable instructions may reside in any type of computer readable medium.
Exemplary Memory Design
A typical multiple storage level memory design is characterized by a hierarchy of three levels, including a cache level, a main memory, and a backing storage, such as a disc, flash drive, or other storage medium. A table corresponds to the cache and is managed transparently by hardware for the operating system (OS). The table contains a working set of recently program-referenced localities (e.g., lines) of the main memory.
Caching and paging mechanisms support efficient memory management. In paging, the OS fetches fixed size (e.g., 4,096 bytes) blocks called pages from the backing storage into the main memory as required by the processor (e.g., on demand). Physical memory is divided into page frames of a fixed size. The real (e.g., physical) address is used to access cache and main memory. The least significant 12 bits of the real address apply to a particular location in a page.
The upper bits of a real address apply to the page table, which determines if the corresponding partial page resides within the memory and translates the upper bits if it is present. The page table thus translates a page number into a frame number corresponding to the actual physical location of the associated information within the memory. A page table entry (PTE) associates a page number with a frame number. The page table resides within the memory.
The memory system thus generates a virtual effective address for cached data, translates the virtual address into a “real” address corresponding to its physical address in the main memory, and uses the real address to access the memory system. As the page table which performs the virtual-to-real (and e.g., real-to-virtual) address translations typically reside in the memory, the time such translations require adds to memory latency.
To make the translation process more efficient and thus reduce latency, a translation lookaside buffer (TLB) can be used. Typical TLBs comprise a register system with multiple entries (e.g., 64-256, etc.). Thus, a TLB functions as a fast, small cache within the processor with pointers to memory pages. Several bits comprising a virtual address become an address with the TLB. An entry corresponding to this TLB address points to the memory location.
A TLB entry includes the real address, the real upper portion of the physical memory address, and residual bits of the virtual address that are mapped to the pointed-to memory location. The residual bits are compared to the corresponding bits of the virtual reference so as to ensure selecting the correct entry. The TLB provides real addresses used by the cache by translating virtual addresses provided by the processor into real addresses.
Exemplary Computer System
Referring now to FIG. 1, a block diagram of exemplary computer system 12 is shown. It is appreciated that computer system 12 of FIG. 1 described herein illustrates an exemplary configuration of an operational platform upon which embodiments can be implemented. Nevertheless, other computer systems with differing configurations can also be used in place of computer system 12 within embodiments. For example, computer system 12 could be a server system, a personal computer or an embedded computer system.
Computer system 12 includes an address/data bus 10 for communicating information, a central processor 1 coupled with bus 10 for processing information and instructions, a cache 12 coupled to bus 10 for temporarily storing data, a volatile memory unit 2 (e.g., random access memory, static RAM, dynamic RAM, etc.) coupled with bus 10 for storing information and instructions for central processor 1 and a nonvolatile memory units (e.g., read only memory, programmable FROM, flash memory, EPROM, EEPROM, etc.) coupled with bus 10 for storing static information and instructions for processor 1. Computer system 12 may also contain an optional display device 5 coupled to bus 10 for displaying information to the computer user. Moreover, computer system 12 also includes a data storage device 4 (e.g., disk drive) for storing information and instructions.
Also included in computer system 12 of FIG. 1 is an optional alphanumeric input device 6. Device 6 can communicate information and command selections to central processor 1. Computer system 12 also includes an optional cursor control or directing device 7 coupled to bus 10 for communicating user input information and command selections to central processor 1. Computer system 12 also includes signal communication interface 8, which is also coupled to bus 10, and can be a serial port.
FIG. 2 is a block diagram 200 of an exemplary tentative TLB entry 201, a TLB 206 and a plurality of range registers 210, 211, and 212 in accordance with embodiments. The translation lookaside buffer (TLB) 206 comprises a plurality of TLB entries (e.g., TLB entry 220). In accordance with embodiments, a “tentative” TLB entry is a TLB entry before it is entered into the TLB. In accordance with embodiments, a tentative TLB entry can be created from contents of a page table entry (PTE) or can be supplied from other means. It is appreciated that a PTE can be accessed from many sources, one of which is a page table.
Embodiments provide a system and method for identifying tentative TLB entries that contain or have associated with them a physical page number (e.g., physical address) 202 that falls within in a range specified by range registers. Each of the range registers specifies a unique range of memory addresses. For example, range register 210 specifies a range from x1 to y1. Identifying a tentative TLB entry and modifying the tentative TLB entry before it is entered into the translation lookaside buffer (TLB) can be used to handle special cases where conventional mechanisms for entering TLB entries do not work. Embodiments comprise an architecture that includes a finite number of range registers (e.g., range registers 210, 211, and 212). The range registers specify the address ranges for which an exception can be invoked during the construction and insertion of a tentative TLB entry into a TLB.
In one embodiment, as the tentative TLB entry is constructed, the physical address of the tentative TLB entry is examined to see if it falls within the address range specified by range registers. If a tentative TLB entry has a physical page number (e.g., physical address) that falls within the ranges specified by the range registers, an exception is invoked and modification of the tentative TLB entry can be performed. If the physical address lies outside the predetermined ranges, then the tentative TLB entry can be stored into the TLB without modification.
In one embodiment, the physical page number 202 (e.g., physical address) associated with the tentative TLB entry 201 is compared to the address ranges specified by the range registers 210, 211, and 212. If the physical address is within the address ranges specified by the range registers, an exception is invoked and the physical address and/or an attribute of the tentative TLB entry is modified. Once the tentative TLB entry is modified, the tentative TLB is entered into the translation lookaside buffer 206. In one embodiment, the physical address of the tentative TLB entry is modified. In another embodiment, an attribute (e.g., cacheability) of the tentative TLB entry is modified. Out of range entries are stored in the TLB without modification.
FIG. 3 is a block diagram of an exemplary circuit 300 for creating and inserting a TLB entry in a translation lookaside buffer 350. System 300 includes a fill engine 320 for accessing a PTE 302, constructing a tentative TLB entry 201 and invoking a comparison between the physical address of the tentative TLB entry and a predetermined range of physical memory addresses 335. System 300 also includes a comparator 333 coupled to the fill engine 320 for comparing the physical memory address of the tentative TLB entry 201 and range 335. In one embodiment, comparator 333 may reside in fill engine 320. In another embodiment, the comparator may reside in the range register 335 or may be coupled to fill engine 320 externally.
The comparator 333 compares the physical address and the specified range and then determines a match. System 300 also includes a fix-up handler 340 coupled to the comparator 333 and to the fill engine 320 for handling an exception generated by the comparator 333 in response to the comparator 333 determining that the physical memory address associated with the tentative TLB entry 201 is within the predetermined range 335. In response to the exception, the fix-up handler 340 modifies the physical address and/or an attribute of the tentative TLB entry 201 and creates a modified tentative TLB entry 310. The modified tentative TLB entry 310 is then inserted in the TLB 350 by the fill engine 320. Tentative TLB entries having a physical address outside the ranges are stored in the TLB by the fill engine 320 without modification. It is appreciated that the fix-up handler 340 can be implemented in hardware or software.
FIG. 4 is a block diagram of an exemplary tentative TLB entry and a new (e.g., modified) tentative TLB entry in accordance with embodiments. Tentative TLB entry 201 comprises a physical address and attributes “A” 202. After a match, an exception is invoked by the comparator and the fix-up handler 340 of FIG. 3 modifies an attribute or physical address of the tentative TLB entry according to an implementation of the exception invoked. It is appreciated that the attribute modified by the fix-up handler can be a physical memory address or any other attribute associated with the TLB entry, such as cacheability permissions or read/write permissions. After the tentative TLB entry 201 is modified, a new page table entry 310 is created comprising modified physical address and attributes “B” 406. The modified TLB entry is then inserted in the TLB by the fill handler.
FIG. 5 is a flow diagram of an exemplary process 500 for determining if a tentative TLB entry has a physical address that falls within an address range specified by range registers in accordance with embodiments. It is appreciated that the steps performed in process 500 can be implemented in hardware or software. Process 500 begins with step 502, accessing a physical address associated with a tentative TLB entry. The next step 504 is to invoke a comparison and compare the physical address retrieved in step 502 to a predetermined set of address ranges. A match is determined in step 506.
If the physical address is not within the ranges specified by the range registers, the tentative TLB entry is entered into the TLB in step 510. If the physical address is determined to be within the ranges of the range registers, in step 508, the tentative TLB entry is modified in any way appropriate to that particular use of the range register. Any number of modifications can be performed in step 508, depending on the convention of the range register. Any number of modifications can be performed in step 508, depending on the specific needs of the embodiment.
For example, the physical page number can be modified to a remapped address. Or, in another case, the cacheability of the tentative TLB can be modified by altering an attribute of the tentative TLB entry. In one embodiment, any aspect of the tentative TLB can be modified before it is entered into the TLB. The modifications of the tentative TLB entry can be specific to any number of conditions. Once the tentative TLB is modified, the modified tentative TLB entry is entered into the TLB.
Exemplary Implementations
Embodiments relate to the creation of a TLB entry. Specifically, there are a number of cases where it is desirable to identify and modify TLB entries that have a physical address that resides in a predetermined address range specified by a range register before the TLB entry is stored in the TLB.
One exemplary case occurs when using part of an interrupt controller that is architecturally mapped into the memory address space (e.g., a memory map device) residing at a movable address. One such interrupt controller is an APIC (Advanced Programmable Interrupt Controller). An APIC is a special-purpose integrated circuit that functions as an overall manager in an interrupt driven system. The circuit accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest priority, ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination. The APIC is mapped in memory in a way that does not allow the use of conventional mechanisms for creating a TLB entry if that TLB entry has a physical page number within the range of the APIC.
Another exemplary case regarding an address space is graphics related, such as when using a GART (Graphics Address Remapping Table). A GART is a memory based table that specifies an address range in which physical addresses coming from the processor get remapped to a contiguous range of physical memory. A GART is mapped in a way that does not allow the use of conventional mechanisms for creating a TLB entry if that TLB entry has a physical page number within the range of the GART.
In one embodiment, specific implementations of identifying a TLB entry that resides in a finite memory range are specific to code morphing software (CMS). In one implementation, code-morphing software is designed to translate x86 instructions into VLIW (very long instruction word) instructions for the underlying hardware engine. In one embodiment, identifying tentative TLB entries comprising a physical memory address within a specified memory range improves performance of the code morphing software.
In embodiments, a system and method for identifying a TLB entry with a physical page number that is within a specified range has been described. While the disclosure has been described in particular embodiments, it should be appreciated that the disclosure should not be construed as limited by such embodiments, but rather construed according to the following Claims.
The foregoing descriptions of specific embodiments have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the Claims appended hereto and their equivalents.

Claims

1-20. (canceled)

21. An apparatus comprising:

means for determining whether a physical address of a tentative entry of a translation lookaside buffer is within an address range for identification of an exception; and

means for identifying the exception responsive to the means for determining indicating the physical address of the tentative entry of the translation lookaside buffer is included within the address range.

22. The apparatus of claim 21, further comprising:

means for storing the address range.

23. The apparatus of claim 21, wherein the means for determining comprises:

means for comparing the physical address with the address range to determine whether the physical address is included within the address range.

24. The apparatus of claim 21, further comprising:

means for modifying the tentative entry responsive to the exception identified by the means for identifying.

25. The apparatus of claim 24, wherein the means for modifying comprises:

means for altering the physical address of the tentative entry.

26. The apparatus of claim 24, wherein the means for modifying comprises:

means for altering an attribute of the tentative entry.

27. The apparatus of claim 24, further comprising:

means for storing the modified tentative entry in the translation lookaside buffer.

28. An apparatus comprising:

means for storing an address range; and

means for invoking an exception if a physical address of a tentative entry of a translation lookaside buffer is within the address range.

29. The apparatus of claim 28, further comprising:

means for storing the tentative entry in the translation lookaside buffer responsive to the physical address of the tentative entry being outside of the address range.

30. The apparatus of claim 28, wherein the means for invoking comprises:

31. The apparatus of claim 28, further comprising:

means for modifying the tentative entry responsive to the exception invoked by the means for invoking.

32. The apparatus of claim 31, wherein the means for modifying comprises:

means for altering the physical address of the tentative entry.

33. The apparatus of claim 31, wherein the means for modifying comprises:

means for altering an attribute of the tentative entry.

34. The apparatus of claim 31, further comprising:

35. An apparatus comprising:

means for storing an address range; and

means for modifying a tentative entry of a translation lookaside buffer if a physical address of the tentative entry of the translation lookaside buffer is within the address range.

36. The apparatus of claim 35, further comprising:

37. The apparatus of claim 35, wherein the means for modifying comprises:

means for altering the physical address of the tentative entry.

38. The apparatus of claim 35, wherein the means for modifying comprises:

means for altering an attribute of the tentative entry.

39. The apparatus of claim 35, further comprising:

40. The apparatus of claim 35, wherein the address range is associated with at least one of an advanced programmable interrupt controller (APIC) and a graphics address remapping table (GART).