US20120127010A1 - High-order wide band modulators and multiplying digital-to-analog converters using distributed weighting networks - Google Patents
High-order wide band modulators and multiplying digital-to-analog converters using distributed weighting networks Download PDFInfo
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- H—ELECTRICITY
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- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
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- This disclosure relates generally to a distributed weighting network for electrical signals and, more particularly, to a high speed multiplying digital-to-analog-converter (DAC) that employs a distributed weighting network, and to a high speed, high-order wideband quadrature amplitude modulation (QAM) modulator that employs a distributed weighting network and a summing line.
- DAC digital-to-analog-converter
- QAM quadrature amplitude modulation
- digital modulators are used to encode data onto a carrier wave for transmission.
- modulation formats that can be employed for this purpose.
- One popular modulation format is known as quadrature amplitude modulation (QAM).
- Low-order special cases include binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK).
- QPSK quadrature phase shift keying
- Higher-order special cases include 8PSK, 16PSK, rectangular 16 QAM and 64 QAM, and circular 12/4 QAM.
- high-order modulation formats have been achieved at low and moderate modulation rates using DACs to generate baseband or intermediate-frequency (IF) signals, with additional up-conversion to reach the final carrier frequency for transmission.
- DACs baseband or intermediate-frequency
- both a high-order modulation format and a fast modulation rate are used to provide large data throughput.
- Known QAM modulators of this type have sometimes been assembled from multiple monolithic microwave integrated circuits (MMICs).
- MMICs monolithic microwave integrated circuits
- FIG. 1 is a schematic diagram of a two-way resistor divider summing block
- FIG. 2 is a schematic block diagram of a distributed weighting network
- FIG. 3 is a schematic diagram of a standard R-2R resistor ladder distributed weighting network
- FIG. 4 is a schematic diagram of a modified R-2R resistor ladder distributed weighting network
- FIG. 5 is a schematic diagram of a binary-weighted matched impedance distributed summing line
- FIG. 6 is a schematic block diagram of a high speed multiplying digital-to-analog converter using signal/clock distribution lines in a distributed weighting network
- FIG. 7 is a schematic block diagram of a high-order QAM modulator using dual local oscillator (LO) and clock distribution lines and an in-phase/quadrature phase distributed summing line;
- LO local oscillator
- FIG. 8 is a schematic diagram of a resistor divider network employed in the summing blocks in the modulator shown in FIG. 7 ;
- FIG. 9 is a schematic diagram of a high-order 16 QAM modulator
- FIG. 10 is a rectangular 16 QAM constellation showing the use of binary bit weighting
- FIG. 11 is an 8 PSK constellation for a predistorted 16 QAM modulator showing the use of non-binary bit weighting
- FIG. 12 is a schematic diagram of a 12/4 QAM modulator.
- FIG. 13 is a circular 12/4 QAM constellation showing the use of non-binary bit weighting.
- a distributed summing/splitting network that provides arbitrary weighting factors over large bandwidths and can be fabricated on a single chip.
- the network can achieve uniform binary weighting as a special case, and is an extension of common matched-impedance resistive power combiners/splitters. By cascading N such combiners, N input signals can be combined into a single output signal with various weighting factors.
- the network can also be used as a splitter to obtain N output signals with various weighting factors from a single input signal. Although there are limits as to the ultimate accuracy of the weighting, the network takes advantage of modern lithography techniques by using identical resistors.
- Combining the outputs of identically designed cells with a distributed summing network leverages the ability to fabricate well-matched components, such as sub-cells in a monolithic die, along with well-matched elements in a distributed summing line, to obtain a complex circuit with weighting factors that remain well-controlled over large bandwidths.
- the present disclosure also proposes combining the outputs of individual QPSK modulator cells using a distributed summing network, which results in a high-speed wide bandwidth QAM modulator.
- This configuration naturally has its data inputs on the periphery of the circuit, which dramatically simplifies the signal routing for planar monolithic implementations.
- LO local oscillator
- FIG. 1 is a schematic diagram of a summing circuit 10 including a summing block 12 .
- the summing block 12 can be implemented as a resistor Tee network 14 including resistors R 1 , R 2 and R 3 .
- the summing block 12 also includes three ports having port impedances Z 1 , Z 2 and Z 3 .
- Delay elements 16 may be present at each port and define delays ⁇ 1 , ⁇ 2 and ⁇ 3 .
- the summing block 12 provides matched impedances at all three ports Z 1 , Z 2 and Z 3 .
- a valid impedance match can be obtained at high frequencies with a convenient reduction in the physical size of the circuit.
- Two-way resistor dividers are commonly used to equally split signal power from one source into two loads when loss is acceptable. If all three ports of the summing block 12 have the same impedance Zo, then the three resistors R 1 , R 2 and R 3 all have the resistance Zo/3, and the voltage transfer function from any one port to either of the other two ports is 1 ⁇ 2. If this configuration is used for all of the summing blocks 22 in a distributed summing line 20 as shown in FIG. 2 , then input signals x j (t) are naturally combined with the binary weighting at an output signal y(t). This effect can be used as the basis of a digital-to-analog converter ( FIG. 6 ) or a QAM modulator ( FIG. 7 ).
- the resistor values of the resistor divider network 14 can also be used to predistort the constellation of a QAM modulator.
- the expressions for achieving a particular weighting factor are given by equations (1)-(9).
- R 1 and R 2 are presumed to be equal, and ports 1 and 2 are matched to the same impedance Zo.
- the impedance Z 3 and the insertion loss v to and from ports 2 and 3 are functions of an insertion loss w between ports 1 and 2 .
- resistors are used in the summing blocks discussed herein, other embodiments may use other components, such as capacitors or Wilkinson combiners.
- FIG. 2 is a schematic block diagram of a distributed weighting network 20 .
- the network 20 is a series-connected set of two-way power dividers or summing blocks 22 distributed along a transmission line 24 that combine multiple input signals x j (t) into a single output signal y(t). All of the elements of the network 20 can be fabricated on a single chip.
- the summing blocks 22 include the resistor divider network 14 , as discussed above.
- the distributed weighting network 20 is referred to as a summing line, but it can also be used in the reverse direction as a splitter.
- the weighting network 20 may also include optional attenuators 26 in each branch that control the relative weighting of the signals x j (t) and optional attenuators 28 between the summing blocks 22 that control the relative weighting w j of sets of signals. All of the attenuators 26 and 28 may also incorporate loss-less or lossy impedance-matching between the summing blocks 22 . At RF frequencies, it is desirable to match the port impedance of the various blocks 22 to avoid signal reflections that degrade the output signal y(t).
- the signals x j (t) are applied to port 3 of the summing blocks 22 , where the impedance of all of the ports of the summing blocks 22 would be the same.
- each of the resistors R 1 , R 2 and R 3 are 1 ⁇ 3 of the port impedance, and would convert the signals x j (t) to a certain amplitude. If all of the summing blocks 22 are the same, then the distributed weighting network 20 operates as a digital-to-analog converter where the input bits would be the signals x j (t) applied to port 3 of the summing block 22 , and the summed signals would be the analog conversion of the digital bits.
- each summing block 22 the value of the resistors R 1 , R 2 and R 3 provides the weighting factor w j for that block.
- the signals x j (t) applied to port 3 of the summing blocks 22 get modulated onto a carrier wave that is output as the signal y(t), and is defined by the following equation.
- the distributed weighting network 20 is also scalable to an arbitrary number of the input signals x j (t) by inserting additional sections to the left side of the network 20 .
- this is equivalent to adding least significant bits (LSBs) to obtain higher resolution.
- LSBs least significant bits
- the load resistor Z 0 on the left side of the network 20 terminates the unused backward wave.
- a duplicate signal x N (t) may be used instead of a load resistor. For binary weighted configurations, this feature can be used to set the output signal y(t) to a mid-point.
- the network 20 is distributed because the matched impedances allow for transmission lines of arbitrary length to be used for interconnecting summing blocks without degrading the output signal due to internal signal reflections.
- the distributed weighting network 20 can be used at RF and microwave frequencies to overcome a known weakness of the common R-2R ladder.
- FIGS. 3-5 show that an R-2R ladder is equivalent to a special case of the distributed summing network 20 .
- FIG. 3 shows a common R-2R ladder 36 including resistors R and 2R where the signal/data inputs are ideal voltage sources 38 .
- FIG. 4 shows an R-2R ladder 40 where the 2R resistors are partitioned into two resistors in series with values R/2 and 3R/2, and the R resistors are partitioned into two R/2 resistors. By incorporating each 3R/2 resistor as a source impedance, along with a minor modification in the location of the output signal, the R-2R ladder 40 is equivalent to a binary weighted distributed summing line with no transmission lines.
- FIG. 5 is equivalent to FIG. 4 , but explicitly shows the resistor grouping for the summing blocks 46 of the distributed summing line.
- FIG. 6 is a schematic block diagram of a multiplying digital-to-analog converter (MDAC) 50 that is based on the distributed weighting network 20 .
- the MDAC 50 includes summing blocks 52 distributed along a transmission line 54 and BPSK modulators 56 at port 3 of the summing blocks 52 .
- Each of the summing blocks 52 defines a stage or cell of the MDAC 50
- each modulator 56 defines a binary phase shift keying (BPSK) modulator cell.
- a signal x(t) is applied to a signal line 58 and each of the modulators 56 .
- a clock signal CLK is applied to a clock line 60 and a reclocking circuit 62 in each summing stage of the MDAC 50 and a digital signal or bit D is applied to each reclocking circuit 60 .
- the bits D are clocked into the MDAC 50 where they are multiplied with the signal x(t) in the modulators 56 so that the multiplied signal is amplitude controlled in the summing blocks 52 . Therefore, depending on whether the digital bits D are a 1 bit or a 0 bit, or a 1 bit or a ⁇ 1 bit, will depend on whether they are passed into the summing line 54 or not and how they are summed in the summing blocks 52 .
- the optional analog input signal x(t) on the signal line 58 and the BPSK modulator cells provides the multiplying effect.
- Each digital bit D is assigned to one BPSK modulator cell and the distributed summing line 54 takes care of the combining and signal weighting.
- One key advantage of using identical modulator stages is that identical circuits/layouts can be used to obtain highly matched performance.
- the MDAC 50 has thicker weight lines 54 , 58 , and 60 to indicate the transmission lines that are significant to RF performance. For the purposes of this description, it is assumed that the thin lines are either negligibly short or are parallel paths that are electrically identical.
- the data reclocking circuit 62 shows that the same delay matching concepts can be applied to clock distribution to obtain low data skew for the output signal y(t).
- Data buss reclocking with clock propagation in the same direction as the input signal x(t) achieves zero data skew at the output signal y(t).
- FIG. 7 is a block diagram of a high-order QAM modulator 70 that uses a single distributed summing line 72 including summing blocks 74 .
- One side 76 of the modulator 70 receives in-phase signals I and the other side 78 of the modulator 70 receives quadrature phase signals Q.
- an in-phase local oscillator signal LO I is applied to transmission lines 80 and multipliers 82 on the in-phase side 76 and a quadrature phase local oscillator signal LO Q is applied to a transmission line 84 and multipliers 86 on the quadrature phase side 78 .
- an in-phase clock signal CLK I and in-phase data signals D I are applied to optional reclocking circuits 88 on the in-phase side 76 of the modulator 70
- a quadrature phase clock signal CLK Q and quadrature phase signals D Q are applied to optional reclocking circuits 90 on the quadrature phase side 78 of the modulator 70
- the in-phase signals X I from the multipliers 82 are applied to one port of the summing blocks 74 and the quadrature phase signals X Q from the multipliers 86 are applied to another port of the summing blocks 74 .
- FIG. 8 is a schematic diagram of one implementation of the summing blocks 74 that includes six resistors R 1 and R 2 configured in a power divider network 94 to provide the IQ combining and bit-pair weighting in a single network.
- ports a and b are equivalent in function to ports 1 and 2 of the summing block 10 in FIG. 1 .
- R 1 Z o *(1 ⁇ w )/(1+ w ) (13)
- R 2 Z o *1 ⁇ 2(3 w ⁇ 1)/(1 ⁇ w )(1+ w ) (14)
- topology of the QAM modulator in FIG. 7 provides advantages of the topology of the QAM modulator in FIG. 7 .
- data buss reclocking eliminates the need to provide separate clock signals for every data bit, even for high-speed applications.
- only two clock signals are needed instead of 2N clock signals.
- FIG. 9 is a schematic block diagram of a 16 QAM modulator 100 including a summing line 102 having summing blocks 104 and multipliers 106 of the type shown in FIG. 7 .
- an attenuator L 2 is shown between the summing boxes 104 , for a standard rectangular 16 QAM modulator, the attenuator L 2 is set to OdB.
- the summing line 102 naturally implements binary weighting so no extra attenuators are used.
- the 16 states are equally spaced on a 4-by-4 grid as shown in the constellation of FIG. 10 .
- the signal space of this constellation is defined as:
- FIG. 11 shows an 8 PSK modulator constellation obtained from a predistorted 16 QAM modulator.
- the predistorted 16 QAM modulator would be the same as the modulator 100 shown in FIG. 9 , but with an attenuator value for the attenuator L 2 given in equation (16) below.
- the modulator has 16 states, but with bit-mapping, only the 8 states in the middle amplitude ring are used. Due to quadrant symmetry, those 8 states have the same amplitude. With proper bit weighting, the phases are pre-distorted to be all equally spaced in phase in 45° increments.
- a data mapping Table for this 8PSK constellation is given below.
- the signal space of the constellation can be defined as:
- FIG. 12 is a schematic block diagram of a 64 QAM modulator 110 that can be predistorted to obtain circular 12/4 QAM.
- Multipliers 116 on the in-phase side receive the in-phase signals I and an in-phase local oscillator signal LO I
- multipliers 118 on the quadrature phase side receive quadrature phase signals Q and local oscillator signals LO Q .
- Attenuators K 1,3 and K 1,2 are provided on the in-phase side between the multipliers 116 and the summing blocks 112 and attenuators K Q,3 and K Q,2 are provided on the quadrature phase side between the multipliers 118 and the summing blocks 112 .
- Attenuators L 2 and L 3 are provided in the summing line 112 between the summing blocks 114 , as shown.
- FIG. 13 shows a circular 12/4 QAM constellation using a subset of a 64 QAM constellation. Again, with proper bit mapping and weighting, it is possible to predistort the locations of the constellation points to achieve the desired amplitudes and phases.
- a data mapping Table for a 12/4 QAM from a 64 QAM modulator is given below.
- the values of the attenuators L 2 , L 3 , K I,2 , K I,3 , K Q,2 and K Q,3 can be:
- the values of the attenuators L 2 , L 3 , K I,2 , K I,3 , K Q,2 and K Q,3 can be:
- the signal space of the constellation can be defined as:
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Abstract
Description
- 1. Field of the Disclosure
- This disclosure relates generally to a distributed weighting network for electrical signals and, more particularly, to a high speed multiplying digital-to-analog-converter (DAC) that employs a distributed weighting network, and to a high speed, high-order wideband quadrature amplitude modulation (QAM) modulator that employs a distributed weighting network and a summing line.
- 2. Discussion of the Related Art
- As is well understood in the art, digital modulators are used to encode data onto a carrier wave for transmission. There are many suitable modulation formats that can be employed for this purpose. One popular modulation format is known as quadrature amplitude modulation (QAM). Low-order special cases include binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK). Higher-order special cases include 8PSK, 16PSK, rectangular 16 QAM and 64 QAM, and circular 12/4 QAM.
- For some data links, high-order modulation formats have been achieved at low and moderate modulation rates using DACs to generate baseband or intermediate-frequency (IF) signals, with additional up-conversion to reach the final carrier frequency for transmission. For some other data links, both a high-order modulation format and a fast modulation rate are used to provide large data throughput. Known QAM modulators of this type have sometimes been assembled from multiple monolithic microwave integrated circuits (MMICs). One need in the art is for a high speed, high-order QAM modulator for microwave carrier frequencies that can be fabricated on a single monolithic chip with a small size and low weight and a minimal need for alignment and tuning.
-
FIG. 1 is a schematic diagram of a two-way resistor divider summing block; -
FIG. 2 is a schematic block diagram of a distributed weighting network; -
FIG. 3 is a schematic diagram of a standard R-2R resistor ladder distributed weighting network; -
FIG. 4 is a schematic diagram of a modified R-2R resistor ladder distributed weighting network; -
FIG. 5 is a schematic diagram of a binary-weighted matched impedance distributed summing line; -
FIG. 6 is a schematic block diagram of a high speed multiplying digital-to-analog converter using signal/clock distribution lines in a distributed weighting network; -
FIG. 7 is a schematic block diagram of a high-order QAM modulator using dual local oscillator (LO) and clock distribution lines and an in-phase/quadrature phase distributed summing line; -
FIG. 8 is a schematic diagram of a resistor divider network employed in the summing blocks in the modulator shown inFIG. 7 ; -
FIG. 9 is a schematic diagram of a high-order 16 QAM modulator; -
FIG. 10 is a rectangular 16 QAM constellation showing the use of binary bit weighting; -
FIG. 11 is an 8 PSK constellation for a predistorted 16 QAM modulator showing the use of non-binary bit weighting; -
FIG. 12 is a schematic diagram of a 12/4 QAM modulator; and -
FIG. 13 is a circular 12/4 QAM constellation showing the use of non-binary bit weighting. - The following discussion of the embodiments of the disclosure directed to a distributed weighting network for a digital-to-analog converter or a QAM modulator is merely exemplary in nature, and is in no way intended to limit the scope of the disclosure or its applications or uses.
- As will be discussed in detail below, a distributed summing/splitting network that provides arbitrary weighting factors over large bandwidths and can be fabricated on a single chip is provided. The network can achieve uniform binary weighting as a special case, and is an extension of common matched-impedance resistive power combiners/splitters. By cascading N such combiners, N input signals can be combined into a single output signal with various weighting factors. The network can also be used as a splitter to obtain N output signals with various weighting factors from a single input signal. Although there are limits as to the ultimate accuracy of the weighting, the network takes advantage of modern lithography techniques by using identical resistors.
- Combining the outputs of identically designed cells with a distributed summing network is provided. This leverages the ability to fabricate well-matched components, such as sub-cells in a monolithic die, along with well-matched elements in a distributed summing line, to obtain a complex circuit with weighting factors that remain well-controlled over large bandwidths.
- Combining the outputs of individual BPSK modulator cells using a distributed summing network is also provided, which results in a high-speed wide bandwidth multiplying digital-to-analog converter (MDAC).
- The present disclosure also proposes combining the outputs of individual QPSK modulator cells using a distributed summing network, which results in a high-speed wide bandwidth QAM modulator. This configuration naturally has its data inputs on the periphery of the circuit, which dramatically simplifies the signal routing for planar monolithic implementations.
- Distributing a reference local oscillator (LO) to individual modulator cells using a tapped transmission line that is delay matched to the distributed summing network is provided. This combination can maintain the integrity of the weighting up to microwave frequencies.
- Using monotonic-direction signal routing in the physical layout of a distributed summing network to maintain the integrity of a QAM constellation over extremely wide bandwidths by controlling the phase matching of the various RF signal paths is provided.
- Optionally, the use of parallel bank reclocking, one bank for I data and another bank for Q data, along with tapped transmission lines for the clock distribution lines and monotonic-direction signal routing in the physical layout of the device to achieve extremely low data skew in the complete circuit.
- These techniques can also be used on board and module layouts to lower cost by minimizing the need for three-dimensional layout structures, such as RF connectors, to inject data and clock signals to the individual BPSK or QPSK sub-circuits.
-
FIG. 1 is a schematic diagram of asumming circuit 10 including asumming block 12. Thesumming block 12 can be implemented as aresistor Tee network 14 including resistors R1, R2 and R3. Thesumming block 12 also includes three ports having port impedances Z1, Z2 and Z3.Delay elements 16 may be present at each port and define delays τ1, τ2 and τ3. Thesumming block 12 has a weighting wj, where ⅓≦wj<1. When R1j=R2j, this gives the following relationships. -
- The
summing block 12 provides matched impedances at all three ports Z1, Z2 and Z3. When implemented as a thin-film resistor network 14, a valid impedance match can be obtained at high frequencies with a convenient reduction in the physical size of the circuit. - Two-way resistor dividers are commonly used to equally split signal power from one source into two loads when loss is acceptable. If all three ports of the
summing block 12 have the same impedance Zo, then the three resistors R1, R2 and R3 all have the resistance Zo/3, and the voltage transfer function from any one port to either of the other two ports is ½. If this configuration is used for all of thesumming blocks 22 in adistributed summing line 20 as shown inFIG. 2 , then input signals xj(t) are naturally combined with the binary weighting at an output signal y(t). This effect can be used as the basis of a digital-to-analog converter (FIG. 6 ) or a QAM modulator (FIG. 7 ). - The resistor values of the
resistor divider network 14 can also be used to predistort the constellation of a QAM modulator. The expressions for achieving a particular weighting factor are given by equations (1)-(9). For the remainder of this discussion, R1 and R2 are presumed to be equal, andports port 3, the impedance Z3 and the insertion loss v to and fromports ports - Although resistors are used in the summing blocks discussed herein, other embodiments may use other components, such as capacitors or Wilkinson combiners.
-
FIG. 2 is a schematic block diagram of a distributedweighting network 20. Thenetwork 20 is a series-connected set of two-way power dividers or summingblocks 22 distributed along atransmission line 24 that combine multiple input signals xj(t) into a single output signal y(t). All of the elements of thenetwork 20 can be fabricated on a single chip. The summing blocks 22 include theresistor divider network 14, as discussed above. In some applications, the distributedweighting network 20 is referred to as a summing line, but it can also be used in the reverse direction as a splitter. Theweighting network 20 may also includeoptional attenuators 26 in each branch that control the relative weighting of the signals xj(t) andoptional attenuators 28 between the summingblocks 22 that control the relative weighting wj of sets of signals. All of theattenuators various blocks 22 to avoid signal reflections that degrade the output signal y(t). - The signals xj(t) are applied to
port 3 of the summingblocks 22, where the impedance of all of the ports of the summingblocks 22 would be the same. In a basic distributed weighting network, each of the resistors R1, R2 and R3 are ⅓ of the port impedance, and would convert the signals xj(t) to a certain amplitude. If all of the summingblocks 22 are the same, then the distributedweighting network 20 operates as a digital-to-analog converter where the input bits would be the signals xj(t) applied toport 3 of the summingblock 22, and the summed signals would be the analog conversion of the digital bits. In each summingblock 22, the value of the resistors R1, R2 and R3 provides the weighting factor wj for that block. Thus, the signals xj(t) applied toport 3 of the summingblocks 22 get modulated onto a carrier wave that is output as the signal y(t), and is defined by the following equation. -
y(t)=Σj=1 N(Πj≠1,k=1 j−1 w j ·L k)·L j ·v j ·K j ·x j(t) (10) - The distributed
weighting network 20 is also scalable to an arbitrary number of the input signals xj(t) by inserting additional sections to the left side of thenetwork 20. For binary weighting and DAC applications, this is equivalent to adding least significant bits (LSBs) to obtain higher resolution. There are, however, practical limitations on the final accuracy and precision of any given implementation. - The load resistor Z0 on the left side of the
network 20 terminates the unused backward wave. A duplicate signal xN(t) may be used instead of a load resistor. For binary weighted configurations, this feature can be used to set the output signal y(t) to a mid-point. - The
network 20 is distributed because the matched impedances allow for transmission lines of arbitrary length to be used for interconnecting summing blocks without degrading the output signal due to internal signal reflections. Thus, the distributedweighting network 20 can be used at RF and microwave frequencies to overcome a known weakness of the common R-2R ladder. -
FIGS. 3-5 show that an R-2R ladder is equivalent to a special case of the distributed summingnetwork 20.FIG. 3 shows a common R-2R ladder 36 including resistors R and 2R where the signal/data inputs are ideal voltage sources 38.FIG. 4 shows an R-2R ladder 40 where the 2R resistors are partitioned into two resistors in series with values R/2 and 3R/2, and the R resistors are partitioned into two R/2 resistors. By incorporating each 3R/2 resistor as a source impedance, along with a minor modification in the location of the output signal, the R-2R ladder 40 is equivalent to a binary weighted distributed summing line with no transmission lines.FIG. 5 is equivalent toFIG. 4 , but explicitly shows the resistor grouping for the summingblocks 46 of the distributed summing line. -
FIG. 6 is a schematic block diagram of a multiplying digital-to-analog converter (MDAC) 50 that is based on the distributedweighting network 20. TheMDAC 50 includes summingblocks 52 distributed along atransmission line 54 andBPSK modulators 56 atport 3 of the summing blocks 52. Each of the summingblocks 52 defines a stage or cell of theMDAC 50, and each modulator 56 defines a binary phase shift keying (BPSK) modulator cell. A signal x(t) is applied to asignal line 58 and each of themodulators 56. Further, a clock signal CLK is applied to aclock line 60 and areclocking circuit 62 in each summing stage of theMDAC 50 and a digital signal or bit D is applied to eachreclocking circuit 60. The bits D are clocked into theMDAC 50 where they are multiplied with the signal x(t) in themodulators 56 so that the multiplied signal is amplitude controlled in the summing blocks 52. Therefore, depending on whether the digital bits D are a 1 bit or a 0 bit, or a 1 bit or a −1 bit, will depend on whether they are passed into the summingline 54 or not and how they are summed in the summing blocks 52. - The optional analog input signal x(t) on the
signal line 58 and the BPSK modulator cells provides the multiplying effect. Each digital bit D is assigned to one BPSK modulator cell and the distributed summingline 54 takes care of the combining and signal weighting. One key advantage of using identical modulator stages is that identical circuits/layouts can be used to obtain highly matched performance. - At microwave frequencies, it is necessary to account for signal propagation delay on the various transmission lines. The
MDAC 50 hasthicker weight lines - When the propagation velocity of the
signal line 58 is matched to the distributed summingline 54, then simple geometry can be used to ensure that every path that the signal takes, i.e., through any of thevarious BPSK modulators 56, has the same total propagation delay from the input signal x(t) to the output signal y(t). When the propagation velocities are not the same on the various transmission lines, then other techniques may be necessary to obtain the desired level of delay-matching, such as the line with the fast velocity could be meandered. Matched electrical lengths and parallel transmission lines cause the group delay from the input signal x(t) to the combined output signal y(t)to be independent of the specific signal path. - The
data reclocking circuit 62 shows that the same delay matching concepts can be applied to clock distribution to obtain low data skew for the output signal y(t). Data buss reclocking with clock propagation in the same direction as the input signal x(t) achieves zero data skew at the output signal y(t). - For QAM modulator applications, it is desirable to separately amplitude modulate in-phase and quadrature-phase LO signals, and combine the result. It is possible to use two MDACs, one for the in-phase component I and one for the quadrature-phase component Q as amplitude modulators and combine these two MDAC outputs to obtain the final modulator RF output signal. However, for monolithic implementations, it is preferred to combine pairs of similar weighted I and Q signals with a resistive Tee network before injection into a single summing line.
-
FIG. 7 is a block diagram of a high-order QAM modulator 70 that uses a single distributed summingline 72 including summing blocks 74. Oneside 76 of themodulator 70 receives in-phase signals I and theother side 78 of themodulator 70 receives quadrature phase signals Q. In this embodiment, an in-phase local oscillator signal LOI is applied totransmission lines 80 andmultipliers 82 on the in-phase side 76 and a quadrature phase local oscillator signal LOQ is applied to atransmission line 84 andmultipliers 86 on thequadrature phase side 78. Likewise, an in-phase clock signal CLKI and in-phase data signals DI are applied tooptional reclocking circuits 88 on the in-phase side 76 of themodulator 70, and a quadrature phase clock signal CLKQ and quadrature phase signals DQ are applied tooptional reclocking circuits 90 on thequadrature phase side 78 of themodulator 70. The in-phase signals XI from themultipliers 82 are applied to one port of the summingblocks 74 and the quadrature phase signals XQ from themultipliers 86 are applied to another port of the summing blocks 74. -
FIG. 8 is a schematic diagram of one implementation of the summingblocks 74 that includes six resistors R1 and R2 configured in apower divider network 94 to provide the IQ combining and bit-pair weighting in a single network. In this embodiment of summingblock 74, ports a and b are equivalent in function toports block 10 inFIG. 1 . AnIQ combiner 92 in thenetwork 94 may be independent of a corresponding summingblock 96, but it is preferred to make them symmetric (i.e. R1=R3 and R2=R4) to avoid extra loss from the impedance matching network that would otherwise be required. When theIQ combiners 92 are co-located with the summingblock 96, noadditional port interconnect 98 is needed, and it is not necessary to know the actual impedance of that transmission line. Thus, the in-phase signals I and the quadrature phase signals Q are combined in the summingblock 74 and added together along the summingline 72. The binary weighting (w=½) and arbitrary weighting (⅓≦w<1) values of the resistors R1 and R2 are given below in equations 11-14. -
R 1 =Z o/3 (11) -
R 2 =Z o/3 (12) -
R 1 =Z o*(1−w)/(1+w) (13) -
R 2 =Z o*½(3w−1)/(1−w)(1+w) (14) - Other advantages of the topology of the QAM modulator in
FIG. 7 include that it pushes the natural data inputs to the circuit located at the periphery of the diagram. This simplifies data routing and interfacing, especially for planar monolithic implementations. Further, there is only one on/off-chip quadrature split on the reference LO signal. Thus, it would be relatively inexpensive to tune or otherwise control the quadrature balance of the two LO signals. And data buss reclocking eliminates the need to provide separate clock signals for every data bit, even for high-speed applications. Thus, only two clock signals are needed instead of 2N clock signals. -
FIG. 9 is a schematic block diagram of a 16QAM modulator 100 including a summingline 102 having summingblocks 104 andmultipliers 106 of the type shown inFIG. 7 . For a 16 QAM modulator, there will only need to be two IQ stages to provide the 16 total states. Two bits each are used for the in-phase signals I and the quadrature phase signals Q or 24=16 total states. Although an attenuator L2 is shown between the summingboxes 104, for a standard rectangular 16 QAM modulator, the attenuator L2 is set to OdB. The summingline 102 naturally implements binary weighting so no extra attenuators are used. - The 16 states are equally spaced on a 4-by-4 grid as shown in the constellation of
FIG. 10 . The signal space of this constellation is defined as: -
- Where, Ik,Qk ∈ {+1, −1}, N=2, K0=16.
-
FIG. 11 shows an 8 PSK modulator constellation obtained from a predistorted 16 QAM modulator. The predistorted 16 QAM modulator would be the same as themodulator 100 shown inFIG. 9 , but with an attenuator value for the attenuator L2 given in equation (16) below. Again the modulator has 16 states, but with bit-mapping, only the 8 states in the middle amplitude ring are used. Due to quadrant symmetry, those 8 states have the same amplitude. With proper bit weighting, the phases are pre-distorted to be all equally spaced in phase in 45° increments. A data mapping Table for this 8PSK constellation is given below. -
- The signal space of the constellation can be defined as:
-
- Where, Ik, Qk ∈ {+1, −1}, N=2, K0=√{square root over (10)};
-
k 1=½, k 2=¼*2*(cos φ−sin φ)/(cos φ+sin φ); and - φ=22.5°.
-
Data Mapping Table for 8 PSK from 16 QAM Phase Source Data Mapped Signals State (deg) D1 D2 D3 I1 I2 Q1 Q2 0 22.5 0 0 0 +1 +1 +1 −1 1 67.5 0 0 1 +1 −1 +1 +1 2 112.5 0 1 0 −1 +1 +1 +1 3 157.5 0 1 1 −1 −1 +1 −1 4 202.5 1 0 0 −1 −1 −1 +1 5 247.5 1 0 1 −1 +1 −1 −1 6 292.5 1 1 0 +1 −1 −1 −1 7 337.5 1 1 1 +1 +1 −1 +1 -
FIG. 12 is a schematic block diagram of a 64QAM modulator 110 that can be predistorted to obtain circular 12/4 QAM.Multipliers 116 on the in-phase side receive the in-phase signals I and an in-phase local oscillator signal LOI, and multipliers 118 on the quadrature phase side receive quadrature phase signals Q and local oscillator signals LOQ. Attenuators K1,3 and K1,2 are provided on the in-phase side between themultipliers 116 and the summingblocks 112 and attenuators KQ,3 and KQ,2 are provided on the quadrature phase side between the multipliers 118 and the summing blocks 112. Attenuators L2 and L3 are provided in the summingline 112 between the summingblocks 114, as shown. -
FIG. 13 shows a circular 12/4 QAM constellation using a subset of a 64 QAM constellation. Again, with proper bit mapping and weighting, it is possible to predistort the locations of the constellation points to achieve the desired amplitudes and phases. A data mapping Table for a 12/4 QAM from a 64 QAM modulator is given below. For the 12/4QAM modulator 110, the values of the attenuators L2, L3, KI,2, KI,3, KQ,2 and KQ,3 can be: -
L 2=−1.46 dB (18) -
K I,2 =K Q,2=−1.25 dB (19) -
L3=KI,3=KQ,3=0 dB (20) - Alternately, the values of the attenuators L2, L3, KI,2, KI,3, KQ,2 and K Q,3 can be:
-
L2=L3=0 dB (21) -
K I,2 =K Q,2=−2.71 dB (22) -
K I,3 =K Q,3=−1.46 dB (23) - The signal space of the constellation can be defined as:
-
-
(K 1 , K 2 , K 3)=(10+2d, 4−d, 2+d); and - d=0.196125.
-
Data Mapping Table for 12/4 QAM from 64 QAM Phase Source Data Mapped Signals State Mag. (deg) I1′ I2′ Q1′ Q2′ I1 I2 I3 Q1 Q2 Q3 0 16.97 45 +1 +1 +1 +1 +1 +1 −1 +1 +1 −1 1 16.97 75 +1 −1 +1 +1 +1 −1 −1 +1 +1 +1 2 6.21 45 +1 −1 +1 −1 +1 −1 −1 +1 −1 −1 3 16.97 15 +1 +1 +1 −1 +1 +1 +1 +1 −1 −1 4 16.97 105 −1 +1 +1 +1 −1 +1 +1 +1 +1 +1 5 16.97 135 −1 −1 +1 +1 −1 −1 +1 +1 +1 −1 6 16.97 165 −1 −1 +1 −1 −1 −1 −1 +1 −1 −1 7 6.21 135 −1 +1 +1 −1 −1 +1 +1 +1 −1 −1 8 6.21 −135 −1 +1 −1 +1 −1 +1 +1 +1 +1 +1 9 16.97 −165 −1 −1 −1 +1 −1 −1 −1 −1 +1 +1 10 16.97 −135 −1 −1 −1 −1 −1 −1 +1 −1 −1 +1 11 16.97 −105 −1 +1 −1 −1 −1 +1 +1 −1 −1 −1 12 16.97 −15 +1 +1 −1 +1 +1 +1 +1 −1 +1 +1 13 6.21 −45 +1 −1 −1 +1 +1 −1 −1 −1 +1 +1 14 16.97 −75 +1 −1 −1 −1 +1 −1 −1 −1 −1 −1 15 16.97 −45 +1 +1 −1 −1 +1 +1 −1 −1 −1 +1 - The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion, and from the accompanying drawings and claims, that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claims.
Claims (20)
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US3504360A (en) * | 1966-06-27 | 1970-03-31 | Sanders Associates Inc | Logic circuit producing an analog signal corresponding to an additive combination of digital signals |
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US7903013B2 (en) * | 2008-09-22 | 2011-03-08 | Hitachi, Ltd. | Semiconductor device |
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