US20110299201A1 - SSPC For Parallel Arc Fault Detection in DC Power System - Google Patents
SSPC For Parallel Arc Fault Detection in DC Power System Download PDFInfo
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- US20110299201A1 US20110299201A1 US12/796,275 US79627510A US2011299201A1 US 20110299201 A1 US20110299201 A1 US 20110299201A1 US 79627510 A US79627510 A US 79627510A US 2011299201 A1 US2011299201 A1 US 2011299201A1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
- H02H1/0015—Using arc detectors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/087—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current for dc applications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/44—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to the rate of change of electrical quantities
- H02H3/445—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to the rate of change of electrical quantities of DC quantities
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
Definitions
- the subject matter disclosed herein relates generally to the field of solid state power controllers.
- Solid State Power Controllers are used in power distribution systems in, for example, the aerospace industry, as an alternative to traditional electromechanical circuit breakers.
- An SSPC may distribute power to and protect various electrical loads.
- SSPCs provide relatively fast response time, and may eliminate arcing during turn-off transient and bouncing during turn-on transient.
- SSPCs also do not suffer severe degradation during repeated fault isolation in comparison with electromechanical devices.
- SSPCs may be relatively small in weight and size. SSPCs facilitate advanced protection and diagnostics, allowing for efficient power distribution architectures and packaging techniques.
- Parallel arc faults in a direct current (DC) power distribution system are a significant safety concern.
- Causes of parallel arc faults may include wire chafing, dust buildup, temperature extremes, moisture, and insulation breakdown.
- Integration of arc fault detection in the aircraft electrical systems presents significant challenges, including a lack of ground return wires, which are typically required for ground fault protection, transient load characteristics, and zero-tolerance for nuisance trips.
- a method for detecting a parallel arc fault by a solid state power controller (SSPC) in a direct current (DC) power distribution system includes determining whether an output current slew rate from an output current sensor of the SSPC is above an output current slew rate threshold, and, in the event the output current slew rate is above the output current slew rate threshold: setting a power switch of the SSPC to saturation at a current limit; and determining whether an output voltage of the SSPC is above an output voltage threshold, and, in the event the output voltage is above the output voltage threshold: enabling pulse width modulation of the power switch; and determining whether an output voltage waveform and a output current waveform of the SSPC are consistent with a capacitive load attached to an output of the SSPC, and, in the event the output voltage waveform and the output current waveform are not consistent with the capacitive load: issuing a parallel arc fault status; and turning off the power switch.
- SSPC solid state power controller
- a solid state power controller (SSPC) for detecting a parallel arc fault in a direct current (DC) power distribution system includes an input, the input being connected to a DC power source; a power switch connected to the input; an output connected to the power switch, the output being connected to a DC motor controller and associated capacitive load; an output current sensor; an output voltage sensor; and an SSPC controller, the SSPC controller being configured to determine the presence of a parallel arc fault in the DC power distribution system and control the power switch via a gate drive based on inputs from the output current sensor and the output voltage sensor.
- DC direct current
- FIG. 1 illustrates an embodiment of a DC power distribution system with a parallel arc fault.
- FIG. 2 illustrates an embodiment of an SSPC for parallel arc fault detection in a DC power distribution system.
- FIG. 3 illustrates an embodiment of an SSPC controller.
- FIG. 4 illustrates a method of parallel arc fault detection using an SSPC in a DC power distribution system.
- Embodiments of an SSPC for parallel arc fault detection in a DC power distribution system and a method of parallel arc fault detection are provided, with exemplary embodiments being discussed below in detail.
- SSPC technology may be applied to DC electrical power distribution systems, and more specifically to a method and apparatus for detecting parallel arc faults control in DC power distribution systems that employ motor controllers.
- Use of an SSPC in an aircraft electrical distribution system may facilitate incorporation of parallel arc fault protection of SSPC-fed circuitry and loads.
- FIG. 1 illustrates an embodiment of a DC power distribution system 100 with a parallel arc fault 104 .
- DC power distribution system 100 comprises DC power source 101 , SSPC 102 , feeder bus 103 , reverse flow blocking diode 105 , and motor controller 106 , which is connected to a capacitive DC load.
- parallel arc fault 104 may not be extinguished without disconnecting the DC power source 101 .
- the reverse flow blocking diode 105 is not present in order to enable regenerative energy storage, which may improve aircraft fuel efficiency in embodiments in which DC power distribution system 100 is located in an aircraft.
- the energy stored in a DC link capacitor of the capacitive load connected to the motor controller 106 may contribute to arc fault 104 in embodiments in which reverse flow blocking diode 105 is not present.
- FIG. 2 illustrates an embodiment of an SSPC 200 for arc fault detection, which may comprise SSPC 102 of FIG. 1 .
- SSPC 200 receives input power at power input 201 from DC source 101 of FIG. 1 , and powers motor controller 106 of FIG. 1 via power switch 209 (which is controlled by SSPC controller 207 via gate drive 208 ) and power output 213 .
- SSPC controller 207 controls the gate-source voltage (V GS ) and On/Off of power switch 209 via gate drive 208 based on information from input voltage sensor 202 , output voltage sensor 211 , current sensor 210 , temperature sensor 206 , and data communication bus 212 .
- Temperature sensor 206 allows SSPC controller 207 to protect SSPC 200 from overheating during operation.
- SSPC 200 may announce an overtemperature trip and disable gate drive 208 .
- SSPC controller 207 may comprise a DSP-based controller in some embodiments.
- the power switch 209 performs solid-state contactor functions and may comprise a silicon carbide (SiC) junction gate field effect transistor (JFET) in some embodiments, which may have relatively low insertion loss and a relatively fast switching response.
- the internal modules and sensors comprising SSPC 200 are powered by DC control power input 203 via internal power supply 204 and internal power supply output 205 .
- V GS gate-source voltage
- FIG. 3 illustrates an embodiment of an SSPC controller 300 , which may comprise the SSPC controller 207 of FIG. 2 .
- Input 301 receives the SSPC input voltage (V dc — in ) from input voltage sensor 202 of FIG. 2 ;
- input 302 receives the SSPC output voltage (V dc — out ) from output voltage sensor 211 of FIG. 2 , and
- input 303 receives the SSPC output current (I dc — out ) from current sensor 210 of FIG. 2 .
- Gate drive 208 of FIG. 2 receives V GS and On/Off commands for power switch 209 from DSP controller 312 via outputs 313 and 314 .
- the input values from each of inputs 301 - 303 are first sent through signal conditioning blocks 304 A-C, respectively.
- Signal conditioning block 304 A converts V dc — in from input 301 into a scaled signal to be used by the DSP controller 312 after low pass filter 305 .
- the cutoff frequency of low pass filter 305 may be approximately 20 Hz.
- the DSP controller 312 enables operation of SSPC 200 if the input from input 201 is within a normal operating range per DC bus specifications; otherwise, SSPC 200 may be disabled.
- Signal conditioning block 304 B converts V dc — out from input 302 into a scaled signal to be used in the DSP controller 312 after low pass filter 306 .
- the cutoff frequency of low pass filter 306 may be approximately 20 Hz.
- the DSP controller 312 uses the conditioned V dc — out signal in decision making block 404 (discussed below with respect to FIG. 4 ).
- the conditioned V dc — out value from signal conditioning block 304 B is also sent via high pass filter 307 and waveform analyzer 310 to DSP controller 312 .
- the high pass filter 307 and waveform analyzer 310 act to detect non-stationary changes in V dc — out .
- the cutoff frequency of high pass filter 307 may be approximately 20 Hz.
- the waveform analyzer 310 may comprise a set of band pass filters with a bandwidth of up to 100 kHz in some embodiments.
- the DSP controller 312 compares the frequency spectrum of V dc — out with a steady state components associated with the capacitive load 106 in block 407 (discussed below with respect to FIG. 4 ).
- Signal conditioning block 304 C converts I dc — out from input 303 into a scaled signal to be used by the DSP controller 312 after slew rate detector 308 .
- the parallel arc fault detection method of FIG. 4 uses the rate of change information from slew rate detector 308 of I dc — out as compared with a threshold value in block 402 (discussed below with respect to FIG. 4 ).
- High pass filter 309 and waveform analyzer 311 act to detect non-stationary changes in the I dc — out .
- the cutoff frequency of high pass filter 309 may be approximately 20 Hz.
- the waveform analyzer 311 may comprise a set of band pass filters with the bandwidth of up to about 100 kHz.
- the DSP controller 312 compares the frequency spectrum of I dc — out with a steady state components associated with the capacitive load 106 in block 407 (discussed below with respect to FIG. 4 ).
- FIG. 4 illustrates a method for parallel arc fault detection that may be implemented in DSP control 312 of FIG. 3 .
- the SSPC operates normally, with the power switch 209 being turned-on, and the gate-source voltage (V GS ) set to a maximum value (3 Vdc in some embodiments) to allow minimum on-resistance of power switch 209 .
- V GS gate-source voltage
- the V GS of power switch 209 is set saturate the power switch 209 at a reduced voltage level and corresponding current limit in block 403 .
- the saturation current limit may be selected based on the current rating of the load connected to motor controller 106 of FIG. 1 , to avoid significant reduction of the performance of the load during parallel arc fault detection.
- Flow then proceeds to block 404 .
- it is determined if V dc — out (from low pass filter 306 ) is less than a threshold level; this determination may be made within a specified time period.
- V dc — out is determined to be above the threshold level in block 404 , V GS is returned to its maximum value for normal operation of power switch 209 in block 406 , and flow then proceeds to end at block 412 . If V dc — out is less than the threshold level in block 404 , pulse width modulation of power switch 209 at a specified switching frequency with a 50% duty cycle is enabled in block 405 , and flow proceeds to block 407 . In block 407 , it is determined if the waveforms from waveform analyzers 310 and 311 are consistent with the capacitive load connected to motor controller 106 of FIG. 1 , for example, the waveforms may comprise rectangular voltage and triangular current waveforms.
- waveforms from waveform analyzers 310 and 311 are determined to be consistent with the capacitive load in block 407 , then, in block 408 , pulse width modulation of switch 209 is disabled in block 408 , V GS is returned to its maximum value for normal operation of power switch 209 in block 409 , and flow proceeds to end at block 412 . If the waveforms from waveform analyzers 310 and 311 are determined to be not consistent with the capacitive load in block 407 , “parallel arc fault” status is set in block 410 , and power switch 209 is turned off (opened) in block 411 .
- the length of time to detect and confirm a parallel arc fault using method 400 may be limited based on the length of time that power switch 209 may operate at saturation before failure, to ensure acceptable load performance for the load attached to motor controller 106 of FIG. 1 during arc fault detection.
- the technical effects and benefits of exemplary embodiments include relatively fast detection and stopping of parallel arc faults while avoiding nuisance trips by an SSPC in a DC power distribution system.
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- Emergency Protection Circuit Devices (AREA)
- Electric Propulsion And Braking For Vehicles (AREA)
- Direct Current Feeding And Distribution (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
- The subject matter disclosed herein relates generally to the field of solid state power controllers.
- Solid State Power Controllers (SSPCs) are used in power distribution systems in, for example, the aerospace industry, as an alternative to traditional electromechanical circuit breakers. An SSPC may distribute power to and protect various electrical loads. In comparison to electromechanical devices, SSPCs provide relatively fast response time, and may eliminate arcing during turn-off transient and bouncing during turn-on transient. SSPCs also do not suffer severe degradation during repeated fault isolation in comparison with electromechanical devices. SSPCs may be relatively small in weight and size. SSPCs facilitate advanced protection and diagnostics, allowing for efficient power distribution architectures and packaging techniques.
- Parallel arc faults in a direct current (DC) power distribution system, such as an aircraft power distribution system, are a significant safety concern. Causes of parallel arc faults may include wire chafing, dust buildup, temperature extremes, moisture, and insulation breakdown. Integration of arc fault detection in the aircraft electrical systems presents significant challenges, including a lack of ground return wires, which are typically required for ground fault protection, transient load characteristics, and zero-tolerance for nuisance trips.
- According to one aspect of the invention, a method for detecting a parallel arc fault by a solid state power controller (SSPC) in a direct current (DC) power distribution system includes determining whether an output current slew rate from an output current sensor of the SSPC is above an output current slew rate threshold, and, in the event the output current slew rate is above the output current slew rate threshold: setting a power switch of the SSPC to saturation at a current limit; and determining whether an output voltage of the SSPC is above an output voltage threshold, and, in the event the output voltage is above the output voltage threshold: enabling pulse width modulation of the power switch; and determining whether an output voltage waveform and a output current waveform of the SSPC are consistent with a capacitive load attached to an output of the SSPC, and, in the event the output voltage waveform and the output current waveform are not consistent with the capacitive load: issuing a parallel arc fault status; and turning off the power switch.
- According to another aspect of the invention, a solid state power controller (SSPC) for detecting a parallel arc fault in a direct current (DC) power distribution system includes an input, the input being connected to a DC power source; a power switch connected to the input; an output connected to the power switch, the output being connected to a DC motor controller and associated capacitive load; an output current sensor; an output voltage sensor; and an SSPC controller, the SSPC controller being configured to determine the presence of a parallel arc fault in the DC power distribution system and control the power switch via a gate drive based on inputs from the output current sensor and the output voltage sensor.
- Other aspects, features, and techniques of the invention will become more apparent from the following description taken in conjunction with the drawings.
- Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
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FIG. 1 illustrates an embodiment of a DC power distribution system with a parallel arc fault. -
FIG. 2 illustrates an embodiment of an SSPC for parallel arc fault detection in a DC power distribution system. -
FIG. 3 illustrates an embodiment of an SSPC controller. -
FIG. 4 illustrates a method of parallel arc fault detection using an SSPC in a DC power distribution system. - Embodiments of an SSPC for parallel arc fault detection in a DC power distribution system and a method of parallel arc fault detection are provided, with exemplary embodiments being discussed below in detail. SSPC technology may be applied to DC electrical power distribution systems, and more specifically to a method and apparatus for detecting parallel arc faults control in DC power distribution systems that employ motor controllers. Use of an SSPC in an aircraft electrical distribution system may facilitate incorporation of parallel arc fault protection of SSPC-fed circuitry and loads.
-
FIG. 1 illustrates an embodiment of a DCpower distribution system 100 with aparallel arc fault 104. DCpower distribution system 100 comprisesDC power source 101, SSPC 102,feeder bus 103, reverseflow blocking diode 105, and motor controller 106, which is connected to a capacitive DC load. Once started,parallel arc fault 104 may not be extinguished without disconnecting theDC power source 101. In some embodiments, the reverseflow blocking diode 105 is not present in order to enable regenerative energy storage, which may improve aircraft fuel efficiency in embodiments in which DCpower distribution system 100 is located in an aircraft. The energy stored in a DC link capacitor of the capacitive load connected to the motor controller 106 may contribute toarc fault 104 in embodiments in which reverseflow blocking diode 105 is not present. -
FIG. 2 illustrates an embodiment of an SSPC 200 for arc fault detection, which may comprise SSPC 102 ofFIG. 1 . SSPC 200 receives input power atpower input 201 fromDC source 101 ofFIG. 1 , and powers motor controller 106 ofFIG. 1 via power switch 209 (which is controlled by SSPCcontroller 207 via gate drive 208) andpower output 213.SSPC controller 207 controls the gate-source voltage (VGS) and On/Off ofpower switch 209 viagate drive 208 based on information frominput voltage sensor 202,output voltage sensor 211,current sensor 210,temperature sensor 206, anddata communication bus 212.Temperature sensor 206 allows SSPCcontroller 207 to protect SSPC 200 from overheating during operation. If the temperature data fromtemperature sensor 206 is over a predetermined threshold, SSPC 200 may announce an overtemperature trip and disablegate drive 208. SSPCcontroller 207 may comprise a DSP-based controller in some embodiments. Thepower switch 209 performs solid-state contactor functions and may comprise a silicon carbide (SiC) junction gate field effect transistor (JFET) in some embodiments, which may have relatively low insertion loss and a relatively fast switching response. The internal modules and sensors comprising SSPC 200 are powered by DCcontrol power input 203 viainternal power supply 204 and internalpower supply output 205. During normal operation, thepower switch 209 is turned-on, and the gate-source voltage (VGS) ofpower switch 209 is set to a maximum value (about 3 volts DC in some embodiments) to enable minimum on-resistance ofpower switch 209. -
FIG. 3 illustrates an embodiment of anSSPC controller 300, which may comprise theSSPC controller 207 ofFIG. 2 .Input 301 receives the SSPC input voltage (Vdc— in) frominput voltage sensor 202 ofFIG. 2 ;input 302 receives the SSPC output voltage (Vdc— out) fromoutput voltage sensor 211 ofFIG. 2 , andinput 303 receives the SSPC output current (Idc— out) fromcurrent sensor 210 ofFIG. 2 .Gate drive 208 of FIG. 2 receives VGS and On/Off commands forpower switch 209 fromDSP controller 312 viaoutputs signal conditioning blocks 304A-C, respectively. -
Signal conditioning block 304A converts Vdc— in frominput 301 into a scaled signal to be used by theDSP controller 312 afterlow pass filter 305. The cutoff frequency oflow pass filter 305 may be approximately 20 Hz. TheDSP controller 312 enables operation of SSPC 200 if the input frominput 201 is within a normal operating range per DC bus specifications; otherwise, SSPC 200 may be disabled. -
Signal conditioning block 304B converts Vdc— out frominput 302 into a scaled signal to be used in theDSP controller 312 afterlow pass filter 306. The cutoff frequency oflow pass filter 306 may be approximately 20 Hz. TheDSP controller 312 uses the conditioned Vdc— out signal in decision making block 404 (discussed below with respect toFIG. 4 ). The conditioned Vdc— out value fromsignal conditioning block 304B is also sent viahigh pass filter 307 andwaveform analyzer 310 toDSP controller 312. Thehigh pass filter 307 andwaveform analyzer 310 act to detect non-stationary changes in Vdc— out. The cutoff frequency ofhigh pass filter 307 may be approximately 20 Hz. Thewaveform analyzer 310 may comprise a set of band pass filters with a bandwidth of up to 100 kHz in some embodiments. TheDSP controller 312 compares the frequency spectrum of Vdc— out with a steady state components associated with the capacitive load 106 in block 407 (discussed below with respect toFIG. 4 ). -
Signal conditioning block 304C converts Idc— out frominput 303 into a scaled signal to be used by theDSP controller 312 afterslew rate detector 308. The parallel arc fault detection method ofFIG. 4 uses the rate of change information fromslew rate detector 308 of Idc— out as compared with a threshold value in block 402 (discussed below with respect toFIG. 4 ).High pass filter 309 andwaveform analyzer 311 act to detect non-stationary changes in the Idc— out. The cutoff frequency ofhigh pass filter 309 may be approximately 20 Hz. Thewaveform analyzer 311 may comprise a set of band pass filters with the bandwidth of up to about 100 kHz. TheDSP controller 312 compares the frequency spectrum of Idc— out with a steady state components associated with the capacitive load 106 in block 407 (discussed below with respect toFIG. 4 ). -
FIG. 4 illustrates a method for parallel arc fault detection that may be implemented inDSP control 312 ofFIG. 3 . Inblock 401, the SSPC operates normally, with thepower switch 209 being turned-on, and the gate-source voltage (VGS) set to a maximum value (3 Vdc in some embodiments) to allow minimum on-resistance ofpower switch 209. Inblock 402, it is determined if the slew rate of Idc— out (from slew rate detector 308) is greater than a threshold level. If the Idc— out value is not greater than the threshold level inblock 402, flow ends atblock 412. If the Idc out value is greater than the threshold level inblock 402, the VGS ofpower switch 209 is set saturate thepower switch 209 at a reduced voltage level and corresponding current limit inblock 403. The saturation current limit may be selected based on the current rating of the load connected to motor controller 106 ofFIG. 1 , to avoid significant reduction of the performance of the load during parallel arc fault detection. Flow then proceeds to block 404. Inblock 404, it is determined if Vdc— out (from low pass filter 306) is less than a threshold level; this determination may be made within a specified time period. If Vdc— out is determined to be above the threshold level inblock 404, VGS is returned to its maximum value for normal operation ofpower switch 209 inblock 406, and flow then proceeds to end atblock 412. If Vdc— out is less than the threshold level inblock 404, pulse width modulation ofpower switch 209 at a specified switching frequency with a 50% duty cycle is enabled inblock 405, and flow proceeds to block 407. Inblock 407, it is determined if the waveforms fromwaveform analyzers FIG. 1 , for example, the waveforms may comprise rectangular voltage and triangular current waveforms. If the waveforms fromwaveform analyzers block 407, then, inblock 408, pulse width modulation ofswitch 209 is disabled inblock 408, VGS is returned to its maximum value for normal operation ofpower switch 209 inblock 409, and flow proceeds to end atblock 412. If the waveforms fromwaveform analyzers block 407, “parallel arc fault” status is set in block 410, andpower switch 209 is turned off (opened) inblock 411. The length of time to detect and confirm a parallel arcfault using method 400 may be limited based on the length of time thatpower switch 209 may operate at saturation before failure, to ensure acceptable load performance for the load attached to motor controller 106 ofFIG. 1 during arc fault detection. - The technical effects and benefits of exemplary embodiments include relatively fast detection and stopping of parallel arc faults while avoiding nuisance trips by an SSPC in a DC power distribution system.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. While the description of the present invention has been presented for purposes of illustration and description, it is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications, variations, alterations, substitutions, or equivalent arrangement not hereto described will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. Additionally, while various embodiment of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be seen as limited by the foregoing description, but is only limited by the scope of the appended claims.
Claims (18)
Priority Applications (2)
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US12/796,275 US8320090B2 (en) | 2010-06-08 | 2010-06-08 | SSPC for parallel arc fault detection in DC power system |
EP11168606.9A EP2403088B1 (en) | 2010-06-08 | 2011-06-02 | SSPC for parallel arc fault detection in DC power system |
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US12/796,275 US8320090B2 (en) | 2010-06-08 | 2010-06-08 | SSPC for parallel arc fault detection in DC power system |
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US20110299201A1 true US20110299201A1 (en) | 2011-12-08 |
US8320090B2 US8320090B2 (en) | 2012-11-27 |
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US12/796,275 Active 2030-12-31 US8320090B2 (en) | 2010-06-08 | 2010-06-08 | SSPC for parallel arc fault detection in DC power system |
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US8320090B2 (en) | 2012-11-27 |
EP2403088A2 (en) | 2012-01-04 |
EP2403088B1 (en) | 2014-07-16 |
EP2403088A3 (en) | 2013-04-24 |
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