US20110271158A1 - Method and apparatus for testing high capacity/high bandwidth memory devices - Google Patents
Method and apparatus for testing high capacity/high bandwidth memory devices Download PDFInfo
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- US20110271158A1 US20110271158A1 US13/180,301 US201113180301A US2011271158A1 US 20110271158 A1 US20110271158 A1 US 20110271158A1 US 201113180301 A US201113180301 A US 201113180301A US 2011271158 A1 US2011271158 A1 US 2011271158A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
Definitions
- This invention relates to memory devices, and, more particularly, to testing memory devices.
- DRAM dynamic random access memory
- Memory devices are typically tested to ensure the devices are in working order, as some memory cells may be defective.
- Complex testing systems are utilized to test the devices, including generating test signals and reading test data from the memory cells.
- the testing systems are expensive and require significant investment to acquire and set up. Changing or acquiring new test systems would therefore require a prohibitive amount of time and investment.
- FIG. 1 is a block diagram of a computer system that includes a memory device according to an embodiment of the invention.
- FIG. 2 is a block diagram of a memory device according to an embodiment of the invention.
- FIG. 3 is a more detailed block diagram of a memory device according to an embodiment of the invention.
- FIG. 4 is a block diagram of a memory device according to an embodiment of the invention coupled to a conventional tester.
- FIG. 1 A computer system including a high-capacity, high bandwidth memory device 10 that can be tested according to an embodiment of the invention is shown in FIG. 1 connected to a processor 12 through a relatively narrow high-speed bus 14 that is divided into downstream lanes and separate upstream lanes (not shown in FIG. 1 ).
- the memory device 10 includes 4 DRAM die 20 , 22 , 24 , 26 , which may be identical to each other, stacked on top of each other. Although the memory device 10 includes 4 DRAM die 20 , 22 , 24 , 26 , other embodiments of the memory device use a greater or lesser number of DRAM die.
- the DRAM die 20 , 22 , 24 , 26 are stacked on top of a logic die 30 , which serves as the interface with the processor 12 .
- the logic die 30 can implement a variety of functions in the memory device 10 to limit the number of functions that must be implemented in the DRAM die 20 , 22 , 24 , 26 .
- the logic die 30 may perform memory management functions, such power management and refresh of memory cells in the DRAM die 20 , 22 , 24 , 26 .
- the logic die 30 may perform error checking and correcting (“ECC”) functions.
- the DRAM die 20 , 22 , 24 , 26 are connected to each other and to the logic die 30 by a relatively wide bus 34 .
- the bus 34 may be implemented with through silicon vias (“TSVs”), which comprise a large number of conductors extending through the DRAM die 20 , 22 , 24 , 26 at the same locations on the DRAM die and connect to respective conductors formed on the die 20 , 22 , 24 , 26 .
- TSVs through silicon vias
- each of the DRAM die 20 , 22 , 24 , 26 are divided into 16 autonomous partitions, each of which may contain 2 or 4 independent memory banks. In such case, the partitions of each die 20 , 22 , 24 , 26 that are stacked on top each other may be independently accessed for read and write operations.
- Each set of 16 stacked partitions may be referred to as a “vault.”
- the memory device 10 may contain 16 vaults.
- the vault may include a vertical stack of interconnected portions of the memory dies.
- the bus 34 is divided into 16 36-bit bi-directional sub-buses 38 a - p , with each of the 16 36-bit sub-buses coupled to the 4 partitions in a respective vault, one on each of the separate die 20 , 22 , 24 , and 26 .
- Each of these sub-buses may couple 32 bits of a data and 4 ECC bits between the logic die 30 and the DRAM die 20 , 22 , 24 , 26 .
- the relatively narrow high-speed bus 14 connecting the processor 12 to the logic die is divided into 4 16-bit downstream lanes 40 a - d and 4 separate 16-bit upstream lanes 42 a - d .
- the 4 downstream lanes 40 a - d may be connected to a single processor 12 as shown in FIG. 1 , which may be a multi-core processor, to multiple processors (not shown), or to some other memory access device like a memory controller.
- the 4 downstream lanes 40 a - d may operate either independently of each other so that packets are coupled through the lanes 40 a - d at different times and to the same or different vaults.
- one of the functions performed by the logic die 30 is to serialize the read data bits coupled from the DRAM die 20 , 22 , 24 , 26 into serial streams of 16 serial data bits coupled in 16 parallel bits of each upstream lane 42 a - d of the bus 14 .
- the logic die 30 may perform the functions of deserializing 16 serial data bits coupled through one of the 16-bit downstream lanes 40 a - d of the bus 14 to obtain 256 parallel data bits.
- the logic die 30 then couples these 256 bits through one of the 32-bit sub-buses 38 a - p in a serial stream of 8 bits.
- other embodiments may use different numbers of lanes 40 , 42 having different widths or different numbers of sub-buses 38 a - p having different widths, and they may couple data bits having different structures.
- the stacking of multiple DRAM die results in a memory device having a very large capacity.
- the use of a very wide bus connecting the DRAM die allows data to be coupled to and from the DRAM die with a very high bandwidth.
- a logic die 30 that can be tested according to an embodiment of the invention is shown in FIG. 3 connected to the processor 12 and the DRAM die 20 , 22 , 24 , 26 .
- each of the 4 downstream lanes 40 a - d is connected to a respective link interface 50 a - d .
- Each link interface 50 a - d includes a deserializer 54 that converts each serial stream of 16 data bits on each of the 16-bit lanes 40 a - d to 256 parallel bits. Insofar as there are 4 link interfaces 50 a - d , the link interfaces can together output 1024 output parallel bits.
- Each of the link interfaces 50 a - d applies its 256 parallel bits to a respective downstream target 60 a - d , which decodes the command and address portions of the received packet and buffers write data in the event a memory request is for a write operation.
- the downstream targets 60 a - d output their respective commands, addresses and possibly write data to a switch 62 .
- the switch 62 contains 16 multiplexers 64 each of which direct the command, addresses and any write data from any of the downstream targets 60 a - d to its respective vault of the DRAM die 20 , 22 , 24 , 26 .
- each of the downstream targets 60 a - d can access any of the 16 vaults in the DRAM die 20 , 22 , 24 , 26 .
- the multiplexers 64 use the address in the received memory requests to determine if its respective vault is the target of a memory request.
- Each of the multiplexers 64 apply the memory request to a respective one of 16 vault controllers 70 a - p
- Each vault controller 70 a - p includes a write buffer 82 , a read buffer 84 and a command pipeline 86 .
- the command and addresses in memory requests received from the switch 62 are loaded into the command pipeline 86 , and any write data in the memory requests are stored in the write buffer 82 .
- the read buffer 84 is used to store read data from the respective vault, as will be explained in greater detail below. Both the write data from the write buffer 82 and the command from the command pipeline 86 are applied to a memory interface 88 .
- the memory interface 88 may include a sequencer 90 and an ECC and defective memory cell repair system 100 .
- the ECC and repair system 100 uses ECC techniques to check and correct the data read from the DRAM die 20 , 22 , 24 , 26 , and to assist the processor 12 or other memory access device to substitute redundant rows and columns for rows and columns, respectively, containing one or more defective memory cells.
- the sequencer 90 couples commands and addresses from the command pipeline 86 to the DRAM die 20 , 22 , 24 , 26 through a command/address bus 92 and 32-bits of write data from the write buffer 82 and 4 bits of ECC from the ECC and repair system 100 to the DRAM die 20 , 22 , 24 , 26 through a 36-bit data bus 94 .
- write data are loaded into the write buffer 82 as 256 parallel bits, they are output from the buffer 82 in two sets, each set being 128 parallel bits. These 128 bits are then further serialized by the ECC and repair system 100 to 4 sets of 32-bit data, which are coupled thorough the data bus 94 .
- write data are coupled to the write buffer 82 in synchronism with a 500 MHz clock so the data are stored in the write buffer at 16 gigabytes (“GB”) per second.
- the write data are coupled from the write buffer 82 to the DRAM die 20 , 22 , 24 , 26 using a 2 GHz clock so the data are output from the write buffer 82 at 8 GB/s.
- the write buffers 82 will be able to couple the write data to the DRAM die 20 , 22 , 24 , 26 at least as fast as the data are coupled to the write buffer 82 .
- the command and address for the request are coupled to the DRAM die 20 , 22 , 24 , 26 in the same manner as a write request, as explained above.
- 32 bits of read data and 4 ECC bits may be output from the DRAM die 20 , 22 , 24 , 26 through the 36-bit data bus 94 .
- the ECC bits are passed to the ECC and repair system 100 , which uses the ECC bits to check and correct the read data before passing the read data on to the read buffer 84 .
- the ECC and repair system 100 also deserializes the 32 bits of read data into two sets of 128-bit read data.
- the read buffer transmits 256 bits to the switch 62 .
- the switch includes 4 output multiplexers 104 coupled to respective upstream masters 110 a - d .
- Each multiplexer 104 can couple 256 bits of parallel data from any one of the vault controllers 70 a - p to its respective upstream master 110 a - d .
- the upstream masters 110 a - d format the 256 bits of read data into packet data and couple the packet to respective upstream link interfaces 114 a - d .
- Each of the link interfaces 114 - d include a respective serializer 120 that converts the incoming 256 bits to a serial stream of 16 bits on each bit of a respective one of the 16-bit upsteam links 42 a - d.
- the logic chip 30 may receive data on downstream lanes 40 a - d and output data on upstream lanes 42 a - d .
- Input data received in on a downstream lane in 16-bit increments is deserialized into a 256-bit packet and decoded by the relevant vault controller, such as vault controller 60 a.
- Packets received from the vaults are serialized before application to upstream lanes 42 a - d.
- a conventional tester 400 shown in FIG. 4 , has a 16-bit command interface 410 a, a 16-bit address interface 410 b and a 32-bit bi-directional interface 410 c .
- the interfaces 410 a - c do not match up with the downstream lanes 40 a - d and upstream lanes 42 a - d .
- the signals on the command, address, and data interfaces 410 a - c cannot be coupled directly to the downstream lanes 40 a - d or upstream lanes 42 a - d .
- the lanes 40 a - d and 42 a - d are unidirectional and do not support bi-directional communication supported by the data interface 410 c.
- sequential data received on each of the downstream lanes 40 a - d is assembled into a packet that may contain command, address and data information.
- a packet builder and broadcaster 420 is provided.
- the logic chip 30 may be placed in a test mode.
- the test mode may be initiated, for example, by providing a control signal indicative of test operation.
- the packet builder and broadcaster 420 includes a first input port for receiving command signals from the tester over the command interface 410 a, a second input port for receiving address signals from the tester 400 over the address interface 410 b and a third input port for receiving data signals from the tester 400 over the data interface 410 c.
- the packet builder and broadcaster 420 receives command, address and optionally data signals from the tester 400 and reformats the received command, address and data signals into a format recognized by the logic chip 30 .
- the packet builder and broadcaster 420 may pass test command, address, and data signals sequentially to one of the downstream lanes 40 a - d in the case of a write command.
- the test command, address and data signals are then passed through the link interface 50 a to downstream target 60 a to form a packet, as generally described above.
- the packet builder and broadcaster 420 is shown in FIG.
- the packet builder and broadcaster 420 may include the link interfaces 50 a - d , downstream targets 60 a - d , or both.
- the packet builder and broadcaster 420 may repeat the received test commands and apply them to multiple vaults.
- the packet builder and broadcaster 420 may couple a test command to multiple lanes 40 a - d either simultaneously or sequentially.
- the packet builder and broadcaster 420 may also direct a test command to be passed through multiple switches 62 to reach multiple vault controllers 70 a - p .
- the packet builder and broadcaster may vary the received address signal as the test command is repeated such that the test command is directed to multiple vaults.
- Each respective vault controller 70 a - p may receive and decode the broadcast write command as described above with respect to a routine command. In this manner, test signals generated by the conventional tester 400 on a command interface 410 a, address interface 410 b and data interface 410 c may be assembled into packets expected by the vault controllers 70 a - p and broadcast to multiple vaults.
- a packet disassembler and data compare unit 430 receives and compares the test read data returned from multiple vaults. Results of the comparison may be provided as a 32-bit data signal and coupled to the data interface 410 c of the tester 400 .
- the packet disassembler and data compare unit 430 is shown separate from the link interfaces 114 a - d and upstream masters 110 a - d , in some embodiments the packet disassembler and data compare unit 430 may include the link interfaces 114 a - d , upstream masters 110 a - d , or both.
- the data interface 410 c is bidirectional, but each of the lanes 40 a - d and 42 a - d are unidirectional. Accordingly, both the packet builder and broadcaster 420 and the packet disassembler and data compare unit 430 are coupled to the data interface 410 c.
- the output test read data provided to the tester over the data interface 410 c may indicate only that an error exists in one of the vaults tested.
- the tester 400 may then provide test commands directed to a single vault.
- the packet builder and broadcaster 420 would then only pass the test command to a single vault, and an error could be isolated to a particular vault. In some embodiments, this further testing could include an analysis of whether the error was a hard or soft error.
- the packet disassembler and data compare unit 430 may compare read data returned from several vaults and return results of the comparison to the tester 400 . However, in some embodiments, the packet disassembler and data compare unit 430 may simply pass the read data returned from a vault back to the tester 400 for comparison at the tester with read data returned from other vaults, with the data expected to be returned, or both.
- the packet disassembler 430 may format the received read data in a manner expected by the tester 400 , for example, placing the data in 32-bit chunks and coupling the read data to the bi-directional interface 410 c .
- the packet disassembler and data compare unit 430 may sequentially couple read data received from a plurality of vaults to the tester 400 .
- the logic die 30 may include a packet builder and broadcaster 420 and a packet disassembler and data compare unit 430 that allow the stacked memory devices in multiple vaults to be tested using a conventional tester 400 .
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Abstract
Description
- This application is a divisional of U.S. patent application Ser. No. No. 12/132,332, filed Jun. 3, 2008. This application is incorporated by reference herein in its entirety and for all purposes.
- This invention relates to memory devices, and, more particularly, to testing memory devices.
- As memory devices of all types have evolved, continuous strides have been made in improving their performance in a variety of respects. For example, the storage capacity of memory devices has continued to increase at geometric proportions. This increased capacity, coupled with the geometrically higher operating speeds of electronic systems containing memory devices, has made high memory device bandwidth ever more critical. One application in which memory devices, such as dynamic random access memory (“DRAM”) devices, require a higher bandwidth is their use as system memory in computer systems. As the operating speed of processors has increased, processors are able to read and write data at correspondingly higher speeds. Yet conventional DRAM devices often do not have the bandwidth to read and write data at these higher speeds, thereby slowing the performance of conventional computer systems. This problem is exacerbated by the trend toward multi-core processors and multiple processor computer system. It is currently estimated that computer systems operating as high-end servers are idle as many as 3 out of every 4 clock cycles because of the limited data bandwidth of system memory devices. In fact, the limited bandwidth of DRAM devices operating as system memory can reduce the performance of computer systems to as low as 10% of the performance of which they would otherwise be capable.
- Various attempts have been made to increase the data bandwidth of memory devices. For example, wider internal data buses have been used to transfer data to and from arrays with a higher bandwidth. However, doing so usually requires that write data be serialized and read data deserialized at the memory device interface. Another approach has been to simply scale up the size of memory devices or conversely shrink their feature sizes, but, for a variety of reasons, scaling has been incapable of keeping up with the geometric increase in the demand for higher data bandwidths. Proposals have also been made to stack several integrated circuit memory devices in the same package, but doing so threatens to create a large number of other problems that must be overcome.
- Memory devices are typically tested to ensure the devices are in working order, as some memory cells may be defective. Complex testing systems are utilized to test the devices, including generating test signals and reading test data from the memory cells. The testing systems are expensive and require significant investment to acquire and set up. Changing or acquiring new test systems would therefore require a prohibitive amount of time and investment. As memory device design changes to increase the data bandwidth of the devices, however, the memory devices themselves may become incompatible with conventional test equipment.
- Therefore, a need exists for a method and apparatus to test new memory designs utilizing conventional test equipment.
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FIG. 1 is a block diagram of a computer system that includes a memory device according to an embodiment of the invention. -
FIG. 2 is a block diagram of a memory device according to an embodiment of the invention. -
FIG. 3 is a more detailed block diagram of a memory device according to an embodiment of the invention. -
FIG. 4 is a block diagram of a memory device according to an embodiment of the invention coupled to a conventional tester. - A computer system including a high-capacity, high
bandwidth memory device 10 that can be tested according to an embodiment of the invention is shown inFIG. 1 connected to aprocessor 12 through a relatively narrow high-speed bus 14 that is divided into downstream lanes and separate upstream lanes (not shown inFIG. 1 ). Thememory device 10 includes 4 DRAM die 20, 22, 24, 26, which may be identical to each other, stacked on top of each other. Although thememory device 10 includes 4 DRAM die 20, 22, 24, 26, other embodiments of the memory device use a greater or lesser number of DRAM die. The DRAM die 20, 22, 24, 26 are stacked on top of alogic die 30, which serves as the interface with theprocessor 12. Thelogic die 30 can implement a variety of functions in thememory device 10 to limit the number of functions that must be implemented in theDRAM die - The DRAM die 20, 22, 24, 26 are connected to each other and to the logic die 30 by a relatively
wide bus 34. Thebus 34 may be implemented with through silicon vias (“TSVs”), which comprise a large number of conductors extending through the DRAM die 20, 22, 24, 26 at the same locations on the DRAM die and connect to respective conductors formed on the die 20, 22, 24, 26. In one embodiment, each of the DRAM die 20, 22, 24, 26 are divided into 16 autonomous partitions, each of which may contain 2 or 4 independent memory banks. In such case, the partitions of eachdie memory device 10 may contain 16 vaults. The vault may include a vertical stack of interconnected portions of the memory dies. - As shown in
FIG. 2 , in one embodiment, thebus 34 is divided into 16 36-bit bi-directional sub-buses 38 a-p, with each of the 16 36-bit sub-buses coupled to the 4 partitions in a respective vault, one on each of theseparate die speed bus 14 connecting theprocessor 12 to the logic die is divided into 4 16-bit downstream lanes 40 a-d and 4 separate 16-bit upstream lanes 42 a-d. The 4 downstream lanes 40 a-d may be connected to asingle processor 12 as shown inFIG. 1 , which may be a multi-core processor, to multiple processors (not shown), or to some other memory access device like a memory controller. The 4 downstream lanes 40 a-d may operate either independently of each other so that packets are coupled through the lanes 40 a-d at different times and to the same or different vaults. - As explained in greater detail below, one of the functions performed by the
logic die 30 is to serialize the read data bits coupled from theDRAM die bus 14. Similarly, the logic die 30 may perform the functions of deserializing 16 serial data bits coupled through one of the 16-bit downstream lanes 40 a-d of thebus 14 to obtain 256 parallel data bits. The logic die 30 then couples these 256 bits through one of the 32-bit sub-buses 38 a-p in a serial stream of 8 bits. However, other embodiments may use different numbers of lanes 40, 42 having different widths or different numbers of sub-buses 38 a-p having different widths, and they may couple data bits having different structures. As will be appreciated by one skilled in the art, the stacking of multiple DRAM die results in a memory device having a very large capacity. Further, the use of a very wide bus connecting the DRAM die allows data to be coupled to and from the DRAM die with a very high bandwidth. - A
logic die 30 that can be tested according to an embodiment of the invention is shown inFIG. 3 connected to theprocessor 12 and the DRAM die 20, 22, 24, 26. As shown inFIG. 3 , each of the 4 downstream lanes 40 a-d is connected to a respective link interface 50 a-d. Each link interface 50 a-d includes adeserializer 54 that converts each serial stream of 16 data bits on each of the 16-bit lanes 40 a-d to 256 parallel bits. Insofar as there are 4 link interfaces 50 a-d, the link interfaces can together output 1024 output parallel bits. - Each of the link interfaces 50 a-d applies its 256 parallel bits to a respective downstream target 60 a-d, which decodes the command and address portions of the received packet and buffers write data in the event a memory request is for a write operation. The downstream targets 60 a-d output their respective commands, addresses and possibly write data to a
switch 62. Theswitch 62 contains 16multiplexers 64 each of which direct the command, addresses and any write data from any of the downstream targets 60 a-d to its respective vault of the DRAM die 20, 22, 24, 26. Thus, each of the downstream targets 60 a-d can access any of the 16 vaults in the DRAM die 20, 22, 24, 26. Themultiplexers 64 use the address in the received memory requests to determine if its respective vault is the target of a memory request. Each of themultiplexers 64 apply the memory request to a respective one of 16 vault controllers 70 a-p. - Each vault controller 70 a-p includes a
write buffer 82, aread buffer 84 and acommand pipeline 86. The command and addresses in memory requests received from theswitch 62 are loaded into thecommand pipeline 86, and any write data in the memory requests are stored in thewrite buffer 82. The readbuffer 84 is used to store read data from the respective vault, as will be explained in greater detail below. Both the write data from thewrite buffer 82 and the command from thecommand pipeline 86 are applied to amemory interface 88. Thememory interface 88 may include asequencer 90 and an ECC and defective memorycell repair system 100. The ECC andrepair system 100 uses ECC techniques to check and correct the data read from the DRAM die 20, 22, 24, 26, and to assist theprocessor 12 or other memory access device to substitute redundant rows and columns for rows and columns, respectively, containing one or more defective memory cells. Thesequencer 90 couples commands and addresses from thecommand pipeline 86 to the DRAM die 20, 22, 24, 26 through a command/address bus 92 and 32-bits of write data from thewrite buffer repair system 100 to the DRAM die 20, 22, 24, 26 through a 36-bit data bus 94. - Although data are loaded into the
write buffer 82 as 256 parallel bits, they are output from thebuffer 82 in two sets, each set being 128 parallel bits. These 128 bits are then further serialized by the ECC andrepair system 100 to 4 sets of 32-bit data, which are coupled thorough thedata bus 94. In the embodiment shown inFIG. 3 , write data are coupled to thewrite buffer 82 in synchronism with a 500 MHz clock so the data are stored in the write buffer at 16 gigabytes (“GB”) per second. The write data are coupled from thewrite buffer 82 to the DRAM die 20, 22, 24, 26 using a 2 GHz clock so the data are output from thewrite buffer 82 at 8 GB/s. Therefore, as long as more than half of the memory requests are not write operations to the same vault, the write buffers 82 will be able to couple the write data to the DRAM die 20, 22, 24, 26 at least as fast as the data are coupled to thewrite buffer 82. - In the event a memory request is for a read operation, the command and address for the request are coupled to the DRAM die 20, 22, 24, 26 in the same manner as a write request, as explained above. In response to a read request, 32 bits of read data and 4 ECC bits may be output from the DRAM die 20, 22, 24, 26 through the 36-
bit data bus 94. The ECC bits are passed to the ECC andrepair system 100, which uses the ECC bits to check and correct the read data before passing the read data on to the readbuffer 84. The ECC andrepair system 100 also deserializes the 32 bits of read data into two sets of 128-bit read data. After 2 sets of 128-bit read data have been stored in the readbuffer 84, the read buffer transmits 256 bits to theswitch 62. The switch includes 4output multiplexers 104 coupled to respective upstream masters 110 a-d. Eachmultiplexer 104 can couple 256 bits of parallel data from any one of the vault controllers 70 a-p to its respective upstream master 110 a-d. The upstream masters 110 a-d format the 256 bits of read data into packet data and couple the packet to respective upstream link interfaces 114 a-d. Each of the link interfaces 114-d include arespective serializer 120 that converts the incoming 256 bits to a serial stream of 16 bits on each bit of a respective one of the 16-bit upsteam links 42 a-d. - The above description details how packets may be applied to a group of
DRAM devices logic chip 30 may receive data on downstream lanes 40 a-d and output data on upstream lanes 42 a-d. Input data received in on a downstream lane in 16-bit increments is deserialized into a 256-bit packet and decoded by the relevant vault controller, such asvault controller 60 a. Packets received from the vaults are serialized before application to upstream lanes 42 a-d. - A
conventional tester 400, shown inFIG. 4 , has a 16-bit command interface 410 a, a 16-bit address interface 410 b and a 32-bitbi-directional interface 410 c. The interfaces 410 a-c do not match up with the downstream lanes 40 a-d and upstream lanes 42 a-d. The signals on the command, address, and data interfaces 410 a-c cannot be coupled directly to the downstream lanes 40 a-d or upstream lanes 42 a-d. For example, the lanes 40 a-d and 42 a-d are unidirectional and do not support bi-directional communication supported by the data interface 410 c. Furthermore, sequential data received on each of the downstream lanes 40 a-d is assembled into a packet that may contain command, address and data information. - To match signals provided by the
tester 400 with information expected by the downstream lanes 40 a-d of thelogic chip 30, a packet builder andbroadcaster 420 is provided. Thelogic chip 30 may be placed in a test mode. The test mode may be initiated, for example, by providing a control signal indicative of test operation. The packet builder andbroadcaster 420 includes a first input port for receiving command signals from the tester over thecommand interface 410 a, a second input port for receiving address signals from thetester 400 over theaddress interface 410 b and a third input port for receiving data signals from thetester 400 over the data interface 410 c. - In the test mode, according to one embodiment, the packet builder and
broadcaster 420 receives command, address and optionally data signals from thetester 400 and reformats the received command, address and data signals into a format recognized by thelogic chip 30. For example, the packet builder andbroadcaster 420 may pass test command, address, and data signals sequentially to one of the downstream lanes 40 a-d in the case of a write command. The test command, address and data signals are then passed through thelink interface 50 a todownstream target 60 a to form a packet, as generally described above. Although the packet builder andbroadcaster 420 is shown inFIG. 4 separate from the link interfaces 50 a-d and downstream targets 60 a-d, in some embodiments the packet builder andbroadcaster 420 may include the link interfaces 50 a-d, downstream targets 60 a-d, or both. - It may be desirable to test multiple vaults using the same test command. Accordingly, the packet builder and
broadcaster 420 may repeat the received test commands and apply them to multiple vaults. For example, the packet builder andbroadcaster 420 may couple a test command to multiple lanes 40 a-d either simultaneously or sequentially. The packet builder andbroadcaster 420 may also direct a test command to be passed throughmultiple switches 62 to reach multiple vault controllers 70 a-p. The packet builder and broadcaster may vary the received address signal as the test command is repeated such that the test command is directed to multiple vaults. Each respective vault controller 70 a-p may receive and decode the broadcast write command as described above with respect to a routine command. In this manner, test signals generated by theconventional tester 400 on acommand interface 410 a,address interface 410 b anddata interface 410 c may be assembled into packets expected by the vault controllers 70 a-p and broadcast to multiple vaults. - As test read data is returned from the vaults in test mode, a packet disassembler and data compare
unit 430 receives and compares the test read data returned from multiple vaults. Results of the comparison may be provided as a 32-bit data signal and coupled to the data interface 410 c of thetester 400. Although the packet disassembler and data compareunit 430 is shown separate from the link interfaces 114 a-d and upstream masters 110 a-d, in some embodiments the packet disassembler and data compareunit 430 may include the link interfaces 114 a-d, upstream masters 110 a-d, or both. The data interface 410 c is bidirectional, but each of the lanes 40 a-d and 42 a-d are unidirectional. Accordingly, both the packet builder andbroadcaster 420 and the packet disassembler and data compareunit 430 are coupled to the data interface 410 c. - Because the packet disassembler and data compare
unit 430 conducts a comparison of test read data received from multiple vaults, the output test read data provided to the tester over the data interface 410 c may indicate only that an error exists in one of the vaults tested. To isolate an error to a particular vault, thetester 400 may then provide test commands directed to a single vault. The packet builder andbroadcaster 420 would then only pass the test command to a single vault, and an error could be isolated to a particular vault. In some embodiments, this further testing could include an analysis of whether the error was a hard or soft error. - As described above, the packet disassembler and data compare
unit 430 may compare read data returned from several vaults and return results of the comparison to thetester 400. However, in some embodiments, the packet disassembler and data compareunit 430 may simply pass the read data returned from a vault back to thetester 400 for comparison at the tester with read data returned from other vaults, with the data expected to be returned, or both. Thepacket disassembler 430 may format the received read data in a manner expected by thetester 400, for example, placing the data in 32-bit chunks and coupling the read data to thebi-directional interface 410 c. The packet disassembler and data compareunit 430 may sequentially couple read data received from a plurality of vaults to thetester 400. - Accordingly, the logic die 30 may include a packet builder and
broadcaster 420 and a packet disassembler and data compareunit 430 that allow the stacked memory devices in multiple vaults to be tested using aconventional tester 400. - From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, although the embodiments of the invention are explained in the context of stacked DRAM die, it will be understood that the stacked die may be other types of memory device die, such as flash memory device die. Accordingly, the invention is not limited except as by the appended claims.
Claims (8)
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110067039A1 (en) * | 2009-09-11 | 2011-03-17 | Sean Eilert | Autonomous memory architecture |
US20110320894A1 (en) * | 2010-06-28 | 2011-12-29 | Qualcomm Incorporated | Surrogate Circuit For Testing An Interface |
US8539312B2 (en) | 2008-08-15 | 2013-09-17 | Microns Technology, Inc. | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system |
US8751754B2 (en) | 2008-05-29 | 2014-06-10 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
US8793460B2 (en) | 2008-07-21 | 2014-07-29 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
US8861246B2 (en) | 2010-12-16 | 2014-10-14 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
US9146811B2 (en) | 2008-07-02 | 2015-09-29 | Micron Technology, Inc. | Method and apparatus for repairing high capacity/high bandwidth memory devices |
US9171597B2 (en) | 2013-08-30 | 2015-10-27 | Micron Technology, Inc. | Apparatuses and methods for providing strobe signals to memories |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
WO2016187221A1 (en) * | 2015-05-18 | 2016-11-24 | Micron Technology, Inc | Apparatus having dice to perorm refresh operations |
US9659630B2 (en) | 2008-07-02 | 2017-05-23 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
US10003675B2 (en) | 2013-12-02 | 2018-06-19 | Micron Technology, Inc. | Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data |
CN112435709A (en) * | 2020-12-03 | 2021-03-02 | 中科驭数(北京)科技有限公司 | High-bandwidth memory test system, test method and test equipment |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7979757B2 (en) | 2008-06-03 | 2011-07-12 | Micron Technology, Inc. | Method and apparatus for testing high capacity/high bandwidth memory devices |
US8127185B2 (en) * | 2009-01-23 | 2012-02-28 | Micron Technology, Inc. | Memory devices and methods for managing error regions |
US8612809B2 (en) | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US9164679B2 (en) | 2011-04-06 | 2015-10-20 | Patents1, Llc | System, method and computer program product for multi-thread operation involving first memory of a first memory class and second memory of a second memory class |
US9158546B1 (en) | 2011-04-06 | 2015-10-13 | P4tents1, LLC | Computer program product for fetching from a first physical memory between an execution of a plurality of threads associated with a second physical memory |
US9170744B1 (en) | 2011-04-06 | 2015-10-27 | P4tents1, LLC | Computer program product for controlling a flash/DRAM/embedded DRAM-equipped system |
US9176671B1 (en) | 2011-04-06 | 2015-11-03 | P4tents1, LLC | Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9417754B2 (en) | 2011-08-05 | 2016-08-16 | P4tents1, LLC | User interface system, method, and computer program product |
US8924786B2 (en) * | 2012-06-28 | 2014-12-30 | Intel Corporation | No-touch stress testing of memory I/O interfaces |
US9135100B2 (en) | 2013-03-14 | 2015-09-15 | Micron Technology, Inc. | Cooperative memory error detection and repair |
US9223665B2 (en) | 2013-03-15 | 2015-12-29 | Micron Technology, Inc. | Apparatuses and methods for memory testing and repair |
US9170296B2 (en) | 2013-08-06 | 2015-10-27 | Globalfoundries U.S.2 Llc | Semiconductor device defect monitoring using a plurality of temperature sensing devices in an adjacent semiconductor device |
CN105117310A (en) * | 2015-07-30 | 2015-12-02 | 浪潮电子信息产业股份有限公司 | Linux system-based memory read-write bandwidth optimization test method |
KR20170060205A (en) * | 2015-11-23 | 2017-06-01 | 에스케이하이닉스 주식회사 | Stacked memory device and semiconductor memory system |
US10838645B2 (en) * | 2019-04-22 | 2020-11-17 | Micron Technology, Inc. | Memory writing operations with consideration for thermal thresholds |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5774475A (en) * | 1996-12-05 | 1998-06-30 | National Semiconductor Corporation | Testing scheme that re-uses original stimulus for testing circuitry embedded within a larger circuit |
US5982684A (en) * | 1998-05-28 | 1999-11-09 | Intel Corporation | Parallel access testing of a memory array |
US6181616B1 (en) * | 1998-09-03 | 2001-01-30 | Micron Technology, Inc. | Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test |
US6285211B1 (en) * | 1997-07-16 | 2001-09-04 | Altera Corporation | I/O buffer circuit with pin multiplexing |
US6839260B2 (en) * | 2000-01-18 | 2005-01-04 | Hitachi, Ltd. | Semiconductor device having different types of memory cell arrays stacked in a vertical direction |
US20050174877A1 (en) * | 2004-02-06 | 2005-08-11 | Soon-Jae Cho | Bus arrangement and method thereof |
US7171596B2 (en) * | 2002-09-11 | 2007-01-30 | Infineon Technologies Ag | Circuit and method for testing embedded DRAM circuits through direct access mode |
Family Cites Families (94)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5263032A (en) | 1991-06-27 | 1993-11-16 | Digital Equipment Corporation | Computer system operation with corrected read data function |
US5179303A (en) | 1991-10-24 | 1993-01-12 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
US5748914A (en) | 1995-10-19 | 1998-05-05 | Rambus, Inc. | Protocol for communication with dynamic memory |
JP3691170B2 (en) * | 1996-08-30 | 2005-08-31 | 株式会社ルネサステクノロジ | Test circuit |
US6247138B1 (en) | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
JPH11213666A (en) | 1998-01-30 | 1999-08-06 | Mitsubishi Electric Corp | Output circuit and synchronous semiconductor memory device |
TW440767B (en) | 1998-06-02 | 2001-06-16 | Fujitsu Ltd | Method of and apparatus for correctly transmitting signals at high speed without waveform distortion |
US6177807B1 (en) | 1999-05-28 | 2001-01-23 | International Business Machines Corporation | High frequency valid data strobe |
US6401213B1 (en) | 1999-07-09 | 2002-06-04 | Micron Technology, Inc. | Timing circuit for high speed memory |
JP4216415B2 (en) | 1999-08-31 | 2009-01-28 | 株式会社ルネサステクノロジ | Semiconductor device |
JP2001236797A (en) * | 1999-12-17 | 2001-08-31 | Fujitsu Ltd | Self-test circuit and memory device incorporating it |
JP2001195899A (en) * | 2000-01-06 | 2001-07-19 | Mitsubishi Electric Corp | Semiconductor memory |
DE10002130A1 (en) | 2000-01-19 | 2001-08-02 | Infineon Technologies Ag | Method and device for alternately operating a read-write memory in the one-memory operating mode and in the entangled multi-memory operating mode |
US6745275B2 (en) | 2000-01-25 | 2004-06-01 | Via Technologies, Inc. | Feedback system for accomodating different memory module loading |
US7168005B2 (en) * | 2000-09-14 | 2007-01-23 | Cadence Design Systems, Inc. | Programable multi-port memory BIST with compact microcode |
US20030120858A1 (en) | 2000-09-15 | 2003-06-26 | Matrix Semiconductor, Inc. | Memory devices and methods for use therewith |
US6574626B1 (en) * | 2000-09-29 | 2003-06-03 | Agilent Technologies, Inc. | Method and apparatus for administration of extended memory |
US6418068B1 (en) | 2001-01-19 | 2002-07-09 | Hewlett-Packard Co. | Self-healing memory |
US20020100231A1 (en) | 2001-01-26 | 2002-08-01 | Miller Robert J. | Textured laminate flooring |
US6714476B2 (en) | 2001-02-15 | 2004-03-30 | Ibm Corporation | Memory array with dual wordline operation |
TW483258B (en) | 2001-02-22 | 2002-04-11 | Realtek Semiconductor Corp | Phase interpolating circuit and the apparatus composed of phase interpolating circuits for generating phase interpolating signal |
US6658523B2 (en) | 2001-03-13 | 2003-12-02 | Micron Technology, Inc. | System latency levelization for read data |
US6417695B1 (en) | 2001-03-15 | 2002-07-09 | Micron Technology, Inc. | Antifuse reroute of dies |
JP2003014819A (en) | 2001-07-03 | 2003-01-15 | Matsushita Electric Ind Co Ltd | Semiconductor wiring board, semiconductor device, test method therefor and mounting method therefor |
JP4437519B2 (en) | 2001-08-23 | 2010-03-24 | スパンション エルエルシー | Memory controller for multilevel cell memory |
US6938133B2 (en) | 2001-09-28 | 2005-08-30 | Hewlett-Packard Development Company, L.P. | Memory latency and bandwidth optimizations |
US6889334B1 (en) | 2001-10-02 | 2005-05-03 | Advanced Micro Devices, Inc. | Multimode system for calibrating a data strobe delay for a memory read operation |
DE10163653A1 (en) | 2001-12-21 | 2003-07-03 | Bosch Gmbh Robert | Device for radar system e.g. for speed control in vehicle, uses demodulated reception signals specifically as input signals for device |
US7197101B2 (en) | 2002-01-02 | 2007-03-27 | Intel Corporation | Phase interpolator based clock recovering |
US7203259B2 (en) | 2002-01-02 | 2007-04-10 | Intel Corporation | Phase interpolator |
US6650157B2 (en) | 2002-01-11 | 2003-11-18 | Sun Microsystems, Inc. | Using a push/pull buffer to improve delay locked loop performance |
JP4004811B2 (en) | 2002-02-06 | 2007-11-07 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP2003303139A (en) | 2002-04-09 | 2003-10-24 | Nec Corp | Redundancy memory module and memory controller |
US7035150B2 (en) | 2002-10-31 | 2006-04-25 | Infineon Technologies Ag | Memory device with column select being variably delayed |
US20040098545A1 (en) | 2002-11-15 | 2004-05-20 | Pline Steven L. | Transferring data in selectable transfer modes |
JP4274811B2 (en) | 2003-02-17 | 2009-06-10 | 株式会社ルネサステクノロジ | Synchronous semiconductor memory device |
JP4291596B2 (en) * | 2003-02-26 | 2009-07-08 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit testing apparatus and semiconductor integrated circuit manufacturing method using the same |
JP4419049B2 (en) | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | Memory module and memory system |
US7184916B2 (en) * | 2003-05-20 | 2007-02-27 | Cray Inc. | Apparatus and method for testing memory cards |
US7447950B2 (en) | 2003-05-20 | 2008-11-04 | Nec Electronics Corporation | Memory device and memory error correction method |
US7061273B2 (en) | 2003-06-06 | 2006-06-13 | Rambus Inc. | Method and apparatus for multi-mode driver |
JP2005025827A (en) | 2003-06-30 | 2005-01-27 | Toshiba Corp | Semiconductor integrated circuit device and its error detecting and correcting method |
US20050071707A1 (en) | 2003-09-30 | 2005-03-31 | Hampel Craig E. | Integrated circuit with bi-modal data strobe |
WO2005043384A1 (en) | 2003-10-24 | 2005-05-12 | Microchip Technology Incorporated | Method and system for fast access to stack memory |
JP2005191083A (en) | 2003-12-24 | 2005-07-14 | Fujitsu Ltd | Semiconductor integrated circuit and method for evaluating wiring thereof |
US7107424B1 (en) | 2004-03-25 | 2006-09-12 | Emc Corporation | Memory read strobe pulse optimization training system |
JP2005353168A (en) | 2004-06-10 | 2005-12-22 | Canon Inc | Memory interface circuit and memory interface method |
US20050289435A1 (en) | 2004-06-29 | 2005-12-29 | Mulla Dean A | Fast approximate DINV calculation in parallel with coupled ECC generation or correction |
KR100630343B1 (en) | 2004-07-14 | 2006-09-29 | 삼성전자주식회사 | Clock data recovery circuit with analog phase interpolator and clock data recovering method using the same |
US7539800B2 (en) | 2004-07-30 | 2009-05-26 | International Business Machines Corporation | System, method and storage medium for providing segment level sparing |
US7389375B2 (en) | 2004-07-30 | 2008-06-17 | International Business Machines Corporation | System, method and storage medium for a multi-mode memory buffer device |
DE602004014371D1 (en) | 2004-09-10 | 2008-07-24 | St Microelectronics Srl | Memory with built-in error correction code facility |
US7135905B2 (en) | 2004-10-12 | 2006-11-14 | Broadcom Corporation | High speed clock and data recovery system |
US7464241B2 (en) | 2004-11-22 | 2008-12-09 | Intel Corporation | Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding |
US7200021B2 (en) * | 2004-12-10 | 2007-04-03 | Infineon Technologies Ag | Stacked DRAM memory chip for a dual inline memory module (DIMM) |
JP2006277872A (en) * | 2005-03-30 | 2006-10-12 | Elpida Memory Inc | Semiconductor memory device and its test method |
JP4309368B2 (en) | 2005-03-30 | 2009-08-05 | エルピーダメモリ株式会社 | Semiconductor memory device |
US7296195B2 (en) | 2005-05-02 | 2007-11-13 | Credence Systems Corporation | Bit synchronization for high-speed serial device testing |
TWI289851B (en) | 2005-05-04 | 2007-11-11 | Univ Tsinghua | Semiconductor memory and method of correcting errors for the same |
US7317256B2 (en) | 2005-06-01 | 2008-01-08 | Intel Corporation | Electronic packaging including die with through silicon via |
US8619452B2 (en) | 2005-09-02 | 2013-12-31 | Google Inc. | Methods and apparatus of stacking DRAMs |
US7464225B2 (en) | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US7631245B2 (en) | 2005-09-26 | 2009-12-08 | Sandisk Il Ltd. | NAND flash memory controller exporting a NAND interface |
US7802169B2 (en) | 2005-12-12 | 2010-09-21 | Mediatek Inc. | Error correction devices and correction methods |
US20080017897A1 (en) * | 2006-01-30 | 2008-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing same |
US8185711B2 (en) | 2006-05-16 | 2012-05-22 | Samsung Electronics Co., Ltd. | Memory module, a memory system including a memory controller and a memory module and methods thereof |
JP4267002B2 (en) | 2006-06-08 | 2009-05-27 | エルピーダメモリ株式会社 | System with controller and memory |
US7694031B2 (en) | 2006-10-31 | 2010-04-06 | Globalfoundries Inc. | Memory controller including a dual-mode memory interconnect |
JP2008140220A (en) | 2006-12-04 | 2008-06-19 | Nec Corp | Semiconductor device |
EP4254413A3 (en) | 2006-12-14 | 2023-12-27 | Rambus Inc. | Multi-die memory device |
US8110899B2 (en) | 2006-12-20 | 2012-02-07 | Intel Corporation | Method for incorporating existing silicon die into 3D integrated stack |
US7984355B2 (en) | 2007-04-09 | 2011-07-19 | Qimonda Ag | Memory module with ranks of memory chips |
US8427891B2 (en) | 2007-04-17 | 2013-04-23 | Rambus Inc. | Hybrid volatile and non-volatile memory device with a shared interface circuit |
US7921264B2 (en) | 2007-06-27 | 2011-04-05 | International Business Machines Corporation | Dual-mode memory chip for high capacity memory subsystem |
US20090016130A1 (en) * | 2007-07-12 | 2009-01-15 | Manfred Menke | Memory device and method of testing a memory device |
US7688652B2 (en) | 2007-07-18 | 2010-03-30 | Mosaid Technologies Incorporated | Storage of data in memory via packet strobing |
US8356138B1 (en) | 2007-08-20 | 2013-01-15 | Xilinx, Inc. | Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP) |
US20090091968A1 (en) | 2007-10-08 | 2009-04-09 | Stefan Dietrich | Integrated circuit including a memory having a data inversion circuit |
KR101396366B1 (en) | 2007-10-22 | 2014-05-20 | 삼성전자주식회사 | Linear digital phase interpolator and semi-digital delay locked loop including the same |
US20090196093A1 (en) | 2008-01-31 | 2009-08-06 | Qimonda Ag | Stacked die memory |
US9252758B2 (en) | 2008-04-08 | 2016-02-02 | Realtek Semiconductor Corporation | Multi-phase phase interpolator |
US8521979B2 (en) | 2008-05-29 | 2013-08-27 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
US7979757B2 (en) | 2008-06-03 | 2011-07-12 | Micron Technology, Inc. | Method and apparatus for testing high capacity/high bandwidth memory devices |
US7710144B2 (en) | 2008-07-01 | 2010-05-04 | International Business Machines Corporation | Controlling for variable impedance and voltage in a memory system |
US7855931B2 (en) | 2008-07-21 | 2010-12-21 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
US8756486B2 (en) | 2008-07-02 | 2014-06-17 | Micron Technology, Inc. | Method and apparatus for repairing high capacity/high bandwidth memory devices |
US8289760B2 (en) | 2008-07-02 | 2012-10-16 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
US8103928B2 (en) | 2008-08-04 | 2012-01-24 | Micron Technology, Inc. | Multiple device apparatus, systems, and methods |
US8127204B2 (en) | 2008-08-15 | 2012-02-28 | Micron Technology, Inc. | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system |
US7872936B2 (en) | 2008-09-17 | 2011-01-18 | Qimonda Ag | System and method for packaged memory |
KR20100037427A (en) | 2008-10-01 | 2010-04-09 | 삼성전자주식회사 | Ac coupling phase interpolator and dll using it |
TWI420818B (en) | 2009-03-10 | 2013-12-21 | Realtek Semiconductor Corp | Method and apparatus for preventing phase interpolation circuit from glitch during clock switching |
JPWO2012060097A1 (en) | 2010-11-02 | 2014-05-12 | 日本電気株式会社 | Memory module and memory system |
US8400808B2 (en) | 2010-12-16 | 2013-03-19 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
-
2008
- 2008-06-03 US US12/132,332 patent/US7979757B2/en active Active
-
2011
- 2011-07-11 US US13/180,301 patent/US8799726B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5774475A (en) * | 1996-12-05 | 1998-06-30 | National Semiconductor Corporation | Testing scheme that re-uses original stimulus for testing circuitry embedded within a larger circuit |
US6285211B1 (en) * | 1997-07-16 | 2001-09-04 | Altera Corporation | I/O buffer circuit with pin multiplexing |
US5982684A (en) * | 1998-05-28 | 1999-11-09 | Intel Corporation | Parallel access testing of a memory array |
US6181616B1 (en) * | 1998-09-03 | 2001-01-30 | Micron Technology, Inc. | Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test |
US6839260B2 (en) * | 2000-01-18 | 2005-01-04 | Hitachi, Ltd. | Semiconductor device having different types of memory cell arrays stacked in a vertical direction |
US7171596B2 (en) * | 2002-09-11 | 2007-01-30 | Infineon Technologies Ag | Circuit and method for testing embedded DRAM circuits through direct access mode |
US20050174877A1 (en) * | 2004-02-06 | 2005-08-11 | Soon-Jae Cho | Bus arrangement and method thereof |
Cited By (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8751754B2 (en) | 2008-05-29 | 2014-06-10 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
US9411538B2 (en) | 2008-05-29 | 2016-08-09 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
US10109343B2 (en) | 2008-07-02 | 2018-10-23 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
US10892003B2 (en) | 2008-07-02 | 2021-01-12 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
US9659630B2 (en) | 2008-07-02 | 2017-05-23 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
US9146811B2 (en) | 2008-07-02 | 2015-09-29 | Micron Technology, Inc. | Method and apparatus for repairing high capacity/high bandwidth memory devices |
US9275698B2 (en) | 2008-07-21 | 2016-03-01 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
US8793460B2 (en) | 2008-07-21 | 2014-07-29 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
US8539312B2 (en) | 2008-08-15 | 2013-09-17 | Microns Technology, Inc. | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system |
US8826101B2 (en) | 2008-08-15 | 2014-09-02 | Micron Technology, Inc. | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system |
US9779057B2 (en) * | 2009-09-11 | 2017-10-03 | Micron Technology, Inc. | Autonomous memory architecture |
US10769097B2 (en) | 2009-09-11 | 2020-09-08 | Micron Technologies, Inc. | Autonomous memory architecture |
US20110067039A1 (en) * | 2009-09-11 | 2011-03-17 | Sean Eilert | Autonomous memory architecture |
US11586577B2 (en) | 2009-09-11 | 2023-02-21 | Micron Technology, Inc. | Autonomous memory architecture |
US20110320894A1 (en) * | 2010-06-28 | 2011-12-29 | Qualcomm Incorporated | Surrogate Circuit For Testing An Interface |
US8464107B2 (en) * | 2010-06-28 | 2013-06-11 | Qualcomm Incorporated | Surrogate circuit for testing an interface |
US8861246B2 (en) | 2010-12-16 | 2014-10-14 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
US9602080B2 (en) | 2010-12-16 | 2017-03-21 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
US9899994B2 (en) | 2010-12-16 | 2018-02-20 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
US9171597B2 (en) | 2013-08-30 | 2015-10-27 | Micron Technology, Inc. | Apparatuses and methods for providing strobe signals to memories |
US9437263B2 (en) | 2013-08-30 | 2016-09-06 | Micron Technology, Inc. | Apparatuses and methods for providing strobe signals to memories |
US10003675B2 (en) | 2013-12-02 | 2018-06-19 | Micron Technology, Inc. | Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data |
US10778815B2 (en) | 2013-12-02 | 2020-09-15 | Micron Technology, Inc. | Methods and systems for parsing and executing instructions to retrieve data using autonomous memory |
WO2016187221A1 (en) * | 2015-05-18 | 2016-11-24 | Micron Technology, Inc | Apparatus having dice to perorm refresh operations |
US10255963B2 (en) | 2015-05-18 | 2019-04-09 | Micron Technology, Inc. | Apparatus having dice to perform refresh operations |
US10008254B2 (en) | 2015-05-18 | 2018-06-26 | Micron Technology, Inc. | Apparatus having dice to perorm refresh operations |
US9570142B2 (en) | 2015-05-18 | 2017-02-14 | Micron Technology, Inc. | Apparatus having dice to perorm refresh operations |
CN112435709A (en) * | 2020-12-03 | 2021-03-02 | 中科驭数(北京)科技有限公司 | High-bandwidth memory test system, test method and test equipment |
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US20090300444A1 (en) | 2009-12-03 |
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