US20110260240A1 - Semiconductor Device - Google Patents

Semiconductor Device Download PDF

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Publication number
US20110260240A1
US20110260240A1 US13/177,292 US201113177292A US2011260240A1 US 20110260240 A1 US20110260240 A1 US 20110260240A1 US 201113177292 A US201113177292 A US 201113177292A US 2011260240 A1 US2011260240 A1 US 2011260240A1
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United States
Prior art keywords
cnt
gate
pattern
recess
semiconductor device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US13/177,292
Inventor
Chi Hwan Jang
Tae Yeon Yeo
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SK Hynix Inc
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Hynix Semiconductor Inc
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Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Priority to US13/177,292 priority Critical patent/US20110260240A1/en
Publication of US20110260240A1 publication Critical patent/US20110260240A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
    • Y10S977/742—Carbon nanotubes, CNTs

Definitions

  • a carbon nano tube for example, is a graphite hollow cylinder having a diameter on the order of several angstroms. Structurally, the CNT is similar to a hexagonal lattice of cylinder-type carbon. The CNT has a quantum characteristic at a low temperature, and the characteristics of a metal or a semiconductor, depending on its chirality.
  • the metal type CNT can carry a current of high density with a given resistance.
  • the semiconductor type CNT can be switched on and off like a field effect transistor (FET).
  • FET field effect transistor
  • the two types of nano tubes can also be combined (sharing electrons). Due to these characteristics, the CNT is an optimum material for the fabrication of a nano-meter-sized semiconductor circuit.
  • the CNT can be, for example, a one-dimensional electric conductor, which means that a one-dimensional quantum mechanical mode carries a current.
  • a CNT based transistor has advantageous electrical properties because diffusion in the material is inhibited, which can enhance device performance.
  • a gate of the current transistor generally includes gate forming materials such as tungsten (W), polysilicon, poly germanium silicide, and tungsten silicide.
  • gate forming materials such as tungsten (W), polysilicon, poly germanium silicide, and tungsten silicide.
  • W tungsten
  • polysilicon polysilicon
  • poly germanium silicide poly germanium silicide
  • tungsten silicide tungsten silicide
  • CNTs have been proposed as new gate forming materials to overcome the problems resulting from the scale-down of semiconductors.
  • a method for forming a gate using a CNT has not been commercialized.
  • the CNT has a cylinder structure, so that a contact surface with silicon (Si) becomes narrow. As a result, it is difficult to control subsequent processes after formation of the CNT gate. It is also necessary to prevent a short channel effect.
  • Various embodiments of the disclosure are directed to providing a semiconductor device and a method for manufacturing the same.
  • the method includes forming a gate structure using a CNT.
  • a gate resistance is reduced and a short channel effect is prevented.
  • a semiconductor device includes a semiconductor substrate comprising a recess, an insulating film disposed over the semiconductor substrate including the recess, and a CNT gate disposed over the recess including the insulating film.
  • the CNT gate includes a grown CNT pattern having a half-cylinder shape and an insulating material formed over the grown CNT pattern.
  • a method for manufacturing a semiconductor device includes etching a recess region of a semiconductor substrate to form a recess; and forming an insulating film over the substrate including the recess.
  • the method further includes forming a CNT seed layer over the insulating layer, and etching the CNT seed layer to form a CNT pattern.
  • the method includes growing the CNT pattern to form a grown CNT pattern.
  • the method further includes forming an insulating material over the grown CNT pattern to form a CNT gate.
  • the recess is formed by an isotropic-etching process.
  • the CNT seed layer is formed by a process selected from the group consisting of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electricity, laser, plasma, vapor synthesis, electrolysis, and combinations thereof.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • electricity laser, plasma, vapor synthesis, electrolysis, and combinations thereof.
  • the CNT pattern is horizontally grown.
  • the insulating material includes a material selected from the group consisting of an oxide film, a nitride film, and a stacked structure thereof.
  • the method can further include etching the insulating material using a CNT gate mask.
  • FIGS. 1 a to 1 j are cross-sectional views illustrating a semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the disclosure.
  • a photoresist film (not shown) is formed over a semiconductor substrate 100 .
  • a first photoresist pattern 110 can be formed, for example, by performing an exposing and developing process on the photoresist film, using a recess mask (not shown).
  • the semiconductor substrate 100 is etched using the first photoresist pattern 110 as an etching mask to form a recess 120 .
  • the recess 120 can be formed, for example, by an isotropic etching process.
  • an insulating film 130 is formed over the semiconductor substrate 100 including the recess 120 .
  • a CNT seed layer 140 is formed over the insulating film 130 .
  • the CNT seed layer 140 can be formed, for example, by chemical vapor deposition (CVD) using CH4, C2H6 or C4H8 gas including carbon in range of 200° C. to 1000° C., physical vapor deposition (PVD), atomic layer deposition (ALD), electricity, laser, plasma, vapor synthesis, electrolysis, and combinations thereof.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a photoresist film (not shown) is formed over the CNT seed layer 140 .
  • a second photoresist pattern 150 can be formed, for example, by performing an exposing and developing process on the photoresist layer using a CNT pattern mask.
  • the CNT seed layer 140 is etched using the second photoresist pattern 150 as an etching mask to form a CNT pattern 160 .
  • the CNT pattern 160 is grown to form a grown CNT pattern 165 having a half-cylinder shape. It is preferable not to remove the second photoresist pattern 150 located over the CNT pattern 160 before growing the grown CNT pattern 165 . Preferably, the CNT pattern 160 is grown horizontally.
  • an insulating material 170 is formed over the semiconductor substrate 100 , including the grown CNT pattern 165 .
  • the second photoresist pattern 150 can be removed before forming the insulating material 170 .
  • the insulating material 170 can include, for example, an oxide film, a nitride film, or a stacked structure thereof.
  • a photoresist film (not shown) is formed over the insulating material 170 .
  • a third photoresist pattern 180 can be formed, for example, by performing an exposing and developing process on the photoresist film, using a CNT gate mask.
  • the insulating material 170 is etched using the third photoresist pattern 180 as an etching mask to form a CNT gate 190 .
  • a method for manufacturing a semiconductor device includes etching a recess region of a semiconductor substrate 100 to form a recess 120 and forming an insulating film 130 and a CNT seed layer 140 over the substrate 100 including the recess 120 .
  • the method further includes etching the CNT seed layer 140 using a CNT pattern mask as an etching mask to form a CNT pattern 160 and growing the CNT pattern 160 to form a grown CNT pattern 165 .
  • the method also includes forming an insulating material 170 over the grown CNT pattern 165 to form a CNT gate 190 .
  • the method can further include etching the insulating material 170 using a CNT gate mask as an etching mask.

Abstract

Disclosed herein are a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a carbon nano tube (CNT). In order to prevent reduction of the gate resistance and the short channel effect, a CNT gate having a grown CNT pattern with a half-cylinder shape is formed over a recess of a semiconductor substrate. The CNT gate has the same effect as a recess gate, and can prevent the short channel effect, improve the speed, and the lower power characteristic of semiconductor devices.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This is a division of U.S. application Ser. No. 12/327,346 filed Dec. 3, 2008, which claims the priority benefit under USC 119 of KR 10-2008-0041443 filed May 2, 2008, the entire respective disclosures of which are incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • Depending on electric characteristics, nano tubes can be embodied into electric elements such as diodes and transistors. A carbon nano tube (CNT), for example, is a graphite hollow cylinder having a diameter on the order of several angstroms. Structurally, the CNT is similar to a hexagonal lattice of cylinder-type carbon. The CNT has a quantum characteristic at a low temperature, and the characteristics of a metal or a semiconductor, depending on its chirality.
  • The metal type CNT can carry a current of high density with a given resistance. The semiconductor type CNT can be switched on and off like a field effect transistor (FET). The two types of nano tubes can also be combined (sharing electrons). Due to these characteristics, the CNT is an optimum material for the fabrication of a nano-meter-sized semiconductor circuit. The CNT can be, for example, a one-dimensional electric conductor, which means that a one-dimensional quantum mechanical mode carries a current.
  • A CNT based transistor has advantageous electrical properties because diffusion in the material is inhibited, which can enhance device performance.
  • In the manufacturing of semiconductor devices, a gate of the current transistor generally includes gate forming materials such as tungsten (W), polysilicon, poly germanium silicide, and tungsten silicide. However, because these gate forming materials have a large resistance, the whole speed of the transistor is reduced and power consumption is increased. Additionally, when the size of the semiconductor is decreased by a conventional method, a resistance of a gate is increased. Thus, it is necessary to develop improved materials.
  • CNTs have been proposed as new gate forming materials to overcome the problems resulting from the scale-down of semiconductors. A method for forming a gate using a CNT, however, has not been commercialized.
  • In the conventional method for forming a CNT, the CNT has a cylinder structure, so that a contact surface with silicon (Si) becomes narrow. As a result, it is difficult to control subsequent processes after formation of the CNT gate. It is also necessary to prevent a short channel effect.
    • SUMMARY OF THE INVENTION
  • Various embodiments of the disclosure are directed to providing a semiconductor device and a method for manufacturing the same. The method includes forming a gate structure using a CNT. By forming the gate using a CNT pattern having a half-cylinder shape, a gate resistance is reduced and a short channel effect is prevented.
  • According to an embodiment of the invention, a semiconductor device includes a semiconductor substrate comprising a recess, an insulating film disposed over the semiconductor substrate including the recess, and a CNT gate disposed over the recess including the insulating film. The CNT gate includes a grown CNT pattern having a half-cylinder shape and an insulating material formed over the grown CNT pattern.
  • According to an embodiment of the invention, a method for manufacturing a semiconductor device includes etching a recess region of a semiconductor substrate to form a recess; and forming an insulating film over the substrate including the recess. The method further includes forming a CNT seed layer over the insulating layer, and etching the CNT seed layer to form a CNT pattern. Still further the method includes growing the CNT pattern to form a grown CNT pattern. The method further includes forming an insulating material over the grown CNT pattern to form a CNT gate.
  • Preferably, the recess is formed by an isotropic-etching process.
  • Preferably, the CNT seed layer is formed by a process selected from the group consisting of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electricity, laser, plasma, vapor synthesis, electrolysis, and combinations thereof.
  • Preferably, the CNT pattern is horizontally grown.
  • Preferably, the insulating material includes a material selected from the group consisting of an oxide film, a nitride film, and a stacked structure thereof.
  • The method can further include etching the insulating material using a CNT gate mask.
  • Additional features of the invention may become apparent to those having ordinary skill in the art from a review of the following detailed description, taken in conjunction with the drawings, and the appended claims.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawings. FIGS. 1 a to 1 j are cross-sectional views illustrating a semiconductor device and a method for manufacturing a semiconductor device according to an embodiment of the disclosure.
  • While the disclosed device and method are susceptible of embodiments in various forms, a specific embodiment is illustrated in the drawings (and will hereafter be described), with the understanding that the disclosure is intended to be illustrative, and is not intended to limit the invention to the specific embodiment described and illustrated herein.
    •  DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT
  • The invention will be described in detail with reference to the drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity, and a layer can be directly formed over a different layer or a substrate or a third layer can be formed between the different layer and the substrate.
  • Referring to FIG. 1 a, a photoresist film (not shown) is formed over a semiconductor substrate 100. A first photoresist pattern 110 can be formed, for example, by performing an exposing and developing process on the photoresist film, using a recess mask (not shown).
  • Referring to FIG. 1 b, the semiconductor substrate 100 is etched using the first photoresist pattern 110 as an etching mask to form a recess 120. The recess 120 can be formed, for example, by an isotropic etching process.
  • Referring to FIGS. 1 c and 1 d, an insulating film 130 is formed over the semiconductor substrate 100 including the recess 120. A CNT seed layer 140 is formed over the insulating film 130. The CNT seed layer 140 can be formed, for example, by chemical vapor deposition (CVD) using CH4, C2H6 or C4H8 gas including carbon in range of 200° C. to 1000° C., physical vapor deposition (PVD), atomic layer deposition (ALD), electricity, laser, plasma, vapor synthesis, electrolysis, and combinations thereof.
  • A photoresist film (not shown) is formed over the CNT seed layer 140. Referring to FIG. 1 e, a second photoresist pattern 150 can be formed, for example, by performing an exposing and developing process on the photoresist layer using a CNT pattern mask.
  • Referring to FIG. 1 f, the CNT seed layer 140 is etched using the second photoresist pattern 150 as an etching mask to form a CNT pattern 160.
  • Referring to FIG. 1 g, the CNT pattern 160 is grown to form a grown CNT pattern 165 having a half-cylinder shape. It is preferable not to remove the second photoresist pattern 150 located over the CNT pattern 160 before growing the grown CNT pattern 165. Preferably, the CNT pattern 160 is grown horizontally.
  • Referring to FIG. 1 h, an insulating material 170 is formed over the semiconductor substrate 100, including the grown CNT pattern 165. The second photoresist pattern 150 can be removed before forming the insulating material 170. The insulating material 170 can include, for example, an oxide film, a nitride film, or a stacked structure thereof.
  • A photoresist film (not shown) is formed over the insulating material 170. Referring to FIGS. 1 i and 1 j, a third photoresist pattern 180 can be formed, for example, by performing an exposing and developing process on the photoresist film, using a CNT gate mask. The insulating material 170 is etched using the third photoresist pattern 180 as an etching mask to form a CNT gate 190.
  • In accordance with an embodiment of the invention, a method for manufacturing a semiconductor device includes etching a recess region of a semiconductor substrate 100 to form a recess 120 and forming an insulating film 130 and a CNT seed layer 140 over the substrate 100 including the recess 120. The method further includes etching the CNT seed layer 140 using a CNT pattern mask as an etching mask to form a CNT pattern 160 and growing the CNT pattern 160 to form a grown CNT pattern 165. The method also includes forming an insulating material 170 over the grown CNT pattern 165 to form a CNT gate 190. The method can further include etching the insulating material 170 using a CNT gate mask as an etching mask.
  • The above embodiments of the disclosure are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the disclosure may be implemented in a dynamic random access memory (DRAM) device or a nonvolatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims (3)

1. A semiconductor device comprising:
an insulating film formed over a semiconductor substrate; and
a carbon nano tube gate obtained by growing a carbon nano tube seed layer over the insulating film.
2. The semiconductor device according to claim 1, wherein the carbon nano tube gate is formed over a recess obtained by etching the semiconductor substrate.
3. The semiconductor device according to claim 1, further comprising an insulating material for insulating the carbon nano tube gate.
US13/177,292 2008-05-02 2011-07-06 Semiconductor Device Abandoned US20110260240A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/177,292 US20110260240A1 (en) 2008-05-02 2011-07-06 Semiconductor Device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2008-0041443 2008-05-02
KR1020080041443A KR101010115B1 (en) 2008-05-02 2008-05-02 Semiconductor Device and Method for Manufacturing the same
US12/327,346 US7998850B2 (en) 2008-05-02 2008-12-03 Semiconductor device and method for manufacturing the same
US13/177,292 US20110260240A1 (en) 2008-05-02 2011-07-06 Semiconductor Device

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Cited By (1)

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TWI638447B (en) * 2016-12-28 2018-10-11 上海新昇半導體科技有限公司 Junctionless gate array memory and the method for preparing the same

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US9966431B2 (en) * 2016-03-23 2018-05-08 Globalfoundries Inc. Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line

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US20070152284A1 (en) * 2005-12-29 2007-07-05 Jeong Ho Park Transistor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI638447B (en) * 2016-12-28 2018-10-11 上海新昇半導體科技有限公司 Junctionless gate array memory and the method for preparing the same

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US7998850B2 (en) 2011-08-16
US20090273025A1 (en) 2009-11-05
KR101010115B1 (en) 2011-01-24
KR20090115539A (en) 2009-11-05

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