US20110241789A1 - Integrated circuit capable of repeatedly using current - Google Patents
Integrated circuit capable of repeatedly using current Download PDFInfo
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- US20110241789A1 US20110241789A1 US12/885,494 US88549410A US2011241789A1 US 20110241789 A1 US20110241789 A1 US 20110241789A1 US 88549410 A US88549410 A US 88549410A US 2011241789 A1 US2011241789 A1 US 2011241789A1
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- 230000008878 coupling Effects 0.000 claims description 23
- 238000010168 coupling process Methods 0.000 claims description 23
- 238000005859 coupling reaction Methods 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 230000003287 optical effect Effects 0.000 description 12
- 238000004891 communication Methods 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 5
- 238000011084 recovery Methods 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 4
- 239000000835 fiber Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1221—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising multiple amplification stages connected in cascade
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
Definitions
- the present invention relates to an integrated circuit of an oscillator and a divider, and more particularly, to an integrated circuit capable of repeatedly using current which has the reduced circuit area and low power consumption.
- the main transmission format of the optical communication system is OC-48 (2.5 Gb/s), furthermore, in next generation, the developing targets of the transmission format are OC-192 (10 Gb/s) and OC-768 (40 Gb/s).
- the conventional optical communication system 1 ′ includes: a transmitting interface 11 ′, a fiber 12 ′ and a receiving interface 13 ′, wherein data are processed and transformed by a first digital circuit 111 ′, a multiplexer 112 ′, a laser-driving device 113 ′ of the transmitting interface 11 ′ in turns, then the data are transformed to an optical format by a laser diode 114 ′ and are transmitted to the receiving interface 13 ′ via the fiber 12 ′; after that, in the receiving interface 13 ′, the data are transformed to an optical current signal by a photodiode 131 ′ and further transformed to a current signal through a transimpedance amplifier (TIA) 132 ′ and a limiting amplifier 133 ′, then a clock and data recovery Circuit 134 ′ recovers the data and the clock thereof to clear signal; finally, the data are divided to multi data by a transimpedance amplifier (TIA) 132 ′ and a limiting amplifier 133 ′, then a clock and
- phase-locked loop circuit (the clock and data recovery circuit 134 ′) includes: a phase frequency detector 1341 ′, a charge pump circuit 1342 ′, a low pass filter 1343 ′, a voltage-controlled oscillator 1344 ′, a buffer 1345 ′, a first divider 1346 ′, and a divider chain 1347 ′, wherein the voltage-controlled oscillator 1344 ′, the buffer 1345 ′and the first divider 1346 ′ belong to high-speed operation circuits, which are the circuits causing mass current and power consumption in the clock and data recovery circuit 134 ′.
- the circuit is continuously operated under high temperature environment and causing, the power consumption per unit area must be strictly limited in an advanced integrated circuit chip with highly reduced circuit area for avoiding the circuit from faction fail and getting reliability problem.
- the circuit area and the power consumption are very important when designing the integrated circuit of the voltage-controlled oscillator, the buffer and the first divider belonging to high-speed operation circuit.
- the inventor of the present application has made great efforts to make inventive research thereon and eventually provided an integrated circuit capable of repeatedly using current.
- the primary objective of the present invention is to provide an integrated circuit capable of repeatedly using current, in which an oscillator and a divider belonging to high frequency operation circuit of an optical communication system are integrated by one single driving current, so as to substantially reduce the whole circuit area and the power consumption of the oscillator and the divider.
- the inventor proposes an integrated circuit capable of repeatedly using current, comprising: a first differential input, which as an inverting amplifier and has a first input, a second input, a first output, and a second output;
- first cross couple pair having a first couple input, a second couple input, and a first couple output, the first cross couple pair as an negative impedance of the first differential input by way of respectively connecting the first couple input and the second couple input to the first output and the second output;
- a second differential input which as the inverting amplifier and has a third input, a fourth input, a third output, and a fourth output;
- a second cross couple pair having a third couple input, a fourth couple input, and a second couple output, the second cross couple pair as the negative impedance of the second differential input by means of connecting the third couple input and the fourth couple input to the third output and the fourth output, respectively;
- a voltage-controlled oscillator having a first oscillator input, a second oscillator input, a first oscillator output, and a second oscillator output, the first oscillator input and the second oscillator input respectively connect to the first couple output and the second couple output for coupling the voltage-controlled oscillator to the first cross couple pair and the second cross couple pair, so as to execute voltage-controlled oscillation of the signal outputted from the first cross couple pair and the second cross couple pair;
- a divider consists of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, moreover, through the connection of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, the divider and the voltage-controlled oscillator are driven by only one single current.
- FIG. 1 is a framework diagram of a conventional optical communication system
- FIG. 2 is the framework diagram of a phase-locked loop circuit
- FIG. 3 is the framework diagram of an integrated circuit capable of repeatedly using current according to the present invention.
- FIG. 4 is a circuit diagram of the integrated circuit capable of repeatedly using current according to the present invention.
- FIGS. 5A and 5B are output spectrum diagrams of the integrated circuit capable of repeatedly using current.
- FIGS. 6A and 6B are phase noise spectrum diagrams of the integrated circuit capable of repeatedly using current.
- the integrated circuit 1 includes: a first differential input 11 , a first cross couple pair 12 , a second differential input 13 , a second cross couple pair 14 , and a voltage-controlled oscillator 15 .
- the first differential input 11 as an inverting amplifier and has a first input V 1 in , a second input V 1 in ′, a first output V 1 o, and a second output V 1 o ′.
- the first cross couple pair 12 has a first couple input Vc 1 in , a second couple input Vc 1 in ′, and a first couple output Vc 1 o, and the first cross couple pair 12 as an negative impedance of the first differential input 11 by way of respectively connecting the first couple input Vc 1 in and the second couple input Vc 1 in ′ to the first output V 1 o and the second output V 1 o ′.
- the second differential input 13 as the inverting amplifier and has a third input V 2 in , a fourth input V 2 in ′, a third output V 2 o, and a fourth output V 2 o ′.
- the second cross couple pair 14 has a third couple input Vc 2 in , a fourth couple input Vc 2 in ′, and a second couple output Vc 2 o, the second cross couple pair 14 as the negative impedance of the second differential input 13 by means of connecting the third couple input Vc 2 in and the fourth couple input Vc 2 in ′ to the third output V 2 o and the fourth output V 2 o ′, respectively.
- the voltage-controlled oscillator 15 has a first oscillator input Vo_in, a second oscillator input Vo_in′, a first oscillator output Vo_out, and a second oscillator output Vo_out′, the first oscillator input Vo_in and the second oscillator input Vo_in′ respectively connect to the first couple output Vc 1 o and the second couple output Vc 2 o for coupling the voltage-controlled oscillator 15 to the first cross couple pair 12 and the second cross couple pair 14 , so as to execute voltage-controlled oscillation of the signal outputted from the first cross couple pair 12 and the second cross couple pair 14 .
- a divider consists of the first differential input 11 , the first cross couple pair 12 , the second differential input 13 , and the second cross couple pair 14 , moreover, through the connection of the first differential input 11 , the first cross couple pair 12 , the second differential input 13 , and the second cross couple pair 14 , the divider and the voltage-controlled oscillator 15 are driven by only one single current; furthermore, the first couple output Vc 1 o and the second couple output Vc 2 o respectively couple to the second input 13 and the first input 11 for forming a positive feedback.
- the first differential input 11 includes: a first transistor Q 1 , a first amplifying resistor R 1 , a second transistor Q 2 , and a second amplifying resistor R 2 , wherein the first amplifying resistor R 1 as an amplifying resistor of the first transistor Q 1 .
- One terminal of the first amplifying resistor R 1 couples to a drain terminal of the first transistor Q 1 and another terminal thereof couples to a DC bias VDD.
- the second transistor Q 2 connects to the first transistor in parallel Q 1 .
- the second amplifying resistor R 2 as the amplifying resistor of the second transistor Q 2 .
- one terminal of the second amplifying resistor R 2 couples to the drain terminal of the second transistor Q 2 and another terminal thereof couples to the DC bias VDD.
- a gate terminal of the first transistor Q 1 is the first input V 1 in of the first differential input 11
- the gate terminal of the second transistor Q 2 is the second input V 1 in ′ of the first differential input 11
- both a source terminal of the first transistor Q 1 and the source terminal of the second transistor Q 2 couple to the second couple output Vc 2 o.
- the first cross couple pair 12 further includes a third transistor Q 3 and a fourth transistor Q 4 . Wherein the gate terminal of the third transistor Q 3 connects to the drain terminal of the fourth transistor Q 4 , and the gate terminal of the fourth transistor Q 4 connects to the drain terminal of the third transistor Q 3 , moreover, the drain terminals of the third transistor Q 3 and the fourth transistor Q 4 couple to each other.
- the second differential input 13 further includes: a fifth transistor Q 3 , a third amplifying resistor R 3 , a sixth transistor Q 6 , and a fourth amplifying resistor R 4 , wherein the third amplifying resistor R 3 as the amplifying resistor of the fifth transistor Q 5 .
- One terminal of the third amplifying resistor R 3 couples to the drain terminal of the fifth transistor Q 5 and another terminal thereof couples to the DC bias VDD.
- the sixth transistor Q 6 connects to the fifth transistor Q 5 in parallel, and the fourth amplifying resistor R 4 as the amplifying resistor of the sixth transistor Q 6 .
- One terminal of the fourth amplifying resistor R 4 couples to the drain terminal of the sixth transistor Q 6 and another terminal thereof couples to the DC bias VDD.
- the gate terminal of the fifth transistor Q 2 is the third input V 2 in of the second differential input 13
- the gate terminal of the sixth transistor Q 6 is the fourth input V 2 in ′ of the second differential input 13
- both the source terminals the fifth transistor Q 5 and the sixth transistor Q 6 couple to the first couple output Vc 1 o
- the second cross couple pair 14 further includes a seventh transistor Q 7 and an eighth transistor Q 8 .
- the gate terminal of the seventh transistor Q 7 connects to the drain terminal of the eighth transistor Q 8
- the gate terminal of the eighth transistor Q 8 connects to the drain terminal of the seventh transistor Q 7 , furthermore, the drain terminals of the seventh transistor Q 7 and the eighth transistor Q 8 couple to each other.
- the voltage-controlled oscillator further includes: a ninth transistor Q 9 , a tenth transistor Q 10 , a first tuning capacitor C 1 , a second tuning capacitor C 2 , and an inductor L, wherein the tenth transistor Q 10 couples to the drain terminal of the ninth transistor Q 9 by the gate terminal thereof, and the gate terminal of the ninth transistor Q 9 couples to the drain terminal of the tenth transistor Q 10 , so as to make the ninth transistor Q 9 and the tenth transistor Q 10 forming the negative resistor.
- One terminal of the first tuning capacitor C 1 couples to the drain terminal of the ninth transistor Q 9 , and another terminal thereof couples to a tuning voltage Vtune.
- One terminal of the second tuning capacitor C 2 couples to the drain terminal of the tenth transistor Q 10 , and another terminal thereof couples to the tuning voltage Vtune.
- One terminal of the inductor L couples to the drain terminal of the ninth transistor Q 9 and another terminal thereof couples to drain terminal of the tenth transistor Q 10 , so that the inductor L forms two LC oscillators with the first tuning capacitor C 1 and the second tuning capacitor C 2 .
- the LC tank of the LC oscillator induces an equivalent parallel resistance when the LC oscillator oscillates, and the equivalent parallel resistance may be offset by the negative formed by the ninth transistor Q 9 and the tenth transistor Q 10 , so as to maintain the oscillation energy.
- the output of the voltage-controlled oscillator 15 not connecting any buffer amplifiers that makes the voltage-controlled oscillator 15 has a simple output load and suppresses the noise.
- the gate terminal of the first transistor Q 1 is the first input V 1 in of the first differential input 11
- the gate terminal of the first transistor Q 1 couples to the drain terminal of the eighth transistor Q 8
- a latch effect is formed.
- the gate terminal of the second transistor Q 2 is the second input V 1 in ′ of the first differential input 11
- the gate terminal of the second transistor Q 2 couples to the drain terminal of the seventh transistor Q 7 and the latch effect is formed.
- the integrated circuit 1 of the present invention integrates the divider and the voltage-controlled oscillator 15 , so as to drive the divider by way of the single current of the voltage-controlled oscillator 15 .
- a simulation software of high frequency circuit has been used, please refer to FIGS. 5A and 5B , output spectrum diagrams of the integrated circuit capable of repeatedly using current are illustrated.
- FIG. 5A when the tuning voltage Vtune is 0V, the first oscillator output Vo_out outputs a first high frequency signal with a output power ⁇ 7.5 dBm around frequency 9.313 GHz; Furthermore, As shown in FIG. 5B , when the tuning voltage Vtune is 1.8V, the first oscillator output Vo_out outputs the first high frequency signal with the output power ⁇ 6.91 dBm around frequency 9.69 GHz.
- phase noise spectrum diagrams of the integrated circuit capable of repeatedly using current are illustrated.
- the integrated circuit 1 of the present invention when the tuning voltage Vtune is 0V, the integrated circuit 1 of the present invention induced a phase noise with a measurement value ⁇ 113.458 dBc/Hz around frequency 1 MHz;
- the tuning voltage Vtune when the tuning voltage Vtune is 1.8V, the integrated circuit 1 induced the phase noise with the measurement value ⁇ 113.458 dBc/Hz around frequency 1 MHz. According to the above mention, it is easily to know that the integrated circuit 1 induces slight phase noise.
- the integrated circuit capable of repeatedly using current has a excellent simulation performance with the oscillator output frequency 9.3 ⁇ 9.7 GHz, the power consumption 3.9 mW and the phase noise ⁇ 113 ⁇ 110 dBc/Hz.
- the present invention has the following advantages:
Abstract
The invention relates to an integrated circuit capable of repeatedly using current, the integrated circuit comprises: a first differential input, a first cross couple pair, a second differential input, a second cross couple pair, and a voltage-controlled oscillator, wherein a divider consists of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, moreover, through the connection of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, the divider and the voltage-controlled oscillator may be drove by only one single current, so that the circuit area, the power consumption, and the phase noise of the integrated circuit are simultaneously reduced.
Description
- 1. Technical Field
- The present invention relates to an integrated circuit of an oscillator and a divider, and more particularly, to an integrated circuit capable of repeatedly using current which has the reduced circuit area and low power consumption.
- 2. Description of Related Art
- With the development of the Internet, demands of the data transmission speed and the data transmission capacity are increasing. For this reason, an optical communication system using a fiber as a data transmission medium is extensively used in each of levels of the Internet Network. The main transmission format of the optical communication system is OC-48 (2.5 Gb/s), furthermore, in next generation, the developing targets of the transmission format are OC-192 (10 Gb/s) and OC-768 (40 Gb/s).
- Referring to
FIG. 1 , a framework diagram of a conventional optical communication system is illustrated. As shown inFIG. 1 , the conventionaloptical communication system 1′ includes: atransmitting interface 11′, afiber 12′ and areceiving interface 13′, wherein data are processed and transformed by a firstdigital circuit 111′, amultiplexer 112′, a laser-driving device 113′ of thetransmitting interface 11′ in turns, then the data are transformed to an optical format by alaser diode 114′ and are transmitted to thereceiving interface 13′ via thefiber 12′; after that, in thereceiving interface 13′, the data are transformed to an optical current signal by aphotodiode 131′ and further transformed to a current signal through a transimpedance amplifier (TIA) 132′ and alimiting amplifier 133′, then a clock anddata recovery Circuit 134′ recovers the data and the clock thereof to clear signal; finally, the data are divided to multi data by ademux 135′ and transmitted to a seconddigital circuit 136′ for processing. - In the conventional
optical communication system 1′, the clock anddata recovery circuit 134′ can be a phase-locked loop circuit, referring toFIG. 2 , the framework diagram of a phase-locked loop circuit is illustrated, as shown inFIG. 2 , phase-locked loop circuit (the clock anddata recovery circuit 134′) includes: aphase frequency detector 1341′, acharge pump circuit 1342′, alow pass filter 1343′, a voltage-controlledoscillator 1344′, abuffer 1345′, afirst divider 1346′, and adivider chain 1347′, wherein the voltage-controlledoscillator 1344′, thebuffer 1345′and thefirst divider 1346′ belong to high-speed operation circuits, which are the circuits causing mass current and power consumption in the clock anddata recovery circuit 134′. - However, as the circuit is continuously operated under high temperature environment and causing, the power consumption per unit area must be strictly limited in an advanced integrated circuit chip with highly reduced circuit area for avoiding the circuit from faction fail and getting reliability problem. Thus, in the conventional optical communication system, the circuit area and the power consumption are very important when designing the integrated circuit of the voltage-controlled oscillator, the buffer and the first divider belonging to high-speed operation circuit.
- Accordingly, in view of the whole circuit area and the power consumption of the voltage-controlled oscillator, the buffer and the first divider in the conventional optical communication system, the inventor of the present application has made great efforts to make inventive research thereon and eventually provided an integrated circuit capable of repeatedly using current.
- The primary objective of the present invention is to provide an integrated circuit capable of repeatedly using current, in which an oscillator and a divider belonging to high frequency operation circuit of an optical communication system are integrated by one single driving current, so as to substantially reduce the whole circuit area and the power consumption of the oscillator and the divider.
- Accordingly, to achieve the abovementioned primary objective, the inventor proposes an integrated circuit capable of repeatedly using current, comprising: a first differential input, which as an inverting amplifier and has a first input, a second input, a first output, and a second output;
- a first cross couple pair, having a first couple input, a second couple input, and a first couple output, the first cross couple pair as an negative impedance of the first differential input by way of respectively connecting the first couple input and the second couple input to the first output and the second output;
- a second differential input, which as the inverting amplifier and has a third input, a fourth input, a third output, and a fourth output;
- a second cross couple pair, having a third couple input, a fourth couple input, and a second couple output, the second cross couple pair as the negative impedance of the second differential input by means of connecting the third couple input and the fourth couple input to the third output and the fourth output, respectively; and
- a voltage-controlled oscillator, having a first oscillator input, a second oscillator input, a first oscillator output, and a second oscillator output, the first oscillator input and the second oscillator input respectively connect to the first couple output and the second couple output for coupling the voltage-controlled oscillator to the first cross couple pair and the second cross couple pair, so as to execute voltage-controlled oscillation of the signal outputted from the first cross couple pair and the second cross couple pair;
- wherein a divider consists of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, moreover, through the connection of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, the divider and the voltage-controlled oscillator are driven by only one single current.
- The invention as well as a preferred mode of use and advantages thereof will be best understood by referring to the following detailed description of an illustrative embodiment in conjunction with the accompanying drawings, wherein:
-
FIG. 1 is a framework diagram of a conventional optical communication system; -
FIG. 2 is the framework diagram of a phase-locked loop circuit; -
FIG. 3 is the framework diagram of an integrated circuit capable of repeatedly using current according to the present invention; -
FIG. 4 is a circuit diagram of the integrated circuit capable of repeatedly using current according to the present invention; -
FIGS. 5A and 5B are output spectrum diagrams of the integrated circuit capable of repeatedly using current; and -
FIGS. 6A and 6B are phase noise spectrum diagrams of the integrated circuit capable of repeatedly using current. - To more clearly describe an integrated circuit capable of repeatedly using current according to the present invention, embodiments of the present invention will be described in detail with reference to the attached drawings hereinafter.
- Referring to
FIG. 3 , a framework diagram of an integrated circuit capable of repeatedly using current according to the present invention is illustrated, as shown inFIG. 3 , the integratedcircuit 1 includes: a firstdifferential input 11, a firstcross couple pair 12, a seconddifferential input 13, a secondcross couple pair 14, and a voltage-controlledoscillator 15. - Continuously referring to
FIG. 3 , the firstdifferential input 11 as an inverting amplifier and has a first input V1 in, a second input V1 in′, a first output V1 o, and a second output V1 o′. The firstcross couple pair 12 has a first couple input Vc1 in, a second couple input Vc1 in′, and a first couple output Vc1 o, and the firstcross couple pair 12 as an negative impedance of the firstdifferential input 11 by way of respectively connecting the first couple input Vc1 in and the second couple input Vc1 in′ to the first output V1 o and the second output V1 o′. The seconddifferential input 13 as the inverting amplifier and has a third input V2 in, a fourth input V2 in′, a third output V2 o, and a fourth output V2 o′. The secondcross couple pair 14 has a third couple input Vc2 in, a fourth couple input Vc2 in′, and a second couple output Vc2 o, the secondcross couple pair 14 as the negative impedance of the seconddifferential input 13 by means of connecting the third couple input Vc2 in and the fourth couple input Vc2 in′ to the third output V2 o and the fourth output V2 o′, respectively. The voltage-controlledoscillator 15 has a first oscillator input Vo_in, a second oscillator input Vo_in′, a first oscillator output Vo_out, and a second oscillator output Vo_out′, the first oscillator input Vo_in and the second oscillator input Vo_in′ respectively connect to the first couple output Vc1 o and the second couple output Vc2 o for coupling the voltage-controlledoscillator 15 to the firstcross couple pair 12 and the secondcross couple pair 14, so as to execute voltage-controlled oscillation of the signal outputted from the firstcross couple pair 12 and the secondcross couple pair 14. - In the
integrated circuit 1 described above, a divider consists of the firstdifferential input 11, the firstcross couple pair 12, the seconddifferential input 13, and the secondcross couple pair 14, moreover, through the connection of the firstdifferential input 11, the firstcross couple pair 12, the seconddifferential input 13, and the secondcross couple pair 14, the divider and the voltage-controlledoscillator 15 are driven by only one single current; furthermore, the first couple output Vc1 o and the second couple output Vc2 o respectively couple to thesecond input 13 and thefirst input 11 for forming a positive feedback. - Please refer to
FIG. 4 , which illustrates a circuit diagram of the integrated circuit capable of repeatedly using current according to the present invention, as shown inFIG. 4 , the firstdifferential input 11 includes: a first transistor Q1, a first amplifying resistor R1, a second transistor Q2, and a second amplifying resistor R2, wherein the first amplifying resistor R1 as an amplifying resistor of the first transistor Q1. One terminal of the first amplifying resistor R1 couples to a drain terminal of the first transistor Q1 and another terminal thereof couples to a DC bias VDD. The second transistor Q2 connects to the first transistor in parallel Q1. The second amplifying resistor R2 as the amplifying resistor of the second transistor Q2. one terminal of the second amplifying resistor R2 couples to the drain terminal of the second transistor Q2 and another terminal thereof couples to the DC bias VDD. - Referring to
FIGS. 3 and 4 together, a gate terminal of the first transistor Q1 is the first input V1 in of the firstdifferential input 11, the gate terminal of the second transistor Q2 is the second input V1 in′ of the firstdifferential input 11, and both a source terminal of the first transistor Q1 and the source terminal of the second transistor Q2 couple to the second couple output Vc2 o. The firstcross couple pair 12 further includes a third transistor Q3 and a fourth transistor Q4. Wherein the gate terminal of the third transistor Q3 connects to the drain terminal of the fourth transistor Q4, and the gate terminal of the fourth transistor Q4 connects to the drain terminal of the third transistor Q3, moreover, the drain terminals of the third transistor Q3 and the fourth transistor Q4 couple to each other. - Referring to
FIG. 4 again, the seconddifferential input 13 further includes: a fifth transistor Q3, a third amplifying resistor R3, a sixth transistor Q6, and a fourth amplifying resistor R4, wherein the third amplifying resistor R3 as the amplifying resistor of the fifth transistor Q5. One terminal of the third amplifying resistor R3 couples to the drain terminal of the fifth transistor Q5 and another terminal thereof couples to the DC bias VDD. The sixth transistor Q6 connects to the fifth transistor Q5 in parallel, and the fourth amplifying resistor R4 as the amplifying resistor of the sixth transistor Q6. One terminal of the fourth amplifying resistor R4 couples to the drain terminal of the sixth transistor Q6 and another terminal thereof couples to the DC bias VDD. - Please refer to
FIGS. 3 and 4 again, the gate terminal of the fifth transistor Q2 is the third input V2 in of the seconddifferential input 13, the gate terminal of the sixth transistor Q6 is the fourth input V2 in′ of the seconddifferential input 13, and both the source terminals the fifth transistor Q5 and the sixth transistor Q6 couple to the first couple output Vc1 o. Moreover, the secondcross couple pair 14 further includes a seventh transistor Q7 and an eighth transistor Q8. The gate terminal of the seventh transistor Q7 connects to the drain terminal of the eighth transistor Q8, and the gate terminal of the eighth transistor Q8 connects to the drain terminal of the seventh transistor Q7, furthermore, the drain terminals of the seventh transistor Q7 and the eighth transistor Q8 couple to each other. - Continuously referring to
FIG. 4 , the voltage-controlled oscillator further includes: a ninth transistor Q9, a tenth transistor Q10, a first tuning capacitor C1, a second tuning capacitor C2, and an inductor L, wherein the tenth transistor Q10 couples to the drain terminal of the ninth transistor Q9 by the gate terminal thereof, and the gate terminal of the ninth transistor Q9 couples to the drain terminal of the tenth transistor Q10, so as to make the ninth transistor Q9 and the tenth transistor Q10 forming the negative resistor. One terminal of the first tuning capacitor C1 couples to the drain terminal of the ninth transistor Q9, and another terminal thereof couples to a tuning voltage Vtune. One terminal of the second tuning capacitor C2 couples to the drain terminal of the tenth transistor Q10, and another terminal thereof couples to the tuning voltage Vtune. One terminal of the inductor L couples to the drain terminal of the ninth transistor Q9 and another terminal thereof couples to drain terminal of the tenth transistor Q10, so that the inductor L forms two LC oscillators with the first tuning capacitor C1 and the second tuning capacitor C2. Thus, the LC tank of the LC oscillator induces an equivalent parallel resistance when the LC oscillator oscillates, and the equivalent parallel resistance may be offset by the negative formed by the ninth transistor Q9 and the tenth transistor Q10, so as to maintain the oscillation energy. - Moreover, in the above-mentioned voltage-controlled
oscillator 15, it is able to adjust the capacitances of the first capacitor and the second capacitor via modulating the tuning voltage Vtune, so as to modulate the output oscillation frequency of the LC oscillators. Besides, the output of the voltage-controlledoscillator 15 not connecting any buffer amplifiers that makes the voltage-controlledoscillator 15 has a simple output load and suppresses the noise. As shown inFIG. 4 , for the gate terminal of the first transistor Q1 is the first input V1 in of the firstdifferential input 11, the gate terminal of the first transistor Q1 couples to the drain terminal of the eighth transistor Q8, then a latch effect is formed. Similarly, for the gate terminal of the second transistor Q2 is the second input V1 in′ of the firstdifferential input 11, the gate terminal of the second transistor Q2 couples to the drain terminal of the seventh transistor Q7 and the latch effect is formed. - The
integrated circuit 1 of the present invention integrates the divider and the voltage-controlledoscillator 15, so as to drive the divider by way of the single current of the voltage-controlledoscillator 15. In order to prove the practicability of theintegrated circuit 1, a simulation software of high frequency circuit has been used, please refer toFIGS. 5A and 5B , output spectrum diagrams of the integrated circuit capable of repeatedly using current are illustrated. As shown inFIG. 5A , when the tuning voltage Vtune is 0V, the first oscillator output Vo_out outputs a first high frequency signal with a output power −7.5 dBm around frequency 9.313 GHz; Furthermore, As shown inFIG. 5B , when the tuning voltage Vtune is 1.8V, the first oscillator output Vo_out outputs the first high frequency signal with the output power −6.91 dBm around frequency 9.69 GHz. - Referring to
FIGS. 6A and 6B , phase noise spectrum diagrams of the integrated circuit capable of repeatedly using current are illustrated. As shown inFIG. 6A , when the tuning voltage Vtune is 0V, theintegrated circuit 1 of the present invention induced a phase noise with a measurement value −113.458 dBc/Hz aroundfrequency 1 MHz; Furthermore, As shown inFIG. 6B , when the tuning voltage Vtune is 1.8V, theintegrated circuit 1 induced the phase noise with the measurement value −113.458 dBc/Hz aroundfrequency 1 MHz. According to the above mention, it is easily to know that theintegrated circuit 1 induces slight phase noise. Moreover, in a operation voltage 1.8V, the integrated circuit capable of repeatedly using current has a excellent simulation performance with the oscillator output frequency 9.3˜9.7 GHz, the power consumption 3.9 mW and the phase noise −113˜−110 dBc/Hz. - Thus, the integrated circuit capable of repeatedly using current of the present invention have been disclosed completely and clearly in the above description. In summary, the present invention has the following advantages:
-
- 1. The voltage-controlled oscillator and the divider belonging to high frequency operation circuit of an optical communication system are integrated by one single driving current, so as to substantially reduce the designed circuit area.
- 2. It just uses the DC bias and the tuning voltage in the integrated circuit of the present invention, and the transistors in the integrated circuit are not connected to other biases, for this reason, the area of inter-line is reduced so as to design the circuit layout easily and comfortably.
- 3. The voltage-controlled oscillator is made of merely one inductor and two tuning capacitors, so that the whole area of the integrated circuit is very small and capable of applying in SOC (system on chip).
- 4. The integrated circuit of the present invention is high-frequency operation but low power consumption and low phase noise.
- The above description is made on embodiments of the present invention. However, the embodiments are not intended to limit scope of the present invention, and all equivalent implementations or alterations within the spirit of the present invention still fall within the scope of the present invention.
Claims (10)
1. An integrated circuit capable of repeatedly using current, comprising:
a first differential input, being as an inverting amplifier and having a first input, a second input, a first output, and a second output;
a first cross couple pair, having a first couple input, a second couple input, and a first couple output, the first cross couple pair being as an negative impedance of the first differential input by way of respectively connecting the first couple input and the second couple input to the first output and the second output;
a second differential input, being as the inverting amplifier and having a third input, a fourth input, a third output, and a fourth output;
a second cross couple pair, having a third couple input, a fourth couple input, and a second couple output, the second cross couple pair being as the negative impedance of the second differential input by means of connecting the third couple input and the fourth couple input to the third output and the fourth output, respectively; and
a voltage-controlled oscillator, having a first oscillator input, a second oscillator input, a first oscillator output, and a second oscillator output, the first oscillator input and the second oscillator input respectively connecting to the first couple output and the second couple output for coupling the voltage-controlled oscillator to the first cross couple pair and the second cross couple pair, so as to execute voltage-controlled oscillation of the signal outputted from the first cross couple pair and the second cross couple pair;
wherein a divider consists of the first differential input, the first cross couple pair, the second differential input, and the second cross couple pair, moreover, through the connection of the first differential input, the first cross couple pair, the second differential, and the second cross couple pair, the divider and the voltage-controlled oscillator being driven by only one single current.
2. The integrated circuit capable of repeatedly using current of claim 1 , wherein the first differential input further comprises:
a first transistor;
a first amplifying resistor, being as an amplifying resistor of the first transistor, one terminal of the first amplifying resistor coupling to a drain terminal of the first transistor and another terminal thereof coupling to a DC bias;
a second transistor, connecting to the first transistor in parallel; and
a second amplifying resistor, being as the amplifying resistor of the second transistor, one terminal of the second amplifying resistor coupling to the drain terminal of the second transistor and another terminal thereof coupling to the DC bias.
3. The integrated circuit capable of repeatedly using current of claim 2 , wherein a gate terminal of the first transistor is the first input of the first differential input, the gate terminal of the second transistor being the second input of the first differential input, and both a source terminal of the first transistor and the source terminal of the second transistor coupling to the second couple output.
4. The integrated circuit capable of repeatedly using current of claim 1 , wherein the first cross couple pair further comprises a third transistor and a fourth transistor, a gate terminal of the third transistor connecting to a drain terminal of the fourth transistor, and the gate terminal of the fourth transistor connecting to the drain terminal of the third transistor, moreover, the drain terminals of the third transistor and the fourth transistor coupling to each other.
5. The integrated circuit capable of repeatedly using current of claim 1 , wherein the second differential input further comprises:
a fifth transistor;
a third amplifying resistor, being as an amplifying resistor of the fifth transistor, one terminal of the third amplifying resistor coupling to a drain terminal of the fifth transistor and another terminal thereof coupling to a DC bias;
a sixth transistor, connecting to the fifth transistor in parallel; and
a fourth amplifying resistor, being as the amplifying resistor of the sixth transistor, one terminal of the fourth amplifying resistor coupling to the drain terminal of the sixth transistor and another terminal thereof coupling to the DC bias.
6. The integrated circuit capable of repeatedly using current of claim 5 , wherein a gate terminal of the fifth transistor is the third input of the second differential input, the gate terminal of the sixth transistor is the fourth input of the second differential input, and both a source terminal of the fifth transistor and the source terminal of the sixth transistor coupling to the first couple output.
7. The integrated circuit capable of repeatedly using current of claim 1 , wherein the second cross couple pair further comprises a seventh transistor and an eighth transistor, a gate terminal of the seventh transistor connecting to a drain terminal of the eighth transistor, and the gate terminal of the eighth transistor connecting to the drain terminal of the seventh transistor, moreover, the drain terminals of the seventh transistor and the eighth transistor coupling to each other.
8. The integrated circuit capable of repeatedly using current of claim 1 , wherein the voltage-controlled oscillator further comprises:
a ninth transistor;
a tenth transistor, coupling to a drain terminal of the ninth transistor by a gate terminal thereof, and the gate terminal of the ninth transistor coupling to the drain terminal of the tenth transistor, so as to make the ninth transistor and the tenth transistor forming the negative resistor;
a first tuning capacitor, one terminal of the first tuning capacitor coupling to the drain terminal of the ninth transistor, and another terminal thereof coupling to a tuning voltage;
a second tuning capacitor, one terminal of the second tuning capacitor coupling to the drain terminal of the tenth transistor, and another terminal thereof coupling to the tuning voltage; and
an inductor, one terminal of the inductor coupling to the drain terminal of the ninth transistor and another terminal thereof coupling to drain terminal of the tenth transistor, the inductor being able to form two LC oscillators with the first tuning capacitor and the second tuning capacitor.
9. The integrated circuit capable of repeatedly using current of claim 8 , wherein the capacitances of the first capacitor and the second capacitor can be adjusted by modulating the tuning voltage, so as to modulate the oscillating frequency of the LC oscillators.
10. The integrated circuit capable of repeatedly using current of claim 1 , wherein the first couple output and the second couple output respectively couple to the second input and the first input for forming a positive feedback.
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TW099110148 | 2010-04-01 | ||
TW099110148A TW201136147A (en) | 2010-04-01 | 2010-04-01 | Integrated circuit capable of repeatedly using currents |
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Cited By (1)
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---|---|---|---|---|
US20110230155A1 (en) * | 2010-03-16 | 2011-09-22 | Stmicroelectronics S.R.L. | Millimeter wave oscillator |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20090096494A1 (en) * | 2004-12-02 | 2009-04-16 | Austriamicrosystems Ag | Circuit Arrangement For Generating A Complex Signal And The Use Of This Circuit Arrangement In A High-Frequency Transmitter Or Receiver |
US7750693B2 (en) * | 2007-06-05 | 2010-07-06 | O2Micro, Inc. | Frequency divider including latch circuits |
US7961057B2 (en) * | 2008-08-28 | 2011-06-14 | Mediatek Singapore Pte Ltd | Voltage controlled oscillator |
US8031019B2 (en) * | 2009-02-02 | 2011-10-04 | Qualcomm Incorporated | Integrated voltage-controlled oscillator circuits |
-
2010
- 2010-04-01 TW TW099110148A patent/TW201136147A/en unknown
- 2010-09-18 US US12/885,494 patent/US20110241789A1/en not_active Abandoned
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US20090096494A1 (en) * | 2004-12-02 | 2009-04-16 | Austriamicrosystems Ag | Circuit Arrangement For Generating A Complex Signal And The Use Of This Circuit Arrangement In A High-Frequency Transmitter Or Receiver |
US7750693B2 (en) * | 2007-06-05 | 2010-07-06 | O2Micro, Inc. | Frequency divider including latch circuits |
US7961057B2 (en) * | 2008-08-28 | 2011-06-14 | Mediatek Singapore Pte Ltd | Voltage controlled oscillator |
US8031019B2 (en) * | 2009-02-02 | 2011-10-04 | Qualcomm Incorporated | Integrated voltage-controlled oscillator circuits |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20110230155A1 (en) * | 2010-03-16 | 2011-09-22 | Stmicroelectronics S.R.L. | Millimeter wave oscillator |
US8489054B2 (en) * | 2010-03-16 | 2013-07-16 | Stmicroelectronics S.R.L. | Millimeter wave oscillator |
US8792845B2 (en) | 2010-03-16 | 2014-07-29 | Stmicroelectronics S.R.L. | Oscillator |
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