US20110091209A1 - Selector in switching matrix, line redundant method, and line redundant system - Google Patents
Selector in switching matrix, line redundant method, and line redundant system Download PDFInfo
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- US20110091209A1 US20110091209A1 US12/908,580 US90858010A US2011091209A1 US 20110091209 A1 US20110091209 A1 US 20110091209A1 US 90858010 A US90858010 A US 90858010A US 2011091209 A1 US2011091209 A1 US 2011091209A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5625—Operations, administration and maintenance [OAM]
- H04L2012/5627—Fault tolerance and recovery
Definitions
- the present invention relates to a selector, line redundant method, and line redundant system which realize line switching in a switching matrix to recover from line troubles and the like and, more particularly, to a line redundant scheme which has a simple hardware arrangement and allows line switching on a port basis.
- APS switching control schemes
- a physical layer scheme using K1/K2 bytes on a SONET framer as control information for the opposite side
- an ATM layer scheme using an OAM (Operation Administration and Maintenance) cell called an APS cell as control information for the opposite side.
- the physical layer scheme includes two types of schemes, namely a (1+1) scheme and (1:1) scheme.
- a (1+1) scheme on the transmission side, a data signal is copied, and the identical data signals are simultaneously sent out to the two connections, i.e., the working route and protection route.
- the data signal On the reception side, the data signal is normally received through the working route.
- the connection on the reception side is switched from the working route to the protection route, thereby continuing the communication of a main data signal.
- a main data signal and sub-data signal are respectively received through the working route and protection route.
- data signals from the two routes are normally received through the respective routes.
- the connection is switched from the working route to the protection route on both the sides, i.e., the transmission side and reception side, thereby continuing the communication of the main data signal.
- the (1+1) scheme to which the present invention is applied requires a bridge function of distributing a data signal sent to the working route on the transmission side to the protection route as well, a selector function of cutting off a data signal, of data signals input to a switch on the reception side, which is sent from the protection route, and a function of performing line switching control on a port on the opposite side by using K1/K2 bytes on a SONET frame.
- a conventional arrangement for a line redundant system for realizing APS is disclosed in Japanese Unexamined Patent Application Publication (KOKAI) No. 9-275405.
- KKAI Japanese Unexamined Patent Application Publication
- a selector (input cutoff circuit) and bridge (output-side distribution circuit) exist on a common switching fabric.
- FIG. 1 shows an example of the overall arrangement of the system in a case wherein terminals 1 and 4 communicate with each other.
- the terminals 1 and 4 communicate with each other through ATM switching matrixes 2 and 3 .
- Dual transmission paths are set between the ATM switching matrixes 2 and 3 by APS based on the (1+1) scheme.
- Dotted lines 16 indicate the flows of data signals sent out from the terminal 1 to the terminal 4 . Note that in FIG. 1 , an illustration of the flows of data signals from the terminal 4 to the terminal 1 is omitted.
- FIG. 2 shows the detailed arrangements of a common switching fabric 13 a, 0-system line accommodating section 30 a - 0 , and 1-system line accommodating section 40 a - 1 of the ATM switching matrix 2 shown in FIG. 1 . Note that FIG. 2 also shows the arrangement of a portion which receives data signals to be sent from the terminal 4 to the terminal 1 .
- FIG. 3 is a block diagram showing the detailed arrangement of the ATM switching matrix 3 in APS operation.
- the internal arrangement of the ATM switching matrix 3 is the same as that of the ATM switching matrix 2 , and the letter added to the end of the reference numeral of each component is changed from a to b.
- the 0/1-system line accommodating sections 30 a - 0 and 40 a - 1 of the ATM switching matrix 2 are respectively connected to 0/1-system line accommodating sections 30 b - 0 and 40 b - 1 of the ATM switching matrix 3 .
- a selector 19 b in FIG. 3 exhibits a state after APS operation; the selector 19 b selects an output from the 1-system line accommodating section 40 b - 1 and cuts off an output from the 0-system line accommodating section 30 b - 0 .
- the data signal transmitted from the terminal 1 is input to the ATM switching matrix 2 through a line accommodating section 12 a and bridged (distributed) to the 0-system line accommodating section 30 a - 0 and 1-system line accommodating section 40 a - 1 by the common switching fabric 13 a .
- the resultant signals are then output to a working route 14 and protection route 15 , respectively.
- the data signal input from the working route 14 to the ATM switching matrix 3 arrives at the terminal 4 through the 0-system line accommodating section 30 b - 0 , a common switching fabric 13 b , and a line accommodating section. 12 b .
- the data signal input from the protection route 15 to the ATM switching matrix 3 is input to the common switching fabric 13 b through the 1-system line accommodating section 40 b - 1 , but the output to the line accommodating section 12 b is cut off by the selector ( 19 b in FIG. 3 ) in the common switching fabric 13 b.
- the ATM switching matrix 2 is constituted by the common switching fabric 13 a , the 0-system line accommodating section 30 a - 0 , the 1-system line accommodating section 40 a - 1 , and an OS (Operating System) 50 a .
- the line accommodating sections are comprised of transmission/input interfaces (to be referred to as line IFs hereinafter) 32 a and 33 a (0-system side) and 42 a and 43 a (1-system side), output ports 34 a - 1 to 34 a -N (0-system side) and 44 a - 1 to 44 a -N (1-system side) for accommodating a plurality of lines (N lines for each line IF in FIG.
- the output ports 34 a - 1 to 34 a -N and 44 a - 1 to 44 a -N and input ports 35 a - 1 to 35 a -N and 45 a - 1 to 45 a -N are constituted by an optical module (not shown), a framer (not shown) for interfacing between a physical layer and an ATM layer, and the like.
- the respective pairs of 0/1-system transmission/input ports in the 0-system line accommodating section 30 a - 0 and 1-system line accommodating section 40 a - 1 are connected to switch IFs 17 a - 1 to 17 a - n to realize a redundant arrangement.
- each of the pairs of output ports ( 34 a - 1 and 44 a - 1 ), . . . , ( 34 a -N and 44 a -N) and of input ports ( 35 a - 1 and 45 a - 1 ), . . . , ( 35 a -N and 45 a -N) has an APS redundant arrangement.
- the common switching fabric 13 a is comprised of a switch core 16 a , switch IFs 17 a - 1 to 17 a - n , and switch control section 80 a .
- the switch core 16 a has 2n interfaces on the transmission/reception side for the switch IFs 17 a - 1 to 17 a - n and switches ATM cells from the respective switch IFs.
- the switch IFs 17 a - 1 to 17 a - n connect the interfaces of the common switching fabric 13 a to the 0/1-system line accommodating sections in pairs.
- the switch control section 80 a controls the dual redundant arrangement in cooperation with the OS 50 a.
- a bridge 18 a and selector 19 a are accommodated in the switch IFs 17 a - 1 to 17 a - n .
- the bridge 18 a has a function of simultaneously distributing a data signal from the switch core 16 a to the 0-system line accommodating section 30 a - 0 to the 1-system line accommodating section 40 a - 1 .
- the selector 19 a has a cutoff function of inhibiting an unselected data signal from being input to the switch core 16 a by selecting one of the 0/1-system line accommodating section pair 30 a - 0 and 40 a - 1 .
- the remaining input ports 35 b - 2 (not shown) to 35 b -N in normal operation in the 0-system line accommodating section 30 b - 0 are also switched to the input orts 45 b - 2 (not shown) to 45 b -N in the 1-system line accommodating section 40 b - 1 .
- cell loss may occur in the input ports 35 b - 2 (not shown) to 35 b -N which are normally operated.
- selectors 19 b since switching from the working route to the protection route is performed by the selector 19 b , selectors 19 b must be provided for all the switch IFs 17 b - 1 to 17 b - n in the common switching fabric 13 b . Consequently, the internal hardware arrangement of the common switching fabric 13 b is complicated.
- the present invention has been made in view of the foregoing circumstances in the prior art, and has for its object to provide a line redundant method which performs line switching based on the (1+1) APS scheme on a port basis by using a selector having a cutoff function of outputting/not outputting one data signal of a plurality of data signals input from a switching matrix, and a line redundant system for implementing the method.
- a line redundant method comprising:
- the selector step is implemented by using a framer function for the data signal.
- a line redundant system comprising:
- bridge means for simultaneously outputting data signals to a plurality of grouped line accommodating sections connected to a common switching fabric in a switching matrix, and selector means for outputting only a data signal, of data signals input from another switching matrix other than the switching matrix to a plurality of grouped input ports in the line accommodating sections, which is required in the common switching fabric from the input port to the common switching fabric, and cutting off the data signals from other input ports other than the input port.
- the selector means is implemented by using a framer provided for the input port.
- the selector function of cutting off a data signal output from a line accommodating section in the protection route to the common switching fabric can be implemented on a port basis. This eliminates the necessity of switch the remaining input ports during normal operation in the same line accommodating section, and hence prevents the occurrence of cell loss due to switching.
- each switch IF in the common switching fabric needs not have a selector, the hardware arrangement of the common switching fabric can be simplified as compared with the conventional schemes.
- FIG. 1 is a block diagram showing the overall arrangement of a conventional line redundant system to explain a conventional line redundant scheme for ATM switching matrixes and the system therefor;
- FIG. 2 is a block diagram showing the detailed arrangement of an ATM switching matrix 2 at the time of APS operation in the arrangement shown in FIG. 1 ;
- FIG. 3 is a block diagram showing the detailed arrangement of an ATM switching matrix 3 at the time of APS operation in the arrangement shown in FIG. 1 ;
- FIG. 4 is a block diagram showing the overall arrangement of a line redundant system to explain a line redundant scheme for ATM switching matrixes and the system therefor according to an embodiment of the present invention
- FIG. 5 is a block diagram showing the detailed arrangement of an ATM switching matrix 102 at the time of APS operation in the arrangement shown in FIG. 4 ;
- FIG. 6 is a block diagram showing the detailed arrangement of an ATM switching matrix 103 at the time of APS operation in the arrangement shown in FIG. 4 ;
- FIG. 7 is a block diagram showing an example of path setting on the transmission side of an APS line.
- FIG. 8 is a block diagram showing an example of path setting on the reception side of the APS line.
- FIG. 4 shows an example of the overall arrangement of a system in a case wherein terminals 101 and 104 communicate with each other. Note that in the present invention, as in the prior art, a description about the detection of a trouble in the working route and the exchange of control information with opposite ports by using K1/K2 bytes after the detection, which are general techniques, will be omitted.
- FIG. 5 shows the detailed arrangements a common switching fabric 113 a, 0-system line accommodating section 130 a - 0 , and 1-system line accommodating section 140 a - 1 in APS operation in an ATM switching matrix 102 in FIG. 4 .
- the ATM switching matrix 102 is constituted by the common switching fabric 113 a , the 0-system line accommodating section 130 a - 0 , the 1-system line accommodating section 140 a - 1 , and an OS 150 a for controlling the ATM switching matrix 102 .
- Each line accommodating section accommodates a plurality of lines (N lines for each line IF in FIG. 5 ).
- the common switching fabric 113 a is comprised of switch IFs 117 a - 1 to 117 a - n each of which accommodates one pair of 0-system line accommodating section 130 a - 0 and 1-system line accommodating section 140 a - 1 , a switch core 116 a for analyzing the header information of a data signal and distributing the information to each line accommodating section, and a switch control section 180 a .
- Each switch IF accommodates a bridge 118 a which simultaneously distributes data from the switch core 116 a to the 0-system line accommodating section 130 a - 0 to the 1-system line accommodating section 140 a - 1 .
- the operation of the bridge 118 a is the same as that of the bridge 18 a in the prior art, and hence a description thereof will be omitted.
- FIG. 6 shows the detailed arrangements of a common switching fabric 113 b, 0-system line accommodating section 130 b - 0 , and 1-system line accommodating section 140 b - 1 in APS operation in the ATM switching matrix 103 in FIG. 4 .
- the arrangement of the embodiment of the present invention shown in FIG. 6 differs from that of the prior art shown in FIG. 3 in that a selector function is implemented, at the time of switching, for the data signals respectively input from the ATM switching matrix 102 and ATM switching matrix 2 to an ATM switching matrix 103 and ATM switching matrix 3 through a protection route 115 and protection route 15 .
- the selector function is implemented on the common switching fabric 13 b side in the ATM switching matrix 3 .
- the selector function is implemented at input ports 135 b - 1 to 135 b -N in the 0-system line accommodating section 130 b - 0 and input ports 145 b - 1 to 145 b -N in the 1-system line accommodating section 140 b - 1 .
- the following are the details of the selector function in a case wherein after a trouble occurs in a working route 114 , the data signal received by the 0-system input port 135 b - 1 through the working route 114 is cut off, and the data signal received by the 1-system input port 145 b - 1 through the protection route 115 is switched to be output to the common switching fabric 113 b side.
- the switching control function using K1/K2 bytes, an OS 150 b for controlling the ATM switching matrix 103 , and a line control section for a 0-system line control section 131 b and 1-system line control section 141 b cooperate with each other to determine a specific one of the 0-system input port 135 b - 1 and 1-system input port 145 b - 1 from which a data signal should be output.
- the OS 150 b and the line control section cooperate with each other to generate control signals so as to cut off the data signal output from the input port 135 b - 1 through the 0-system line control section 131 b and output a data signal from the input port 145 b - 1 through the 1-system line control section 141 b.
- the above selector function can be implemented by, for example, SONET framers that are originally provided for the input ports 135 b - 1 to 135 b -N and 145 b - 1 to 145 b -N.
- a SONET framer has a determination function of determining whether or not to output a data signal from the SONET framer as well as a function of assembling ATM cells into a SONET frame.
- the selector function can therefore be implemented by using the determination function.
- the arrangement of the present invention eliminates the necessity of the selectors 19 b (see FIG. 3 ) respectively arranged in the switch IFs 17 b - 1 to 17 b - n on the common switching fabric 13 b , and can simplify the hardware arrangement of the common switching fabric 113 b as indicated by a switch IF 117 b - 1 in FIG. 6 . Note that the use of this function has no influence on the remaining ports accommodated in the same system.
- path setting To allow data signals to pass through the ATM switching matrixes 102 and 103 , path setting must be done in advance. This path setting is performed such that 0- and 1-system line accommodating sections are paired.
- FIG. 7 shows an example of path setting on the transmission side of an APS line.
- a path is established from a input port 155 a of a line accommodating section 112 a to a output port 134 a - 1 of the 0-system line accommodating section 130 a - 0 .
- a switch IF (not shown) in the common switching fabric 113 a bridges (distributes) a data signal from the 0-system side to output it to the 1-system line accommodating section 140 a - 1 as well.
- path setting for a switch core (not shown) in the common switching fabric 113 a is performed with respect to the 0-system line accommodating section 130 a - 0 . That is, in the 0-system line accommodating section 130 a - 0 , path setting is performed from the switch core to the output port 134 a - 1 . In addition, in the 1-system line accommodating section 140 a - 1 to which the data signal from the 0-system side is bridged, path setting is also performed for a input port 144 a - 1 from the switch core (not shown).
- FIG. 8 shows an example of path setting on the reception side of an APS line.
- a path is established from the input port 135 b - 1 of the 0-system line accommodating section 130 b - 0 to a output port 154 b of a line accommodating section 112 b .
- a path is established from the input port 145 b - 1 of the 1-system line accommodating section 140 b - 1 , which pairs up with the above port, to the output port 154 b of the line accommodating section 112 b.
- path setting is always performed on both the transmission and reception sides of line accommodating section pairs. Note that when one of an APS line accommodating section pair is extracted, and the other is inserted, the OS that controls the ATM switching matrix performs path setting for the inserted line accommodating section again by using path setting for a line accommodating section that is not extracted.
- an ATM switching matrix is used as a switching matrix
- an ATM cell is used as a data signal.
- the switching matrix and data signal are not limited to those described above as long as they comply with the APS specifications.
- the present invention can also be applied to a line redundant scheme in an IP over SONET system which directly transmits IP packets through a SONET network.
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Abstract
There is provided a line redundant method for implementation of line switching in a switching matrix, including the bridge step of outputting a data signal to a plurality of redundant lines in the switching matrix, and the selector step of selecting only a data signal, of a plurality of data signals input from another switching matrix other than the switching matrix through the plurality of redundant lines, which is input through a redundant line required in the switching matrix, and not selecting the data signals input to the switching matrix through the lines other than the required redundant line. A line redundant system for implementing this method is also provided.
Description
- 1. Field of the Invention
- The present invention relates to a selector, line redundant method, and line redundant system which realize line switching in a switching matrix to recover from line troubles and the like and, more particularly, to a line redundant scheme which has a simple hardware arrangement and allows line switching on a port basis.
- 2. Description of the Prior Art
- Recently, demands have arisen for an improvement in the reliability of an ATM (Asynchronous Transfer Mode) switching network with respect to line troubles. As a line redundant scheme in a case wherein ATM switching is realized on a SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy) network, an APS (Automatic Protection Switching)-scheme is available, in which when a failure occurs in a Working route (Working Connection), the route is automatically switched to a protection route (Protection Connection) to continue the communication. As standards for this scheme, Bellcore (Bell Communications Research) standards, ANSI (American National Standards Institute) T1.105.01-1998, ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) G.783, and the like are defined.
- There are two types of switching control schemes in APS, namely a physical layer scheme using K1/K2 bytes on a SONET framer as control information for the opposite side and an ATM layer scheme using an OAM (Operation Administration and Maintenance) cell called an APS cell as control information for the opposite side.
- The physical layer scheme includes two types of schemes, namely a (1+1) scheme and (1:1) scheme. In this case, in the (1+1) scheme, on the transmission side, a data signal is copied, and the identical data signals are simultaneously sent out to the two connections, i.e., the working route and protection route. On the reception side, the data signal is normally received through the working route. When a trouble occurs on the working route, only the connection on the reception side is switched from the working route to the protection route, thereby continuing the communication of a main data signal.
- In the (1:1) scheme, on the transmission side, a main data signal and sub-data signal are respectively received through the working route and protection route. On the reception side, data signals from the two routes are normally received through the respective routes. When a trouble occurs on the working route, the connection is switched from the working route to the protection route on both the sides, i.e., the transmission side and reception side, thereby continuing the communication of the main data signal.
- Of the above two types of physical layer schemes, the (1+1) scheme to which the present invention is applied requires a bridge function of distributing a data signal sent to the working route on the transmission side to the protection route as well, a selector function of cutting off a data signal, of data signals input to a switch on the reception side, which is sent from the protection route, and a function of performing line switching control on a port on the opposite side by using K1/K2 bytes on a SONET frame.
- For example, a conventional arrangement for a line redundant system for realizing APS is disclosed in Japanese Unexamined Patent Application Publication (KOKAI) No. 9-275405. In an embodiment in this reference, the arrangement of a dual redundant system in an ATM switch is described. A selector (input cutoff circuit) and bridge (output-side distribution circuit) exist on a common switching fabric.
- The operation of this conventional system will be described below with reference to
FIGS. 1 , 2, and 3. -
FIG. 1 shows an example of the overall arrangement of the system in a case whereinterminals 1 and 4 communicate with each other. Theterminals 1 and 4 communicate with each other throughATM switching matrixes ATM switching matrixes terminal 1 to the terminal 4. Note that inFIG. 1 , an illustration of the flows of data signals from the terminal 4 to theterminal 1 is omitted. -
FIG. 2 shows the detailed arrangements of acommon switching fabric 13 a, 0-system line accommodating section 30 a-0, and 1-system line accommodating section 40 a-1 of theATM switching matrix 2 shown inFIG. 1 . Note thatFIG. 2 also shows the arrangement of a portion which receives data signals to be sent from the terminal 4 to theterminal 1. -
FIG. 3 is a block diagram showing the detailed arrangement of theATM switching matrix 3 in APS operation. In this case, the internal arrangement of theATM switching matrix 3 is the same as that of theATM switching matrix 2, and the letter added to the end of the reference numeral of each component is changed from a to b. The 0/1-system line accommodating sections 30 a-0 and 40 a-1 of theATM switching matrix 2 are respectively connected to 0/1-systemline accommodating sections 30 b-0 and 40 b-1 of theATM switching matrix 3. Aselector 19 b inFIG. 3 exhibits a state after APS operation; theselector 19 b selects an output from the 1-systemline accommodating section 40 b-1 and cuts off an output from the 0-systemline accommodating section 30 b-0. - As is obvious from
FIGS. 1 and 2 , the data signal transmitted from theterminal 1 is input to theATM switching matrix 2 through a line accommodating section 12 a and bridged (distributed) to the 0-system line accommodating section 30 a-0 and 1-system line accommodating section 40 a-1 by thecommon switching fabric 13 a. The resultant signals are then output to a working route 14 and protection route 15, respectively. - As is obvious from
FIGS. 1 and 3 , the data signal input from the working route 14 to theATM switching matrix 3 arrives at the terminal 4 through the 0-systemline accommodating section 30 b-0, acommon switching fabric 13 b, and a line accommodating section. 12 b. On the other hand, the data signal input from the protection route 15 to theATM switching matrix 3 is input to thecommon switching fabric 13 b through the 1-systemline accommodating section 40 b-1, but the output to the line accommodating section 12 b is cut off by the selector (19 b inFIG. 3 ) in thecommon switching fabric 13 b. - The detailed arrangement of a conventional APS scheme will be described with reference to
FIG. 2 . Assume that a general technique is used as a switching control function using K1/K2 bytes. A description about the detection of a trouble in the working route and the exchange of control information with opposite ports by using K1/K2 bytes after the detection will therefore be omitted. - Referring to
FIG. 2 , theATM switching matrix 2 is constituted by thecommon switching fabric 13 a, the 0-system line accommodating section 30 a-0, the 1-system line accommodating section 40 a-1, and an OS (Operating System) 50 a. The line accommodating sections are comprised of transmission/input interfaces (to be referred to as line IFs hereinafter) 32 a and 33 a (0-system side) and 42 a and 43 a (1-system side), output ports 34 a-1 to 34 a-N (0-system side) and 44 a-1 to 44 a-N (1-system side) for accommodating a plurality of lines (N lines for each line IF inFIG. 2 ), input ports 35 a-1 to 35 a-N (0-system side) and 45 a-1 to 45 a-N (1-system side), andline control sections OS 50 a, by using opposite ports and K1/K2 bytes of SONET frames in APS operation. - The output ports 34 a-1 to 34 a-N and 44 a-1 to 44 a-N and input ports 35 a-1 to 35 a-N and 45 a-1 to 45 a-N are constituted by an optical module (not shown), a framer (not shown) for interfacing between a physical layer and an ATM layer, and the like. The respective pairs of 0/1-system transmission/input ports in the 0-system line accommodating section 30 a-0 and 1-system line accommodating section 40 a-1 are connected to switch IFs 17 a-1 to 17 a-n to realize a redundant arrangement.
- For example, referring to
FIG. 2 , each of the pairs of output ports (34 a-1 and 44 a-1), . . . , (34 a-N and 44 a-N) and of input ports (35 a-1 and 45 a-1), . . . , (35 a-N and 45 a-N) has an APS redundant arrangement. - The
common switching fabric 13 a is comprised of aswitch core 16 a, switch IFs 17 a-1 to 17 a-n, andswitch control section 80 a. Theswitch core 16 a has 2n interfaces on the transmission/reception side for the switch IFs 17 a-1 to 17 a-n and switches ATM cells from the respective switch IFs. The switch IFs 17 a-1 to 17 a-n connect the interfaces of thecommon switching fabric 13 a to the 0/1-system line accommodating sections in pairs. Theswitch control section 80 a controls the dual redundant arrangement in cooperation with the OS 50 a. - A
bridge 18 a andselector 19 a are accommodated in the switch IFs 17 a-1 to 17 a-n. Thebridge 18 a has a function of simultaneously distributing a data signal from theswitch core 16 a to the 0-system line accommodating section 30 a-0 to the 1-system line accommodating section 40 a-1. Theselector 19 a has a cutoff function of inhibiting an unselected data signal from being input to theswitch core 16 a by selecting one of the 0/1-system line accommodating section pair 30 a-0 and 40 a-1. - As is obvious from the detailed arrangement of the
ATM switching matrix 3 inFIG. 3 , the following problems arise when a plurality ofoutput ports 34 b-1 to 34 b-N and 44 b-1 to 44 b-N andinput ports 35 b-1 to 35 b-N and 45 b-1 to 45 b-N are accommodated on the plurality of line accommodatingsections 30 b-0 and 40 b-1 a predetermined number of ports at a time, and aselector 19 b (input cutoff circuit) exists in theswitch IF 17 b-1 in thecommon switching fabric 13 b. - Even when only switching from the
input port 35 b-1 in the 0-systemline accommodating section 30 b-0 on the working route to theinput port 45 b-1 in the 1-systemline accommodating section 40 b-1 on the protection route is to be performed, since theselector 19 b exists in thecommon switching fabric 13 b, switching cannot be done on a input port basis. Hence, switching is done on a line accommodating section basis. As a consequence, theremaining input ports 35 b-2 (not shown) to 35 b-N in normal operation in the 0-systemline accommodating section 30 b-0 are also switched to theinput orts 45 b-2 (not shown) to 45 b-N in the 1-systemline accommodating section 40 b-1. When such switching occurs, cell loss may occur in theinput ports 35 b-2 (not shown) to 35 b-N which are normally operated. - In addition, since switching from the working route to the protection route is performed by the
selector 19 b,selectors 19 b must be provided for all theswitch IFs 17 b-1 to 17 b-n in thecommon switching fabric 13 b. Consequently, the internal hardware arrangement of thecommon switching fabric 13 b is complicated. - The present invention has been made in view of the foregoing circumstances in the prior art, and has for its object to provide a line redundant method which performs line switching based on the (1+1) APS scheme on a port basis by using a selector having a cutoff function of outputting/not outputting one data signal of a plurality of data signals input from a switching matrix, and a line redundant system for implementing the method.
- In order to achieve the above object, according to the first aspect of the present invention, there is provided a line redundant method, comprising:
- the bridge step of outputting a data signal to a plurality of redundant lines in a switching matrix; and
- the selector step of selecting only a data signal, of a plurality of data signals input from another switching matrix other than the switching matrix through the plurality of redundant lines, which is input through a redundant line required in the switching matrix, and not selecting the data signals input to the switching matrix through the lines other than the required redundant line.
- In the first aspect, the selector step is implemented by using a framer function for the data signal.
- In order to realize the above object, according to the second aspect of the present invention, there is provided a line redundant system, comprising:
- bridge means for simultaneously outputting data signals to a plurality of grouped line accommodating sections connected to a common switching fabric in a switching matrix, and selector means for outputting only a data signal, of data signals input from another switching matrix other than the switching matrix to a plurality of grouped input ports in the line accommodating sections, which is required in the common switching fabric from the input port to the common switching fabric, and cutting off the data signals from other input ports other than the input port.
- In the second aspect, the selector means is implemented by using a framer provided for the input port.
- With the above arrangement, when line switching is performed by the (1+1) APS scheme, the selector function of cutting off a data signal output from a line accommodating section in the protection route to the common switching fabric can be implemented on a port basis. This eliminates the necessity of switch the remaining input ports during normal operation in the same line accommodating section, and hence prevents the occurrence of cell loss due to switching.
- In addition, since each switch IF in the common switching fabric needs not have a selector, the hardware arrangement of the common switching fabric can be simplified as compared with the conventional schemes.
- The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principle of the present invention are shown by way of illustrative examples.
-
FIG. 1 is a block diagram showing the overall arrangement of a conventional line redundant system to explain a conventional line redundant scheme for ATM switching matrixes and the system therefor; -
FIG. 2 is a block diagram showing the detailed arrangement of anATM switching matrix 2 at the time of APS operation in the arrangement shown inFIG. 1 ; -
FIG. 3 is a block diagram showing the detailed arrangement of anATM switching matrix 3 at the time of APS operation in the arrangement shown inFIG. 1 ; -
FIG. 4 is a block diagram showing the overall arrangement of a line redundant system to explain a line redundant scheme for ATM switching matrixes and the system therefor according to an embodiment of the present invention; -
FIG. 5 is a block diagram showing the detailed arrangement of anATM switching matrix 102 at the time of APS operation in the arrangement shown inFIG. 4 ; -
FIG. 6 is a block diagram showing the detailed arrangement of anATM switching matrix 103 at the time of APS operation in the arrangement shown inFIG. 4 ; -
FIG. 7 is a block diagram showing an example of path setting on the transmission side of an APS line; and -
FIG. 8 is a block diagram showing an example of path setting on the reception side of the APS line. - A preferred embodiment of the present invention will be described below with reference to
FIGS. 4 to 8 . -
FIG. 4 shows an example of the overall arrangement of a system in a case whereinterminals -
FIG. 5 shows the detailed arrangements acommon switching fabric 113 a, 0-system line accommodating section 130 a-0, and 1-system line accommodating section 140 a-1 in APS operation in anATM switching matrix 102 inFIG. 4 . TheATM switching matrix 102 is constituted by thecommon switching fabric 113 a, the 0-system line accommodating section 130 a-0, the 1-system line accommodating section 140 a-1, and anOS 150 a for controlling theATM switching matrix 102. Each line accommodating section accommodates a plurality of lines (N lines for each line IF inFIG. 5 ). Thecommon switching fabric 113 a is comprised of switch IFs 117 a-1 to 117 a-n each of which accommodates one pair of 0-system line accommodating section 130 a-0 and 1-system line accommodating section 140 a-1, aswitch core 116 a for analyzing the header information of a data signal and distributing the information to each line accommodating section, and aswitch control section 180 a. Each switch IF accommodates a bridge 118 a which simultaneously distributes data from theswitch core 116 a to the 0-system line accommodating section 130 a-0 to the 1-system line accommodating section 140 a-1. Note that the operation of the bridge 118 a is the same as that of thebridge 18 a in the prior art, and hence a description thereof will be omitted. -
FIG. 6 shows the detailed arrangements of acommon switching fabric 113 b, 0-systemline accommodating section 130 b-0, and 1-systemline accommodating section 140 b-1 in APS operation in theATM switching matrix 103 inFIG. 4 . The arrangement of the embodiment of the present invention shown inFIG. 6 differs from that of the prior art shown inFIG. 3 in that a selector function is implemented, at the time of switching, for the data signals respectively input from theATM switching matrix 102 andATM switching matrix 2 to anATM switching matrix 103 andATM switching matrix 3 through aprotection route 115 and protection route 15. - In the prior art shown in
FIG. 3 , the selector function is implemented on thecommon switching fabric 13 b side in theATM switching matrix 3. In contrast, in the embodiment of the present invention shown inFIG. 6 , the selector function is implemented atinput ports 135 b-1 to 135 b-N in the 0-systemline accommodating section 130 b-0 andinput ports 145 b-1 to 145 b-N in the 1-systemline accommodating section 140 b-1. - For example, the following are the details of the selector function in a case wherein after a trouble occurs in a working
route 114, the data signal received by the 0-system input port 135 b-1 through the workingroute 114 is cut off, and the data signal received by the 1-system input port 145 b-1 through theprotection route 115 is switched to be output to thecommon switching fabric 113 b side. - The switching control function using K1/K2 bytes, an
OS 150 b for controlling theATM switching matrix 103, and a line control section for a 0-systemline control section 131 b and 1-systemline control section 141 b cooperate with each other to determine a specific one of the 0-system input port 135 b-1 and 1-system input port 145 b-1 from which a data signal should be output. When the occurrence of a trouble in the workingroute 114 is detected, theOS 150 b and the line control section cooperate with each other to generate control signals so as to cut off the data signal output from theinput port 135 b-1 through the 0-systemline control section 131 b and output a data signal from theinput port 145 b-1 through the 1-systemline control section 141 b. - That is, in the present invention, when the data signal bridged on the transmission side is input and a trouble occurs in the working route, line switching control is performed such that the data signal output from the 0-system input port of the pair of 0- and 1-system input ports is cut off, and the 1-system input port whose output has been cut off is allowed to output a data signal. In this manner, the selector function is implemented.
- The above selector function can be implemented by, for example, SONET framers that are originally provided for the
input ports 135 b-1 to 135 b-N and 145 b-1 to 145 b-N. - A SONET framer has a determination function of determining whether or not to output a data signal from the SONET framer as well as a function of assembling ATM cells into a SONET frame. The selector function can therefore be implemented by using the determination function.
- Note that not only SONET framers but also many commercially available framers have the function of inhibiting an input data signal from being output to the common switching fabric side. Therefore, in units other than ATM switching matrixes incorporating SONET framers, the data signals input to various framers can be cut off (selected) for each port in a line accommodating section before the outputting of the signals to the common switching fabric side by using the same function of the framers in the ports.
- The arrangement of the present invention eliminates the necessity of the
selectors 19 b (seeFIG. 3 ) respectively arranged in theswitch IFs 17 b-1 to 17 b-n on thecommon switching fabric 13 b, and can simplify the hardware arrangement of thecommon switching fabric 113 b as indicated by a switch IF 117 b-1 inFIG. 6 . Note that the use of this function has no influence on the remaining ports accommodated in the same system. - As described above, when it is necessary to perform line switching from the
input port 135 b-1 in the working route in the 0-systemline accommodating section 130 b-0 to theinput port 145 b-1 in the protection route in the 1-systemline accommodating section 140 b-1, only the corresponding ports can be switched. That is, since the remaininginput ports 135 b-2 (not shown) to 135 b-N during normal operation in the 0-systemline accommodating section 130 b-0 in which thereception circuit port 135 b-1 is accommodated are not forcibly switched to thereception circuit ports 145 b-2 (not shown) to 145 b-N in the 1-systemline accommodating section 140 b-1, cell loss does not easily occur in lines input to theinput ports 135 b-2 (not shown) to 135 b-N during normal operation. - To allow data signals to pass through the
ATM switching matrixes -
FIG. 7 shows an example of path setting on the transmission side of an APS line. As is obvious fromFIG. 7 , a path is established from ainput port 155 a of a lineaccommodating section 112 a to a output port 134 a-1 of the 0-system line accommodating section 130 a-0. On the transmission side, a switch IF (not shown) in thecommon switching fabric 113 a bridges (distributes) a data signal from the 0-system side to output it to the 1-system line accommodating section 140 a-1 as well. Even if, therefore, the 0-system line accommodating section 130 a-0 is extracted, path setting for a switch core (not shown) in thecommon switching fabric 113 a is performed with respect to the 0-system line accommodating section 130 a-0. That is, in the 0-system line accommodating section 130 a-0, path setting is performed from the switch core to the output port 134 a-1. In addition, in the 1-system line accommodating section 140 a-1 to which the data signal from the 0-system side is bridged, path setting is also performed for a input port 144 a-1 from the switch core (not shown). -
FIG. 8 shows an example of path setting on the reception side of an APS line. As is obvious fromFIG. 8 , a path is established from theinput port 135 b-1 of the 0-systemline accommodating section 130 b-0 to a output port 154 b of a lineaccommodating section 112 b. At the same time, a path is established from theinput port 145 b-1 of the 1-systemline accommodating section 140 b-1, which pairs up with the above port, to the output port 154 b of theline accommodating section 112 b. - As described above, path setting is always performed on both the transmission and reception sides of line accommodating section pairs. Note that when one of an APS line accommodating section pair is extracted, and the other is inserted, the OS that controls the ATM switching matrix performs path setting for the inserted line accommodating section again by using path setting for a line accommodating section that is not extracted.
- In the above description, an ATM switching matrix is used as a switching matrix, and an ATM cell is used as a data signal. However, the switching matrix and data signal are not limited to those described above as long as they comply with the APS specifications. For example, the present invention can also be applied to a line redundant scheme in an IP over SONET system which directly transmits IP packets through a SONET network.
Claims (22)
1-8. (canceled)
9. A method comprising:
receiving, by a first port, a first data signal;
one of forwarding the received first data signal to a network device or cutting-off forwarding of the received first data signal to the network device using a first function of a first framer implemented at the first port;
receiving, by a second port, a second data signal, the second port being different than the first port;
one of forwarding the received second data signal to the network device or cutting-off forwarding of the received second data signal to the network device using a second function of a second framer implemented at the second port, the second function being different than the first function.
10. The method of claim 9 , where the one of forwarding the received first data signal to the network device or cutting-off forwarding of the received first data signal to the network device includes:
forwarding the received first data signal to the network device, when the first data signal is being received normally; and
cutting-off forwarding of the received first data signal to the network device, when the first data signal is being received abnormally.
11. The method of claim 9 , where the one of forwarding the received second data signal to the network device or cutting-off forwarding of the received second data signal to the network device includes:
forwarding the received second data signal to the network device, when the first data signal is being received abnormally; and
cutting-off forwarding of the received second data signal to the network device, when the first data signal is being received normally.
12. The method of claim 9 , further comprising:
generating at least one first control signal;
cutting-off, based on the generated at least one first control signal, forwarding of the received first data signal to the network device; and
forwarding, based on the generated at least one first control signal, the received second data signal to the network device.
13. The method of claim 12 , where the received first data signal is received via a first route,
the method further comprising:
detecting a failure in the first route; and
generating the at least one first control signal based on the detecting.
14. The method of claim 12 , further comprising:
generating at least one second control signal;
cutting-off, based on the generated at least one second control signal, forwarding of the received second data signal to the network device; and
forwarding, based on the generated at least one second control signal, the received first data signal to the network device.
15. The method of claim 14 , where the generated at least one second control signal is based on the first route functioning without a failure.
16. The method of claim 9 , where the network device includes an Asynchronous Transfer Mode (ATM) switching matrix, and where at least one of the received first data signal or the received second data signal comprises an ATM cell.
17. The method of claim 9 , further comprising:
performing path setting; and
forwarding, based on the performed path setting, at least one of the received first data signal or the received second data signal.
18. A system comprising:
a device to:
receive, at a first port, a first data signal;
receive, at a second port, a second data signal,
where the first port is different than the second port;
one of forward the received first data signal in the device or cut-off forwarding of the received first data signal in the device using a first function of a first framer implemented at the first port; and
one of forward the received second data signal in the device or cut-off forwarding of the received second data signal in the device using a second function of a second framer implemented at the second port,
where the second function is different than the first function.
19. The system of claim 18 , where the device includes an Asynchronous Transfer Mode (ATM) switching matrix, and where at least one of the received first data signal or the received second data signal comprises an ATM cell.
20. The system of claim 18 , where, when one of forwarding the received first data signal in the device or cutting-off forwarding of the received first data signal in the device, the device is to:
forward the received first data signal in the device when the first data signal is being received normally via a first route; and
cut-off forwarding of the received first data signal in the device when the first data signal is being received abnormally via the first route.
21. The system of claim 20 , where the device is further to:
generate one or more signals based on a detected failure in the first route,
forward, based on the generated one or more signals, the received second data signal, and
cut-off, based on the generated one or more signals, forwarding of the received first data signal.
22. The system of claim 18 , where, when one of forwarding the received second data signal in the device or cutting-off forwarding of the received second data signal in the device, the device is to:
forward the received second data signal in the device when the first data signal is being received abnormally via a first route; and
cut-off forwarding of the received second data signal in the device when the first data signal is being received normally via the first route.
23. The system of claim 18 , where the device is further to:
receive, at a third port, a third data signal,
forward, using a function of a third framer implemented at the third port, the received third data signal in the device,
receive, at a fourth port, a fourth data signal, and
cut-off, using a function of a fourth framer implemented at the fourth port, forwarding of the received fourth data signal in the device.
24. A device comprising:
a first input port to receive a first data signal;
a first framer, implemented at the first input port, to:
one of forward the received first data signal in the device or cut-off forwarding of the received first data signal in the device using a first function;
a second, different input port to receive a second data signal; and
a second framer, implemented at the second input port, to:
one of forward the received second data signal in the device or cut-off forwarding of the received second data signal in the device using a second, different function.
25. The device of claim 24 , where the received first data signal is received via a first route,
the device further comprising:
a component to generate at least one signal based on a failure of the first route,
where, based on the generated at least one signal, the first framer is to cut-off forwarding of the received first data signal, and the second framer is to forward the received second data signal.
26. The device of claim 25 , where the component is to generate at least one second signal, and
where, based on the generated at least one second signal, the first framer is to forward the received first data signal, and the second framer is to cut-off forwarding of the received second data signal.
27. The device of claim 24 , where the device comprises a switching matrix.
28. The device of claim 24 , the device further comprising:
a third framer to:
cut-off forwarding, using a third function of the third framer, a third data signal in the device, when the third data signal is being received abnormally; and
a fourth framer to:
forward, using a fourth function of the fourth framer, a fourth data signal in the device, when the third data signal is being received abnormally.
29. The device of claim 28 , where the third framer is to forward, using the third function and based on the third data signal being received normally, the third data signal in the device, and
where the fourth framer is to cut-off, using the fourth function and based on the third data signal being received normally, forwarding of the fourth data signal in the device.
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US12/330,256 US7839772B2 (en) | 2001-10-10 | 2008-12-08 | Line redundant device and method |
US12/908,580 US20110091209A1 (en) | 2001-10-10 | 2010-10-20 | Selector in switching matrix, line redundant method, and line redundant system |
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US7881188B2 (en) | 2006-02-03 | 2011-02-01 | Genband Us Llc | Methods, systems, and computer program products for implementing link redundancy in a media gateway |
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US8179807B2 (en) * | 2007-11-06 | 2012-05-15 | Lsi Corporation | In-band communication of alarm status information in a synchronous transport communication system |
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US8472311B2 (en) | 2010-02-04 | 2013-06-25 | Genband Us Llc | Systems, methods, and computer readable media for providing instantaneous failover of packet processing elements in a network |
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US7839772B2 (en) | 2010-11-23 |
US7477595B2 (en) | 2009-01-13 |
JP2003124979A (en) | 2003-04-25 |
US20090092044A1 (en) | 2009-04-09 |
US20030067870A1 (en) | 2003-04-10 |
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