US20110086450A1 - Method of manufacturing thin film transistor array substrate - Google Patents
Method of manufacturing thin film transistor array substrate Download PDFInfo
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- US20110086450A1 US20110086450A1 US12/878,737 US87873710A US2011086450A1 US 20110086450 A1 US20110086450 A1 US 20110086450A1 US 87873710 A US87873710 A US 87873710A US 2011086450 A1 US2011086450 A1 US 2011086450A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Definitions
- the present invention relates to a method of manufacturing a thin film transistor array substrate. More particularly, the present invention relates to a method of manufacturing a thin film transistor array substrate having a reduced number of mask processes.
- a liquid crystal display adjusts light transmittance of liquid crystals using an electric field to thereby display an image.
- the liquid crystal display drives the liquid crystals by an electric field generated between a pixel electrode and a common electrode.
- the liquid crystal display includes a thin film transistor (TFT) array substrate and a color filter array substrate that are positioned opposite each other and are attached to each other, a spacer that is positioned between the two array substrates to keep a cell gap between the two array substrates constant, and a liquid crystal layer filled in the cell gap.
- TFT thin film transistor
- the thin film transistor array substrate includes a plurality of signal lines, a plurality of thin film transistors, a plurality of pixel electrodes, and an alignment layer coated for an orientation of the liquid crystals.
- the color filter array substrate includes a color filter for a color representation, a black matrix for preventing a light leakage, a common electrode, and an alignment layer coated for an orientation of the liquid crystals.
- the thin film transistor array substrate is typically manufactured using a plurality of mask processes including a semiconductor process.
- One mask process includes a large number of processes such as a thin film deposition process, a cleansing process, a photolithography process, an etching process, a photoresist peeling process, and a testing process.
- a thin film deposition process such as a thin film deposition process, a cleansing process, a photolithography process, an etching process, a photoresist peeling process, and a testing process.
- an increase in the number of mask processes results in an increase in the manufacturing cost of the liquid crystal display. Accordingly, an efforts to reduce the number of mask processes in the manufacture of the thin film transistor array substrate have been continuously made.
- the number of mask processes has recently been reduced to three (i.e., 3-mask process) through various processes such as a lift-off process.
- the number of mask processes still needs to be reduced to be equal to or less than two (i.e., 2-mask process) so as to further reduce the manufacturing cost of the liquid crystal display.
- the present invention is directed to a method of manufacturing a thin film transistor array substrate that substantially obviates one of more of the problems due to limitations and disadvantages of the related art.
- An advantage of the invention is to provide a method of manufacturing a thin film transistor array substrate having a reduced number of mask processes.
- a method of manufacturing a thin film transistor array substrate comprising sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate; forming a first resist pattern having three height levels on the second conductive material; forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern; depositing a passivation layer on the substrate, in which the first resist pattern is removed, and then forming a second resist pattern on the passivation layer; removing the second resist pattern and the passivation layer in a pixel region through an etching process using the second resist pattern; depositing a third conductive material on an entire surface of the substrate including the
- the method of manufacturing a thin film transistor array substrate may be manufactured using an imprinting process and only one photomask.
- FIG. 1 is a plane view of a thin film transistor array substrate according to an exemplary embodiment of the invention
- FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1 ;
- FIGS. 3A to 3I are cross-sectional views sequentially illustrating each stage of a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the invention using a 2-mask process;
- FIG. 4 illustrates a rationale to expose an auxiliary connection pattern
- FIG. 5 is a graph illustrating degradation characteristics of a thin film transistor depending on a material of a passivation layer.
- FIG. 6 is a cross-sectional view illustrating the form of a resist pattern having three height levels using an imprinting process.
- FIG. 1 is a plane view of a thin film transistor array substrate according to an exemplary embodiment of the invention.
- FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1 .
- a thin film transistor array substrate includes gate lines 2 and data lines 4 that cross each other on a lower substrate 1 with a gate insulating layer 20 interposed between the gate lines 2 and the data lines 4 , a thin film transistor 6 formed at each crossing of the gate lines 2 and the data lines 4 , pixel electrodes 14 formed in pixel regions defined by a cross structure of the gate lines 2 and the data lines 4 , storage capacitors Cst overlapping the gate lines 2 , a gate pad 46 connected to the gate lines 2 , and a data pad (not shown) connected to the data lines 4 .
- the thin film transistor array substrate further includes first and second slit units SL 1 and SL 2 formed around the crossings of the gate lines 2 and the data lines 4 , third and fourth slit units SL 3 and SL 4 formed around channels of the thin film transistors 6 , and a fifth slit unit SL 5 formed around a formation area of the storage capacitor Cst.
- the gate lines 2 supply a gate signal and the data lines 4 supply a data signal.
- the gate insulating layer 20 is interposed therebetween, to define the pixel regions based on the crossing structure of the gate line 2 and data line 4 .
- the gate lines 2 are formed using a first conductive pattern (or a gate metal pattern), and the data lines 4 are formed using a second conductive pattern (or a source/drain metal pattern).
- the first conductive pattern underlying the data lines 4 is over-etched through the first and second slit units SL 1 and SL 2 and is electrically separated from the gate lines 2 .
- the thin film transistors 6 are switched on or off in response to a gate signal of the gate lines 2 , and charge the pixel electrodes 14 with a data signal of the data lines 4 .
- Each of the thin film transistors 6 includes a gate electrode 8 connected to the gate lines 2 , a source electrode 10 connected to the data lines 4 , and a drain electrode 12 connected to the pixel electrode 14 .
- Each of the thin film transistors 6 further includes an active layer 30 and an ohmic contact layer 32 .
- the active layer 30 overlaps the gate electrode 8 with the gate insulating layer 20 interposed between the gate electrode 8 and the active layer 30 and forms a channel between the source electrode 10 and the drain electrode 12 .
- the ohmic contact layer 32 is formed on the active layer 30 excluding the channel from the active layer 30 , so as to ohmic-contact the source electrode 10 and the drain electrode 12 .
- the active layer 30 and the ohmic contact layer 32 overlap the data lines 4 , a storage electrode (not shown), and a data pad lower electrode (not shown) formed using the second conductive pattern as well as the source electrode 10 and the drain electrode 12 .
- the first conductive pattern underlying the source electrode 10 is over-etched through the third slit unit SL 3 and is electrically separated from the gate electrode 8 .
- the first conductive pattern underlying the drain electrode 12 is over-etched through the fourth slit unit SL 4 and is electrically separated from the gate electrode 8 .
- a passivation layer 38 covers the thin film transistor 6 , and protects the channels of the thin film transistor 6 from an external environment.
- the pixel electrode 14 is formed in the pixel region and is connected by an edge to the drain electrode 12 of the thin film transistor 6 .
- the pixel electrode 14 is formed using a third conductive pattern.
- the first conductive pattern is exposed under an end of the drain electrode 12 to be connected to the pixel electrode 14 to form an auxiliary connection pattern 16 .
- the auxiliary connection pattern 16 prevents a disconnection from occurring between the pixel electrode 14 and the drain electrode 12 when the pixel electrode 14 and the drain electrode 12 are connected to each other.
- the pixel electrode 14 forms an electric field along with a common electrode (not shown) positioned opposite the pixel electrode 14 .
- Liquid crystal molecules charged between an upper substrate (not shown) opposite the lower substrate 1 and the lower substrate 1 rotate by the electric field between the pixel electrode 14 and the common electrode.
- a transmittance of light transmitted by the pixel region varies depending on a rotation level of the liquid crystal molecules, thereby achieving a gray scale.
- the storage capacitor Cst is formed by a partial overlap between the gate line 2 and the second conductive pattern with the gate insulating layer 20 , the active layer 30 , and the ohmic contact layer 32 interposed between the second conductive pattern and the gate lines 2 .
- the storage capacitor Cst stably holds a pixel signal charged to the pixel electrode 14 until a next pixel signal is applied.
- the first conductive pattern 48 underlying the second conductive pattern is over-etched by the fifth slit unit SL 5 and is electrically separated from the gate lines 2 .
- the fifth slit unit SL 5 prevents a short between the pixel electrode 14 and the gate lines 2 when the storage capacitor Cst is formed.
- the gate pad 46 is connected to a gate driver (not shown) and supplies the gate signal to the gate line 2 .
- the gate pad 46 includes a gate pad lower electrode 42 extending from the gate lines 2 and a gate pad upper electrode 44 directly connected to the gate pad lower electrode 42 .
- the gate pad upper electrode 44 is formed using the third conductive pattern material.
- the data pad is connected to a data driver (not shown) and supplies the data signal to the data lines 4 .
- the data pad may include a data pad lower electrode extending from the data lines 4 and a data pad upper electrode directly connected to the data pad lower electrode.
- the data pad upper electrode may be formed using the third conductive pattern material.
- a method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the invention is described below with reference to FIGS. 3A to 31 .
- a first conductive material 2 ′, the gate insulating layer 20 , a semiconductor layer including an amorphous silicon layer 30 ′ and an n + -doped amorphous silicon layer 32 ′, a second conductive material 4 ′, and a first photoresist 35 are sequentially coated on the entire surface of the lower substrate 1 using a deposition method such as a plasma enhanced chemical vapor deposition (PECVD) method and a sputtering method.
- PECVD plasma enhanced chemical vapor deposition
- the first and second conductive materials 2 ′ and 4 ′ may be, for example, Cr, MoW, MoTi, Cr/Al, Cu, Al(Nd), Mo/Al, Mo/Al(Nd), and Cr/Al(Nd).
- the gate insulating layer 20 may be formed of an inorganic insulating material such as SiNx and SiOx. Other materials may be used for the gate insulating layer 20 .
- the first photoresist is patterned through a photolithography process using a first mask 100 to form a first photoresist pattern 35 having three height levels.
- the first mask 100 is implemented as a half tone mask including a transmission unit 102 , a first transflective unit 104 , a second transflective unit 106 , and a shielding unit 108 .
- an amount of light transmitted by the first transflective unit 104 is more than an amount of light transmitted by the second transflective unit 106 .
- the first photoresist pattern corresponding to the transmission unit 102 is removed through an exposure process.
- a height level of the first photoresist pattern corresponding to the first transflective unit 104 is reduced to a first level L 1 through the exposure process.
- a height level of the first photoresist pattern corresponding to the second transflective unit 106 is reduced to a second level L 2 that is greater than the first level L 1 through the exposure process.
- a height level of the first photoresist corresponding to the shielding unit 108 is held at a third level L 3 in a deposition process.
- a removed portion of the first photoresist corresponding to the transmission unit 102 corresponds to an area of the lower substrate 1 , on which the gate lines, the gate pad, the data lines, the data pad, the thin film transistors, and the storage capacitors are not formed, and a formation area of the first to fifth slit units SL 1 to SL 5 .
- the first photoresist pattern 35 with the first height level L 1 corresponds to a formation area of the gate line not overlapping a formation area of the data lines and a formation area of the storage capacitor, a formation area of the gate electrode not overlapping a formation area of the channel of the thin film transistor, a formation area of the auxiliary connection pattern, and a formation area of the gate pad lower electrode.
- the first photoresist pattern 35 with the second height level L 2 corresponds to the formation area of the channel of the thin film transistor.
- the first photoresist pattern 35 with the third height level L 3 corresponds to formation areas of the data lines, the source electrode, the drain electrode, and the storage capacitor.
- the second conductive material 4 ′ is patterned through a first wet etching process using the first photoresist pattern 35 , and then the n + -doped amorphous silicon layer 32 ′, the amorphous silicon layer 30 ′, and the gate insulating layer 20 are simultaneously patterned through a first dry etching process using the first photoresist pattern 35 . Subsequently, the first conductive material 2 ′ is patterned through the first wet etching process using the first photoresist pattern 35 .
- the first to fifth slit units SL 1 to SL 5 are formed in an area corresponding to the removed portion of the first photoresist, and the area of the lower substrate 1 , on which the gate lines 2 , the gate pad, the data lines, the data pad, the thin film transistor, and the storage capacitor are not formed, is exposed in the removed portion of the first photoresist.
- the first conductive material 2 ′ is over-etched so as to have an undercut structure and is sufficiently removed around the first to fifth slit units SL 1 to SL 5 .
- a second conductive pattern group 4 ′′ including the data lines, the source electrode, the drain electrode forming an integral body along with the source electrode, and the data pad lower electrode is formed, a semiconductor pattern including the ohmic contact layer 32 and the active layer 30 is formed, and a first conductive pattern group including the gate lines 2 , the gate electrode 8 , the gate pad lower electrode, and the auxiliary connection pattern 16 is formed.
- the entire height level of the first photoresist pattern 35 is reduced to the first level L 1 through a first ashing process using O 2 plasma.
- a second wet etching process, a second dry etching process, and the second wet etching process are sequentially performed using the first photoresist pattern 35 having the first height level L 1 to expose a portion of the gate lines 2 not overlapping the data lines, a portion of the gate electrodes 8 not overlapping the channels, a portion of the auxiliary connection pattern 16 , and the gate pad lower electrode.
- a rationale to expose the portion of the auxiliary connection pattern 16 is to prevent a disconnection between the pixel electrode 14 and the drain electrode 12 when the pixel electrode 14 is deposited in a subsequent process as shown in FIG. 4(B) . If the portion of the auxiliary connection pattern 16 is not exposed as shown in FIG. 4(A) , a disconnection occurs between the pixel electrode 14 and the drain electrode 12 may be generated when the pixel electrode 14 is deposited because the auxiliary connection pattern 16 has the undercut structure as shown in FIG. 3B .
- the entire height level of the first photoresist pattern 35 is reduced to the second level L 2 through a second ashing process using O 2 plasma to remove the first photoresist pattern 35 on the channel.
- a third wet etching process and a third dry etching process are sequentially performed using the first photoresist pattern 35 having the second height level L 2 to etch the second conductive pattern group 4 ′′ of the channel and the ohmic contact layer 32 .
- the active layer 30 of the channel is exposed, and the source electrode 10 and the drain electrode 12 are separated from each other.
- the first photoresist pattern 35 remaining in the second conductive pattern group 4 ′′ is completely removed through a strip process.
- a passivation layer 38 is coated on the entire surface of the lower substrate 1 in which the first photoresist pattern 35 is removed using a deposition method such as the PECVD method.
- the passivation layer 38 may be formed of an inorganic insulating material such as SiNx and SiOx or an organic insulating material such as polyimide. Other materials may be used.
- the inorganic insulating material is more advantageous than the organic insulating material because of the degradation characteristic of the thin film transistor resulting from a gate bias stress. More specifically, a shift level of a threshold voltage of the thin film transistor resulting from the gate bias stress when the passivation layer 38 formed of SiNx is used as shown in FIG.
- a horizontal axis indicates a voltage Vg applied to the gate electrode of the thin film transistor
- a vertical axis indicates a current Id flowing in the thin film transistor.
- a second photoresist material is coated on the entire surface of the passivation layer.
- the second photoresist is then patterned through a photolithography process using a second mask 200 to form a second photoresist pattern 40 .
- the second mask 200 includes a transmission unit 202 and a shielding unit 204 .
- the second photoresist material corresponding to the transmission unit 202 is removed through an exposure process to expose the passivation layer 38 in the pixel region, the passivation layer 38 on the gate pad lower electrode, and the passivation layer 38 on the auxiliary connection pattern 16 . Further, the second photoresist material corresponding to the shielding unit 204 remains.
- a fourth dry etching process is performed using the second photoresist pattern 40 to remove the exposed passivation layer 38 .
- the passivation layer 38 is over-etched so as to have the undercut structure around the pixel region.
- a transparent third conductive material such as ITO, IZO, and TO is coated on the entire surface of the lower substrate 1 including the position in which the passivation layer 38 is partially removed using a deposition method such as the sputtering method. Subsequently, the remaining passivation layer 38 and a third conductive pattern 14 ′ on the remaining passivation layer 38 are removed using a lift-off process.
- the pixel electrode 14 formed of a transparent material and is connected to the side of the drain electrode 12 and the auxiliary connection pattern 16 in the pixel region and partially overlaps the storage capacitor. Further, the gate pad upper electrode directly connected to the gate pad lower electrode and the data pad upper electrode directly connected to the data pad lower electrode are formed.
- the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the invention may be implemented using two photomasks.
- the method of manufacturing the thin film transistor array substrate according to another exemplary embodiment of the invention may form a resist pattern 35 having three height levels L 1 ⁇ L 3 through an imprinting process, instead of the photolithography process using a first mask 100 that was discussed above with reference to FIG. 3A .
- the thin film transistor array substrate may be manufactured using the mold and only one photomask (i.e., the second mask 200 ).
- the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the invention can be greatly simplified by reducing the number of mask processes (i.e., 2-mask process). As a result, the cost required to manufacture the thin film transistor array substrate can be greatly reduced.
Abstract
Description
- This application claims the benefit of Korea Patent Application No. 10-2009-0097711, filed on Oct. 14, 2009, which is incorporated by reference for all purposes as if fully set forth herein.
- 1. Field of the Invention
- The present invention relates to a method of manufacturing a thin film transistor array substrate. More particularly, the present invention relates to a method of manufacturing a thin film transistor array substrate having a reduced number of mask processes.
- 2. Discussion of the Related Art
- A liquid crystal display adjusts light transmittance of liquid crystals using an electric field to thereby display an image. The liquid crystal display drives the liquid crystals by an electric field generated between a pixel electrode and a common electrode.
- The liquid crystal display includes a thin film transistor (TFT) array substrate and a color filter array substrate that are positioned opposite each other and are attached to each other, a spacer that is positioned between the two array substrates to keep a cell gap between the two array substrates constant, and a liquid crystal layer filled in the cell gap.
- The thin film transistor array substrate includes a plurality of signal lines, a plurality of thin film transistors, a plurality of pixel electrodes, and an alignment layer coated for an orientation of the liquid crystals. The color filter array substrate includes a color filter for a color representation, a black matrix for preventing a light leakage, a common electrode, and an alignment layer coated for an orientation of the liquid crystals.
- The thin film transistor array substrate is typically manufactured using a plurality of mask processes including a semiconductor process. One mask process includes a large number of processes such as a thin film deposition process, a cleansing process, a photolithography process, an etching process, a photoresist peeling process, and a testing process. Thus, an increase in the number of mask processes results in an increase in the manufacturing cost of the liquid crystal display. Accordingly, an efforts to reduce the number of mask processes in the manufacture of the thin film transistor array substrate have been continuously made. The number of mask processes has recently been reduced to three (i.e., 3-mask process) through various processes such as a lift-off process.
- However, the number of mask processes still needs to be reduced to be equal to or less than two (i.e., 2-mask process) so as to further reduce the manufacturing cost of the liquid crystal display.
- Accordingly, the present invention is directed to a method of manufacturing a thin film transistor array substrate that substantially obviates one of more of the problems due to limitations and disadvantages of the related art.
- Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
- An advantage of the invention is to provide a method of manufacturing a thin film transistor array substrate having a reduced number of mask processes.
- In one aspect, there is a method of manufacturing a thin film transistor array substrate, comprising sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate; forming a first resist pattern having three height levels on the second conductive material; forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern; depositing a passivation layer on the substrate, in which the first resist pattern is removed, and then forming a second resist pattern on the passivation layer; removing the second resist pattern and the passivation layer in a pixel region through an etching process using the second resist pattern; depositing a third conductive material on an entire surface of the substrate including the pixel region; and removing the second resist pattern and the third conductive material deposited on the remaining passivation layer through a lift-off process to pattern a pixel electrode; and forming a pixel electrode connected to the drain electrode in the pixel region.
- In another aspect, the method of manufacturing a thin film transistor array substrate may be manufactured using an imprinting process and only one photomask.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
-
FIG. 1 is a plane view of a thin film transistor array substrate according to an exemplary embodiment of the invention; -
FIG. 2 is a cross-sectional view taken along line I-I′ ofFIG. 1 ; -
FIGS. 3A to 3I are cross-sectional views sequentially illustrating each stage of a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the invention using a 2-mask process; -
FIG. 4 illustrates a rationale to expose an auxiliary connection pattern; and -
FIG. 5 is a graph illustrating degradation characteristics of a thin film transistor depending on a material of a passivation layer. -
FIG. 6 is a cross-sectional view illustrating the form of a resist pattern having three height levels using an imprinting process. - Reference will now be made in detail to embodiments of the invention examples of which are illustrated in the accompanying drawings.
-
FIG. 1 is a plane view of a thin film transistor array substrate according to an exemplary embodiment of the invention.FIG. 2 is a cross-sectional view taken along line I-I′ ofFIG. 1 . - As shown in
FIGS. 1 and 2 , a thin film transistor array substrate according to an exemplary embodiment of the invention includesgate lines 2 anddata lines 4 that cross each other on alower substrate 1 with agate insulating layer 20 interposed between thegate lines 2 and thedata lines 4, athin film transistor 6 formed at each crossing of thegate lines 2 and thedata lines 4,pixel electrodes 14 formed in pixel regions defined by a cross structure of thegate lines 2 and thedata lines 4, storage capacitors Cst overlapping thegate lines 2, agate pad 46 connected to thegate lines 2, and a data pad (not shown) connected to thedata lines 4. The thin film transistor array substrate further includes first and second slit units SL1 and SL2 formed around the crossings of thegate lines 2 and thedata lines 4, third and fourth slit units SL3 and SL4 formed around channels of thethin film transistors 6, and a fifth slit unit SL5 formed around a formation area of the storage capacitor Cst. - The
gate lines 2 supply a gate signal and thedata lines 4 supply a data signal. Thegate insulating layer 20 is interposed therebetween, to define the pixel regions based on the crossing structure of thegate line 2 anddata line 4. Thegate lines 2 are formed using a first conductive pattern (or a gate metal pattern), and thedata lines 4 are formed using a second conductive pattern (or a source/drain metal pattern). The first conductive pattern underlying thedata lines 4 is over-etched through the first and second slit units SL1 and SL2 and is electrically separated from thegate lines 2. - The
thin film transistors 6 are switched on or off in response to a gate signal of thegate lines 2, and charge thepixel electrodes 14 with a data signal of thedata lines 4. Each of thethin film transistors 6 includes agate electrode 8 connected to thegate lines 2, asource electrode 10 connected to thedata lines 4, and adrain electrode 12 connected to thepixel electrode 14. Each of thethin film transistors 6 further includes anactive layer 30 and anohmic contact layer 32. Theactive layer 30 overlaps thegate electrode 8 with thegate insulating layer 20 interposed between thegate electrode 8 and theactive layer 30 and forms a channel between thesource electrode 10 and thedrain electrode 12. Theohmic contact layer 32 is formed on theactive layer 30 excluding the channel from theactive layer 30, so as to ohmic-contact thesource electrode 10 and thedrain electrode 12. Theactive layer 30 and theohmic contact layer 32 overlap thedata lines 4, a storage electrode (not shown), and a data pad lower electrode (not shown) formed using the second conductive pattern as well as thesource electrode 10 and thedrain electrode 12. The first conductive pattern underlying thesource electrode 10 is over-etched through the third slit unit SL3 and is electrically separated from thegate electrode 8. The first conductive pattern underlying thedrain electrode 12 is over-etched through the fourth slit unit SL4 and is electrically separated from thegate electrode 8. - A
passivation layer 38 covers thethin film transistor 6, and protects the channels of thethin film transistor 6 from an external environment. - The
pixel electrode 14 is formed in the pixel region and is connected by an edge to thedrain electrode 12 of thethin film transistor 6. Thepixel electrode 14 is formed using a third conductive pattern. The first conductive pattern is exposed under an end of thedrain electrode 12 to be connected to thepixel electrode 14 to form anauxiliary connection pattern 16. Theauxiliary connection pattern 16 prevents a disconnection from occurring between thepixel electrode 14 and thedrain electrode 12 when thepixel electrode 14 and thedrain electrode 12 are connected to each other. Thepixel electrode 14 forms an electric field along with a common electrode (not shown) positioned opposite thepixel electrode 14. Liquid crystal molecules charged between an upper substrate (not shown) opposite thelower substrate 1 and thelower substrate 1 rotate by the electric field between thepixel electrode 14 and the common electrode. A transmittance of light transmitted by the pixel region varies depending on a rotation level of the liquid crystal molecules, thereby achieving a gray scale. - The storage capacitor Cst is formed by a partial overlap between the
gate line 2 and the second conductive pattern with thegate insulating layer 20, theactive layer 30, and theohmic contact layer 32 interposed between the second conductive pattern and thegate lines 2. The storage capacitor Cst stably holds a pixel signal charged to thepixel electrode 14 until a next pixel signal is applied. In the storage capacitor Cst, the firstconductive pattern 48 underlying the second conductive pattern is over-etched by the fifth slit unit SL5 and is electrically separated from the gate lines 2. The fifth slit unit SL5 prevents a short between thepixel electrode 14 and thegate lines 2 when the storage capacitor Cst is formed. - The
gate pad 46 is connected to a gate driver (not shown) and supplies the gate signal to thegate line 2. Thegate pad 46 includes a gate padlower electrode 42 extending from thegate lines 2 and a gate padupper electrode 44 directly connected to the gate padlower electrode 42. The gate padupper electrode 44 is formed using the third conductive pattern material. - The data pad is connected to a data driver (not shown) and supplies the data signal to the data lines 4. The data pad may include a data pad lower electrode extending from the
data lines 4 and a data pad upper electrode directly connected to the data pad lower electrode. The data pad upper electrode may be formed using the third conductive pattern material. - A method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the invention is described below with reference to
FIGS. 3A to 31 . - As shown in
FIG. 3A , a firstconductive material 2′, thegate insulating layer 20, a semiconductor layer including anamorphous silicon layer 30′ and an n+-dopedamorphous silicon layer 32′, a secondconductive material 4′, and afirst photoresist 35 are sequentially coated on the entire surface of thelower substrate 1 using a deposition method such as a plasma enhanced chemical vapor deposition (PECVD) method and a sputtering method. The first and secondconductive materials 2′ and 4′ may be, for example, Cr, MoW, MoTi, Cr/Al, Cu, Al(Nd), Mo/Al, Mo/Al(Nd), and Cr/Al(Nd). Other materials may be used for the first and secondconductive materials 2′ and 4′. Thegate insulating layer 20 may be formed of an inorganic insulating material such as SiNx and SiOx. Other materials may be used for thegate insulating layer 20. - Subsequently, the first photoresist is patterned through a photolithography process using a
first mask 100 to form afirst photoresist pattern 35 having three height levels. For this, thefirst mask 100 is implemented as a half tone mask including atransmission unit 102, afirst transflective unit 104, asecond transflective unit 106, and ashielding unit 108. In thefirst mask 100, an amount of light transmitted by thefirst transflective unit 104 is more than an amount of light transmitted by thesecond transflective unit 106. The first photoresist pattern corresponding to thetransmission unit 102 is removed through an exposure process. A height level of the first photoresist pattern corresponding to thefirst transflective unit 104 is reduced to a first level L1 through the exposure process. A height level of the first photoresist pattern corresponding to thesecond transflective unit 106 is reduced to a second level L2 that is greater than the first level L1 through the exposure process. A height level of the first photoresist corresponding to theshielding unit 108 is held at a third level L3 in a deposition process. A removed portion of the first photoresist corresponding to thetransmission unit 102 corresponds to an area of thelower substrate 1, on which the gate lines, the gate pad, the data lines, the data pad, the thin film transistors, and the storage capacitors are not formed, and a formation area of the first to fifth slit units SL1 to SL5. Thefirst photoresist pattern 35 with the first height level L1 corresponds to a formation area of the gate line not overlapping a formation area of the data lines and a formation area of the storage capacitor, a formation area of the gate electrode not overlapping a formation area of the channel of the thin film transistor, a formation area of the auxiliary connection pattern, and a formation area of the gate pad lower electrode. Thefirst photoresist pattern 35 with the second height level L2 corresponds to the formation area of the channel of the thin film transistor. Thefirst photoresist pattern 35 with the third height level L3 corresponds to formation areas of the data lines, the source electrode, the drain electrode, and the storage capacitor. - As shown in
FIG. 3B , the secondconductive material 4′ is patterned through a first wet etching process using thefirst photoresist pattern 35, and then the n+-dopedamorphous silicon layer 32′, theamorphous silicon layer 30′, and thegate insulating layer 20 are simultaneously patterned through a first dry etching process using thefirst photoresist pattern 35. Subsequently, the firstconductive material 2′ is patterned through the first wet etching process using thefirst photoresist pattern 35. As a result, the first to fifth slit units SL1 to SL5 are formed in an area corresponding to the removed portion of the first photoresist, and the area of thelower substrate 1, on which thegate lines 2, the gate pad, the data lines, the data pad, the thin film transistor, and the storage capacitor are not formed, is exposed in the removed portion of the first photoresist. The firstconductive material 2′ is over-etched so as to have an undercut structure and is sufficiently removed around the first to fifth slit units SL1 to SL5. Further, a secondconductive pattern group 4″ including the data lines, the source electrode, the drain electrode forming an integral body along with the source electrode, and the data pad lower electrode is formed, a semiconductor pattern including theohmic contact layer 32 and theactive layer 30 is formed, and a first conductive pattern group including thegate lines 2, thegate electrode 8, the gate pad lower electrode, and theauxiliary connection pattern 16 is formed. - As shown in
FIG. 3C , the entire height level of thefirst photoresist pattern 35 is reduced to the first level L1 through a first ashing process using O2 plasma. Subsequently, a second wet etching process, a second dry etching process, and the second wet etching process are sequentially performed using thefirst photoresist pattern 35 having the first height level L1 to expose a portion of thegate lines 2 not overlapping the data lines, a portion of thegate electrodes 8 not overlapping the channels, a portion of theauxiliary connection pattern 16, and the gate pad lower electrode. A rationale to expose the portion of theauxiliary connection pattern 16 is to prevent a disconnection between thepixel electrode 14 and thedrain electrode 12 when thepixel electrode 14 is deposited in a subsequent process as shown inFIG. 4(B) . If the portion of theauxiliary connection pattern 16 is not exposed as shown inFIG. 4(A) , a disconnection occurs between thepixel electrode 14 and thedrain electrode 12 may be generated when thepixel electrode 14 is deposited because theauxiliary connection pattern 16 has the undercut structure as shown inFIG. 3B . - As shown in
FIG. 3D , the entire height level of thefirst photoresist pattern 35 is reduced to the second level L2 through a second ashing process using O2 plasma to remove thefirst photoresist pattern 35 on the channel. Subsequently, a third wet etching process and a third dry etching process are sequentially performed using thefirst photoresist pattern 35 having the second height level L2 to etch the secondconductive pattern group 4″ of the channel and theohmic contact layer 32. Hence, theactive layer 30 of the channel is exposed, and thesource electrode 10 and thedrain electrode 12 are separated from each other. Subsequently, thefirst photoresist pattern 35 remaining in the secondconductive pattern group 4″ is completely removed through a strip process. - As shown in
FIG. 3E , apassivation layer 38 is coated on the entire surface of thelower substrate 1 in which thefirst photoresist pattern 35 is removed using a deposition method such as the PECVD method. Thepassivation layer 38 may be formed of an inorganic insulating material such as SiNx and SiOx or an organic insulating material such as polyimide. Other materials may be used. The inorganic insulating material is more advantageous than the organic insulating material because of the degradation characteristic of the thin film transistor resulting from a gate bias stress. More specifically, a shift level of a threshold voltage of the thin film transistor resulting from the gate bias stress when thepassivation layer 38 formed of SiNx is used as shown inFIG. 5(A) is less than a shift level of a threshold voltage of the thin film transistor resulting from the gate bias stress when thepassivation layer 38 formed of polyimide is used as shown inFIG. 5(B) . The shift level of the threshold voltage of the thin film transistor is proportional to a degradation degree of the thin film transistor, and the degradation characteristic of the thin film transistor inversely affects the image quality. InFIG. 5 , a horizontal axis indicates a voltage Vg applied to the gate electrode of the thin film transistor, and a vertical axis indicates a current Id flowing in the thin film transistor. - As shown in
FIG. 3F , a second photoresist material is coated on the entire surface of the passivation layer. The second photoresist is then patterned through a photolithography process using asecond mask 200 to form asecond photoresist pattern 40. For this, thesecond mask 200 includes atransmission unit 202 and ashielding unit 204. In thesecond mask 200, the second photoresist material corresponding to thetransmission unit 202 is removed through an exposure process to expose thepassivation layer 38 in the pixel region, thepassivation layer 38 on the gate pad lower electrode, and thepassivation layer 38 on theauxiliary connection pattern 16. Further, the second photoresist material corresponding to theshielding unit 204 remains. - As shown in
FIG. 3G , a fourth dry etching process is performed using thesecond photoresist pattern 40 to remove the exposedpassivation layer 38. Thepassivation layer 38 is over-etched so as to have the undercut structure around the pixel region. - As shown in
FIG. 3H , a transparent third conductive material such as ITO, IZO, and TO is coated on the entire surface of thelower substrate 1 including the position in which thepassivation layer 38 is partially removed using a deposition method such as the sputtering method. Subsequently, the remainingpassivation layer 38 and a thirdconductive pattern 14′ on the remainingpassivation layer 38 are removed using a lift-off process. - As shown in
FIG. 3I , thepixel electrode 14, formed of a transparent material and is connected to the side of thedrain electrode 12 and theauxiliary connection pattern 16 in the pixel region and partially overlaps the storage capacitor. Further, the gate pad upper electrode directly connected to the gate pad lower electrode and the data pad upper electrode directly connected to the data pad lower electrode are formed. - As a result, the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the invention may be implemented using two photomasks.
- Further, as shown in
FIG. 6 , the method of manufacturing the thin film transistor array substrate according to another exemplary embodiment of the invention may form a resistpattern 35 having three height levels L1˜L3 through an imprinting process, instead of the photolithography process using afirst mask 100 that was discussed above with reference toFIG. 3A . In this alternate embodiment, the thin film transistor array substrate may be manufactured using the mold and only one photomask (i.e., the second mask 200). - As described above, the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the invention can be greatly simplified by reducing the number of mask processes (i.e., 2-mask process). As a result, the cost required to manufacture the thin film transistor array substrate can be greatly reduced.
- It will be apparent to those skilled in the art that various modifications and variation can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of the invention provided they come within the scope pf the appended claims and their equivalents.
Claims (16)
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US11392003B2 (en) | 2020-02-06 | 2022-07-19 | Au Optronics Corporation | Active device substrate and method for manufacturing the same |
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TWI464788B (en) * | 2011-12-22 | 2014-12-11 | Ind Tech Res Inst | Sensor element array and method of fabricating the same |
CN107863320B (en) * | 2017-11-22 | 2019-04-30 | 深圳市华星光电半导体显示技术有限公司 | VA type thin-film transistor array base-plate and preparation method thereof |
CN113013096B (en) * | 2021-03-01 | 2023-06-02 | 重庆先进光电显示技术研究院 | Array substrate preparation method and array substrate |
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US7932135B1 (en) | 2011-04-26 |
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