US20100319852A1 - Capacitivley coupled plasma reactor having a cooled/heated wafer support with uniform temperature distribution - Google Patents
Capacitivley coupled plasma reactor having a cooled/heated wafer support with uniform temperature distribution Download PDFInfo
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- US20100319852A1 US20100319852A1 US12/855,675 US85567510A US2010319852A1 US 20100319852 A1 US20100319852 A1 US 20100319852A1 US 85567510 A US85567510 A US 85567510A US 2010319852 A1 US2010319852 A1 US 2010319852A1
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- temperature
- electrostatic chuck
- reactor
- evaporator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
Definitions
- a capacitively coupled plasma reactor control over dissociation has been achieved with a wide impedance match space at very high RF source power over a very wide chamber pressure range.
- a wide operating range is attributable, at least in part, to a unique feature of the overhead electrode matched to the RF power source by a fixed impedance matching stub with the following features.
- the electrode capacitance is matched to the plasma reactance at a plasma-electrode resonant frequency.
- the stub resonant frequency, the plasma-electrode resonant frequency and the source frequency are nearly matched at a VHF frequency.
- a highly uniform etch rate across the wafer is attained through a number of features.
- These features include, among other things, the adjustment of the bias power feedpoint impedance on the electrostatic chuck to provide a radially uniform RF impedance across the chuck for both its role as an RF bias power applicator and as an RF return for the VHF source power from the overhead electrode.
- This adjustment is made by dielectric sleeves around the bias feed line of uniquely selected dielectric constants and lengths.
- Another feature is a dielectric ring process kit for the cathode periphery to combat edge effects.
- Other features that can further improve process or etch rate distribution uniformity include dual zone gas feeding, curving of the overhead electrode and plasma steering magnetic fields.
- a plasma reactor that includes many of these key features provides an etch rate distribution uniformity that surpasses the conventional art.
- Conventional cooling systems for regulating the temperature of the wafer support pedestal or electrostatic chuck employ a refrigeration system that cools a refrigerant or coolant medium using a conventional thermal cycle and transfers heat between the coolant and the electrostatic chuck through a separate liquid heat transfer medium.
- the coolant may be a mixture of deionized water with other substances such as glycol and (or) perfluoropolyethers.
- One problem with such systems is that, at high RF power levels (high RF bias power or high RF source power or both), such cooling systems allow the wafer temperature to drift (increase) for a significant period before stabilizing after the onset of RF power. Such temperature drift has two phases.
- the electrostatic chuck In a brief initial phase, the electrostatic chuck is at an ambient (cold) temperature when RF power is first applied, so that the temperature of the first wafer to be introduced climbs rapidly toward equilibrium as the RF heat load slowly heats the chuck. This is undesirable because the wafer temperature rises uncontrollably during processing. Even after the electrostatic chuck (ESC) has been heated by the RF heat load, the wafer temperature drifts upwardly and slowly approaches an equilibrium temperature. Such drift represents a lack of control over wafer temperature, and degrades the process. The drift is caused by the inefficiency of the conventional cooling process.
- ESC electrostatic chuck
- the heat transfer fluid that provides thermal transfer between the ESC and the coolant has a heat propagation time that introduces a significant delay between the time a temperature change is initiated in the refrigeration loop and the time that the wafer actually experiences the temperature change.
- the heat propagation time delay there is a heat propagation time delay between the cooled portion of the ESC base and the wafer at the top of the ESC, this time delay being determined by the mass and heat capacity of the materials in the ESC.
- a plasma reactor for processing a workpiece includes a reactor chamber, an electrostatic chuck within the chamber for supporting a workpiece, an RF plasma bias power generator coupled to apply RF power to the electrostatic chuck and a refrigeration loop having an evaporator inside the electrostatic chuck with a refrigerant inlet and a refrigerant outlet.
- the refrigeration loop can further include a compressor coupled at least indirectly to the outlet of the evaporator, a condenser coupled to an outlet of the compressor and an expansion valve coupled between an output of the condenser and the inlet of the evaporator.
- the evaporator includes a meandering passageway distributed in a plane beneath a top surface of the electrostatic chuck.
- an accumulator can be coupled between the outlet of the evaporator and an input of the compressor, for converting liquid form of the refrigerant received from the evaporator outlet into vapor.
- refrigerant within the evaporator is apportioned between a vapor phase and a liquid phase.
- heat transfer between the electrostatic chuck and the refrigerant within the evaporator is a constant-temperature process. This feature improves uniformity of temperature distribution across a diameter of the electrostatic chuck.
- the liquid-to-vapor ratio of refrigerant flowing through the evaporator is greater at the refrigerant outlet than at the refrigerant inlet of the evaporator, whereby heat transfer from the electrostatic chuck to the refrigeration loop occurs principally through contribution to the latent heat of vaporization of the refrigerant.
- the difference between the liquid to vapor ratios at the refrigerant inlet and outlet of the evaporator is a function of the contribution to the latent heat of vaporization of the refrigerant by heat from the electrostatic chuck.
- FIG. 1 illustrates a capacitively coupled plasma reactor embodying features of the invention.
- FIG. 2 is a schematic diagram of the RF bias power feed circuit of the reactor of FIG. 1 .
- FIG. 3 is a top view corresponding to FIG. 2 .
- FIG. 4 is a detailed diagram of a coaxial feed portion of the circuit of FIG. 2 .
- FIG. 5 illustrates a first dielectric ring process kit in the reactor of FIG. 1 .
- FIG. 6 illustrates a second dielectric ring process kit in the reactor of FIG. 1 .
- FIG. 7 illustrates a system including the reactor of FIG. 1 embodying the invention.
- FIG. 8 is a graph of the temperature as a function of enthalpy of the coolant inside the evaporator of FIG. 7 , and further depicting the dome-shaped liquid-vapor phase boundary.
- FIG. 9 is a block flow diagram of a two-phase constant temperature cooling process of the invention.
- FIG. 10 depicts an exemplary wafer temperature-time profile that may be realized using the invention.
- FIGS. 11A and 11B are contemporary timing diagrams of the wafer temperature and wafer backside gas pressure, respectively, in accordance with a process for stepping the wafer temperature down in advance of a corresponding ESC temperature change.
- FIGS. 12A and 12B are contemporary timing diagrams of the wafer temperature and wafer backside gas pressure, respectively, in accordance with a process for stepping the wafer temperature down after completion of a corresponding ESC temperature change.
- FIG. 13 illustrates a system similar to that of FIG. 7 but having multiple temperature control loops governing respectively multiple temperature zones.
- FIG. 14 illustrates an optical temperature sensor of the invention as installed in the ESC of FIG. 7 or FIG. 13 .
- FIG. 15 illustrates an upper probe of the temperature sensor of FIG. 14 .
- FIG. 16 illustrates a lower probe of the temperature sensor of FIG. 14 .
- FIG. 17 is an enlarged view of a portion of FIG. 14 showing how the upper and lower probes are joined together within the ESC.
- a plasma reactor includes a reactor chamber 100 with a wafer support 105 at the bottom of the chamber supporting a semiconductor wafer 110 .
- a semiconductor ring 115 surrounds the wafer 110 .
- the semiconductor ring 115 is supported on the grounded chamber body 127 by a dielectric (quartz) ring 120 .
- the chamber 100 is bounded at the top by a disc shaped overhead aluminum electrode 125 supported at a predetermined gap length above the wafer 110 on grounded chamber body 127 by a dielectric (quartz) seal 130 .
- An RF generator 150 applies RF plasma source power to the electrode 125 .
- RF power from the generator 150 is coupled through a coaxial cable 162 matched to the generator 150 and into a coaxial stub 135 connected to the electrode 125 .
- the stub 135 has a characteristic impedance, resonant frequency determined by its length, and provides an impedance match between the electrode 125 and the 50 Ohm coaxial cable 162 or the 50 Ohm output of the RF power generator 150 .
- the chamber body is connected to the RF return (RF ground) of the RF generator 150 .
- the RF path from the overhead electrode 125 to RF ground is affected by the capacitance of the semiconductor ring 115 , the dielectric ring 120 and the dielectric seal 130 .
- the wafer support 105 , the wafer 110 and the semiconductor ring 115 provide the primary RF return path for RF power applied to the electrode 125 .
- a large impedance match space is realized when the source power frequency, the plasma electrode resonance frequency and the stub resonance frequency are nearly matched.
- three frequencies are slightly offset from one another, with the source power frequency being 162 MHz (optimized for 300 mm wafers), the electrode-plasma resonant frequency being slightly below 162 MHz, and the stub resonance frequency being slightly above 162 MHz, in order to achieve a de-tuning effect which advantageously reduces the system Q.
- Such a reduction in system Q renders the reactor performance less susceptible to changes in conditions inside the chamber, so that the entire process is much more stable and can be carried out over a far wider process window.
- the electrode capacitance is matched to the magnitude of the negative capacitance of the plasma, and the resulting electrode-plasma resonant frequency and the source power frequency are at least nearly matched.
- the match is possible if the source power frequency is a VHF frequency.
- An advantage of choosing the capacitance of the electrode 125 in this manner, and then matching the resultant electrode-plasma resonant frequency and the source power frequency, is that resonance of the electrode and plasma near the source power frequency provides a wider impedance match and wider process window, and consequently much greater immunity to changes in process conditions, and therefore greater performance stability. Matching the stub resonance frequency to the electrode plasma resonant frequency minimizes reflections at the stub-electrode interface.
- the entire processing system is rendered less sensitive to variations in operating conditions, e.g., shifts in plasma impedance, and therefore more reliable along with a greater range of process applicability.
- the system Q is reduced to broaden the process window by slightly offsetting the stub resonant frequency, the electrode plasma resonant frequency and the plasma source power frequency from one another.
- the use of the higher VHF source power frequency proportionately decreases the Q as well. Decreasing system Q broadens the impedance match space of the system, so that its performance is not as susceptible to changes in plasma conditions or deviations from manufacturing tolerances.
- the workpiece support cathode 105 includes a metal base layer 05 supporting a lower insulation layer 10 , an electrically conductive mesh layer 15 overlying the lower insulation layer 10 and a thin top insulation layer 20 covering the conductive mesh layer 15 .
- the semiconductor workpiece or wafer 110 is placed on top of the top insulation layer 20 .
- RF bias power is coupled to the conductive mesh layer 15 to control ion bombardment energy at the surface of the wafer 110 .
- the conductive mesh 15 also can be used for electrostatically chucking and de-chucking the wafer 110 , and in such a case can be connected to a chucking voltage source in the well-known fashion.
- the conductive mesh 15 therefore is not necessarily grounded and can have, alternately, a floating electric potential or a fixed D.C. potential in accordance with conventional chucking and de-chucking operations.
- the metal base layer 05 typically (but not necessarily) is connected to ground, and forms part of a return path for VHF power radiated by the overhead electrode 125 .
- An RF bias generator 40 produces power in the HF band (e.g., 13.56 MHz). Its RF bias impedance match element 45 is coupled to the conductive mesh 15 by an elongate conductor 25 (hereinafter referred to as an RF conductor) extending through the workpiece support cathode 105 .
- the RF conductor 25 is insulated from grounded conductors such as the aluminum base layer 05 .
- the RF conductor 25 has a top termination or bias power feed point 25 a in electrical contact with the conductive mesh 15 .
- FIG. 2 is a schematic illustration corresponding to FIG. 1 of the circuit consisting of the VHF overhead electrode 125 , the RF bias applied through the workpiece support cathode 105 and the elements of the cathode 105 .
- FIG. 3 is a top plan view corresponding to FIG. 1 of the plane of the wafer 110 , with the termination or feed point 25 a of the RF conductor 25 being shown in hidden (dashed) line.
- the RF return path provided by the workpiece support cathode 105 consists of two portions in the plane of the wafer 110 , namely a radially inner portion 30 centered about and extending outwardly from the feed point 25 a and a radially outer annular portion 35 .
- the RF return paths provided by the two portions 30 , 35 are different, and therefore the two portions 30 , 35 present different impedances to the VHF power radiated by the overhead electrode 125 . Such differences may cause non-uniformities in radial distribution across the wafer surface of impedance to the VHF power, giving rise to nonuniform radial distribution of plasma ion density near the surface of the workpiece.
- a dielectric cylindrical sleeve 50 surrounds the RF conductor 25 .
- the axial length and the dielectric constant of the material constituting the sleeve 50 determine the feed point impedance presented by the RF conductor 25 to the VHF power.
- the length and dielectric constant of the sleeve 50 is selected to bring the feed point impedance to nearly zero at the VHF source power frequency (e.g., 162 MHz).
- the impedance presented by the outer region 35 surrounding the feed point 25 a is nearly a short at 162 MHz (due mainly to the presence of the conductive mesh 15 ).
- the sleeve 50 may bring the feed point impedance at the source power frequency to a value closer to that of the surrounding region.
- the impedance of the region surrounding the feed point is determined mainly by the conductive mesh 15 .
- the sleeve 50 can include additional features facilitating the foregoing improvement in VHF power deposition while simultaneously solving a separate problem, namely improving the uniformity in the electric field created by the RF bias power (at 13.56 MHz for example) applied to the wafer 110 by the RF conductor 25 .
- the problem is how to adjust radial distribution of VHF power coupling for maximum uniformity of plasma ion density while simultaneously adjusting the HF bias power electric field distribution across the wafer surface for maximum uniformity.
- FIG. 4 is an enlarged view corresponding to FIGS. 1-3 showing how the sleeve 50 can be divided into three sections, namely a top section 52 , a middle section 54 and a bottom section 56 .
- the length and dielectric constant of the sleeve top section 52 is selected and fixed to optimize the HF bias power deposition exclusively, and the lengths and dielectric constants of the remaining sleeve sections 54 , 56 are then selected to optimize VHF source power deposition by the overhead electrode while leaving the HF bias power deposition optimized.
- FIG. 5 corresponds to an enlarged view of FIG. 1 illustrating the additional feature of an annular RF coupling ring that is placed over and in electrical contact with the outer periphery of the wafer support cathode 105 .
- the top insulation layer 20 is surrounded by a removable ring 80 whose top surface 80 a is coplanar with the top surface of the wafer 110 .
- the removable ring 80 can be formed of a process-compatible material such as silicon, for example.
- removable metal ground ring 85 surrounds the removable ring 80 , its top surface 85 a being coplanar with that of the removable ring 80 .
- a generally planar surface is provided across the top of the wafer support cathode 105 bounded by the periphery of the ground ring 85 , facing the generally planar surface of the bottom of the overhead electrode 125 .
- capacitive coupling by the overhead electrode 125 is enhanced near the outer portion of the workpiece 110 by placing an RF coupling ring 90 over the removable ring 80 and over grounded ring 85 .
- the RF coupling ring 90 may be a conductor, a semiconductor or a dielectric. If the coupling ring 90 is a dielectric, then capacitive coupling to the plasma near the wafer periphery is enhanced by the presence of the dielectric material. If the RF coupling ring 90 is a conductor, it in effect narrows the electrode-to-counterelectrode spacing and thereby enhances capacitance near the peripheral region of the wafer 110 .
- the electrode-to-counterelectrode spacing is h 1 everywhere in the process zone except at the periphery occupied by the RF coupling ring 90 where the spacing is reduced from h 1 by the height h 2 of the coupling ring 90 .
- the increased capacitive coupling of source power enhances ion density at the periphery.
- the increase in ion density extends inwardly from the RF coupling ring 90 and extends over a peripheral portion of the workpiece 110 .
- the plasma ion density over the workpiece 110 is less center high and may tend toward being more nearly uniform, or possibly slightly edge-high. This condition is optimized by a careful selection of the height (thickness) h 2 of the RF coupling ring 90 .
- FIG. 6 illustrates a modification of the reactor of FIG. 5 in which a second RF coupling ceiling ring 95 is attached to the periphery of the bottom surface of the overhead electrode 125 and overlies the first RF coupling ring 90 . If each ring 90 , 95 has a thickness (height) of h 3 , then the electrode-to-counterelectrode distance near the wafer periphery is reduced by twice h 3 and the capacitance in that region is enhanced proportionately, as in the reactor of FIG. 5 .
- plasma ion density distribution uniformity is improved. Any remaining non-uniformities can be corrected by plasma-steering magnetic fields controlled by a plasma distribution controller 57 (shown in FIG. 1 ) governing D.C. current sources 58 , 59 that drive overhead coils 60 , 65 .
- planar electrode surface 125 a Another modification that can be employed to enhance plasma processing uniformity across the diameter of the wafer 110 is to change the planar electrode surface 125 a to a convex curved electrode surface 125 b .
- the degree of curvature can be selected to compensate for non-uniform plasma ion density radial distribution that may exist with the planar electrode surface 125 a.
- FIG. 7 is an enlarged view of the wafer support pedestal 105 of FIG. 1 , revealing the internal structure of the pedestal 105 .
- the pedestal 105 embodies an electrostatic chuck (ESC), as described in FIG. 2 , FIG. 7 showing that the aluminum base 05 contains coolant flow passages 200 with a coolant inlet 201 and a coolant outlet 202 .
- the internal coolant flow passages 200 constitute the evaporator of refrigeration loop, the evaporator 200 being internally contained with the ESC base 05 .
- the remaining elements of the refrigeration loop are external of the ESC 105 , and include (in order of coolant flow direction, starting from the coolant outlet 202 ) an accumulator 204 , a compressor 206 , a condenser 208 and an expansion valve 210 having a variable orifice size, all of which are of the type well-known in the art.
- An advantage of locating the evaporator 200 inside the ESC base 05 is that the delay and losses inherent in the thermal transfer fluid of the prior art are eliminated.
- the refrigeration loop (i.e., the evaporator 200 , the accumulator 204 , the compressor 206 , the condenser 208 , the expansion valve 210 and the conduits coupling them together contain a refrigerant (also referred to as a coolant or coolant medium) of a conventional type having very low electrical conductivity.
- a refrigerant also referred to as a coolant or coolant medium
- the heat flow rate of the refrigeration loop is increased ten-fold or more by operating the refrigeration loop 200 , 204 , 206 , 208 , 210 so that the coolant in the evaporator is divided between a liquid phase and a vapor phase.
- the liquid-to-vapor ratio at the inlet 201 is sufficiently high to allow for a decrease in this ratio at the outlet 202 . This guarantees that all (or nearly all) heat transfer between the ESC base 05 and the coolant within the evaporator 200 occurs through contribution to the latent heat of evaporation of the coolant.
- the heat flow in the refrigeration loop exceeds, by a factor of 10, the heat flow in a single-phase cooling cycle.
- FIG. 8 is a phase diagram depicting the enthalpy of the coolant inside the evaporator 200 as a function of temperature.
- the temperature-enthalpy boundary between the three phases (liquid, solid, vapor) is a liquid-vapor dome 216 beneath which the coolant exists in both liquid and vapor phases.
- the coolant is a sub-cooled (100%) liquid phase while to the higher enthalpy side of the dome 216 the coolant is a superheat (100%) vapor.
- the coolant flow rate established by the compressor 206 , the orifice size of the expansion valve 210 and the opening size of a bypass valve 212 that will be discussed later herein are selected by the skilled worker so that the temperature and enthalpy of the coolant inside the evaporator 200 stays under or within the liquid-vapor dome 216 of the phase diagram of FIG. 8 .
- the pressure inside the evaporator 200 is maintained at a constant level provided that a constant ESC base temperature is desired, so that there is theoretically no temperature change as the coolant flows through the evaporator, as indicated by the perfectly horizontal lines of constant pressure 218 a , 218 b of FIG. 8 .
- the coolant's temperature/enthalpy coordinates follow a line of constant pressure (e.g., line 218 a ) entering the evaporator 200 at a low enthalpy (labeled “inlet” in FIG. 8 ) and exiting at a higher enthalpy (labeled “outlet” in FIG. 8 ), with the entry and exit enthalpies lying inside or on the boundary of the liquid-vapor dome 216 .
- FIG. 8 shows that a greater increase in enthalpy (absorbed heat) is achieved at lower coolant temperatures.
- the advantage is that the wafer temperature distribution is about as uniform as the electric field distribution across the ESC, so that the etch rate uniformity achieved under the most favorable conditions by the electrical features discussed earlier herein (e.g., the RF bias feedpoint impedance adjustment by multiple dielectric sleeves and the dielectric edge ring process kit) is maintained even under the highest RF heat loads, a result heretofore unattainable.
- This result renders the reactor of FIGS. 1-7 useful for plasma processing under the current design rules (small feature sizes) and for several generations of future design rules in which feature sizes may shrink even further, a significant advantage.
- This advantage is combined with the extremely high heat capacity of cooling through latent heat of vaporization (discussed above), which provides about an order of magnitude greater heat flow rate than conventional (sensible) heat transfer via the coolant mass heat capacity.
- the first step in this method is to enhance or optimize uniformity of radial distribution of the ESC temperature by maintaining the coolant that is inside the evaporator 200 within a range of temperatures and enthalpies at which the heat transfer is through contributions to (or deductions from) the coolant's latent heat of vaporization.
- This step is depicted in block 300 of FIG. 9 .
- the step of block 300 may be carried out by limiting variation in the orifice or opening size of the expansion valve 210 to a range which confines the temperature and enthalpy of the coolant in the evaporator 200 to lie inside the liquid-vapor dome 216 of the temperature-enthalpy diagram of FIG. 8 (block 302 of FIG. 9 ).
- the skilled worker can readily determine the adjustment range of the expansion valve that confines the coolant inside the liquid-vapor dome 216 of FIG. 8 .
- the step of block 300 may also be carried out by adjusting the compressor-to-evaporator bypass flow valve 212 within a range in which the coolant inside the evaporator 200 is maintained inside the liquid-vapor dome 216 of FIG. 8 (block 304 of FIG. 9 ).
- the adjustment of the bypass valve 212 (in the step of block 304 ) and the adjustment of the expansion valve 210 (in the step of block 302 ) may be combined to achieve the desired result.
- the next step is to control the ESC temperature (block 306 of FIG. 9 ). This may be accomplished by adjusting the expansion valve 210 within the range established in the step of block 300 until a desired ESC temperature is reached (block 308 of FIG. 9 ). Alternatively, the ESC temperature may be controlled by adjusting the compressor-to-evaporator bypass valve 212 within the range established in the step of block 304 . This latter step corresponds to block 310 of FIG. 9 . Temperature control may also be carried out by performing the steps of blocks 308 and 310 together.
- variable orifice size of the expansion valve 210 is the primary control over cooling rate and wafer temperature
- additional or alternative temperature control and, if desired, heating of the wafer is provided by a compressor-to-evaporator bypass valve 212 .
- Complete conversion of all liquid coolant to the gas phase in the accumulator 204 can be ensured using a compressor-to-accumulator bypass valve 214 .
- ESC Inlet temperature ⁇ 10 to +50 deg C.
- ESC Inlet pressure 160 to 200 PSIG ESC Inlet liquid-vapor ratio: 40%-60% liquid ESC Inlet-Outlet max temperature difference: 5 deg C.
- ESC Inlet-Outlet max pressure difference 10 PSI ESC Outlet Liquid-vapor ratio: 10% liquid Accumulator outlet temperature: 60 to 80 deg C.
- Accumulator outlet pressure 25 to 35 PSIG Accumulator outlet liquid-vapor ratio: 100% vapor
- Compressor flow rate 4 gal per min Compressor outlet pressure: 260-270 PSIG Compressor outlet temperature: 80-100 deg C.
- Compressor outlet liquid-vapor ratio 100% vapor Condenser outlet temperature: 20-40 deg C.
- Condenser outlet pressure 250 PSIG Condenser liquid-vapor ratio: 100% vapor Expansion valve outlet liquid-vapor ratio: 80%
- the invention may be implemented with some small excursion beyond that limit.
- the coolant's liquid-vapor ratio may at least nearly reach zero at the evaporator outlet 202 , or may reach zero just before the evaporator outlet 202 , in which case a very small amount of sensible heating may occur. In such a case, the vast majority of heat transfer still occurs through the latent heat of vaporization, only a small fraction occurring through sensible heating, so that the advantages of the invention are realized nonetheless.
- the wafer temperature may be controlled or held at a desired temperature under a given RF heat load on the wafer 110 using a temperature feedback control loop governing either (or both) the expansion valve 210 and the bypass valve 212 , although the simplest implementation controls the expansion valve 210 only.
- the actual temperature is sensed at a temperature probe, which may be a temperature probe 220 in the ESC insulating layer 10 , a temperature probe 221 in the ESC base 05 , a temperature probe 222 at the ESC evaporator inlet 201 or a temperature probe 223 at the ESC evaporator outlet 202 or a combination of any or all of these probes.
- a feedback control loop processor 224 governs the orifice opening size of the expansion valve 210 in response to input or inputs from one or more of the temperature probes.
- the processor 224 is furnished with a user-selected desired temperature value, which may be stored in a memory or user interface 225 .
- the processor 224 compares the current temperature measured by at least one of the probes (e.g., by the probe 220 in the ESC insulating layer) against the desired temperature value.
- the processor 224 then computes an error value as the difference between the desired and measured temperature values, and determines from the error a correction to the orifice size of the expansion valve 210 that is likely to reduce the error.
- the processor 224 then causes the expansion valve orifice size to change in accordance with the correction. This cycle is repeated during the entire duration of a wafer process to control the wafer temperature.
- the wafer is cooled to avoid overheating from absorbed RF power by cooling the electrostatic chuck or wafer support pedestal.
- Thermal conductivity between the wafer 110 and the cooled ESC 105 is enhanced by injection under pressure of a thermally conductive gas (such as helium) into the interface between the backside of the wafer 110 and the top surface of the ESC 105 , a technique well-known in the art.
- a thermally conductive gas such as helium
- gas channels 226 are formed in the top surface of the ESC insulating layer 20 and a pressurized helium supply 228 is coupled to the internal ESC gas channels 226 through a backside gas pressure valve 229 .
- the wafer 110 is electrostatically clamped down onto the top surface of the insulating layer 20 by a D.C. clamping voltage applied by a clamp voltage source 128 to the grid electrode 15 .
- the thermal conductivity between the wafer 110 and the ESC top layer 20 is determined by the clamping voltage and by the thermally conductive gas (helium) pressure on the wafer backside.
- Highly agile (quick) wafer temperature control is carried out in accordance with the present invention by varying the backside gas pressure (by controlling the valve 229 ) so as to adjust the wafer temperature to the desired level.
- the thermal conductivity between the wafer and the ESC top layer 20 is changed, which changes the balance between (a) the heat absorbed by the wafer 110 from RF power applied to the grid electrode 15 or coupled to the plasma and (b) the heat drawn from the wafer to the cooled ESC. Changing this balance necessarily changes the wafer temperature.
- a feedback control loop governing the backside gas pressure can therefore be employed for agile or highly responsive control of the wafer temperature. The response of the wafer temperature to changes in the backside gas pressure is extremely quick (temperature changes reaching equilibrium within a second or less).
- a temperature regulation system employing the backside gas pressure provides agile temperature control capable of making fast adjustments to wafer temperature.
- FIG. 7 illustrates such an agile temperature feedback control system, in which a feedback control loop processor 230 governs the backside gas pressure valve 229 .
- a feedback control loop processor 230 governs the backside gas pressure valve 229 .
- One (or more) of the temperature sensors 220 , 221 , 222 or 223 in the ESC may be connected to an input of the processor 230 .
- a user interface or memory 231 may provide a user-selected or desired temperature to the processor 230 .
- the processor 230 computes an error signal as the difference between the current temperature measurement (from one of the sensors 220 , 221 , 222 ) and the desired temperature.
- the processor 230 determines from that difference a correction to the current setting of the backside gas pressure valve that would tend to reduce the temperature error, and changes the valve opening in accordance with that correction.
- a wafer temperature that is deviating above the desired temperature would require increasing the backside gas pressure to increase thermal conductivity to the cooled ESC and bring down the wafer temperature.
- the converse is true in the case of a wafer temperature deviating below the desired temperature.
- the wafer temperature can thus be controlled and set to new temperatures virtually instantly within a temperature range whose lower limit corresponds to the chilled temperature of the ESC and whose upper limit is determined by the RF heat load on the wafer.
- the wafer temperature cannot be increased in the absence of an RF heat load and the wafer temperature cannot be cooled below the temperature of the ESC. If this temperature range is sufficient, then any conventional technique may be used to maintain the ESC at a desired chilled temperature to facilitate the agile temperature feedback control loop governing the backside gas pressure.
- the agile temperature feedback control loop governing the backside gas pressure valve 229 and the large range temperature feedback control loop governing the refrigeration expansion valve 210 may be operated simultaneously in a cooperative combination under the control of a master processor 232 controlling both feedback control loop processors 224 , 230 .
- the large range temperature feedback control loop (involving the refrigeration loop consisting of the evaporator 200 , the compressor 206 , the condenser 208 and the expansion valve 210 ) controls the workpiece temperature by changing the temperature of the electrostatic chuck 105 .
- the temperature range is limited only by the thermal capacity of the refrigeration loop and can therefore set the workpiece temperature to any temperature within a very large range (e.g., ⁇ 10 deg C. to +150 deg C.).
- the rate at which it can effect a desired change in workpiece temperature at a particular moment is limited by the thermal mass of the electrostatic chuck 105 . This rate is so slow that, for example, with an electrostatic chuck for supporting a 300 mm workpiece or silicon wafer, a 10 degree C. change in workpiece temperature can require on the order of a minute or more from the time the refrigeration unit begins to change the thermal conditions of the coolant to meet the new temperature until the workpiece temperature finally reaches the new temperature.
- the agile temperature feedback control loop does not change the electrostatic chuck temperature (at least not directly) but merely changes the thermal conductivity between the workpiece and the electrostatic chuck.
- the rate at which the workpiece temperature responds to such a change is extremely high because it is limited only by the rate at which the backside gas pressure can be changed and the thermal mass of the workpiece.
- the backside gas pressure responds to movement of the valve 229 in a small fraction of a second in a typical system.
- the thermal mass is so low that the wafer (workpiece) temperature responds to changes in the backside gas pressure within a matter of a few seconds or a fraction of a second.
- the workpiece temperature response of agile feedback loop is comparatively instantaneous.
- the range over which the agile feedback loop can change the workpiece temperature is quite limited: the highest workpiece temperature that can be attained is limited by the RF heat load on the wafer, while the lowest temperature cannot be below the current temperature of the electrostatic chuck 105 .
- the advantages of each one compensate for the limitations of the other, because their combination provides a large workpiece temperature range and a very fast response.
- the master processor 232 may be programmed to effect large temperature changes using the large range feedback control loop (the processor 224 ) and effect quick but smaller temperature changes using the agile feedback control loop (the processor 230 ).
- FIG. 10 is a graph of one example of wafer temperature behavior over time.
- the solid line depicts the long term temperature behavior, in which the master processor 232 effects slow large changes in wafer temperature using the large range feedback control loop with the processor 224 .
- the dashed line depicts fast perturbations in temperature, in which the master processor 232 effects fast but small changes in wafer temperature using the agile feedback control loop with the processor 230 .
- the dual loop control afforded by the master processor 232 can be employed to (nearly) instantly move the wafer temperature to a new desired level and hold it there while the ESC temperature slowly changes to the new desired temperature.
- FIGS. 11A and 11B This is illustrated in FIGS. 11A and 11B .
- the solid line in FIG. 11A depicts the wafer temperature behavior over time in which the wafer temperature is stepped down to a lower temperature at time t 1 and held there, at which time the refrigeration loop (dashed line) begins to cool down the ESC to the lower temperature, which is not reached by the ESC until time t 2 .
- the fast change in wafer temperature at time t 1 and its temperature stability thereafter is accomplished by the agile control loop 230 .
- the agile control loop processor 230 receives the new (lower) desired wafer temperature at time t 1 and responds by immediately increasing the backside gas pressure ( FIG. 11B ) to step the wafer temperature down to the new temperature at time t 1 .
- the ESC temperature begins to fall in order to drive the ESC to (or slightly below) the new temperature at time t 1 , so that processor 224 increases the refrigeration cooling rate of the ESC to drive its temperature down.
- FIGS. 12A and 12B illustrates how the ESC temperature change may be delayed while the refrigeration loop is allowed to slowly adjust to a new temperature.
- FIG. 12A depicts temperature behavior over time while FIG. 12B depicts the corresponding backside gas pressure profile over time.
- the dual loop control afforded by the master processor 232 can be employed to temporarily hold the wafer temperature constant (solid line of FIG. 12A ) at an initial temperature level while, beginning at time t 1 , the refrigeration loop takes the ESC through a large but slow temperature excursion (dashed line of FIG. 12A ). Then, the wafer temperature is allowed to step down to the new ESC temperature.
- the agile temperature control loop steps up the backside gas pressure to step the wafer temperature down to the ESC temperature.
- the ESC 105 may be divided into plural radial zones, and different independent feedback control loops may separately control the temperature in each zone.
- An advantage of this feature is that different radial zones of the wafer 110 may be kept at different temperatures during processing so as to further reduce process or etch rate distribution non-uniformities.
- the ESC 105 is divided into two temperature control zones, namely a radially inner zone 234 and a radially outer zone 236 , and a separate temperature control apparatus is provided for each zone 234 , 236 .
- the radially inner zone 234 of the aluminum base 05 contains inner zone coolant flow passages 200 a with a coolant inlet 201 a and a coolant outlet 202 a .
- the inner zone coolant flow passages 200 a constitute the inner zone evaporator of an inner zone refrigeration loop, the evaporator 200 a being internally contained with the inner zone 234 of the ESC base 05 .
- the remaining elements of the inner zone refrigeration loop are external of the ESC 105 , and include (in order of coolant flow direction, starting from the coolant outlet 202 a ) an accumulator 204 a , a compressor 206 a , a condenser 208 a and an expansion valve 210 a having a variable orifice size, all of which are of the type well-known in the art.
- the radially outer zone 236 of the aluminum base 05 contains outer zone coolant flow passages 200 b with a coolant inlet 201 b and a coolant outlet 202 b .
- the outer zone coolant flow passages 200 b constitute the outer zone evaporator of an outer zone refrigeration loop, the evaporator 200 b being internally contained with the outer zone 236 of the ESC base 05 .
- the remaining elements of the outer zone refrigeration loop are external of the ESC 105 , and include (in order of coolant flow direction, starting from the coolant outlet 202 b ) an accumulator 204 b , a compressor 206 b , a condenser 208 b and an expansion valve 210 b having a variable orifice size, all of which are of the type well-known in the art.
- Temperature in the inner zone 234 is sensed at one or more of the following inner zone temperature probes: probe 220 a in the inner zone 234 of the ESC insulating layer 10 , probe 221 a in the inner zone of the ESC base 05 , probe 222 a at the inner zone evaporator inlet 201 a or probe 223 a at the inner zone evaporator outlet 202 a.
- An inner zone feedback control loop processor 224 a governs the orifice opening size of the inner zone expansion valve 210 a in response to input or inputs from one or more of the inner zone temperature probes.
- the inner zone processor 224 a is furnished with a user-selected desired inner zone temperature value, which may be stored in a memory or user interface 225 a .
- the inner zone processor 224 a compares the current temperature measured by at least one of the probes (e.g., the probe 220 a in the ESC insulating layer) against the desired temperature value and corrects the orifice size of the inner zone expansion valve 210 a accordingly.
- An outer zone feedback control loop processor 224 b governs the orifice opening size of the outer zone expansion valve 210 b in response to input or inputs from one or more of the outer zone temperature probes.
- the outer zone processor 224 b is furnished with a user-selected desired outer zone temperature value, which may be stored in a memory or user interface 225 b .
- the outer zone processor 224 b compares the current temperature measured by at least one of the probes (e.g., the outer zone probe 220 b in the ESC insulating layer) against the desired temperature value and corrects the orifice size of the outer zone expansion valve 210 b accordingly.
- thermal conductivity between the wafer 110 and the cooled ESC 105 is enhanced by injection under pressure of a thermally conductive gas (such as helium) into the interface between the backside of the wafer 110 and the top surface of the ESC 105 , a technique well-known in the art.
- a thermally conductive gas such as helium
- inner zone gas channels 226 a are formed in inner zone 234 of the top surface of the ESC insulating layer 20 and a pressurized helium supply 228 a is coupled to the inner zone gas channels 226 a through an inner zone backside gas pressure valve 229 a .
- the wafer 110 is electrostatically clamped down onto the top surface of the insulating layer 20 by a D.C.
- the thermal conductivity between the wafer 110 and the ESC top layer 20 is determined by the clamping voltage and by the thermally conductive gas (helium) pressure on the wafer backside.
- Highly agile (quick) wafer temperature control is carried out in the inner temperature zone 234 by controlling the inner zone valve 229 a so as to adjust the wafer temperature to the desired level.
- An inner zone agile feedback control loop processor 230 a governs the inner zone backside gas pressure valve 229 a .
- One (or more) of the inner zone temperature sensors 220 a , 221 a , 222 a or 223 a in the ESC inner zone 234 may be connected to an input of the inner zone agile processor 230 a .
- An inner zone user interface or memory 231 a may provide a user-selected or desired temperature to the inner zone agile processor 230 a .
- the processor 230 a senses an error as the difference between the current temperature measurement (from one of the inner zone sensors 220 a , 221 a , 222 a ) and the desired temperature, and changes the opening of the inner zone backside gas valve 229 a accordingly.
- outer zone gas channels 226 b are formed in outer zone 236 of the top surface of the ESC insulating layer 20 and the pressurized helium supply 228 b is coupled to the outer zone gas channels 226 b through an outer zone backside gas pressure valve 229 b .
- Highly agile (quick) wafer temperature control is carried out in the outer temperature zone 236 by controlling the outer zone valve 229 b so as to adjust the wafer temperature to the desired level.
- An outer zone agile feedback control loop processor 230 b governs the outer zone backside gas pressure valve 229 b .
- One (or more) of the outer zone temperature sensors 220 b , 221 b , 222 b or 223 b in the ESC outer zone 236 may be connected to an input of the outer zone agile processor 230 b .
- An outer zone user interface or memory 231 b may provide a user-selected or desired temperature to the inner zone agile processor 230 b .
- the processor 230 b senses an error as the difference between the current temperature measurement (from one of the outer zone sensors 220 b , 221 b , 222 b ) and the desired temperature, and changes the opening of the outer zone backside gas valve 229 b accordingly.
- the radial profile of the wafer temperature may be controlled over a large range with agile response.
- FIG. 14 depicts a preferred temperature probe 238 installed in the plasma reactor of FIG. 1 .
- the probe 238 consists of two separable portions, namely an upper probe 239 installed in the ESC 105 and a lower probe 240 installed in a portion of the reactor chamber beneath and supporting the ESC 105 , namely a chamber host base 241 .
- the upper probe 239 is depicted in the enlarged view of FIG. 15 , and lies in an area of high RF electric potential (i.e., inside the ESC insulating layer or puck 10 , 20 ).
- the upper probe 239 is firmly inserted in an elongate axial hole within the ESC 105 that closely fits the upper probe 239 , and the tip of the upper probe 239 lies very close (e.g., within 3 to 3.5 mm) to the top surface of the puck 20 .
- the advantage is that the probe 239 is sufficiently close to the wafer 110 to minimize or eliminate temperature measurement errors.
- This area of the ESC has very high electric field potential during processing so that any electrical properties that the upper probe 239 may have would have profound effects on plasma processing on the wafer.
- the upper probe 239 therefore includes RF compatibility features which minimize or eliminate any effect that the probe 239 might otherwise have on the electric field or on the RF impedance distribution.
- Such RF compatibility features ensure that the probe 239 does not distort or perturb the ESC electric field or RF impedance distribution that has been so carefully adjusted with the features of the feedpoint impedance adjustment of FIGS. 2-4 and/or the dielectric ring process kit of FIGS. 5-6 (for example).
- the RF compatibility features of the upper probe 239 include a complete absence of any conductive materials within the probe 239 , an orientation of the probe in the axial direction (to minimize its effect on the radial electric field or RF impedance distribution) and its small diameter, which is on the order of a fraction of a Debeye length of the plasma in the chamber.
- an electrically nonconductive optical temperature transducer 242 e.g., a phosphor material whose blackbody radiation spectrum is a well-known function of its temperature.
- the optical temperature transducer 242 is coupled to a long thin optical fiber 243 contained within the thin axial upper probe 239 .
- the upper probe 239 further includes an opaque cylindrical dielectric sleeve 244 surrounding the optical fiber 243 and preferably consisting of glass-impregnated plastic.
- the optical temperature transducer 242 is capped by a dielectric cap 245 of a material that is, preferably, identical to the dielectric material of the ESC puck 10 , 20 , which in the preferred embodiment is aluminum nitride.
- This latter feature ensures that the temperature behavior of the material contacting the optical temperature transducer 242 (i.e., the cap 245 ) is identical to the material whose temperature is to be measured (i.e., the ESC puck layer 20 that is in direct contact with the wafer 110 ).
- the upper probe 239 further includes a mounting plate 246 that is removably fastened to the bottom surface of the ESC base 05 .
- the mounting plate 246 supports a spring housing 247 containing a coil spring 248 compressed between a shoulder 245 of the housing 247 and an annular ring 249 fastened to a portion of the probe sleeve 244 lying within the housing 247 .
- the coil spring 248 is compressed to force the tip of the probe 239 to self-align to the top end of the hole.
- the lower probe 240 is shown in the enlarged view of FIG. 16 and includes an optical fiber 250 surrounded by an opaque lower cylindrical sleeve 251 . Since the lower probe 240 is below the grounded conductive ESC base 05 , it is located outside of areas of high RF electric fields, and therefore need not be formed of non-conductive materials. In fact, the lower cylindrical sleeve 251 may be formed of steel, for example. The top end 252 of the lower probe 240 is tightly received within a hole 253 in the mounting plate 246 of the upper probe 239 .
- the lower probe 240 further includes a mounting plate 254 that is removably fastened to the bottom surface of the chamber housing host base 241 .
- the mounting plate 254 supports a spring housing 255 containing a coil spring 256 compressed between a shoulder 257 of the housing 255 and an annular ring 258 fastened to a portion of the lower probe sleeve 251 lying within the housing 255 .
- the coil spring 256 is compressed to force the tip of the lower probe 240 to self-align to the top end of the hole 253 .
- the resulting self-alignment of the lower probe 240 against the upper probe 239 is illustrated in FIG.
- FIG. 14 depicts a single temperature probe whose tip lies near the top of the ESC 105
- another identical probe may be placed in a lower portion of the ESC but at the same radial location as first probe.
- Other identical probes may be placed at different radial (azimuthal) locations within the ESC but in the same height (axial location) as other probes.
- the temperature probes 220 a , 220 b of the different temperature zones 234 , 236 of FIG. 13 may each be of the type described above in FIGS. 13-16 and are located at different radial locations at a common axial height.
- any or all such processors may be implemented in a single common processor programmed to perform the functions of each of the individual feedback control loop processors.
- other resources associated with the different control loops such as the dual helium supplies 228 a , 228 b , may be implemented with a single supply or resource with separately controlled interfaces (e.g., such as a single helium supply and dual pressure control valves 229 a , 229 b ).
- a common RF bias power source may be employed to apply different levels of RF bias power to the inner and outer mesh electrodes 15 a , 15 b .
- separate RF bias power generators may be employed to realize the separate RF bias power levels.
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Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 11/409,292 filed Apr. 21, 2006 entitled CAPACITIVELY COUPLED PLASMA REACTOR HAVING A COOLED/HEATED WAFER SUPPORT WITH UNIFORM TEMPERATURE DISTRIBUTION by Paul Brillhart, et al., which claims the benefit of U.S. Provisional Patent Application Ser. No. 60/725,763 filed Oct. 11, 2005. All of the above applications are hereby incorporated by reference in their entirety.
- In a capacitively coupled plasma reactor, control over dissociation has been achieved with a wide impedance match space at very high RF source power over a very wide chamber pressure range. Such a wide operating range is attributable, at least in part, to a unique feature of the overhead electrode matched to the RF power source by a fixed impedance matching stub with the following features. First, the electrode capacitance is matched to the plasma reactance at a plasma-electrode resonant frequency. The stub resonant frequency, the plasma-electrode resonant frequency and the source frequency are nearly matched at a VHF frequency. A highly uniform etch rate across the wafer is attained through a number of features. These features include, among other things, the adjustment of the bias power feedpoint impedance on the electrostatic chuck to provide a radially uniform RF impedance across the chuck for both its role as an RF bias power applicator and as an RF return for the VHF source power from the overhead electrode. This adjustment is made by dielectric sleeves around the bias feed line of uniquely selected dielectric constants and lengths. Another feature is a dielectric ring process kit for the cathode periphery to combat edge effects. Other features that can further improve process or etch rate distribution uniformity include dual zone gas feeding, curving of the overhead electrode and plasma steering magnetic fields. A plasma reactor that includes many of these key features provides an etch rate distribution uniformity that surpasses the conventional art.
- With rapid shrinking of circuit feature sizes, the requirements for etch rate distribution uniformity are so stringent that small temperature variations across the wafer must now be minimized or eliminated, with the added proviso that future sophisticated process recipes designed to meet the latest stringent requirements will require agile and highly accurate time-changing wafer temperature profiling, and/or RF heat load profiling. Such changes must be effected or compensated with the greatest temperature uniformity across the wafer. How to do all this without degrading the now highly uniform etch rate distribution currently afforded by the reactor is a difficult problem. Moreover, such highly accurate and agile temperature control or profiling requires accurate temperature sensing at the wafer. However, introduction of temperature probes near the wafer will create parasitic RF fields which distort the fine effects of the feed-point impedance dielectric sleeves and the dielectric ring process kit, defeating their purpose. Temperature non-uniformities at the wafer arising from lack of control, to the extent that they impact the etch chemistry, will have the same ultimate effect of distorting an otherwise uniform environment.
- Conventional cooling systems for regulating the temperature of the wafer support pedestal or electrostatic chuck employ a refrigeration system that cools a refrigerant or coolant medium using a conventional thermal cycle and transfers heat between the coolant and the electrostatic chuck through a separate liquid heat transfer medium. The coolant may be a mixture of deionized water with other substances such as glycol and (or) perfluoropolyethers. One problem with such systems is that, at high RF power levels (high RF bias power or high RF source power or both), such cooling systems allow the wafer temperature to drift (increase) for a significant period before stabilizing after the onset of RF power. Such temperature drift has two phases. In a brief initial phase, the electrostatic chuck is at an ambient (cold) temperature when RF power is first applied, so that the temperature of the first wafer to be introduced climbs rapidly toward equilibrium as the RF heat load slowly heats the chuck. This is undesirable because the wafer temperature rises uncontrollably during processing. Even after the electrostatic chuck (ESC) has been heated by the RF heat load, the wafer temperature drifts upwardly and slowly approaches an equilibrium temperature. Such drift represents a lack of control over wafer temperature, and degrades the process. The drift is caused by the inefficiency of the conventional cooling process.
- Another problem is that rapid temperature variations between two temperature levels cannot be carried out for two reasons. First, the heat transfer fluid that provides thermal transfer between the ESC and the coolant has a heat propagation time that introduces a significant delay between the time a temperature change is initiated in the refrigeration loop and the time that the wafer actually experiences the temperature change. Secondly, there is a heat propagation time delay between the cooled portion of the ESC base and the wafer at the top of the ESC, this time delay being determined by the mass and heat capacity of the materials in the ESC.
- One of the most difficult problems is that under high RF heat load on the wafer requiring high rates of thermal transfer through the cooled ESC, the thermal transfer fluid temperature changes significantly as it flows through the fluid passages within the ESC, so that temperature distribution across the ESC (and therefore across the wafer) becomes non-uniform. Such non-uniformities have not presented a significant problem under older design rules (larger semiconductor circuit feature sizes) because etch rate uniformity across the wafer diameter was not as critical at the earlier (larger) feature sizes/design rules. However, the current feature sizes have dictated the extremely uniform electric fields across the ESC achieved by the features described above (e.g., RF bias feedpoint impedance adjustment, process kit dielectric edge rings). However, the high RF heat loads, dictated by some of the latest plasma etch process recipes, cause temperature non-uniformities across the wafer diameter (due to sensible heating of the thermal transfer fluid within the ESC) that distort an otherwise uniform etch rate distribution across the wafer. It has seemed that this problem cannot be avoided without limiting the RF power applied to the wafer. However, as etch rate uniformity requirements become more stringent in the future, further reduction in RF power limits to satisfy such requirements will produce more anemic process results, which will ultimately be unacceptable. Therefore, there is a need for a way of extracting heat from the wafer under high RF heat load conditions without introducing temperature non-uniformities across the ESC or across the wafer.
- A plasma reactor for processing a workpiece includes a reactor chamber, an electrostatic chuck within the chamber for supporting a workpiece, an RF plasma bias power generator coupled to apply RF power to the electrostatic chuck and a refrigeration loop having an evaporator inside the electrostatic chuck with a refrigerant inlet and a refrigerant outlet. The refrigeration loop can further include a compressor coupled at least indirectly to the outlet of the evaporator, a condenser coupled to an outlet of the compressor and an expansion valve coupled between an output of the condenser and the inlet of the evaporator. Preferably, the evaporator includes a meandering passageway distributed in a plane beneath a top surface of the electrostatic chuck. Optionally, an accumulator can be coupled between the outlet of the evaporator and an input of the compressor, for converting liquid form of the refrigerant received from the evaporator outlet into vapor. Preferably, refrigerant within the evaporator is apportioned between a vapor phase and a liquid phase. As a result, heat transfer between the electrostatic chuck and the refrigerant within the evaporator is a constant-temperature process. This feature improves uniformity of temperature distribution across a diameter of the electrostatic chuck. When the wafer is being cooled, for example, the liquid-to-vapor ratio of refrigerant flowing through the evaporator is greater at the refrigerant outlet than at the refrigerant inlet of the evaporator, whereby heat transfer from the electrostatic chuck to the refrigeration loop occurs principally through contribution to the latent heat of vaporization of the refrigerant. The difference between the liquid to vapor ratios at the refrigerant inlet and outlet of the evaporator is a function of the contribution to the latent heat of vaporization of the refrigerant by heat from the electrostatic chuck.
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FIG. 1 illustrates a capacitively coupled plasma reactor embodying features of the invention. -
FIG. 2 is a schematic diagram of the RF bias power feed circuit of the reactor ofFIG. 1 . -
FIG. 3 is a top view corresponding toFIG. 2 . -
FIG. 4 is a detailed diagram of a coaxial feed portion of the circuit ofFIG. 2 . -
FIG. 5 illustrates a first dielectric ring process kit in the reactor ofFIG. 1 . -
FIG. 6 illustrates a second dielectric ring process kit in the reactor ofFIG. 1 . -
FIG. 7 illustrates a system including the reactor ofFIG. 1 embodying the invention. -
FIG. 8 is a graph of the temperature as a function of enthalpy of the coolant inside the evaporator ofFIG. 7 , and further depicting the dome-shaped liquid-vapor phase boundary. -
FIG. 9 is a block flow diagram of a two-phase constant temperature cooling process of the invention. -
FIG. 10 depicts an exemplary wafer temperature-time profile that may be realized using the invention. -
FIGS. 11A and 11B are contemporary timing diagrams of the wafer temperature and wafer backside gas pressure, respectively, in accordance with a process for stepping the wafer temperature down in advance of a corresponding ESC temperature change. -
FIGS. 12A and 12B are contemporary timing diagrams of the wafer temperature and wafer backside gas pressure, respectively, in accordance with a process for stepping the wafer temperature down after completion of a corresponding ESC temperature change. -
FIG. 13 illustrates a system similar to that ofFIG. 7 but having multiple temperature control loops governing respectively multiple temperature zones. -
FIG. 14 illustrates an optical temperature sensor of the invention as installed in the ESC ofFIG. 7 orFIG. 13 . -
FIG. 15 illustrates an upper probe of the temperature sensor ofFIG. 14 . -
FIG. 16 illustrates a lower probe of the temperature sensor ofFIG. 14 . -
FIG. 17 is an enlarged view of a portion ofFIG. 14 showing how the upper and lower probes are joined together within the ESC. - Referring to
FIG. 1 , a plasma reactor includes areactor chamber 100 with awafer support 105 at the bottom of the chamber supporting asemiconductor wafer 110. Asemiconductor ring 115 surrounds thewafer 110. Thesemiconductor ring 115 is supported on the groundedchamber body 127 by a dielectric (quartz)ring 120. Thechamber 100 is bounded at the top by a disc shapedoverhead aluminum electrode 125 supported at a predetermined gap length above thewafer 110 on groundedchamber body 127 by a dielectric (quartz)seal 130. AnRF generator 150 applies RF plasma source power to theelectrode 125. RF power from thegenerator 150 is coupled through acoaxial cable 162 matched to thegenerator 150 and into acoaxial stub 135 connected to theelectrode 125. Thestub 135 has a characteristic impedance, resonant frequency determined by its length, and provides an impedance match between theelectrode 125 and the 50 Ohmcoaxial cable 162 or the 50 Ohm output of theRF power generator 150. The chamber body is connected to the RF return (RF ground) of theRF generator 150. The RF path from theoverhead electrode 125 to RF ground is affected by the capacitance of thesemiconductor ring 115, thedielectric ring 120 and thedielectric seal 130. Thewafer support 105, thewafer 110 and thesemiconductor ring 115 provide the primary RF return path for RF power applied to theelectrode 125. - A large impedance match space is realized when the source power frequency, the plasma electrode resonance frequency and the stub resonance frequency are nearly matched. Preferably, three frequencies are slightly offset from one another, with the source power frequency being 162 MHz (optimized for 300 mm wafers), the electrode-plasma resonant frequency being slightly below 162 MHz, and the stub resonance frequency being slightly above 162 MHz, in order to achieve a de-tuning effect which advantageously reduces the system Q. Such a reduction in system Q renders the reactor performance less susceptible to changes in conditions inside the chamber, so that the entire process is much more stable and can be carried out over a far wider process window.
- The electrode capacitance is matched to the magnitude of the negative capacitance of the plasma, and the resulting electrode-plasma resonant frequency and the source power frequency are at least nearly matched. For the typical metal and dielectric etch process conditions (i.e., plasma density between 109-1012 ions/cc, a 2-inch gap and an electrode diameter on the order of roughly 12 inches), the match is possible if the source power frequency is a VHF frequency.
- An advantage of choosing the capacitance of the
electrode 125 in this manner, and then matching the resultant electrode-plasma resonant frequency and the source power frequency, is that resonance of the electrode and plasma near the source power frequency provides a wider impedance match and wider process window, and consequently much greater immunity to changes in process conditions, and therefore greater performance stability. Matching the stub resonance frequency to the electrode plasma resonant frequency minimizes reflections at the stub-electrode interface. The entire processing system is rendered less sensitive to variations in operating conditions, e.g., shifts in plasma impedance, and therefore more reliable along with a greater range of process applicability. - In accordance with a further aspect, the system Q is reduced to broaden the process window by slightly offsetting the stub resonant frequency, the electrode plasma resonant frequency and the plasma source power frequency from one another. The use of the higher VHF source power frequency proportionately decreases the Q as well. Decreasing system Q broadens the impedance match space of the system, so that its performance is not as susceptible to changes in plasma conditions or deviations from manufacturing tolerances.
- Continuing to refer to
FIG. 1 , theworkpiece support cathode 105 includes a metal base layer 05 supporting alower insulation layer 10, an electricallyconductive mesh layer 15 overlying thelower insulation layer 10 and a thintop insulation layer 20 covering theconductive mesh layer 15. The semiconductor workpiece orwafer 110 is placed on top of thetop insulation layer 20. RF bias power is coupled to theconductive mesh layer 15 to control ion bombardment energy at the surface of thewafer 110. Theconductive mesh 15 also can be used for electrostatically chucking and de-chucking thewafer 110, and in such a case can be connected to a chucking voltage source in the well-known fashion. Theconductive mesh 15 therefore is not necessarily grounded and can have, alternately, a floating electric potential or a fixed D.C. potential in accordance with conventional chucking and de-chucking operations. The metal base layer 05 typically (but not necessarily) is connected to ground, and forms part of a return path for VHF power radiated by theoverhead electrode 125. - An
RF bias generator 40 produces power in the HF band (e.g., 13.56 MHz). Its RF biasimpedance match element 45 is coupled to theconductive mesh 15 by an elongate conductor 25 (hereinafter referred to as an RF conductor) extending through theworkpiece support cathode 105. TheRF conductor 25 is insulated from grounded conductors such as the aluminum base layer 05. TheRF conductor 25 has a top termination or biaspower feed point 25 a in electrical contact with theconductive mesh 15. -
FIG. 2 is a schematic illustration corresponding toFIG. 1 of the circuit consisting of the VHFoverhead electrode 125, the RF bias applied through theworkpiece support cathode 105 and the elements of thecathode 105. -
FIG. 3 is a top plan view corresponding toFIG. 1 of the plane of thewafer 110, with the termination or feedpoint 25 a of theRF conductor 25 being shown in hidden (dashed) line. The RF return path provided by theworkpiece support cathode 105 consists of two portions in the plane of thewafer 110, namely a radiallyinner portion 30 centered about and extending outwardly from thefeed point 25 a and a radially outerannular portion 35. The RF return paths provided by the twoportions portions overhead electrode 125. Such differences may cause non-uniformities in radial distribution across the wafer surface of impedance to the VHF power, giving rise to nonuniform radial distribution of plasma ion density near the surface of the workpiece. - In order to solve this problem, a dielectric cylindrical sleeve 50 (shown in the enlarged view of
FIG. 2 ) surrounds theRF conductor 25. The axial length and the dielectric constant of the material constituting thesleeve 50 determine the feed point impedance presented by theRF conductor 25 to the VHF power. In one example, the length and dielectric constant of thesleeve 50 is selected to bring the feed point impedance to nearly zero at the VHF source power frequency (e.g., 162 MHz). The impedance presented by theouter region 35 surrounding thefeed point 25 a is nearly a short at 162 MHz (due mainly to the presence of the conductive mesh 15). Therefore, in the latter example thesleeve 50 may bring the feed point impedance at the source power frequency to a value closer to that of the surrounding region. Here, the impedance of the region surrounding the feed point is determined mainly by theconductive mesh 15. As a result, a more uniform radial distribution of impedance is attained, for more uniform capacitive coupling of VHF source power. - The
sleeve 50 can include additional features facilitating the foregoing improvement in VHF power deposition while simultaneously solving a separate problem, namely improving the uniformity in the electric field created by the RF bias power (at 13.56 MHz for example) applied to thewafer 110 by theRF conductor 25. The problem is how to adjust radial distribution of VHF power coupling for maximum uniformity of plasma ion density while simultaneously adjusting the HF bias power electric field distribution across the wafer surface for maximum uniformity. -
FIG. 4 is an enlarged view corresponding toFIGS. 1-3 showing how thesleeve 50 can be divided into three sections, namely atop section 52, amiddle section 54 and abottom section 56. The length and dielectric constant of thesleeve top section 52 is selected and fixed to optimize the HF bias power deposition exclusively, and the lengths and dielectric constants of the remainingsleeve sections - Center-high plasma distribution non-uniformity is reduced by selectively enhancing capacitive coupling from the
overhead electrode 125 to the plasma in the vicinity of the workpiece periphery.FIG. 5 corresponds to an enlarged view ofFIG. 1 illustrating the additional feature of an annular RF coupling ring that is placed over and in electrical contact with the outer periphery of thewafer support cathode 105. As shown inFIG. 5 , thetop insulation layer 20 is surrounded by aremovable ring 80 whosetop surface 80 a is coplanar with the top surface of thewafer 110. Theremovable ring 80 can be formed of a process-compatible material such as silicon, for example. Optionally, removablemetal ground ring 85 surrounds theremovable ring 80, itstop surface 85 a being coplanar with that of theremovable ring 80. A generally planar surface is provided across the top of thewafer support cathode 105 bounded by the periphery of theground ring 85, facing the generally planar surface of the bottom of theoverhead electrode 125. As a result, capacitive coupling across the entire processing zone bounded by theoverhead electrode 125 and thewafer support cathode 105 is generally uniform. In order to overcome non-uniformity inherent in the center-high plasma ion density distribution of the reactor, capacitive coupling by theoverhead electrode 125 is enhanced near the outer portion of theworkpiece 110 by placing anRF coupling ring 90 over theremovable ring 80 and over groundedring 85. TheRF coupling ring 90 may be a conductor, a semiconductor or a dielectric. If thecoupling ring 90 is a dielectric, then capacitive coupling to the plasma near the wafer periphery is enhanced by the presence of the dielectric material. If theRF coupling ring 90 is a conductor, it in effect narrows the electrode-to-counterelectrode spacing and thereby enhances capacitance near the peripheral region of thewafer 110. Thus, the electrode-to-counterelectrode spacing is h1 everywhere in the process zone except at the periphery occupied by theRF coupling ring 90 where the spacing is reduced from h1 by the height h2 of thecoupling ring 90. The increased capacitive coupling of source power enhances ion density at the periphery. The increase in ion density extends inwardly from theRF coupling ring 90 and extends over a peripheral portion of theworkpiece 110. Thus, the plasma ion density over theworkpiece 110 is less center high and may tend toward being more nearly uniform, or possibly slightly edge-high. This condition is optimized by a careful selection of the height (thickness) h2 of theRF coupling ring 90. -
FIG. 6 illustrates a modification of the reactor ofFIG. 5 in which a second RFcoupling ceiling ring 95 is attached to the periphery of the bottom surface of theoverhead electrode 125 and overlies the firstRF coupling ring 90. If eachring FIG. 5 . - With the
RF coupling ring 90 and thedielectric sleeve 50, plasma ion density distribution uniformity is improved. Any remaining non-uniformities can be corrected by plasma-steering magnetic fields controlled by a plasma distribution controller 57 (shown inFIG. 1 ) governing D.C.current sources - Another modification that can be employed to enhance plasma processing uniformity across the diameter of the
wafer 110 is to change theplanar electrode surface 125 a to a convexcurved electrode surface 125 b. The degree of curvature can be selected to compensate for non-uniform plasma ion density radial distribution that may exist with theplanar electrode surface 125 a. -
FIG. 7 is an enlarged view of thewafer support pedestal 105 ofFIG. 1 , revealing the internal structure of thepedestal 105. Thepedestal 105 embodies an electrostatic chuck (ESC), as described inFIG. 2 ,FIG. 7 showing that the aluminum base 05 containscoolant flow passages 200 with acoolant inlet 201 and acoolant outlet 202. The internalcoolant flow passages 200 constitute the evaporator of refrigeration loop, theevaporator 200 being internally contained with the ESC base 05. The remaining elements of the refrigeration loop are external of theESC 105, and include (in order of coolant flow direction, starting from the coolant outlet 202) anaccumulator 204, acompressor 206, acondenser 208 and anexpansion valve 210 having a variable orifice size, all of which are of the type well-known in the art. An advantage of locating theevaporator 200 inside the ESC base 05 is that the delay and losses inherent in the thermal transfer fluid of the prior art are eliminated. The refrigeration loop (i.e., theevaporator 200, theaccumulator 204, thecompressor 206, thecondenser 208, theexpansion valve 210 and the conduits coupling them together contain a refrigerant (also referred to as a coolant or coolant medium) of a conventional type having very low electrical conductivity. - In order to overcome the problem of thermal drift during processing, the heat flow rate of the refrigeration loop is increased ten-fold or more by operating the
refrigeration loop inlet 201 is sufficiently high to allow for a decrease in this ratio at theoutlet 202. This guarantees that all (or nearly all) heat transfer between the ESC base 05 and the coolant within theevaporator 200 occurs through contribution to the latent heat of evaporation of the coolant. As a result, the heat flow in the refrigeration loop exceeds, by a factor of 10, the heat flow in a single-phase cooling cycle. This condition is satisfied provided the decrease in the coolant's liquid-to-vapor ratio from theinlet 201 to theoutlet 202 is sufficiently limited so that at least a very small amount of liquid remains at (or just before) theoutlet 202. This requires that the coolant capacity of the refrigeration loop is not exceeded by the RF heat load on the wafer. One way of ensuring this is to provide the refrigeration loop with a maximum cooling capacity that is about twice the maximum anticipated heat load on the wafer. In one implementation of a reactor of the type depicted inFIGS. 1-7 , the maximum cooling rate of the refrigeration loop was between about three and four times the maximum anticipated heat load on the wafer. The heat load on the wafer was about 30% of the applied RF power on the wafer. The liquid-to-vapor ratio was between about 40% and 60% at theinlet 201 and about 10% at theoutlet 202. -
FIG. 8 is a phase diagram depicting the enthalpy of the coolant inside theevaporator 200 as a function of temperature. The temperature-enthalpy boundary between the three phases (liquid, solid, vapor) is a liquid-vapor dome 216 beneath which the coolant exists in both liquid and vapor phases. To the lower enthalpy side of the dome 21E, the coolant is a sub-cooled (100%) liquid phase while to the higher enthalpy side of thedome 216 the coolant is a superheat (100%) vapor. At the apex of the dome is the triple point at which all three phases of the coolant are present simultaneously. The controllable parameters of the refrigerant loop ofFIG. 7 , (i.e., the coolant flow rate established by thecompressor 206, the orifice size of theexpansion valve 210 and the opening size of abypass valve 212 that will be discussed later herein) are selected by the skilled worker so that the temperature and enthalpy of the coolant inside theevaporator 200 stays under or within the liquid-vapor dome 216 of the phase diagram ofFIG. 8 . The pressure inside theevaporator 200 is maintained at a constant level provided that a constant ESC base temperature is desired, so that there is theoretically no temperature change as the coolant flows through the evaporator, as indicated by the perfectly horizontal lines ofconstant pressure FIG. 8 . (In actual practice, there is a negligible temperature difference across the ESC inlet andoutlet evaporator 200 absorbs heat from the ESC base 05, its internal energy U increases, causing its enthalpy to increase (where enthalpy is U+PV, P and V being pressure and volume inside the evaporator 200). To satisfy the requirement for two-phase heat transfer through latent heat of evaporation exclusively (or nearly exclusively) as defined above, the coolant's enthalpy/temperature coordinates must remain inside the liquid-vapor dome 216 ofFIG. 8 . Thus, for a constant pressure, the coolant's temperature/enthalpy coordinates follow a line of constant pressure (e.g.,line 218 a) entering theevaporator 200 at a low enthalpy (labeled “inlet” inFIG. 8 ) and exiting at a higher enthalpy (labeled “outlet” inFIG. 8 ), with the entry and exit enthalpies lying inside or on the boundary of the liquid-vapor dome 216.FIG. 8 shows that a greater increase in enthalpy (absorbed heat) is achieved at lower coolant temperatures. - Maintaining the coolant inside the
evaporator 200 ofFIG. 7 within the liquid-vapor dome of FIG. 8—to guarantee heat extraction through the latent heat of vaporization almost exclusively—solves the problem of non-uniform temperature across the wafer under high RF heat loads. This is because heat transfer via the latent heat of vaporization is a constant-temperature process. As it absorbs heat, the coolant inside theevaporator 200 does not change temperature. Instead, it changes phase, going from liquid to vapor. Thus, all the coolant throughout the evaporator 200 (the fluid passages inside the ESC base 5) is at a uniform temperature regardless of the magnitude of the RF heat load on the wafer. The advantage is that the wafer temperature distribution is about as uniform as the electric field distribution across the ESC, so that the etch rate uniformity achieved under the most favorable conditions by the electrical features discussed earlier herein (e.g., the RF bias feedpoint impedance adjustment by multiple dielectric sleeves and the dielectric edge ring process kit) is maintained even under the highest RF heat loads, a result heretofore unattainable. This result renders the reactor ofFIGS. 1-7 useful for plasma processing under the current design rules (small feature sizes) and for several generations of future design rules in which feature sizes may shrink even further, a significant advantage. This advantage is combined with the extremely high heat capacity of cooling through latent heat of vaporization (discussed above), which provides about an order of magnitude greater heat flow rate than conventional (sensible) heat transfer via the coolant mass heat capacity. - Operation of the reactor of
FIG. 7 in the foregoing manner that results in heat transfer through the coolant's latent heat of vaporization corresponds to the method illustrated inFIG. 9 . The first step in this method is to enhance or optimize uniformity of radial distribution of the ESC temperature by maintaining the coolant that is inside theevaporator 200 within a range of temperatures and enthalpies at which the heat transfer is through contributions to (or deductions from) the coolant's latent heat of vaporization. This step is depicted in block 300 ofFIG. 9 . The step of block 300 may be carried out by limiting variation in the orifice or opening size of theexpansion valve 210 to a range which confines the temperature and enthalpy of the coolant in theevaporator 200 to lie inside the liquid-vapor dome 216 of the temperature-enthalpy diagram ofFIG. 8 (block 302 ofFIG. 9 ). For a given coolant and for a given coolant flow rate, the skilled worker can readily determine the adjustment range of the expansion valve that confines the coolant inside the liquid-vapor dome 216 ofFIG. 8 . The step of block 300 may also be carried out by adjusting the compressor-to-evaporatorbypass flow valve 212 within a range in which the coolant inside theevaporator 200 is maintained inside the liquid-vapor dome 216 ofFIG. 8 (block 304 ofFIG. 9 ). The adjustment of the bypass valve 212 (in the step of block 304) and the adjustment of the expansion valve 210 (in the step of block 302) may be combined to achieve the desired result. - Once heat transfer through the latent heat of vaporization in the
evaporator 200 has been established by the step of block 300, the next step is to control the ESC temperature (block 306 ofFIG. 9 ). This may be accomplished by adjusting theexpansion valve 210 within the range established in the step of block 300 until a desired ESC temperature is reached (block 308 ofFIG. 9 ). Alternatively, the ESC temperature may be controlled by adjusting the compressor-to-evaporator bypass valve 212 within the range established in the step of block 304. This latter step corresponds to block 310 ofFIG. 9 . Temperature control may also be carried out by performing the steps of blocks 308 and 310 together. - While the variable orifice size of the
expansion valve 210 is the primary control over cooling rate and wafer temperature, additional or alternative temperature control and, if desired, heating of the wafer, is provided by a compressor-to-evaporator bypass valve 212. Complete conversion of all liquid coolant to the gas phase in theaccumulator 204 can be ensured using a compressor-to-accumulator bypass valve 214. - While the skilled worker can readily select a suitable coolant, a flow rate by the
compressor 206 and an orifice size of the expansion valve that satisfies the foregoing conditions, the following is provided as a working example in which two-phase cooling is achieved: - ESC Inlet temperature: −10 to +50 deg C.
ESC Inlet pressure: 160 to 200 PSIG
ESC Inlet liquid-vapor ratio: 40%-60% liquid
ESC Inlet-Outlet max temperature difference: 5 deg C.
ESC Inlet-Outlet max pressure difference: 10 PSI
ESC Outlet Liquid-vapor ratio: 10% liquid
Accumulator outlet temperature: 60 to 80 deg C.
Accumulator outlet pressure: 25 to 35 PSIG
Accumulator outlet liquid-vapor ratio: 100% vapor
Compressor flow rate: 4 gal per min
Compressor outlet pressure: 260-270 PSIG
Compressor outlet temperature: 80-100 deg C.
Compressor outlet liquid-vapor ratio: 100% vapor
Condenser outlet temperature: 20-40 deg C.
Condenser outlet pressure: 250 PSIG
Condenser liquid-vapor ratio: 100% vapor
Expansion valve outlet liquid-vapor ratio: 80% - Some evaporation occurs between the expansion valve outlet and the
ESC coolant inlet 201, which explains the decrease in liquid-vapor ratio from 80% to 60% from theexpansion valve 210 to theESC inlet 201. While it may be preferable to constrain the thermal cycle within the liquid-vapor dome 216 ofFIG. 8 (as discussed above), the invention may be implemented with some small excursion beyond that limit. In particular, the coolant's liquid-vapor ratio may at least nearly reach zero at theevaporator outlet 202, or may reach zero just before theevaporator outlet 202, in which case a very small amount of sensible heating may occur. In such a case, the vast majority of heat transfer still occurs through the latent heat of vaporization, only a small fraction occurring through sensible heating, so that the advantages of the invention are realized nonetheless. - Referring again to
FIGS. 1 and 7 , the wafer temperature may be controlled or held at a desired temperature under a given RF heat load on thewafer 110 using a temperature feedback control loop governing either (or both) theexpansion valve 210 and thebypass valve 212, although the simplest implementation controls theexpansion valve 210 only. The actual temperature is sensed at a temperature probe, which may be atemperature probe 220 in theESC insulating layer 10, atemperature probe 221 in the ESC base 05, atemperature probe 222 at theESC evaporator inlet 201 or atemperature probe 223 at theESC evaporator outlet 202 or a combination of any or all of these probes. For this purpose, a feedbackcontrol loop processor 224 governs the orifice opening size of theexpansion valve 210 in response to input or inputs from one or more of the temperature probes. Theprocessor 224 is furnished with a user-selected desired temperature value, which may be stored in a memory oruser interface 225. During each successive processing cycle, theprocessor 224 compares the current temperature measured by at least one of the probes (e.g., by theprobe 220 in the ESC insulating layer) against the desired temperature value. Theprocessor 224 then computes an error value as the difference between the desired and measured temperature values, and determines from the error a correction to the orifice size of theexpansion valve 210 that is likely to reduce the error. Theprocessor 224 then causes the expansion valve orifice size to change in accordance with the correction. This cycle is repeated during the entire duration of a wafer process to control the wafer temperature. - In conventional reactors, the wafer is cooled to avoid overheating from absorbed RF power by cooling the electrostatic chuck or wafer support pedestal. Thermal conductivity between the
wafer 110 and the cooledESC 105 is enhanced by injection under pressure of a thermally conductive gas (such as helium) into the interface between the backside of thewafer 110 and the top surface of theESC 105, a technique well-known in the art. For this purpose,gas channels 226 are formed in the top surface of theESC insulating layer 20 and apressurized helium supply 228 is coupled to the internalESC gas channels 226 through a backsidegas pressure valve 229. Thewafer 110 is electrostatically clamped down onto the top surface of the insulatinglayer 20 by a D.C. clamping voltage applied by aclamp voltage source 128 to thegrid electrode 15. The thermal conductivity between thewafer 110 and theESC top layer 20 is determined by the clamping voltage and by the thermally conductive gas (helium) pressure on the wafer backside. Highly agile (quick) wafer temperature control is carried out in accordance with the present invention by varying the backside gas pressure (by controlling the valve 229) so as to adjust the wafer temperature to the desired level. As the backside gas pressure is changed, the thermal conductivity between the wafer and theESC top layer 20 is changed, which changes the balance between (a) the heat absorbed by thewafer 110 from RF power applied to thegrid electrode 15 or coupled to the plasma and (b) the heat drawn from the wafer to the cooled ESC. Changing this balance necessarily changes the wafer temperature. A feedback control loop governing the backside gas pressure can therefore be employed for agile or highly responsive control of the wafer temperature. The response of the wafer temperature to changes in the backside gas pressure is extremely quick (temperature changes reaching equilibrium within a second or less). By way of comparison, changing the temperature of the base of the ESC orwafer support pedestal 105 does not cause the wafer to reach a new (elevated or depressed) equilibrium or steady state wafer temperature for on the order of minute (depending upon the thermal mass of the ESC 105). Therefore, a temperature regulation system employing the backside gas pressure provides agile temperature control capable of making fast adjustments to wafer temperature. -
FIG. 7 illustrates such an agile temperature feedback control system, in which a feedbackcontrol loop processor 230 governs the backsidegas pressure valve 229. One (or more) of thetemperature sensors processor 230. A user interface ormemory 231 may provide a user-selected or desired temperature to theprocessor 230. During each successive processing cycle, theprocessor 230 computes an error signal as the difference between the current temperature measurement (from one of thesensors processor 230 determines from that difference a correction to the current setting of the backside gas pressure valve that would tend to reduce the temperature error, and changes the valve opening in accordance with that correction. For example, a wafer temperature that is deviating above the desired temperature would require increasing the backside gas pressure to increase thermal conductivity to the cooled ESC and bring down the wafer temperature. The converse is true in the case of a wafer temperature deviating below the desired temperature. The wafer temperature can thus be controlled and set to new temperatures virtually instantly within a temperature range whose lower limit corresponds to the chilled temperature of the ESC and whose upper limit is determined by the RF heat load on the wafer. For example, the wafer temperature cannot be increased in the absence of an RF heat load and the wafer temperature cannot be cooled below the temperature of the ESC. If this temperature range is sufficient, then any conventional technique may be used to maintain the ESC at a desired chilled temperature to facilitate the agile temperature feedback control loop governing the backside gas pressure. - The agile temperature feedback control loop governing the backside
gas pressure valve 229 and the large range temperature feedback control loop governing therefrigeration expansion valve 210 may be operated simultaneously in a cooperative combination under the control of amaster processor 232 controlling both feedbackcontrol loop processors - The large range temperature feedback control loop (involving the refrigeration loop consisting of the
evaporator 200, thecompressor 206, thecondenser 208 and the expansion valve 210) controls the workpiece temperature by changing the temperature of theelectrostatic chuck 105. The temperature range is limited only by the thermal capacity of the refrigeration loop and can therefore set the workpiece temperature to any temperature within a very large range (e.g., −10 deg C. to +150 deg C.). However, the rate at which it can effect a desired change in workpiece temperature at a particular moment is limited by the thermal mass of theelectrostatic chuck 105. This rate is so slow that, for example, with an electrostatic chuck for supporting a 300 mm workpiece or silicon wafer, a 10 degree C. change in workpiece temperature can require on the order of a minute or more from the time the refrigeration unit begins to change the thermal conditions of the coolant to meet the new temperature until the workpiece temperature finally reaches the new temperature. - In contrast, in making a desired change or correction in workpiece temperature, the agile temperature feedback control loop does not change the electrostatic chuck temperature (at least not directly) but merely changes the thermal conductivity between the workpiece and the electrostatic chuck. The rate at which the workpiece temperature responds to such a change is extremely high because it is limited only by the rate at which the backside gas pressure can be changed and the thermal mass of the workpiece. The backside gas pressure responds to movement of the
valve 229 in a small fraction of a second in a typical system. For a typical 300 mm silicon wafer, the thermal mass is so low that the wafer (workpiece) temperature responds to changes in the backside gas pressure within a matter of a few seconds or a fraction of a second. Therefore, relative to the time scale over which the large range temperature control loop effects changes in workpiece temperature, the workpiece temperature response of agile feedback loop is comparatively instantaneous. However, the range over which the agile feedback loop can change the workpiece temperature is quite limited: the highest workpiece temperature that can be attained is limited by the RF heat load on the wafer, while the lowest temperature cannot be below the current temperature of theelectrostatic chuck 105. However, in combining the agile and large range temperature control loops together, the advantages of each one compensate for the limitations of the other, because their combination provides a large workpiece temperature range and a very fast response. - The
master processor 232 may be programmed to effect large temperature changes using the large range feedback control loop (the processor 224) and effect quick but smaller temperature changes using the agile feedback control loop (the processor 230).FIG. 10 is a graph of one example of wafer temperature behavior over time. The solid line depicts the long term temperature behavior, in which themaster processor 232 effects slow large changes in wafer temperature using the large range feedback control loop with theprocessor 224. The dashed line depicts fast perturbations in temperature, in which themaster processor 232 effects fast but small changes in wafer temperature using the agile feedback control loop with theprocessor 230. - The dual loop control afforded by the
master processor 232 can be employed to (nearly) instantly move the wafer temperature to a new desired level and hold it there while the ESC temperature slowly changes to the new desired temperature. This is illustrated inFIGS. 11A and 11B . The solid line inFIG. 11A depicts the wafer temperature behavior over time in which the wafer temperature is stepped down to a lower temperature at time t1 and held there, at which time the refrigeration loop (dashed line) begins to cool down the ESC to the lower temperature, which is not reached by the ESC until time t2. The fast change in wafer temperature at time t1 and its temperature stability thereafter is accomplished by theagile control loop 230. The agilecontrol loop processor 230 receives the new (lower) desired wafer temperature at time t1 and responds by immediately increasing the backside gas pressure (FIG. 11B ) to step the wafer temperature down to the new temperature at time t1. In the meantime, the ESC temperature begins to fall in order to drive the ESC to (or slightly below) the new temperature at time t1, so thatprocessor 224 increases the refrigeration cooling rate of the ESC to drive its temperature down. This forces the agilecontrol loop processor 230 to decrease backside gas pressure after; time t1 to maintain the desired wafer temperature, until the ESC reaches the correct temperature at time t2, after which the backside gas pressure remains constant. - The example of
FIGS. 12A and 12B illustrates how the ESC temperature change may be delayed while the refrigeration loop is allowed to slowly adjust to a new temperature.FIG. 12A depicts temperature behavior over time whileFIG. 12B depicts the corresponding backside gas pressure profile over time. As illustrated inFIGS. 12A and 12B , the dual loop control afforded by themaster processor 232 can be employed to temporarily hold the wafer temperature constant (solid line ofFIG. 12A ) at an initial temperature level while, beginning at time t1, the refrigeration loop takes the ESC through a large but slow temperature excursion (dashed line ofFIG. 12A ). Then, the wafer temperature is allowed to step down to the new ESC temperature. This is accomplished by cooling the ESC while constantly decreasing the backside gas pressure beginning at time t1. Then, after the desired ESC temperature is reached at time t2, the agile temperature control loop steps up the backside gas pressure to step the wafer temperature down to the ESC temperature. - 1. Large Range Temperature Control Loop:
- The
ESC 105 may be divided into plural radial zones, and different independent feedback control loops may separately control the temperature in each zone. An advantage of this feature is that different radial zones of thewafer 110 may be kept at different temperatures during processing so as to further reduce process or etch rate distribution non-uniformities. In the example ofFIG. 13 , theESC 105 is divided into two temperature control zones, namely a radiallyinner zone 234 and a radiallyouter zone 236, and a separate temperature control apparatus is provided for eachzone electrode 15 into plural radial zones (such as concentric inner andouter zones - The radially
inner zone 234 of the aluminum base 05 contains inner zone coolant flow passages 200 a with acoolant inlet 201 a and acoolant outlet 202 a. The inner zone coolant flow passages 200 a constitute the inner zone evaporator of an inner zone refrigeration loop, the evaporator 200 a being internally contained with theinner zone 234 of the ESC base 05. The remaining elements of the inner zone refrigeration loop are external of theESC 105, and include (in order of coolant flow direction, starting from thecoolant outlet 202 a) anaccumulator 204 a, acompressor 206 a, acondenser 208 a and anexpansion valve 210 a having a variable orifice size, all of which are of the type well-known in the art. The radiallyouter zone 236 of the aluminum base 05 contains outer zonecoolant flow passages 200 b with acoolant inlet 201 b and acoolant outlet 202 b. The outer zonecoolant flow passages 200 b constitute the outer zone evaporator of an outer zone refrigeration loop, theevaporator 200 b being internally contained with theouter zone 236 of the ESC base 05. The remaining elements of the outer zone refrigeration loop are external of theESC 105, and include (in order of coolant flow direction, starting from thecoolant outlet 202 b) anaccumulator 204 b, acompressor 206 b, acondenser 208 b and anexpansion valve 210 b having a variable orifice size, all of which are of the type well-known in the art. Temperature in theinner zone 234 is sensed at one or more of the following inner zone temperature probes: probe 220 a in theinner zone 234 of theESC insulating layer 10, probe 221 a in the inner zone of the ESC base 05, probe 222 a at the innerzone evaporator inlet 201 a or probe 223 a at the innerzone evaporator outlet 202 a. - An inner zone feedback
control loop processor 224 a governs the orifice opening size of the innerzone expansion valve 210 a in response to input or inputs from one or more of the inner zone temperature probes. Theinner zone processor 224 a is furnished with a user-selected desired inner zone temperature value, which may be stored in a memory oruser interface 225 a. During each successive processing cycle, theinner zone processor 224 a compares the current temperature measured by at least one of the probes (e.g., theprobe 220 a in the ESC insulating layer) against the desired temperature value and corrects the orifice size of the innerzone expansion valve 210 a accordingly. An outer zone feedbackcontrol loop processor 224 b governs the orifice opening size of the outerzone expansion valve 210 b in response to input or inputs from one or more of the outer zone temperature probes. Theouter zone processor 224 b is furnished with a user-selected desired outer zone temperature value, which may be stored in a memory oruser interface 225 b. During each successive processing cycle, theouter zone processor 224 b compares the current temperature measured by at least one of the probes (e.g., theouter zone probe 220 b in the ESC insulating layer) against the desired temperature value and corrects the orifice size of the outerzone expansion valve 210 b accordingly. - 2. Agile Temperature Feedback Control Loop:
- In both
temperature zones wafer 110 and the cooledESC 105 is enhanced by injection under pressure of a thermally conductive gas (such as helium) into the interface between the backside of thewafer 110 and the top surface of theESC 105, a technique well-known in the art. In theinner temperature zone 234, innerzone gas channels 226 a are formed ininner zone 234 of the top surface of theESC insulating layer 20 and apressurized helium supply 228 a is coupled to the innerzone gas channels 226 a through an inner zone backsidegas pressure valve 229 a. Thewafer 110 is electrostatically clamped down onto the top surface of the insulatinglayer 20 by a D.C. clamping voltage applied by aclamp voltage source 128 to the grid electrode 15 (i.e., 15 a and 15 b). The thermal conductivity between thewafer 110 and theESC top layer 20 is determined by the clamping voltage and by the thermally conductive gas (helium) pressure on the wafer backside. Highly agile (quick) wafer temperature control is carried out in theinner temperature zone 234 by controlling theinner zone valve 229 a so as to adjust the wafer temperature to the desired level. An inner zone agile feedbackcontrol loop processor 230 a governs the inner zone backsidegas pressure valve 229 a. One (or more) of the innerzone temperature sensors inner zone 234 may be connected to an input of the inner zoneagile processor 230 a. An inner zone user interface ormemory 231 a may provide a user-selected or desired temperature to the inner zoneagile processor 230 a. During each successive processing cycle, theprocessor 230 a senses an error as the difference between the current temperature measurement (from one of theinner zone sensors backside gas valve 229 a accordingly. - In the
outer temperature zone 236, outerzone gas channels 226 b are formed inouter zone 236 of the top surface of theESC insulating layer 20 and thepressurized helium supply 228 b is coupled to the outerzone gas channels 226 b through an outer zone backsidegas pressure valve 229 b. Highly agile (quick) wafer temperature control is carried out in theouter temperature zone 236 by controlling theouter zone valve 229 b so as to adjust the wafer temperature to the desired level. An outer zone agile feedbackcontrol loop processor 230 b governs the outer zone backsidegas pressure valve 229 b. One (or more) of the outerzone temperature sensors outer zone 236 may be connected to an input of the outer zoneagile processor 230 b. An outer zone user interface ormemory 231 b may provide a user-selected or desired temperature to the inner zoneagile processor 230 b. During each successive processing cycle, theprocessor 230 b senses an error as the difference between the current temperature measurement (from one of theouter zone sensors backside gas valve 229 b accordingly. - With the combination of the agile and large range inner and outer feedback control loops described above with reference to
FIG. 13 , the radial profile of the wafer temperature may be controlled over a large range with agile response. - Temperature Probe with Minimal or No RF Parasitics:
-
FIG. 14 depicts apreferred temperature probe 238 installed in the plasma reactor ofFIG. 1 . Theprobe 238 consists of two separable portions, namely anupper probe 239 installed in theESC 105 and alower probe 240 installed in a portion of the reactor chamber beneath and supporting theESC 105, namely achamber host base 241. Theupper probe 239 is depicted in the enlarged view ofFIG. 15 , and lies in an area of high RF electric potential (i.e., inside the ESC insulating layer orpuck 10, 20). Theupper probe 239 is firmly inserted in an elongate axial hole within theESC 105 that closely fits theupper probe 239, and the tip of theupper probe 239 lies very close (e.g., within 3 to 3.5 mm) to the top surface of thepuck 20. (The advantage is that theprobe 239 is sufficiently close to thewafer 110 to minimize or eliminate temperature measurement errors.) This area of the ESC has very high electric field potential during processing so that any electrical properties that theupper probe 239 may have would have profound effects on plasma processing on the wafer. Theupper probe 239 therefore includes RF compatibility features which minimize or eliminate any effect that theprobe 239 might otherwise have on the electric field or on the RF impedance distribution. Such RF compatibility features ensure that theprobe 239 does not distort or perturb the ESC electric field or RF impedance distribution that has been so carefully adjusted with the features of the feedpoint impedance adjustment ofFIGS. 2-4 and/or the dielectric ring process kit ofFIGS. 5-6 (for example). The RF compatibility features of theupper probe 239 include a complete absence of any conductive materials within theprobe 239, an orientation of the probe in the axial direction (to minimize its effect on the radial electric field or RF impedance distribution) and its small diameter, which is on the order of a fraction of a Debeye length of the plasma in the chamber. These features are made possible by employing an electrically nonconductive optical temperature transducer 242 (e.g., a phosphor material) whose blackbody radiation spectrum is a well-known function of its temperature. Theoptical temperature transducer 242 is coupled to a long thinoptical fiber 243 contained within the thin axialupper probe 239. Theupper probe 239 further includes an opaque cylindricaldielectric sleeve 244 surrounding theoptical fiber 243 and preferably consisting of glass-impregnated plastic. Theoptical temperature transducer 242 is capped by adielectric cap 245 of a material that is, preferably, identical to the dielectric material of theESC puck ESC puck layer 20 that is in direct contact with the wafer 110). - The
upper probe 239 further includes a mountingplate 246 that is removably fastened to the bottom surface of the ESC base 05. The mountingplate 246 supports aspring housing 247 containing acoil spring 248 compressed between ashoulder 245 of thehousing 247 and anannular ring 249 fastened to a portion of theprobe sleeve 244 lying within thehousing 247. As theupper probe 239 is inserted into theESC 105 and presses against the top end of the hole within the ESC, thecoil spring 248 is compressed to force the tip of theprobe 239 to self-align to the top end of the hole. - The
lower probe 240 is shown in the enlarged view ofFIG. 16 and includes anoptical fiber 250 surrounded by an opaque lowercylindrical sleeve 251. Since thelower probe 240 is below the grounded conductive ESC base 05, it is located outside of areas of high RF electric fields, and therefore need not be formed of non-conductive materials. In fact, the lowercylindrical sleeve 251 may be formed of steel, for example. Thetop end 252 of thelower probe 240 is tightly received within ahole 253 in the mountingplate 246 of theupper probe 239. Thelower probe 240 further includes a mountingplate 254 that is removably fastened to the bottom surface of the chamberhousing host base 241. The mountingplate 254 supports aspring housing 255 containing acoil spring 256 compressed between ashoulder 257 of thehousing 255 and anannular ring 258 fastened to a portion of thelower probe sleeve 251 lying within thehousing 255. As thetip 252 of thelower probe 240 is inserted into thehole 253 of the upperprobe mounting plate 246 and pressed against the top end of thehole 253, thecoil spring 256 is compressed to force the tip of thelower probe 240 to self-align to the top end of thehole 253. The resulting self-alignment of thelower probe 240 against theupper probe 239 is illustrated inFIG. 17 , which shows that the facing ends of the upper probeoptical fiber 243 and the lower probeoptical fiber 250 are in nearly perfect alignment. Signal conditioning circuitry converts the light received from the optical fiber at the bottom end of thelower probe fiber 250 and converts it to a digital signal for use by one of the feedback control loop processors. WhileFIG. 14 depicts a single temperature probe whose tip lies near the top of theESC 105, another identical probe may be placed in a lower portion of the ESC but at the same radial location as first probe. Other identical probes may be placed at different radial (azimuthal) locations within the ESC but in the same height (axial location) as other probes. Thus, the temperature probes 220 a, 220 b of thedifferent temperature zones FIG. 13 may each be of the type described above inFIGS. 13-16 and are located at different radial locations at a common axial height. - While certain embodiments of the invention have been described as including different feedback control loop processors, any or all such processors may be implemented in a single common processor programmed to perform the functions of each of the individual feedback control loop processors. Similarly, other resources associated with the different control loops, such as the dual helium supplies 228 a, 228 b, may be implemented with a single supply or resource with separately controlled interfaces (e.g., such as a single helium supply and dual
pressure control valves conductive mesh electrode 15 is divided into inner andouter electrodes outer mesh electrodes - While the invention has been described in detail by specific reference to preferred embodiments, it is understood that variations and modifications thereof may be made without departing from the true spirit and scope of the invention.
Claims (20)
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US11/409,292 US8092638B2 (en) | 2005-10-11 | 2006-04-21 | Capacitively coupled plasma reactor having a cooled/heated wafer support with uniform temperature distribution |
US12/855,675 US20100319852A1 (en) | 2005-10-11 | 2010-08-12 | Capacitivley coupled plasma reactor having a cooled/heated wafer support with uniform temperature distribution |
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Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4742689A (en) * | 1986-03-18 | 1988-05-10 | Mydax, Inc. | Constant temperature maintaining refrigeration system using proportional flow throttling valve and controlled bypass loop |
US4798650A (en) * | 1987-03-27 | 1989-01-17 | Fujitsu Limited | Method of dry etching aluminum |
US4835977A (en) * | 1983-11-18 | 1989-06-06 | Teledyne Industries, Inc. | Apparatus and method of air-conditioning parked aircraft |
US5625526A (en) * | 1993-06-01 | 1997-04-29 | Tokyo Electron Limited | Electrostatic chuck |
US5937660A (en) * | 1993-07-26 | 1999-08-17 | Lau; Billy Ying Bui | Quick cooling air conditioning system |
US6262397B1 (en) * | 1999-03-30 | 2001-07-17 | Tokyo Electron Ltd. | Heat treatment apparatus and heat treatment method |
US20010020365A1 (en) * | 2000-03-09 | 2001-09-13 | Hideo Kubo | Refrigeration system utilizing incomplete evaporation of refrigerant in evaporator |
US6792762B1 (en) * | 1999-11-10 | 2004-09-21 | Hitachi, Ltd. | Gas turbine equipment and gas turbine cooling method |
US20040187514A1 (en) * | 2003-03-27 | 2004-09-30 | Doug Franck | Refrigeration system and method for beverage dispenser |
US20040261449A1 (en) * | 2003-06-24 | 2004-12-30 | Memory Stephen B. | Refrigeration system |
US20050199341A1 (en) * | 2002-10-01 | 2005-09-15 | Tokyo Electron Limited | Method and system for analyzing data from a plasma process |
US20070169491A1 (en) * | 2004-02-19 | 2007-07-26 | Cowans Kenneth W | Thermal control system and method |
US7794617B2 (en) * | 2006-03-23 | 2010-09-14 | Tokyo Electron Limited | Plasma etching method, plasma processing apparatus, control program and computer readable storage medium |
US20100303680A1 (en) * | 2005-10-11 | 2010-12-02 | Buchberger Douglas A Jr | Capacitively coupled plasma reactor having very agile wafer temperature control |
US20100314046A1 (en) * | 2005-10-20 | 2010-12-16 | Paul Lukas Brillhart | Plasma reactor with a multiple zone thermal control feed forward control apparatus |
US7988872B2 (en) * | 2005-10-11 | 2011-08-02 | Applied Materials, Inc. | Method of operating a capacitively coupled plasma reactor with dual temperature control loops |
US8034180B2 (en) * | 2005-10-11 | 2011-10-11 | Applied Materials, Inc. | Method of cooling a wafer support at a uniform temperature in a capacitively coupled plasma reactor |
US8043971B2 (en) * | 2003-02-07 | 2011-10-25 | Tokyo Electron Limited | Plasma processing apparatus, ring member and plasma processing method |
US8075729B2 (en) * | 2004-10-07 | 2011-12-13 | Applied Materials, Inc. | Method and apparatus for controlling temperature of a substrate |
US8092638B2 (en) * | 2005-10-11 | 2012-01-10 | Applied Materials Inc. | Capacitively coupled plasma reactor having a cooled/heated wafer support with uniform temperature distribution |
Family Cites Families (104)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2707868A (en) | 1951-06-29 | 1955-05-10 | Goodman William | Refrigerating system, including a mixing valve |
US3826304A (en) | 1967-10-11 | 1974-07-30 | Universal Oil Prod Co | Advantageous configuration of tubing for internal boiling |
GB1454508A (en) | 1973-04-26 | 1976-11-03 | Shipowners Cargo Res Assoc | Refrigeration control systems |
DE2521405C3 (en) | 1975-05-14 | 1978-03-16 | Basf Ag, 6700 Ludwigshafen | fungicide |
US4313783A (en) | 1980-05-19 | 1982-02-02 | Branson International Plasma Corporation | Computer controlled system for processing semiconductor wafers |
US4384918A (en) | 1980-09-30 | 1983-05-24 | Fujitsu Limited | Method and apparatus for dry etching and electrostatic chucking device used therein |
US4681398A (en) * | 1983-01-03 | 1987-07-21 | Switchcraft, Inc. | Fiber optic connector and method of assembly |
US4752141A (en) | 1985-10-25 | 1988-06-21 | Luxtron Corporation | Fiberoptic sensing of temperature and/or other physical parameters |
US4883354A (en) * | 1985-10-25 | 1989-11-28 | Luxtron Corporation | Fiberoptic sensing of temperature and/or other physical parameters |
US4934155A (en) | 1986-03-18 | 1990-06-19 | Mydax, Inc. | Refrigeration system |
US4705951A (en) | 1986-04-17 | 1987-11-10 | Varian Associates, Inc. | Wafer processing system |
JPS6329220A (en) | 1986-07-23 | 1988-02-06 | Matsushita Electric Ind Co Ltd | Optical temperature sensor |
GB2202324B (en) | 1987-03-11 | 1991-01-23 | Plessey Co Plc | Improvements relating to optical fibre sensing system |
US5057968A (en) | 1989-10-16 | 1991-10-15 | Lockheed Corporation | Cooling system for electronic modules |
US5556204A (en) * | 1990-07-02 | 1996-09-17 | Hitachi, Ltd. | Method and apparatus for detecting the temperature of a sample |
KR0165898B1 (en) | 1990-07-02 | 1999-02-01 | 미다 가쓰시게 | Vacuum processing method and apparatus |
US5258614A (en) | 1991-05-13 | 1993-11-02 | The Babcock & Wilcox Company | Optical fiber loop temperature sensor |
US6077384A (en) | 1994-08-11 | 2000-06-20 | Applied Materials, Inc. | Plasma reactor having an inductive antenna coupling power through a parallel plate electrode |
US5815396A (en) | 1991-08-12 | 1998-09-29 | Hitachi, Ltd. | Vacuum processing device and film forming device and method using same |
US5551249A (en) | 1992-10-05 | 1996-09-03 | Van Steenburgh, Jr.; Leon R. | Liquid chiller with bypass valves |
US5567267A (en) | 1992-11-20 | 1996-10-22 | Tokyo Electron Limited | Method of controlling temperature of susceptor |
JP3375995B2 (en) | 1992-11-25 | 2003-02-10 | ミネソタ マイニング アンド マニュファクチャリング カンパニー | Medical temperature sensor |
US5662770A (en) | 1993-04-16 | 1997-09-02 | Micron Technology, Inc. | Method and apparatus for improving etch uniformity in remote source plasma reactors with powered wafer chucks |
US5471850A (en) | 1993-07-09 | 1995-12-05 | Acurex Corporation | Refrigeration system and method for very large scale integrated circuits |
US6544379B2 (en) | 1993-09-16 | 2003-04-08 | Hitachi, Ltd. | Method of holding substrate and substrate holding system |
US5650082A (en) | 1993-10-29 | 1997-07-22 | Applied Materials, Inc. | Profiled substrate heating |
US5410889A (en) | 1994-01-14 | 1995-05-02 | Thermo King Corporation | Methods and apparatus for operating a refrigeration system |
US5549756A (en) | 1994-02-02 | 1996-08-27 | Applied Materials, Inc. | Optical pyrometer for a thin film deposition system |
US5742022A (en) | 1995-04-19 | 1998-04-21 | Dct Avanced Engineering, Inc. | Industrial workcell system and method |
US5762009A (en) | 1995-06-07 | 1998-06-09 | Alliant Techsystems, Inc. | Plasma energy recycle and conversion (PERC) reactor and process |
US5787723A (en) | 1995-08-21 | 1998-08-04 | Manitowoc Foodservice Group, Inc. | Remote ice making machine |
JPH09172001A (en) | 1995-12-15 | 1997-06-30 | Sony Corp | Method and device for controlling temperature in semiconductor manufacturing apparatus |
US5701758A (en) * | 1996-01-30 | 1997-12-30 | Haramoto; Cary | Refrigeration system accumulating vessel having a brazed, metal-clad deflector |
US6063710A (en) | 1996-02-26 | 2000-05-16 | Sony Corporation | Method and apparatus for dry etching with temperature control |
US5761023A (en) | 1996-04-25 | 1998-06-02 | Applied Materials, Inc. | Substrate support with pressure zones having reduced contact area and temperature feedback |
JP3360265B2 (en) | 1996-04-26 | 2002-12-24 | 東京エレクトロン株式会社 | Plasma processing method and plasma processing apparatus |
US6205803B1 (en) | 1996-04-26 | 2001-03-27 | Mainstream Engineering Corporation | Compact avionics-pod-cooling unit thermal control method and apparatus |
US6108189A (en) | 1996-04-26 | 2000-08-22 | Applied Materials, Inc. | Electrostatic chuck having improved gas conduits |
JPH10150025A (en) | 1996-11-20 | 1998-06-02 | Mitsubishi Electric Corp | Plasma reactor |
US5748435A (en) | 1996-12-30 | 1998-05-05 | Applied Materials, Inc. | Apparatus for controlling backside gas pressure beneath a semiconductor wafer |
US5994675A (en) | 1997-03-07 | 1999-11-30 | Semitool, Inc. | Semiconductor processing furnace heating control system |
US5878583A (en) | 1997-04-01 | 1999-03-09 | Manitowoc Foodservice Group, Inc. | Ice making machine and control method therefore |
US6286451B1 (en) | 1997-05-29 | 2001-09-11 | Applied Materials, Inc. | Dome: shape and temperature controlled surfaces |
US5970731A (en) | 1997-11-21 | 1999-10-26 | International Business Machines Corporation | Modular refrigeration system |
WO1999028745A1 (en) | 1997-11-27 | 1999-06-10 | MAX-PLANCK-Gesellschaft zur Förderung der Wissenschaften e.V. | Identification and characterization of interacting molecules by automated interaction mating |
US6091060A (en) | 1997-12-31 | 2000-07-18 | Temptronic Corporation | Power and control system for a workpiece chuck |
US6018616A (en) | 1998-02-23 | 2000-01-25 | Applied Materials, Inc. | Thermal cycling module and process using radiant heat |
US6076366A (en) | 1998-04-03 | 2000-06-20 | Denso Corporation | Refrigerating cycle system with hot-gas bypass passage |
US6015465A (en) | 1998-04-08 | 2000-01-18 | Applied Materials, Inc. | Temperature control system for semiconductor process chamber |
US6033482A (en) | 1998-04-10 | 2000-03-07 | Applied Materials, Inc. | Method for igniting a plasma in a plasma processing chamber |
US6080272A (en) | 1998-05-08 | 2000-06-27 | Micron Technology, Inc. | Method and apparatus for plasma etching a wafer |
US5886866A (en) | 1998-07-06 | 1999-03-23 | Applied Materials, Inc. | Electrostatic chuck having a combination electrode structure for substrate chucking, heating and biasing |
US6196553B1 (en) * | 1998-07-30 | 2001-03-06 | Litton Systems, Inc. | Fiber optical connector seal |
US6125025A (en) | 1998-09-30 | 2000-09-26 | Lam Research Corporation | Electrostatic dechucking method and apparatus for dielectric workpieces in vacuum processors |
US6098408A (en) | 1998-11-11 | 2000-08-08 | Advanced Micro Devices | System for controlling reflection reticle temperature in microlithography |
BR0007811B1 (en) | 1999-01-12 | 2009-01-13 | Steam compression system and Method to operate the system. | |
US6185958B1 (en) | 1999-11-02 | 2001-02-13 | Xdx, Llc | Vapor compression system and method |
US6169274B1 (en) | 1999-03-01 | 2001-01-02 | Tokyo Electron Ltd. | Heat treatment apparatus and method, detecting temperatures at plural positions each different in depth in holding plate, and estimating temperature of surface of plate corresponding to detected result |
US6094334A (en) | 1999-03-02 | 2000-07-25 | Applied Materials, Inc. | Polymer chuck with heater and method of manufacture |
US6320736B1 (en) | 1999-05-17 | 2001-11-20 | Applied Materials, Inc. | Chuck having pressurized zones of heat transfer gas |
US6709715B1 (en) | 1999-06-17 | 2004-03-23 | Applied Materials Inc. | Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds |
US6318384B1 (en) | 1999-09-24 | 2001-11-20 | Applied Materials, Inc. | Self cleaning method of forming deep trenches in silicon substrates |
US6740853B1 (en) | 1999-09-29 | 2004-05-25 | Tokyo Electron Limited | Multi-zone resistance heater |
US6412344B1 (en) | 1999-11-15 | 2002-07-02 | Rosemount Aerospace Inc. | Fluid level sensor with dry couplant |
US6461980B1 (en) | 2000-01-28 | 2002-10-08 | Applied Materials, Inc. | Apparatus and process for controlling the temperature of a substrate in a plasma reactor chamber |
IT1319823B1 (en) * | 2000-01-28 | 2003-11-03 | Pres Block Spa | TAKE-OFF BODY FOR A QUICK-RELEASE SAFETY COUPLING. |
US6481886B1 (en) * | 2000-02-24 | 2002-11-19 | Applied Materials Inc. | Apparatus for measuring pedestal and substrate temperature in a semiconductor wafer processing system |
JP4096491B2 (en) | 2000-03-15 | 2008-06-04 | 株式会社デンソー | Refrigeration cycle equipment |
US6900596B2 (en) | 2002-07-09 | 2005-05-31 | Applied Materials, Inc. | Capacitively coupled plasma reactor with uniform radial distribution of plasma |
US7030335B2 (en) * | 2000-03-17 | 2006-04-18 | Applied Materials, Inc. | Plasma reactor with overhead RF electrode tuned to the plasma with arcing suppression |
US6853141B2 (en) | 2002-05-22 | 2005-02-08 | Daniel J. Hoffman | Capacitively coupled plasma reactor with magnetic plasma control |
US6353210B1 (en) | 2000-04-11 | 2002-03-05 | Applied Materials Inc. | Correction of wafer temperature drift in a plasma reactor based upon continuous wafer temperature measurements using and in-situ wafer temperature optical probe |
US6685798B1 (en) | 2000-07-06 | 2004-02-03 | Applied Materials, Inc | Plasma reactor having a symmetrical parallel conductor coil antenna |
JP2002043381A (en) | 2000-07-19 | 2002-02-08 | Tokyo Electron Ltd | Water temperature controller |
US20050230047A1 (en) | 2000-08-11 | 2005-10-20 | Applied Materials, Inc. | Plasma immersion ion implantation apparatus |
US6583980B1 (en) | 2000-08-18 | 2003-06-24 | Applied Materials Inc. | Substrate support tolerant to thermal expansion stresses |
US6468384B1 (en) | 2000-11-09 | 2002-10-22 | Novellus Systems, Inc. | Predictive wafer temperature control system and method |
US6557371B1 (en) | 2001-02-08 | 2003-05-06 | York International Corporation | Apparatus and method for discharging fluid |
US20020139477A1 (en) | 2001-03-30 | 2002-10-03 | Lam Research Corporation | Plasma processing method and apparatus with control of plasma excitation power |
US20020144786A1 (en) | 2001-04-05 | 2002-10-10 | Angstron Systems, Inc. | Substrate temperature control in an ALD reactor |
US7080940B2 (en) | 2001-04-20 | 2006-07-25 | Luxtron Corporation | In situ optical surface temperature measuring techniques and devices |
US6668570B2 (en) | 2001-05-31 | 2003-12-30 | Kryotech, Inc. | Apparatus and method for controlling the temperature of an electronic device under test |
JP2003014988A (en) * | 2001-06-28 | 2003-01-15 | Ykk Corp | Optical connector and ferrule for optical connector used therefor |
US6564563B2 (en) | 2001-06-29 | 2003-05-20 | International Business Machines Corporation | Logic module refrigeration system with condensation control |
US6543246B2 (en) | 2001-07-24 | 2003-04-08 | Kryotech, Inc. | Integrated circuit cooling apparatus |
US6681580B2 (en) | 2001-09-12 | 2004-01-27 | Manitowoc Foodservice Companies, Inc. | Ice machine with assisted harvest |
JP2003174016A (en) | 2001-12-07 | 2003-06-20 | Tokyo Electron Ltd | Vacuum-treating device |
US6705095B2 (en) | 2002-03-08 | 2004-03-16 | Kinetics Thermal Systems, Inc. | Semiconductor process tool incorporating heat exchanger |
US20040040664A1 (en) * | 2002-06-03 | 2004-03-04 | Yang Jang Gyoo | Cathode pedestal for a plasma etch reactor |
US7195693B2 (en) | 2002-06-05 | 2007-03-27 | Advanced Thermal Sciences | Lateral temperature equalizing system for large area surfaces during processing |
US7156951B1 (en) | 2002-06-21 | 2007-01-02 | Lam Research Corporation | Multiple zone gas distribution apparatus for thermal control of semiconductor wafer |
WO2004025199A1 (en) | 2002-09-10 | 2004-03-25 | Tokyo Electron Limited | Processing device, and processing device maintenance method |
US6899796B2 (en) | 2003-01-10 | 2005-05-31 | Applied Materials, Inc. | Partially filling copper seed layer |
JP2003243492A (en) | 2003-02-19 | 2003-08-29 | Hitachi High-Technologies Corp | Wafer treatment device and wafer stage, and wafer treatment method |
US20040173311A1 (en) * | 2003-03-04 | 2004-09-09 | Tomoyoshi Ichimaru | Plasma processing apparatus and method |
US7269358B2 (en) * | 2003-08-01 | 2007-09-11 | Optium Corporation | Optical transmitter for increased effective modal bandwidth transmission |
JP2005079539A (en) * | 2003-09-03 | 2005-03-24 | Hitachi Ltd | Plasma treatment apparatus |
JP2005085803A (en) | 2003-09-04 | 2005-03-31 | Shinwa Controls Co Ltd | Susceptor |
US7043930B2 (en) | 2004-01-30 | 2006-05-16 | Carrier Corporation | Two phase or subcooling reheat system |
US7138067B2 (en) | 2004-09-27 | 2006-11-21 | Lam Research Corporation | Methods and apparatus for tuning a set of plasma processing steps |
JP4191120B2 (en) | 2004-09-29 | 2008-12-03 | 株式会社日立ハイテクノロジーズ | Plasma processing equipment |
US7436645B2 (en) | 2004-10-07 | 2008-10-14 | Applied Materials, Inc. | Method and apparatus for controlling temperature of a substrate |
US7905109B2 (en) | 2005-09-14 | 2011-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Rapid cooling system for RTP chamber |
US20070095097A1 (en) | 2005-11-03 | 2007-05-03 | Cowans Kenneth W | Thermal control system and method |
-
2006
- 2006-04-21 US US11/409,292 patent/US8092638B2/en active Active
-
2010
- 2010-08-12 US US12/855,675 patent/US20100319852A1/en not_active Abandoned
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4835977A (en) * | 1983-11-18 | 1989-06-06 | Teledyne Industries, Inc. | Apparatus and method of air-conditioning parked aircraft |
US4742689A (en) * | 1986-03-18 | 1988-05-10 | Mydax, Inc. | Constant temperature maintaining refrigeration system using proportional flow throttling valve and controlled bypass loop |
US4798650A (en) * | 1987-03-27 | 1989-01-17 | Fujitsu Limited | Method of dry etching aluminum |
US5625526A (en) * | 1993-06-01 | 1997-04-29 | Tokyo Electron Limited | Electrostatic chuck |
US5937660A (en) * | 1993-07-26 | 1999-08-17 | Lau; Billy Ying Bui | Quick cooling air conditioning system |
US6262397B1 (en) * | 1999-03-30 | 2001-07-17 | Tokyo Electron Ltd. | Heat treatment apparatus and heat treatment method |
US6792762B1 (en) * | 1999-11-10 | 2004-09-21 | Hitachi, Ltd. | Gas turbine equipment and gas turbine cooling method |
US20010020365A1 (en) * | 2000-03-09 | 2001-09-13 | Hideo Kubo | Refrigeration system utilizing incomplete evaporation of refrigerant in evaporator |
US20050199341A1 (en) * | 2002-10-01 | 2005-09-15 | Tokyo Electron Limited | Method and system for analyzing data from a plasma process |
US8043971B2 (en) * | 2003-02-07 | 2011-10-25 | Tokyo Electron Limited | Plasma processing apparatus, ring member and plasma processing method |
US20040187514A1 (en) * | 2003-03-27 | 2004-09-30 | Doug Franck | Refrigeration system and method for beverage dispenser |
US20040261449A1 (en) * | 2003-06-24 | 2004-12-30 | Memory Stephen B. | Refrigeration system |
US20070169491A1 (en) * | 2004-02-19 | 2007-07-26 | Cowans Kenneth W | Thermal control system and method |
US20080319587A1 (en) * | 2004-02-19 | 2008-12-25 | Cowans Kenneth W | Thermal control system and method |
US7765820B2 (en) * | 2004-02-19 | 2010-08-03 | Advanced Thermal Sciences, Corp. | Thermal control system and method |
US8075729B2 (en) * | 2004-10-07 | 2011-12-13 | Applied Materials, Inc. | Method and apparatus for controlling temperature of a substrate |
US8157951B2 (en) * | 2005-10-11 | 2012-04-17 | Applied Materials, Inc. | Capacitively coupled plasma reactor having very agile wafer temperature control |
US8092638B2 (en) * | 2005-10-11 | 2012-01-10 | Applied Materials Inc. | Capacitively coupled plasma reactor having a cooled/heated wafer support with uniform temperature distribution |
US20100303680A1 (en) * | 2005-10-11 | 2010-12-02 | Buchberger Douglas A Jr | Capacitively coupled plasma reactor having very agile wafer temperature control |
US7988872B2 (en) * | 2005-10-11 | 2011-08-02 | Applied Materials, Inc. | Method of operating a capacitively coupled plasma reactor with dual temperature control loops |
US8337660B2 (en) * | 2005-10-11 | 2012-12-25 | B/E Aerospace, Inc. | Capacitively coupled plasma reactor having very agile wafer temperature control |
US8034180B2 (en) * | 2005-10-11 | 2011-10-11 | Applied Materials, Inc. | Method of cooling a wafer support at a uniform temperature in a capacitively coupled plasma reactor |
US8021521B2 (en) * | 2005-10-20 | 2011-09-20 | Applied Materials, Inc. | Method for agile workpiece temperature control in a plasma reactor using a thermal model |
US8012304B2 (en) * | 2005-10-20 | 2011-09-06 | Applied Materials, Inc. | Plasma reactor with a multiple zone thermal control feed forward control apparatus |
US20110068085A1 (en) * | 2005-10-20 | 2011-03-24 | Paul Lukas Brillhart | Method of processing a workpiece in a plasma reactor using multiple zone feed forward thermal control |
US20110065279A1 (en) * | 2005-10-20 | 2011-03-17 | Buchberger Jr Douglas A | Method of processing a workpiece in a plasma reactor using feed forward thermal control |
US20100314046A1 (en) * | 2005-10-20 | 2010-12-16 | Paul Lukas Brillhart | Plasma reactor with a multiple zone thermal control feed forward control apparatus |
US8221580B2 (en) * | 2005-10-20 | 2012-07-17 | Applied Materials, Inc. | Plasma reactor with wafer backside thermal loop, two-phase internal pedestal thermal loop and a control processor governing both loops |
US7794617B2 (en) * | 2006-03-23 | 2010-09-14 | Tokyo Electron Limited | Plasma etching method, plasma processing apparatus, control program and computer readable storage medium |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8801893B2 (en) * | 2005-10-11 | 2014-08-12 | Be Aerospace, Inc. | Method of cooling a wafer support at a uniform temperature in a capacitively coupled plasma reactor |
US20100300621A1 (en) * | 2005-10-11 | 2010-12-02 | Paul Lukas Brillhart | Method of cooling a wafer support at a uniform temperature in a capacitively coupled plasma reactor |
US20100303680A1 (en) * | 2005-10-11 | 2010-12-02 | Buchberger Douglas A Jr | Capacitively coupled plasma reactor having very agile wafer temperature control |
US8157951B2 (en) * | 2005-10-11 | 2012-04-17 | Applied Materials, Inc. | Capacitively coupled plasma reactor having very agile wafer temperature control |
US8337660B2 (en) * | 2005-10-11 | 2012-12-25 | B/E Aerospace, Inc. | Capacitively coupled plasma reactor having very agile wafer temperature control |
US20070081294A1 (en) * | 2005-10-11 | 2007-04-12 | Applied Materials, Inc. | Capacitively coupled plasma reactor having very agile wafer temperature control |
US8329586B2 (en) | 2005-10-20 | 2012-12-11 | Applied Materials, Inc. | Method of processing a workpiece in a plasma reactor using feed forward thermal control |
US8608900B2 (en) | 2005-10-20 | 2013-12-17 | B/E Aerospace, Inc. | Plasma reactor with feed forward thermal control system using a thermal model for accommodating RF power changes or wafer temperature changes |
US8980044B2 (en) | 2005-10-20 | 2015-03-17 | Be Aerospace, Inc. | Plasma reactor with a multiple zone thermal control feed forward control apparatus |
US9911578B2 (en) | 2009-12-03 | 2018-03-06 | Lam Research Corporation | Small plasma chamber systems and methods |
US9111729B2 (en) | 2009-12-03 | 2015-08-18 | Lam Research Corporation | Small plasma chamber systems and methods |
US9735020B2 (en) | 2010-02-26 | 2017-08-15 | Lam Research Corporation | System, method and apparatus for plasma etch having independent control of ion generation and dissociation of process gas |
US9190289B2 (en) | 2010-02-26 | 2015-11-17 | Lam Research Corporation | System, method and apparatus for plasma etch having independent control of ion generation and dissociation of process gas |
US9449793B2 (en) | 2010-08-06 | 2016-09-20 | Lam Research Corporation | Systems, methods and apparatus for choked flow element extraction |
US9967965B2 (en) | 2010-08-06 | 2018-05-08 | Lam Research Corporation | Distributed, concentric multi-zone plasma source systems, methods and apparatus |
US8999104B2 (en) | 2010-08-06 | 2015-04-07 | Lam Research Corporation | Systems, methods and apparatus for separate plasma source control |
US9155181B2 (en) | 2010-08-06 | 2015-10-06 | Lam Research Corporation | Distributed multi-zone plasma source systems, methods and apparatus |
TWI550711B (en) * | 2011-11-16 | 2016-09-21 | 蘭姆研究公司 | System, method and apparatus of a wedge-shaped parallel plate plasma reactor for substrate processing |
WO2013074701A1 (en) * | 2011-11-16 | 2013-05-23 | Lam Research Corporation | System, method and apparatus of a wedge-shaped parallel plate plasma reactor for substrate processing |
US9177762B2 (en) | 2011-11-16 | 2015-11-03 | Lam Research Corporation | System, method and apparatus of a wedge-shaped parallel plate plasma reactor for substrate processing |
US8872525B2 (en) | 2011-11-21 | 2014-10-28 | Lam Research Corporation | System, method and apparatus for detecting DC bias in a plasma processing chamber |
US9083182B2 (en) | 2011-11-21 | 2015-07-14 | Lam Research Corporation | Bypass capacitors for high voltage bias power in the mid frequency RF range |
US9508530B2 (en) | 2011-11-21 | 2016-11-29 | Lam Research Corporation | Plasma processing chamber with flexible symmetric RF return strap |
US10622195B2 (en) | 2011-11-22 | 2020-04-14 | Lam Research Corporation | Multi zone gas injection upper electrode system |
US9263240B2 (en) | 2011-11-22 | 2016-02-16 | Lam Research Corporation | Dual zone temperature control of upper electrodes |
US9396908B2 (en) | 2011-11-22 | 2016-07-19 | Lam Research Corporation | Systems and methods for controlling a plasma edge region |
US11127571B2 (en) | 2011-11-22 | 2021-09-21 | Lam Research Corporation | Peripheral RF feed and symmetric RF return for symmetric RF delivery |
US8898889B2 (en) | 2011-11-22 | 2014-12-02 | Lam Research Corporation | Chuck assembly for plasma processing |
US10586686B2 (en) | 2011-11-22 | 2020-03-10 | Law Research Corporation | Peripheral RF feed and symmetric RF return for symmetric RF delivery |
US10283325B2 (en) | 2012-10-10 | 2019-05-07 | Lam Research Corporation | Distributed multi-zone plasma source systems, methods and apparatus |
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