US20100264514A1 - Semiconductor device and a method of increasing a resistance value of an electric fuse - Google Patents

Semiconductor device and a method of increasing a resistance value of an electric fuse Download PDF

Info

Publication number
US20100264514A1
US20100264514A1 US12760648 US76064810A US2010264514A1 US 20100264514 A1 US20100264514 A1 US 20100264514A1 US 12760648 US12760648 US 12760648 US 76064810 A US76064810 A US 76064810A US 2010264514 A1 US2010264514 A1 US 2010264514A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
electric fuse
insulator layer
semiconductor device
trench
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12760648
Inventor
Takeshi Iwamoto
Kazushi Kono
Masashi Arakawa
Toshiaki Yonezu
Shigeki Obayashi
Original Assignee
Takeshi Iwamoto
Kazushi Kono
Masashi Arakawa
Toshiaki Yonezu
Shigeki Obayashi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02Details
    • H01H85/04Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a continuation of U.S. application Ser. No. 11/683,053, filed Mar. 7, 2007; and which application claims priority from Japanese patent application No. 2006-256226 filed on Sep. 21, 2006, the entire contents of which are hereby incorporated by reference into this application.
  • BACKGROUND OF THE INVENTION
  • The present invention relates to a semiconductor device which receives the supply of an electric current so as to be permitted to increase the resistance of the device itself, and a method of increasing the resistance of an electric fuse.
  • Hitherto, there has been used a fuse which receives the supply of an electric current to be permitted to increase the resistance of the fuse itself. In the present specification, such a fuse is called an electric fuse. The electric fuse is set inside an insulator layer. In the specification, a structure having an insulator layer and an electric fuse is called an electric fuse structure. In the specification, an increase in the resistance of an electric fuse is, for example, a phenomenon that the value of an electric current flowing into the electric fuse becomes small, that is, the electric fuse turns into a state that the fuse has a higher resistance than before, or a phenomenon that the flow of an electric current between two elements connected to both ends of the electric fuse stops completely, that is, the electric fuse is cut or melted/cut, or the resistance of the electric fuse becomes infinite. Examples of the electric fuse described in the specification include a fuse for making the use of an electric circuit impossible, a fuse which is used in an analog device or the like to adjust the voltage of the device, and a fuse which is used as a tag for leaving the hysteresis of a process, a test result or the like.
  • [Patent Document 1] Pamphlet of WO 97/12401
  • [Patent Document 2] U.S. Pat. No. 5,969,404
  • [Patent Document 3] U.S. Pat. No. 6,323,535
  • [Patent Document 4] U.S. Pat. No. 6,433,404
  • [Patent Non-document 1] V. Klee et al., “A 0.13 μm logic based embedded DRAM technology with electrical fuses, Cu interconnect in SiLk™, sub-7 ns access and its extension to the 0.10 μm generation”, IEDM Conference (2001).
  • SUMMARY OF THE INVENTION
  • Increases in the resistance of conventional electric fuses are realized by an electromigration phenomenon. For this reason, in some cases, it is necessary to supply a large electric current to an electric fuse. In such cases, a structure around the electric fuse may be damaged by heat generated from the fuse.
  • In light of the above-mentioned problems, the present invention has been made. Thus, an object of the invention is to provide a semiconductor device which is permitted to increase the resistance of the device itself without damaging any surrounding structure, and a method of increasing the resistance of an electric fuse.
  • An aspect of the present invention is a semiconductor device comprising an insulator layer and an electric fuse formed in the insulator layer. The electric fuse has a larger linear expansion coefficient than that of the insulator layer, and further has a lower melting point than that of the insulator layer.
  • According to this structure, the resistance of the electric fuse can be increased even if the value of an electric current supplied to the electric fuse is small. Accordingly, the amount of heat generated from the electric fuse is small. As a result, a structure around the electric fuse is prevented from being damaged.
  • Another aspect of the invention is a semiconductor device comprising a semiconductor substrate, a gate electrode formed over the semiconductor substrate, an interlayer dielectric covering the gate electrode, a fine layer formed over the interlayer dielectric, a semiglobal layer formed over the fine layer, a global layer formed over the semiglobal layer, and an electric fuse formed in at least one selected from the fine layer, the semiglobal layer, and the global layer.
  • According to this structure, when an electric current is supplied to the electric fuse, the distance over which heat generated from the electric fuse reaches the semiconductor substrate is large; therefore, the resistance of the electric fuse can be increased without damaging the semiconductor substrate.
  • Still another aspect of the invention is a semiconductor device comprising an insulator layer, and an electric fuse which is formed in the insulator layer, and has a meandering shape comprising a linear portion and a bent portion, wherein the distance between moieties near the bent portion is smaller than the distance between moieties other than the moieties near the bent portion.
  • According to this structure, heat from a central portion of the electric fuse does not diffuse outside easily since the electric fuse is meandering. Therefore, a structure around the electric fuse is restrained from being damaged by heat generated from the electric fuse. Moreover, a time required for an increase in the resistance of the electric fuse can be shortened since a large amount of heat is locally given only to the bent portion.
  • A different aspect of the invention is a method of increasing the resistance of an electric fuse wherein an electric current is supplied to the electric fuse which is any one of the above-mentioned electric fuses. In this way, the electric fuse is melted and is further cracked. Thereafter, a part of the melted electric fuse is absorbed into the crack by use of a capillary phenomenon. As a result, a discontinuous portion is formed in the electric fuse. According to this method, an electric fuse can be cut by a smaller electric current than that given to an electric fuse in any conventional method of using electromigration to cut the electric fuse.
  • A further different aspect of the invention is a method of increasing the resistance of an electric fuse comprising the steps of: supplying an electric current to the electric fuse which is anyone of the above-mentioned electric fuses, thereby making the electric fuse narrow by use of pinch effect; and then stopping the supply of the electric current, thereby forming a cavity in the electric fuse by use of retaining force of the electric fuse. According to this method, an electric fuse can be cut by a smaller electric current than that given to an electric fuse in the above-mentioned method of cutting the electric fuse by use of a capillary phenomenon.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic view illustrating a structure of an electronic circuit to which an electric fuse of an embodiment of the invention is fitted.
  • FIG. 2 is a view illustrating a structure of the whole of a semiconductor device wherein an electric fuse structure of the embodiment is formed.
  • FIG. 3 is a schematic view illustrating the electric fuse of the embodiment which has a meandering shape.
  • FIG. 4 is a sectional view taken on line IV-IV in FIG. 3.
  • FIG. 5 is a schematic view illustrating the electric fuse of the embodiment which is made only of a liner portion.
  • FIG. 6 is a sectional view taken on line VI-VI in FIG. 5.
  • FIG. 7 is a schematic view illustrating another example of the electric fuse of the embodiment which has a meandering shape.
  • FIG. 8 is a photograph showing a state that linear portions of an electric fuse of the embodiment which has a meandering shape contact each other by leakage or solid dissolution.
  • FIG. 9 is a view illustrating a basic example of the electric fuse structure of the embodiment.
  • FIG. 10 is a first different example of the electric fuse structure of the embodiment.
  • FIG. 11A is a second different example of the electric fuse structure of the embodiment.
  • FIG. 11B is a third different example of the electric fuse structure of the embodiment.
  • FIG. 12A is a fourth different example of the electric fuse structure of the embodiment.
  • FIG. 12B is a fifth different example of the electric fuse structure of the embodiment.
  • FIG. 13 is a sixth different example of the electric fuse structure of the embodiment.
  • FIG. 14A is a seventh different example of the electric fuse structure of the embodiment.
  • FIG. 14B is an eighth different example of the electric fuse structure of the embodiment.
  • FIG. 15 is a ninth different example of the electric fuse structure of the embodiment.
  • FIG. 16A is a tenth different example of the electric fuse structure of the embodiment.
  • FIG. 16B is an eleventh different example of the electric fuse structure of the embodiment.
  • FIG. 17 is a twelfth different example of the electric fuse structure of the embodiment.
  • FIG. 18A is a thirteenth different example of the electric fuse structure of the embodiment.
  • FIG. 18B is a fourteenth different example of the electric fuse structure of the embodiment.
  • FIG. 19 is a fifteenth different example of the electric fuse structure of the embodiment.
  • FIG. 20A is a sixteenth different example of the electric fuse structure of the embodiment.
  • FIG. 20B is a seventeenth different example of the electric fuse structure of the embodiment.
  • FIG. 21 is a view for explaining the direction of force acting on the electric fuse which is the basic example of the embodiment when an electric current flows into this electric fuse.
  • FIG. 22 is a view for explaining a state that the electric fuse of the basic example swells.
  • FIG. 23 is a top view illustrating a first state of the electric fuse of the basic example when it is cut.
  • FIG. 24 is a sectional view taken on line XXIV-XXIV in FIG. 23.
  • FIG. 25 is a top view illustrating a second state of the electric fuse of the basic example when it is cut.
  • FIG. 26 is a sectional view taken on line XXVI-XXVI in FIG. 25.
  • FIG. 27 is a top view illustrating a third state of the electric fuse of the basic example when it is cut.
  • FIG. 28 is a sectional view taken on line XXVIII-XXVIII in FIG. 27.
  • FIG. 29 is a top view illustrating a fourth state of the electric fuse of the basic example when it is cut.
  • FIG. 30 is a sectional view taken on line XXX-XXX in FIG. 29.
  • FIG. 31 is a top view illustrating a fifth state of the electric fuse of the basic example when it is cut.
  • FIG. 32 is a sectional view taken on line XXXII-XXXII in FIG. 31.
  • FIG. 33 is a photograph (of across section) showing a state that an electric fuse is absorbed into a crack formed in an insulator layer in an electric fuse structure.
  • FIG. 34 is a photograph (of a top face) showing the state that the electric fuse is absorbed into the crack formed in the insulator layer in the electric fuse structure.
  • FIG. 35 is a view illustrating an electric current pulse as an improper pulse, and an electric current pulse as a proper pulse.
  • FIG. 36 is a photograph showing an electric fuse cut by an electric current pulse as an improper pulse, and an electric fuse cut by an electric current pulse as a proper pulse.
  • FIG. 37 is a graph showing a relationship between rise time of electric current pulses and the ratio of the resistance of an electric fuse after the fuse is cut to that of the electric fuse before the fuse is cut.
  • FIG. 38 is a top view illustrating an example of the position of a cut portion of an electric fuse made only of a linear portion.
  • FIG. 39 is a chart wherein positions of cut portions of plural electric fuses each made only of a linear portion are plotted.
  • FIG. 40 is a view for explaining an electric fuse structure wherein a central portion is selectively to be cut.
  • FIG. 41 is a photograph showing an electric fuse structure wherein a central portion was selectively cut.
  • FIG. 42 is a view illustrating the distance between linear portions.
  • FIG. 43 is a view illustrating a state that linear portions short-circuit through a cut piece.
  • FIG. 44 is a view illustrating an electric fuse structure having a construction for preventing linear portions from short-circuiting.
  • FIG. 45 is a view for explaining a method of cutting an electric fuse by use of pinch effect.
  • FIG. 46 is a photograph showing an electric fuse cut by pinch effect.
  • FIG. 47 is a graph of a relationship between time and the distance between a moiety having a temperature of 600° C. when the temperature of an electric fuse was kept at 1200° C. and the electric fuse.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • With reference to the attached drawings, embodiments of the semiconductor device according to the present invention and the method of increasing the resistance of an electric fuse according to the invention will be described hereinafter.
  • Embodiment 1
  • An electric fuse of an embodiment 1 of the present invention is not any electric fuse formed in the same layer in which a gate electrode is formed, as in the prior art. The electric fuse of the embodiment 1 is formed in a fine layer in a multi-layered structure including the fine layer, a semiglobal layer and a global layer in a semiconductor device. Therefore, the electric fuse is prevented from damaging its semiconductor substrate.
  • According to the structure of the semiconductor device of the embodiment 1, other elements, such as a transistor for controlling the flow of an electric current for increasing the resistance of the fuse, can be arranged in a space from the semiconductor substrate to the electric fuse; therefore, it is possible to make small the occupation area of elements arranged in a direction parallel to a main surface of the semiconductor substrate of the semiconductor device.
  • The increase in the resistance of the electric fuse of the embodiment 1 is realized not by any electromigration phenomenon but a capillary phenomenon. Accordingly, the resistance of the electric fuse can be increased only by causing a relatively small electric current to flow into the electric fuse. As a result, a structure around the electric fuse is prevented from being damaged. Moreover, the time necessary for an increase in the resistance of the electric fuse can be largely shortened.
  • In the embodiment 1, the electric fuse is a member for separating a redundant circuit and any other circuit electrically from each other. However, the usage of the electric fuse of the invention is not limited thereto. The electric fuse of the invention can be applied to any article as long as the article is an article having a resistance that can be increased by receiving the supply of an electric current. The raw material of the electric fuse is suitably a metal or a metal compound. However, the raw material of the electric fuse of the invention is not limited thereto as long as a resistance-increasing method that will be described below can be applied to the raw material.
  • First, the electric fuse structure of the embodiment 1 is specifically described herein. As illustrated in FIG. 1, the electric fuse (electric fuse 10) of the embodiment 1 is set inside a semiconductor device, and is connected to a power source electrode VDD and an earth electrode VSS so as to be present therebetween. A resistor 60 is arranged between a terminal 10 a of the electric fuse 10 and the power source electrode VDD, and a resistor 70 is arranged between a terminal 10 b of the electric fuse 10 and the earth electrode VSS. A transistor 40 and a decision circuit 50 are connected to a wiring between the resistor 70 and the terminal 10 b. The decision circuit 50 is a circuit for detecting whether or not the resistance of the electric fuse 10 turns into a predetermined value or more. An inverter circuit 30 is connected to the gate electrode of the transistor 40. In accordance with an electric signal given from the inverter circuit 30 to the transistor 40, an electric current flows from the power source electrode VDD through the electric fuse 10 to the earth electrode VSS. Accordingly, in the method of increasing the resistance of the electric fuse 10 in the embodiment 1, whether or not the resistance of the electric fuse is increased can be controlled in accordance with an electric signal given to the transistor 40 from the outside. Whether or not the resistance of the electric fuse 10 is over the predetermined value is decided by the decision circuit 50.
  • Next, the structure of the semiconductor of the embodiment 1 is described herein with reference to FIG. 2. The semiconductor device of the embodiment 1 has plural stacked metal wiring layers. The metal wiring layers are named M1, M2, . . . M8 and M9, respectively, in the order from the side of a semiconductor substrate SC upwards. The metal wiring layers are connected to each other through vias. The vias are named V1, V2, . . . , V7 and V8, respectively, in the order from the side of the semiconductor substrate SC upwards.
  • Out of the layers including the metal wiring layers M1, M2, . . . M8 and M9, and the vias V1, V2, . . . , V7 and V8, layers positioned at a lower side are called a fine layer 100, and layers positioned at an upper side are called a global layer 300. The layers positioned between the fine layer 100 and the global layer 300 are called a semiglobal layer 200.
  • The metal wiring layers in the fine layer 100 each have the smallest wiring width and thickness among the metal wiring layers constituting the semiconductor device. The metal wiring layers in the semiglobal layer 200 each have a larger wiring width and a larger thickness than those of the metal wiring layers in the fine layer 100. The metal wiring layers in the global layer 300 each have a larger wiring width and a larger thickness than those of the metal wiring layers in the semiglobal layer 200. Examples of dimensions of the fine layer 100, the semiglobal layer 200 and the global layer 300 are shown in Table 1.
  • TABLE 1
    Wiring width (μm) Wiring thickness (nm)
    Fine layer 0.12 200
    Semiglobal layer 0.3 400
    Global layer 0.6 1000
  • The dimensions of the fine layer 100, the semiglobal layer 200 and the global layer 300 are varied in accordance with the kind of the semiconductor device, and the material of the wirings. Accordingly, Table 1 shows a mere example of a relationship between the dimensions of the three layers.
  • In a conventional semiconductor device, a wiring layer equivalent to a gate electrode layer GA covered with an interlayer dielectric (TEOS: tetraethyl ortho silicate glass) CA shown in FIG. 2 is partially used as an electric fuse. For this reason, when a large electric current is supplied to the electric fuse so as to make the resistance of a predetermined portion of the electric fuse high, a semiconductor substrate of the conventional device and a surrounding portion thereof may be damaged by heat generated from the electric fuse. Against this matter, in the embodiment 1, the electric fuse 10 is arranged near the metal wiring layers M1 to M5 in the fine layer 100.
  • The metal wiring layers M1 to M5, which constitute the fine layer 100, are formed in accordance with a single rule for plural layers (generally, the number of the layers is from about 4 to 6), this matter being different from rules for the metal wiring layers M6 and M7, which constitute the semiglobal layer 200, and for the metal wiring layers M8 and M9, which constitute the global layer 300. Therefore, the electric fuse 10 can be formed in any one of the layers in fine layer 100. For example, the electric fuse 10 can be formed near the metal wiring layer M5, which is formed at a position farthest from the semiconductor substrate SC.
  • Accordingly, when an electric current is supplied to the electric fuse 10, heat generated from the electric fuse 10 is prevented from producing an adverse effect onto the semiconductor substrate SC. Even if the electric fuse 10 is formed in the semiglobal layer 200 or the global layer 300, the electric fuse 10 can be prevented from producing an adverse effect onto the semiconductor substrate SC. In other words, even if the electric fuse 10 is formed in any one of the layers in the fine layer 100, the semiglobal layer 200 and the global layer 300, or the electric fuse 10 and one or more electric fuses equivalent thereto are formed in any two or all of these layers, the electric fuse 10 can be prevented from producing an adverse effect onto the semiconductor substrate SC.
  • In the semiconductor device of the embodiment 1, the metal wiring layer which has a low resistance is used as the electric fuse 10. Thus, even if the value of the electric current supplied to the electric fuse 10 is small, the resistance of the electric fuse 10 can be increased.
  • FIGS. 3 and 4 are a top view and a sectional view of the electric fuse 10 of the embodiment 1 and a portion around the fuse 10, respectively. The electric fuse 10 of the embodiment 1 has a meandering shape composed of linear portions 10 d and bent portions 10 c. The electric fuse structure of the embodiment 1 may have an electric fuse 10 made only of a linear portion, as illustrated in FIGS. 5 and 6. However, when the electric fuse 10 having a meandering shape is compared with any electric fuse which is made only of a linear portion and has the same length as the meandering electric fuse 10, the meandering electric fuse 10 has an advantage that even if the value of an electric current supplied to the fuse 10 is small, the resistance of the fuse 10 can be made larger.
  • As illustrated in FIGS. 3 to 6, in the electric fuse structure of the embodiment 1, the electric fuse 10 is surrounded by the metal wiring layers M1 to M5 and the vias V1 to V4, which are each made of an electroconductive material. The metal wiring layers M1 to M5 and the vias V1 to V4 illustrated in FIGS. 3 to 6 are each an electrically-floating, electroconductive layer, which is electrically insulated from the other electroconductive layers. Accordingly, even if the electric fuse 10 melts out to leak into one or more of the insulator layers around the fuse 10, the metal wiring layers M1 to M5 and the vias V1 to V4 prevent the leaking fuse from producing an adverse effect onto any different electronic circuit.
  • The electric fuse 10 of the embodiment 1 may have a structure as illustrated in FIG. 7. Specifically, the number of bent portions 10 c and that of linear portions 10 d are not each limited to any specific numerical value.
  • FIG. 8 is a photograph showing a state that an example of the electric fuse 10 was actually cut. It can be understood from FIG. 8 that when the electric fuse 10, which is meandering, is cut, its portions adjacent to each other are brought into contact with each other to generate leakage and further a portion below the electric fuse 10 is cracked by an expansion in the volume of the portion converted to a solid solution. In other words, it can be understood that only an idea that the electric fuse 10 is meandered does not make it possible to increase the resistance of the electric fuse 10 while the electric fuse 10 is prevented from producing an adverse effect onto a structure around the fuse 10.
  • Consequently, the electric fuse 10 of the embodiment 1 has a structure illustrated in FIG. 9 in order to increase the resistance of the electric fuse 10 while the electric fuse 10 is prevented from producing an adverse effect onto a structure around the fuse 10.
  • As illustrated in FIG. 9, the electric fuse 10 is made of a main wiring 1 and a barrier film 3 covering the lower face of the main wiring 1 and both side faces of the wiring 1. The electric fuse 10 extends inside a trench 2 a made in the insulator layer 2 and in parallel to the main surface of the semiconductor substrate SC. The electric fuse 10 and the insulator layer 2 are covered with an insulator layer 4. An insulator layer 5 is formed on the insulator layer 4.
  • The main wiring 1 is made of a metal layer or a metal compound layer, and has a lower melting point than the insulator layer 2, the insulator layer 4 and the insulator layer 5 each have. The barrier film 3 is a metal layer or a metal compound layer, or has a structure wherein these layers are stacked. The melting point of the barrier film 3 is higher than that of the main wiring 1 and lower than those of the insulator layers 2 and 4. Furthermore, the linear expansion coefficient of the main wiring 1 is larger than that of the barrier film 3, and the linear expansion coefficient of the barrier film 3 is as large as or larger than that of each of the insulator layers 2, 4 and 5.
  • In the semiconductor device of the embodiment 1, the main wiring 1 is made of a copper film, and the barrier film 3 is a tantalum film. The insulator layers 2 and 5 are each a SiOC film, which is a low-k film having a dielectric constant of 3 or less, and the insulator layer 4 is a SiN film. However, the materials of the main wiring 1, the barrier film 3 and the insulator layers 2, 4 and 5 are not limited to the above-mentioned materials as long as the materials satisfy the above-mentioned relationships about the linear expansion coefficients and the melting points. For example, the insulator layer 4 may be a silicon nitride film (SiN film). The material of the main wiring 1 may be Al, Cu, Ta, Ti or W, as shown in Table 2.
  • TABLE 2
    Linear expansion coefficient (10−6/K) Melting
    300K 600K 800K 1000K point(° C.)
    Al 23.2 28.4 34   660.4
    Cu 16.6 18.9 20.3 22.4 1084.5
    Ta 6.3  7.3 2996
    Ti 8.7 10.4 11.1 11.5 1675
    W 4.5  4.7 5   5.2 3387
    Oxide films or 0.5 to 10 About 1000
    nitride films to 1600
    used in the
    field of
    semiconductors
  • The electric fuse structure of the invention is not limited to the structure illustrated in FIG. 9, and may be a structure shown in each of FIGS. 10 to 20B. The structures shown in FIGS. 10 to 20B basically have a structure similar to the electric fuse structure illustrated in FIG. 9; therefore, the same reference number is attached to each of members or parts common to each other in these structures, and description thereof is not repeated. FIGS. 11A, 12A, 14A, 16A, 18A and 20A correspond to FIGS. 11B, 12B, 14B, 16B, 18B and 20B, respectively. Which of a structure illustrated in FIG. 11A and a structure illustrated in FIG. 11B is formed depends on a used production process. Consequently, in one device, there may be formed both of any one of the structures illustrated in FIGS. 11A, 12A, 14A, 16A, 18A and 20A and a structure corresponding thereto out of the structures illustrated in FIGS. 11B, 12B, 14B, 16B, 18B and 20B.
  • In a structure illustrated in FIG. 10, an insulator layer 4 is composed of an insulator layer 4 a and an insulator layer 4 b. The insulator layer 4 is a SiCO layer, and the insulator layer 4 b is a SiCN layer.
  • In each of the structures illustrated in FIGS. 11A, 11B, 12A and 12B, a barrier film 3 has a three-layer structure. The three-layer structure is composed of a Ta film 3 a formed on side faces of a trench 2 a, a TaN film 3 b formed on inner side faces of the Ta film 3 a, and a Ta film 3 c formed on inner side faces of the TaN film 3 b and the bottom face of the trench 2 a.
  • In the structures illustrated in FIGS. 13 to 20B, a metal cap film 9 made of CoW, CoWP, CoP or CoPB is formed on a main wiring 1. The electric resistance of the metal cap film 9 is higher than that of the main wiring 1. Accordingly, when the metal cap film 9 is made on the main wiring 1, a larger heat is generated than heat generated from only the main wiring 1. In short, the resistance of the electric fuse 10 can be increased in a shorter time. The metal cap film 9 may be formed on the barrier film 3. The metal cap film 9 is formed on the entire upper face of the main wiring 1 so as to have a function of preventing the generation of electromigration of the main wiring 1. In the embodiment 1, the metal cap film 9 made of CoW, CoWP, CoP or CoPB is described as an example of the cap film. However, any film may be formed on the main wiring 1 as long as the film has a higher electric resistance than that of the main wiring 1.
  • In the structures illustrated in FIGS. 17 to 20B, the insulator layer 4 is not formed. In this case, a crack 6 is formed in an insulator layer 5.
  • The following will describe the effect generated when the resistance of the electric fuse of the embodiment 1 increases, in particular, the effect generated when the electric fuse is cut.
  • First, table 3 is used to describe, herein, the volume expansion coefficient of the metal which constitutes the main wiring 1 in the embodiment 1 when the metal is liquefied.
  • TABLE 3
    Density at room Density of Reference:
    temperature liquefied melting point
    (g/cm3) metal (g/cm3) (° C.)
    Aluminum 2.69 2.5 (800° C.)  660.4
    Copper 8.93 7.8 (1200° C.) 1084.5
    Iron 7.86 7.1 (1550° C.) 1535
  • It can be understood from Table 3 that the density of each of the metals is smaller after liquefied than before liquefied. This matter demonstrates that the volume of each of the metals after it is liquefied increases from that of the metal before it is liquefied. As shown in Table 3, the volume expansion coefficients of the metals based on liquefaction are as follows: the volume expansion coefficient of Al is 8% (2.69/2.5=1.08); that of copper is 14% (8.93/7.8=1.14); and that of iron is 11% (7.86/7.1=1.11). It can be therefore understood that the volume expansion coefficient of copper is the highest among aluminum, copper and iron.
  • With reference FIGS. 21 and 22, the effect generated when the resistance of the electric fuse 10 increases, in particular, the effect generated when the electric fuse 10 is cut is described, considering the above-mentioned matters.
  • In an electric fuse 10 illustrated in FIG. 21, an electric current flows along a direction perpendicular to the paper surface, that is, along a direction in which a main wiring 1 extends, whereby Joule heat is generated in the main wiring 1. Thus, the temperature of the main wiring 1 begins to rise. As a result, thermal stress is generated in each of the main wiring 1, a barrier film 3 and insulator layers 2, 4 and 5 on the basis of a difference between linear expansion coefficients thereof.
  • In the electric fuse structure of the embodiment 1, the linear expansion coefficient of the insulator layer 4 is considerably lower than that of the main wiring 1. For this reason, the degree of the expansion of the insulator layer 4 is smaller than that of the main wiring 1. The insulator layer 4 is brought into contact with the main wiring 1. Accordingly, even if the main wiring 1 is to expand, the insulator layer 4 restrains the expansion. As a result, tensile force is generated in the upper portion of the main wiring 1 and compressive force is generated in the lower portion of the insulator layer 4, as illustrated in FIG. 21, so that stress concentration is generated in encircled portions illustrated in FIG. 21.
  • When the temperature of the main wiring 1 further rises, the metal constituting the main wiring 1 changes from the solid to a liquid. In short, the metal undergoes phase change. In this way, the volume of the main wiring 1 further increases. At this time, the expansion of the main wiring 1 is limited by the barrier film 3. For this reason, the main wiring 1 expands only upwards, as represented by white arrows each surrounded by a black line in FIG. 22, whereby the insulator layer 4 is pushed upwards.
  • On the basis of a synergistic effect of the matter that stress concentration is generated at both ends of the upper portion of the main wiring 1 before the main wiring 1 is liquefied and that the insulator layer 4 is pushed upwards, cracks 6 are generated in the insulator layers 4 and 5 from the points where the stress concentration is generated, the points functioning as starting points.
  • By the generation of the cracks 6, a cavity is generated in the insulator layer 4. The width of the cavity is very small. The main wiring 1 is liquefied, and thus the liquefied main wiring 1 is absorbed into the cracks 6 by a capillary phenomenon. As a result, in the main wiring 1, discontinuous portions are formed at positions different from the positions where the cracks 6 are generated.
  • In FIGS. 23 to 32, a series of states that the cutting of the electric fuse 10 progresses as described above are illustrated in succession with time. As the number of one out of these figures is larger than others, the state illustrated in the figure is a state which makes its appearance later. FIGS. 23, 25, 27, 29 and 31 are each a top view, and FIGS. 24, 26, 28, 30 and 32 are each a sectional view.
  • As illustrated in FIGS. 31 and 32, when a predetermined amount of the liquefied main wiring 1 is absorbed into the cracks 6 by a capillary phenomenon, the main wiring 1 and the barrier film 3 are cut. The barrier film 3 is cut by force generated when the main wiring 1 is absorbed. Even if residues of the barrier film 3 slightly remain at this time, the barrier film 3 can be cut without failure by causing a very small electric current to flow into the main wiring 1 continuously. In FIGS. 33 and 34, the electric fuse 10 having an actual cut portion 1000 is illustrated.
  • When the electric fuse 10 is cut by use of a capillary phenomenon as described above, no crack is generated in the insulator layer 2 below the main wiring 1. Moreover, when the electric fuse 10 is heated to a temperature that is slightly higher than the melting point of the main wiring 1, the electric fuse 10 can be cut. It is therefore possible to prevent a thermally adverse effect from being produced on surrounds of the electric fuse 10 and prevent elements, such as a transistor, from damaging the formed semiconductor substrate SC.
  • Embodiment 2
  • With reference to FIGS. 35 and 44, a method of an embodiment 2, wherein the resistance of an electric fuse is increased, is described herein. The electric fuse structure used in the embodiment 2 may be the same as in the embodiment 1.
  • In the embodiment 2, a method for cutting the electric fuse 10 described in the embodiment 1 more certainly is described. Specifically, described is a matter that it is necessary to adjust the rise time of electric pulses caused to flow into the electric fuse 10 in order to cut the electric fuse 10 more certainly.
  • When the electric fuse is cut, the temperature of the main wiring 1 needs to reach the melting point or a higher temperature. However, a phenomenon generated when the electric fuse 10 is cut is varied in accordance with the period from a time when a rise in the temperature of the main wiring 1 starts to a time when the temperature of the main wiring 1 reaches the melting point or a higher temperature. Accordingly, unless this period is adjusted, it is impossible to cut the electric fuse without damaging surrounds of the electric fuse 10.
  • FIG. 35 shows two kinds of electric current pulses which have the same values of currents flowing into the electric fuse 10 but have different rise times and falls times. As illustrated in FIG. 35, the electric current pulse shown as a proper pulse has a far shorter fall time (i.e., a period from a time when the supply of an electric current is started to a time when the supply of an electric current having a constant value starts) than the electric current pulse shown as an improper pulse.
  • FIG. 36 shows a state of the electric fuse 10 which is cut by receiving the supply of electric current pulses as improper pulses as illustrated in FIG. 35, and a state of the electric fuse 10 which is cut by receiving the supply of electric current pulses as proper pulses as illustrated in FIG. 35.
  • As described above, the method of increasing the resistance of the electric fuse 10 in the embodiment 1, in particular, the method of cutting the electric fuse 10 is a method of generating the cracks in the insulator layer 4 to cause the liquefied main wiring 1 to be absorbed into the cracks 6, thereby cutting the main wiring 1. However, if the insulator layer 4 is softened by Joule heat from the main wiring 1, the cracks 6 are not generated in the insulator layer 4; therefore, the electric fuse 10 may not be cut in a short time. If in this case an electric current is caused to flow into the electric fuse 10 for a long time so that heat is continuously generated from the electric fuse 10 over a long time, the surrounding structure of the electric fuse 10 may be damaged.
  • Thus, the shape of electric current pulses for generating the cracks 6 in the insulator layer 4 to cut the electric fuse 10 in a short time will be discussed hereinafter.
  • First, considered is a rise in the temperature of a metallic cube having the same volume as the electric fuse 10 when the cube is uniformly heated in an adiabatic state. The reason why this matter is considered is as follows: it can be estimated that the electric fuse 10 is present in a state equivalent to an adiabatic state since the fuse 10 is surrounded by the insulator layers 2 and 4.
  • TABLE 4
    Wiring Melting
    Specific Melting Heat of Boiling Evaporation Electric Volume film Wiring Wiring point
    heat point melting point heat current resistivity thickness width length Density arrival time
    Material (kJ/(kgK)) (° C.) (kJ/kg) (° C.) (kJ/kg) (mA) (×10−8Ωm) (μm) (μm) (μm) (kg/m3) (μs)
    Al 1 660.4 311.3 2486 10888.9 15 2.7 0.2 0.1 8 2690 0.113
    Cu 0.47 1084.5 213 2580 4789 15 1.6 0.2 0.1 8 8500 0.470
    Al 1 660.4 311.3 2486 10888.9 30 2.7 0.2 0.1 8 2690 0.028
    Cu 0.47 1084.5 213 2580 4789 30 1.6 0.2 0.1 8 8500 0.118
    Calculation conditions
    wiring width: 0.1 μm, wiring thickness: 0.2 μm, wiring length: 8 μm, wiring volume: 0.16 μm3, and applied current: 15 mA, and 30 mA.
  • Herein, a case is considered where electric current pulses which have a current value of 15 mA and 30 mA, respectively, and each have a rise time of 0 μs are each supplied to the metallic cube. The electric pulses are theoretical pulses. The time required until each of the metals is liquefied in this case is shown in Table 4.
  • The melting point arrival time of each of the metals shown in Table 4 is the shortest time ts necessary until the cube of the metal is liquefied. When the value of the current supplied to the cube of Cu is, for example, 15 mA, the shortest time ts, which is necessary until the cube is liquefied, is about 0.5 μs. When the value of the current supplied to the cube of Cu is 30 mA, the shortest time ts is about 0.1 μs.
  • Since the shortest time ts is a time necessary until the cube of a metal reaches the melting point thereof, the time ts does not precisely represent a time required for a rise in the temperature of the electric fuse 10, which is a long and thin line. Since the electric current pulses given to the cube are theoretical pulses which do not have any rise time (rise time=0 μs), the pulses are different from electric current pulses having a rise time.
  • FIG. 37 shows a relationship between the rise time of electric pulses (2 μs) and the ratio of the resistance of the electric fuse 10 after the fuse 10 is cut to that of the electric fuse 10 before the fuse 10 is cut. As can be understood from FIG. 37, when the current value of the electric current pulses is 15 mA and the rise time thereof is 0.5 μs, the electric fuse 10 is cut. However, when the current value of the electric current pulses is 15 mA but the rise time thereof is over 0.5 μs, the resistance of the electric fuse 10 hardly increases. FIG. 37 shows results from an experiment wherein electric current pulses were given to the actual electric fuse 10.
  • From the comparison of the experimental results shown in FIG. 37 with the values estimated theoretically from the use of the values shown in Table 4, it is understood that the above-mentioned shortest time ts can be adopted as an index for deciding the rise time of actual pulses supplied to the electric fuse 10 which is long and thin and is actually used. In other words, it can be considered that when the rise time of electric current pulses given to the actual electric fuse 10 is shorter than the theoretically-estimated shortest time ts, the electric fuse 10 can be properly cut.
  • When it is assumed that the rise time, a time when a constant electric current is caused to flow, and the fall time are equal to each other (tm) under consideration of the above-mentioned matters, the cut time of the electric fuse 10 can be represented by the following expression:

  • Cut time=[rise time]+[time when a constant electric current is caused to flow]+[fall time]=3×[shortest time (ts)]
  • It can be understood from this expression that when an electric current of 15 mA is caused to flow into the electric fuse 10, the electric fuse 10 can be cut in a time of 1.5 μs or less.
  • When the rise time is actually shorter, the following can be admitted even if the width and the thickness of the main wiring 1 are scattered: the adjustment of the time when the constant electric current is caused to flow makes it possible to cut the electric fuse 10 in a time of less than 1 μs.
  • According to the electric fuse cutting method of the embodiment 2, the electric fuse 10 can be cut in a time of about several microseconds. Specifically, according to the electric fuse cutting method of the embodiment 2, the electric fuse 10 can be cut in a very short time which is 1/133 (=1.5 μs/200 μs) of the time required for cutting an electric fuse in the above-mentioned conventional electric fuse cutting method.
  • However, when the electric fuse 10 illustrated in FIGS. 5 and 6, which has only a linear shape, is cut by the above-mentioned method, either one of sites at both sides of the site where the capillary phenomenon is generated is cut. However, the position of the cut portion 1000 cannot be specified. FIGS. 38 and 39 show examples of positions of a crack 6 generated when an electric fuse 10 made only of a linear shape is cut and examples of the position of a cut portion 1000.
  • It is theoretically known that when the length of the electric fuse 10 is 12 μm, the crack 6 is generated at a position 6.6 μm apart from one of ends of the electric fuse 10 and the cut portion 1000 is formed at a position 5.1 μm apart from the end.
  • It is also understood from FIG. 39 that most of the examples of the position of the cut portion 1000 are positioned upstream from the examples of the position of the crack 6 but about measurement results each surrounded by an ellipse, which are different from the other measurement results, the examples of the position of the cut portion 1000 are positioned downstream from the examples of the position of the crack 6. It appears that this tendency is produced regardless of the length of the electric fuse 10. As described herein, when the electric fuse 10 made only of a linear shape is used, there arises a problem that the position of the cut portion 1000 is not easily specified.
  • One method for solving this problem is a method of generating cracks 6 at two sites, and causing the melted main wiring 1 to be absorbed into each of the two sites, thereby cutting the electric fuse 10 at a position between the two sites. For this method, it is effective to use the electric fuse 10 having a meandering shape as illustrated in FIGS. 3 and 4, that is, the electric fuse 10 having bent portions 10 c and linear portions 10 d.
  • According to such an electric fuse, which has a meandering shape, such as an electric fuse 10 illustrated in FIGS. 40 and 41, stress concentration can be generated at positions 2000 which are each near one of bent portions 10 c of the electric fuse 10. For this reason, the position of a cut portion 1000 can be specified. In other words, the cut portion 1000 can be formed at a position between the two bent portions 10 c.
  • However, when the distance S between linear portions 10 d illustrated in FIG. 42 is small, cut pieces are scattered so that the cut linear portions 10 d of the electric fuse 10 may short-circuit, as illustrated in FIG. 43.
  • It is known, from consideration of diffusion of the cut portion 1000 to the outside of a barrier film 3, whether or not the cut linear portions 10 d of the electric fuse 10 short-circuit depends basically on the size of the cut portion 1000. The size of the cut portion 1000 is about less than 0.3 μm; therefore, it is desired that the distance S between the linear portions 10 d of the electric fuse 10, which has the meandering shape, is 0.3 μm or more. In short, it is desired that the distance S between the linear portions 10 d near the cut portion 1000 is larger than the size of the cut portion 1000. As illustrated in FIG. 44, the distance S between linear portions 10 d is 0.3 μm or more; in order to generate stress concentration easily, the distance S0 between line moieties near each bent portion 10 c is desirably smaller than the distance S between the linear portions 10 d.
  • Embodiment 3
  • With reference to FIGS. 45 to 47, a method of an embodiment 3, wherein the resistance of an electric fuse is increased, is described herein. The electric fuse structure in the embodiment 3 may be the same as in the embodiment 1.
  • In the case of using the method of increasing the resistance of an electric fuse according to each of the embodiments 1 and 2, the cracks 6 may not extend immediately in the insulator layer 4. This would be because a considerable large electric current cannot be caused to flow into the electric fuse 10 because of a problem resulting from the structure of the circuit and thus thermal stress generated in the electric fuse structure is not sufficiently large for generating the cracks 6. For this reason, the electric fuse 10 may not be cut by the cutting method described as the embodiment 1 or 2. Accordingly, a method for cutting the electric fuse 10 certainly in this case will be described hereinafter.
  • When an electric current is caused to flow into the electric fuse 10, the main wiring 1 changes from solid to liquid as the temperature of the electric fuse 10 rises. When no crack is generated in the insulator layer 4, an electric current flows into the main wiring 1 in the liquid state. When an electric current of 108 A/m2 or more is caused to flow into the main wiring 1 in this case, electromagnetic force is generated toward the central of the main wiring 1. This is called pinch effect. As a result, a liquefied portion in the main wiring 1 will be shrunken by surface tension and the pinch effect. This pinch effect will be described in detail hereinafter.
  • For simplicity of the description, it is presumed that the main wiring 1 has a columnar shape. When an electric current flows into the main wiring 1, a magnetic field is formed so that Lorentz force F is generated in a direction perpendicular to the direction along which the electric current flows. At this time, the magnetic field B is represented by the following equation (1):
  • B = μ0 × i · s 2 π r
  • When the radius of the above-mentioned column is represented by r (m), the magnetic field B (A/m) and the density j (A/m2) of the current are used to represent the Lorentz force F (N/m3) generated in each unit volume of the main wiring 1 by the following equation (2):
  • F = j · μ0 × i · s 2 π R = μ0 · I π R 2 · I 2 π R
  • In the equation (1), it is presumed that the current density j is uniform. In the formula (I), μ0 is the magnetic permeability, S is any closed surface, I is the value of the current given to the main wiring 1, and R is the distance from the portion which constitutes the main wiring 1 to the center of the column. When the density of the material which constitutes the main wiring 1 is represented by ρ (kg/m3), the acceleration a generated in each unit volume of the main wiring 1 by the Lorentz force F is equal to F/ρ (m/s2).
  • Accordingly, using the acceleration a, the time t (s) when the distance becomes zero, that is, the time when the electric fuse 10 becomes theoretically narrowest is represented by t=√{square root over ( )}(2r/a).
  • When it is presumed that the radius r of the main wiring 1 is 0.075 μm, the applied current is 15 mA, the density ρ is 8780 kg/m3, and the magnetic permeability μ0 is 1.256637×10−6 (H/m), the Lorentz force F, the acceleration a, and the time t are calculated as follows:

  • F=3.3953×1010 N/m3,

  • a=3.8671×106 m/s2, and

  • t=197 ns.
  • It can be considered from the above-mentioned matter that when pinch effect is used, the time (t) necessary for making the main wiring 1 narrowest becomes very short. In other words, it is expected that even if the width of given electric current pulses is small, the diameter of the electric fuse 10 becomes very small by pinch effect. The current density j is 8.49×1011 A/m2.
  • In order to use pinch effect to cut the electric fuse 10, the supply of the electric current (pulses) to the electric fuse 10 is stopped when the liquefied portion of the electric fuse 10 becomes narrowest, that is, the time t when the above-mentioned R becomes zero. From this time, the solidification of the main wiring 1 starts. When the supply of the electric current (pulses) to the electric fuse 10 is stopped, retaining force acts in a direction opposite to the direction along which the electric fuse 10 is shrunken. As a result, the electric fuse 10 starts to swell.
  • When electric current pulses are again supplied to the main wiring 1, a phenomenon that the above-mentioned shrinking force and retaining force are alternately generated is repeated, so that the diameter of the moiety onto which the Lorentz force L of the main wiring 1 acts becomes smaller. Accordingly, at last, the liquefied portion of the main wiring 1 is cut. FIG. 45 illustrates steps of repeating switching-on and switching-off of electric current pulses so as to form a cut portion 1000 on the electric fuse 10.
  • In the method of cutting an electric fuse according to the embodiment 3, shrinking force (Lorentz force L) generated by switching-on of an electric current on the basis of pinch effect and force (retaining force) generated in a swelling direction by switching-off of the electric current act alternately and repeatedly onto the electric fuse 10. Since the main wiring 1 is liquefied at the position where the pinch effect is generated, surface tension is also generated together with the Lorentz force F. At this time, the insulator layers 2, 4 and 5 around the electric fuse 10 are softened by heat from the electric fuse 10. Thus, the electric fuse 10 swells outside. As a result, a central portion of the electric fuse 10 gradually becomes hollow. At last, the electric fuse 10 is cut. The liquefied electric fuse 10 is easily stayed at the lower side thereof by gravity. Thus, the cutting of the electric fuse 10 starts from the upper side thereof.
  • As described above, in the method of cutting an electric fuse according to the embodiment 3, a predetermined electric current pulse is repeatedly given to the electric fuse 10, whereby pinch effect is repeatedly generated. As a result, the electric fuse 10 is cut at its cut portion 1000, as illustrated in FIG. 46.
  • According to the method of cutting an electric fuse according to the embodiment 3 also, the time required until the main wiring 1 is liquefied and the time when an electric current (pulses) is caused to flow into the main wiring 1 are very short; therefore, thermal damage generated around the electric fuse 10 is restrained.
  • In the method of cutting an electric fuse according to the embodiment 3, for example, the temperature of the electric fuse 10 is kept at 1200° C. only for 5 μs. In this case, moieties where the temperature becomes 600° C. or higher in the insulator layers 2, 4 and 5 arranged around the electric fuse 10 are moieties wherein the distance from the electric fuse 10 is less than 0.4 μm. Accordingly, an adverse effect based on heat generated from the electric fuse 10 is hardly produced onto any element arranged around the electric fuse 10.
  • A theory and experimental results have demonstrated that when the electric fuse 10 is cut by pinch effect, a central portion of the fuse 10, which has equal distances from both ends of the fuse 10, is cut.
  • It should be understood that all the embodiments disclosed herein are illustrative and are not restrictive. The scope of the present invention is specified not by the above-mentioned description but by the appended claims. All modifications which have meanings equivalent to the claims or which are within the scope recited in the claims are intended to be included in the invention.

Claims (40)

  1. 1. A semiconductor device, comprising:
    a first insulator layer;
    a first trench formed in the first insulator layer;
    a second trench formed in the first insulator layer;
    an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench, and a first copper metal formed on the first barrier metal and filling in the first trench, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse;
    a first wiring which includes a second barrier metal formed on a bottom surface of the second trench and a side wall of the second trench, and a second copper metal formed on the second barrier metal and filling in the second trench;
    a second insulator layer formed on the first insulator layer, the electric fuse, and the first copper wiring;
    a third insulator layer formed on the second insulator layer;
    a third trench formed in the third insulator layer;
    a second wiring which is formed in the third trench;
    a fourth insulator layer formed over the third insulator layer;
    a fourth trench formed in the fourth insulator layer; and
    a third wiring which is formed in the fourth trench;
    wherein a first thickness of the first wiring is thinner than a third thickness of the third wiring, and a second thickness of the second wiring is thinner than the third thickness of the third wiring; and
    wherein a dielectric relative constant of the first and third insulator layer is 3 or less.
  2. 2. The semiconductor device according to claim 1, further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
    wherein gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.
  3. 3. The semiconductor device according to claim 2, further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse turning into a predetermined value or more.
  4. 4. The semiconductor device according to claim 1, wherein the first thickness of the first wiring is thinner than the second thickness of the second wiring.
  5. 5. The semiconductor device according to claim 1, wherein a linear expansion coefficient of each of the first and second copper metals is higher than that of the first and third insulator layers, and
    wherein each of the first, second copper metals has lower melting point than melting point of each of the first and third insulator layers.
  6. 6. The semiconductor device according to claim 1, wherein the second insulator layer comprises two insulator films.
  7. 7. The semiconductor device according to claim 1, wherein the second insulator layer comprises a SiCN film, a SiN film, or a bi-layered structure film having a SiCN film and a SiCO film.
  8. 8. The semiconductor device according to claim 6, wherein the second insulator layer includes a first compound film of silicon with nitride and a second compound film of silicon with oxide.
  9. 9. The semiconductor device according to claim 8, wherein the first compound film is comprised of SiCN, and the second compound film is comprised of SiCO.
  10. 10. The semiconductor device according to claim 1, wherein the first barrier metal comprises:
    a first metal film which contacts with the first insulator layer at the side wall of the first trench, and is formed along the side wall of the first trench; and
    a second metal film which contacts with the first metal film at the side wall of the first trench, the first insulator layer at the bottom surface of the first trench, and the first copper metal, and is formed along the side wall and the bottom surface of the first trench.
  11. 11. The semiconductor device according to claim 1, wherein the first barrier metal has a higher melting point than a melting point of each of the first and second copper metals.
  12. 12. The semiconductor device according to claim 11, wherein a linear expansion coefficient of the first barrier metal is smaller than that of each of the first and second copper metals and is larger than that of the first and third insulator layers.
  13. 13. The semiconductor device according to claim 11, wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers.
  14. 14. A semiconductor device, comprising:
    a semiconductor substrate;
    a gate electrode formed over the semiconductor substrate;
    an interlayer dielectric covering the gate electrode;
    a fine layer formed over the interlayer dielectric;
    a semiglobal layer formed over the fine layer;
    a global layer formed over the semiglobal layer; and
    an electric fuse formed in the fine layer, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse, the electric fuse including a copper metal,
    wherein the electric fuse is formed in a trench of a first insulator layer of the fine layer, a second insulator layer is formed on the electric fuse and the first insulator layer, and a third insulator layer is formed on the third insulator layer,
    wherein a dielectric relative constant of the first and third insulator layer is 3 or less,
    wherein a thickness of the semiglobal layer is thicker than that of the fine layer, and
    wherein a thickness of the global layer is thicker than that of the semiglobal layer.
  15. 15. The semiconductor device according to claim 14, wherein the fine layers are plural,
    wherein the copper metal has a larger linear expansion coefficient than that of the first insulator layer, and further has a lower melting point than that of the first insulator layer.
  16. 16. A semiconductor device, comprising:
    a first insulator layer;
    a first trench formed in the first insulator layer;
    a second trench formed in the first insulator layer;
    an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench and a first copper metal formed on the first barrier metal and filling in the first trench, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse;
    a first wiring which includes a second barrier metal formed on a bottom surface of the second trench and a side wall of the second trench and a second copper metal formed on the second barrier metal and filling in the second trench;
    a first layer which includes a second insulator layer formed on the first insulator layer, a third insulator layer formed on the second insulator layer, and a second wiring formed in the third insulator layer; and
    a second layer which includes a fourth insulator layer formed over the third insulator layer and a third wiring formed over the third insulator layer;
    wherein a first thickness of the first insulator layer is thinner than a third thickness of the second layer, and a second thickness of the first layer is thinner than the third thickness of the second layer; and
    wherein a dielectric relative constant of the first and third insulator layer is 3 or less.
  17. 17. The semiconductor device according to claim 16, further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
    wherein gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.
  18. 18. The semiconductor device according to claim 17, further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse turning into a predetermined value or more.
  19. 19. The semiconductor device according to claim 16, wherein the first thickness of the first insulator layer is thinner than the second thickness of the first layer.
  20. 20. The semiconductor device according to claim 16, wherein a linear expansion coefficient of each of the first and second copper metals is higher than that of the first and third insulator layers, and
    wherein each of the first, second copper metals has a lower melting point than a melting point of each of the first and third insulator layers.
  21. 21. The semiconductor device according to claim 16, wherein the second insulator layer comprises two insulator films.
  22. 22. The semiconductor device according to claim 16, wherein the second insulator layer comprises a SiCN film, a SiN film, or a bi-layered structure film having a SiCN film and a SiCO film.
  23. 23. The semiconductor device according to claim 21, wherein the second insulator layer includes a first compound film of silicon with nitride and a second compound film of silicon with oxide.
  24. 24. The semiconductor device according to claim 23, wherein the first compound film is comprised of SiCN, and the second compound film is comprised of SiCO.
  25. 25. The semiconductor device according to claim 16, wherein the first barrier metal comprises:
    a first metal film which contacts with the first insulator layer at the side wall of the first trench, and is formed along the side wall of the first trench; and
    a second metal film which contacts with the first metal film at the side wall of the first trench, the first insulator layer at the bottom surface of the first trench, and the first copper metal, and is formed along the side wall and the bottom surface of the first trench.
  26. 26. The semiconductor device according to claim 16, wherein the first barrier metal has a higher melting point than a melting point of each of the first and second copper metals.
  27. 27. The semiconductor device according to claim 26, wherein a linear expansion coefficient of the first barrier metal is smaller than that of each of the first and second copper metals and is larger than that of the first and third insulator layers.
  28. 28. The semiconductor device according to claim 26, wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers.
  29. 29. A semiconductor device, comprising:
    a semiconductor substrate;
    a gate electrode formed over the semiconductor substrate;
    a first insulator layer formed over the gate electrode and the semiconductor substrate;
    a first trench formed in the first insulator layer;
    an electric fuse which includes a first barrier metal formed on a bottom surface of the first trench and a side wall of the first trench, and a copper metal formed on the first barrier metal and filling in the first trench, wherein a resistance value of the electric fuse can be controlled by applying electrical current to the electric fuse;
    a second insulator layer formed on the first insulator layer and the electric fuse; and
    a third insulator layer formed on the second insulator layer,
    wherein a dielectric relative constant of the first and third insulator layer is 3 or less.
  30. 30. The semiconductor device according to claim 29, further comprising: a first transistor which is connected to the electric fuse in series between a first power supply node and a second power supply node whose power supply voltage is lower than that of the first power supply node,
    wherein gate voltage of the first transistor is controlled so as to control applying the electrical current to the electric fuse, thereby to control the resistance value of the electric fuse.
  31. 31. The semiconductor device according to claim 30, further comprising: a decision circuit which receives a signal from a connect node between the first transistor and the electric fuse, and detects whether or not the resistance value of the electric fuse turning into a predetermined value or more.
  32. 32. The semiconductor device according to claim 29, wherein a linear expansion coefficient of the copper metal is higher than that of the first and third insulator layers, and
    wherein the copper metal has a lower melting point than a melting point of each of the first and third insulator layers.
  33. 33. The semiconductor device according to claim 29, wherein the second insulator layer includes two insulator films.
  34. 34. The semiconductor device according to claim 29, wherein the second insulator layer comprises a SiCN film, a SiN film, or a bi-layered structure film having a SiCN film and a SiCO film.
  35. 35. The semiconductor device according to claim 33, wherein the second insulator layer includes a first compound film of silicon with nitride and a second compound film of silicon with oxide.
  36. 36. The semiconductor device according to claim 35, wherein the first compound film is comprised of SiCN, and the second compound film is comprised of SiCO.
  37. 37. The semiconductor device according to claim 29, wherein the first barrier metal comprises:
    a first metal film which contacts with the first insulator layer at the side wall of the first trench, and is formed along the side wall of the first trench; and
    a second metal film which contacts with the first metal film at the side wall of the first trench, the first insulator layer at the bottom surface of the first trench, and the copper metal, and is formed along the side wall and the bottom surface of the first trench.
  38. 38. The semiconductor device according to claim 29, wherein the first barrier metal has a higher melting point than a melting point of the copper metal.
  39. 39. The semiconductor device according to claim 38, wherein a linear expansion coefficient of the first barrier metal is smaller than that of the copper metal and is larger than that of the first and third insulator layers.
  40. 40. The semiconductor device according to claim 38, wherein the first barrier metal has a higher melting point than a melting point of each of the first, second and third insulator layers.
US12760648 2006-03-07 2010-04-15 Semiconductor device and a method of increasing a resistance value of an electric fuse Abandoned US20100264514A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2006-61512 2006-03-07
JP2006061512 2006-03-07
JP2006256226A JP4959267B2 (en) 2006-03-07 2006-09-21 Method of increasing the semiconductor device and the resistance value of the electric fuse
JP2006-256226 2006-09-21
US11683053 US7745905B2 (en) 2006-03-07 2007-03-07 Semiconductor device and a method of increasing a resistance value of an electric fuse
US12760648 US20100264514A1 (en) 2006-03-07 2010-04-15 Semiconductor device and a method of increasing a resistance value of an electric fuse

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US12760648 US20100264514A1 (en) 2006-03-07 2010-04-15 Semiconductor device and a method of increasing a resistance value of an electric fuse
US14033036 US20140021559A1 (en) 2006-03-07 2013-09-20 Semiconductor device and a method of increasing a resistance value of an electric fuse
US14590294 US9508641B2 (en) 2006-03-07 2015-01-06 Semiconductor device and a method increasing a resistance value of an electric fuse
US15298484 US9893013B2 (en) 2006-03-07 2016-10-20 Semiconductor device and a method of increasing a resistance value of an electric fuse
US15869707 US20180138121A1 (en) 2006-03-07 2018-01-12 Semiconductor device and a method of increasing a resistance value of an electric fuse

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11683053 Continuation US7745905B2 (en) 2006-03-07 2007-03-07 Semiconductor device and a method of increasing a resistance value of an electric fuse

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14033036 Continuation US20140021559A1 (en) 2006-03-07 2013-09-20 Semiconductor device and a method of increasing a resistance value of an electric fuse

Publications (1)

Publication Number Publication Date
US20100264514A1 true true US20100264514A1 (en) 2010-10-21

Family

ID=38478095

Family Applications (6)

Application Number Title Priority Date Filing Date
US11683053 Active 2028-08-18 US7745905B2 (en) 2006-03-07 2007-03-07 Semiconductor device and a method of increasing a resistance value of an electric fuse
US12760648 Abandoned US20100264514A1 (en) 2006-03-07 2010-04-15 Semiconductor device and a method of increasing a resistance value of an electric fuse
US14033036 Abandoned US20140021559A1 (en) 2006-03-07 2013-09-20 Semiconductor device and a method of increasing a resistance value of an electric fuse
US14590294 Active US9508641B2 (en) 2006-03-07 2015-01-06 Semiconductor device and a method increasing a resistance value of an electric fuse
US15298484 Active US9893013B2 (en) 2006-03-07 2016-10-20 Semiconductor device and a method of increasing a resistance value of an electric fuse
US15869707 Pending US20180138121A1 (en) 2006-03-07 2018-01-12 Semiconductor device and a method of increasing a resistance value of an electric fuse

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11683053 Active 2028-08-18 US7745905B2 (en) 2006-03-07 2007-03-07 Semiconductor device and a method of increasing a resistance value of an electric fuse

Family Applications After (4)

Application Number Title Priority Date Filing Date
US14033036 Abandoned US20140021559A1 (en) 2006-03-07 2013-09-20 Semiconductor device and a method of increasing a resistance value of an electric fuse
US14590294 Active US9508641B2 (en) 2006-03-07 2015-01-06 Semiconductor device and a method increasing a resistance value of an electric fuse
US15298484 Active US9893013B2 (en) 2006-03-07 2016-10-20 Semiconductor device and a method of increasing a resistance value of an electric fuse
US15869707 Pending US20180138121A1 (en) 2006-03-07 2018-01-12 Semiconductor device and a method of increasing a resistance value of an electric fuse

Country Status (4)

Country Link
US (6) US7745905B2 (en)
JP (1) JP4959267B2 (en)
KR (1) KR101354389B1 (en)
CN (2) CN102157490A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258256A1 (en) * 2004-02-27 2008-10-23 Nobuaki Otsuka Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same
US20100252908A1 (en) * 2009-04-03 2010-10-07 Freescale Semiconductor, Inc. Electrically alterable circuit for use in an integrated circuit device
US9064871B2 (en) 2012-07-18 2015-06-23 International Business Machines Corporation Vertical electronic fuse

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4861051B2 (en) * 2006-05-09 2012-01-25 ルネサスエレクトロニクス株式会社 The semiconductor device and the electric fuse cutting method
US7491585B2 (en) 2006-10-19 2009-02-17 International Business Machines Corporation Electrical fuse and method of making
US8124971B2 (en) * 2007-03-30 2012-02-28 Sandisk 3D Llc Implementation of diffusion barrier in 3D memory
US7629253B2 (en) * 2007-03-30 2009-12-08 Sandisk 3D Llc Method for implementing diffusion barrier in 3D memory
JP5245324B2 (en) * 2007-08-20 2013-07-24 日本電気株式会社 Semiconductor device mounted with a switch element
KR100966975B1 (en) 2007-12-24 2010-06-30 주식회사 하이닉스반도체 A fuse of semiconductor device and method for forming the same
US7956466B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
US8772156B2 (en) * 2008-05-09 2014-07-08 International Business Machines Corporation Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
US7737528B2 (en) * 2008-06-03 2010-06-15 International Business Machines Corporation Structure and method of forming electrically blown metal fuses for integrated circuits
JP2010016062A (en) * 2008-07-01 2010-01-21 Toshiba Corp Semiconductor device
KR101037539B1 (en) * 2008-10-29 2011-05-26 주식회사 하이닉스반도체 Semiconductor device and method for forming semiconductor device
DE102008054073A1 (en) * 2008-10-31 2010-05-12 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device with electronic fuses with increased programming efficiency
KR101095770B1 (en) * 2009-03-09 2011-12-21 주식회사 하이닉스반도체 Semiconductor device and method for forming the same
JP5510862B2 (en) * 2009-03-10 2014-06-04 ルネサスエレクトロニクス株式会社 Semiconductor device
EP2433303A4 (en) * 2009-05-22 2014-09-17 Ibm Structure and method of forming electrically blown metal fuses for integrated circuits
JP5561668B2 (en) * 2009-11-16 2014-07-30 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5537137B2 (en) * 2009-12-10 2014-07-02 ルネサスエレクトロニクス株式会社 The method of manufacturing a semiconductor device and a semiconductor device
JP5581520B2 (en) * 2010-04-08 2014-09-03 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8299567B2 (en) * 2010-11-23 2012-10-30 International Business Machines Corporation Structure of metal e-fuse
FR2972845B1 (en) * 2011-03-17 2016-05-06 Mersen France Sb Sas Method of manufacturing a fuse implementation method of such process, and fuse with means for control of the electromagnetic environment
US20130043556A1 (en) 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
KR20160068212A (en) * 2014-12-05 2016-06-15 삼성전자주식회사 e-Fuse Device and Method for fabricating the same
JP2017004943A (en) * 2015-06-04 2017-01-05 デクセリアルズ株式会社 Fuse element, fuse device, protection device, shorting device, and switch device

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2373117A (en) * 1944-07-17 1945-04-10 Bundy Tubing Co Method of uniting metals
US3565602A (en) * 1968-05-21 1971-02-23 Kobe Steel Ltd Method of producing an alloy from high melting temperature reactive metals
US5757264A (en) * 1995-12-20 1998-05-26 International Business Machines Corporation Electrically adjustable resistor structure
US5969404A (en) * 1995-09-29 1999-10-19 Intel Corporation Silicide agglomeration device
US6162686A (en) * 1998-09-18 2000-12-19 Taiwan Semiconductor Manufacturing Company Method for forming a fuse in integrated circuit application
US6256239B1 (en) * 1998-10-27 2001-07-03 Fujitsu Limited Redundant decision circuit for semiconductor memory device
US6323535B1 (en) * 2000-06-16 2001-11-27 Infineon Technologies North America Corp. Electrical fuses employing reverse biasing to enhance programming
US6362514B1 (en) * 1999-01-19 2002-03-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20020074616A1 (en) * 2000-12-20 2002-06-20 Vincent Chen System and method for one-time programmed memory through direct-tunneling oxide breakdown
US6433404B1 (en) * 2000-02-07 2002-08-13 Infineon Technologies Ag Electrical fuses for semiconductor devices
US6492734B2 (en) * 2001-04-13 2002-12-10 Fujitsu Limited Semiconductor device including damascene wiring and a manufacturing method thereof
US20020185974A1 (en) * 2000-03-08 2002-12-12 Kuniaki Nakano Electric discharge lamp
US20040053487A1 (en) * 2002-09-17 2004-03-18 Taiwan Semiconductor Manufacturing Company Metal fuse for semiconductor devices
US6727590B2 (en) * 2001-11-01 2004-04-27 Renesas Technology Corp. Semiconductor device with internal bonding pad
US20040085405A1 (en) * 2002-10-30 2004-05-06 Samsung Electronics Co., Ltd. Ink-jet printhead
US20040224444A1 (en) * 2003-01-09 2004-11-11 Katsuhiro Hisaka Fuse layout and method of trimming
US6822310B2 (en) * 2002-07-10 2004-11-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US20050179062A1 (en) * 2004-02-12 2005-08-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20060104006A1 (en) * 2004-11-17 2006-05-18 Matsushita Electric Industrial Co., Ltd. Film capacitor and method of manufacturing the same
US7321171B2 (en) * 2000-05-08 2008-01-22 Renesas Technology Corp. Semiconductor integrated circuit device
US7619264B2 (en) * 2005-09-05 2009-11-17 Nec Electronics Corporation Semiconductor device
US20100117190A1 (en) * 2008-11-13 2010-05-13 Harry Chuang Fuse structure for intergrated circuit devices
US7759768B2 (en) * 2002-04-29 2010-07-20 Infineon Technologies Ag Integrated circuit with intergrated capacitor and methods for making same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63160242A (en) * 1986-12-23 1988-07-04 Nec Corp Semiconductor device
JPS63260149A (en) * 1987-04-17 1988-10-27 Nec Corp Semiconductor device
DE4110285A1 (en) * 1991-03-28 1992-10-01 Schwaebische Huettenwerke Gmbh Filter or katalysatorkoerper
DE69432016D1 (en) * 1994-09-13 2003-02-20 St Microelectronics Srl A method for manufacturing integrated circuits and semiconductor wafer generated
JPH0917872A (en) * 1995-06-27 1997-01-17 Fujitsu Ltd Semiconductor device
JP3657788B2 (en) * 1998-10-14 2005-06-08 富士通株式会社 Semiconductor device and manufacturing method thereof
CN1167128C (en) 1999-04-14 2004-09-15 国际商业机器公司 Electrofusion fuse and its array and arrangement
US6288436B1 (en) 1999-07-27 2001-09-11 International Business Machines Corporation Mixed fuse technologies
US6495426B1 (en) 2001-08-09 2002-12-17 Lsi Logic Corporation Method for simultaneous formation of integrated capacitor and fuse
JP3588612B2 (en) * 2002-02-19 2004-11-17 株式会社東芝 Semiconductor device
US6876565B2 (en) * 2002-09-30 2005-04-05 Kabushiki Kaisha Toshiba Semiconductor memory device
JP3778174B2 (en) * 2003-04-14 2006-05-24 ソニー株式会社 Semiconductor device and manufacturing method thereof
JP2005039220A (en) 2003-06-26 2005-02-10 Nec Electronics Corp Semiconductor device
JP4795631B2 (en) 2003-08-07 2011-10-19 ルネサスエレクトロニクス株式会社 Semiconductor device
EP1517136A3 (en) 2003-09-10 2005-03-30 Tokyo Electron Limited Apparatus and method for measuring or applying thermal expansion/shrinkage rate
JP4230334B2 (en) 2003-10-31 2009-02-25 富士通マイクロエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP3808866B2 (en) 2003-12-05 2006-08-16 株式会社東芝 Semiconductor device
JP4619705B2 (en) * 2004-01-15 2011-01-26 株式会社東芝 Semiconductor device
DE102004014925B4 (en) * 2004-03-26 2016-12-29 Infineon Technologies Ag Electronic circuitry
KR100585159B1 (en) * 2004-09-13 2006-05-30 삼성전자주식회사 Method of forming a fuse in semiconductor device
KR100695872B1 (en) * 2005-06-22 2007-03-19 삼성전자주식회사 Fuse of semiconductor device and Method of forming the same
US7254078B1 (en) * 2006-02-22 2007-08-07 International Business Machines Corporation System and method for increasing reliability of electrical fuse programming

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2373117A (en) * 1944-07-17 1945-04-10 Bundy Tubing Co Method of uniting metals
US3565602A (en) * 1968-05-21 1971-02-23 Kobe Steel Ltd Method of producing an alloy from high melting temperature reactive metals
US6258700B1 (en) * 1995-09-29 2001-07-10 Intel Corporation Silicide agglomeration fuse device
US5969404A (en) * 1995-09-29 1999-10-19 Intel Corporation Silicide agglomeration device
US5757264A (en) * 1995-12-20 1998-05-26 International Business Machines Corporation Electrically adjustable resistor structure
US6162686A (en) * 1998-09-18 2000-12-19 Taiwan Semiconductor Manufacturing Company Method for forming a fuse in integrated circuit application
US6256239B1 (en) * 1998-10-27 2001-07-03 Fujitsu Limited Redundant decision circuit for semiconductor memory device
US6362514B1 (en) * 1999-01-19 2002-03-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6433404B1 (en) * 2000-02-07 2002-08-13 Infineon Technologies Ag Electrical fuses for semiconductor devices
US20020185974A1 (en) * 2000-03-08 2002-12-12 Kuniaki Nakano Electric discharge lamp
US7321171B2 (en) * 2000-05-08 2008-01-22 Renesas Technology Corp. Semiconductor integrated circuit device
US6323535B1 (en) * 2000-06-16 2001-11-27 Infineon Technologies North America Corp. Electrical fuses employing reverse biasing to enhance programming
US20020074616A1 (en) * 2000-12-20 2002-06-20 Vincent Chen System and method for one-time programmed memory through direct-tunneling oxide breakdown
US6492734B2 (en) * 2001-04-13 2002-12-10 Fujitsu Limited Semiconductor device including damascene wiring and a manufacturing method thereof
US6727590B2 (en) * 2001-11-01 2004-04-27 Renesas Technology Corp. Semiconductor device with internal bonding pad
US7759768B2 (en) * 2002-04-29 2010-07-20 Infineon Technologies Ag Integrated circuit with intergrated capacitor and methods for making same
US6822310B2 (en) * 2002-07-10 2004-11-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit
US20040053487A1 (en) * 2002-09-17 2004-03-18 Taiwan Semiconductor Manufacturing Company Metal fuse for semiconductor devices
US20040085405A1 (en) * 2002-10-30 2004-05-06 Samsung Electronics Co., Ltd. Ink-jet printhead
US20040224444A1 (en) * 2003-01-09 2004-11-11 Katsuhiro Hisaka Fuse layout and method of trimming
US20050179062A1 (en) * 2004-02-12 2005-08-18 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20060104006A1 (en) * 2004-11-17 2006-05-18 Matsushita Electric Industrial Co., Ltd. Film capacitor and method of manufacturing the same
US7619264B2 (en) * 2005-09-05 2009-11-17 Nec Electronics Corporation Semiconductor device
US20100117190A1 (en) * 2008-11-13 2010-05-13 Harry Chuang Fuse structure for intergrated circuit devices

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Burns et al. High-Temperature Chemicstry ofthe Conversion of Silixanes to Silicon Carbide. Chem. Materi. 1992, 4, pp. 1313-1323 *
Kim et al. Characterization of low-diekectric constant SiOC thin films deposited by PECVD for interlayer dielectrics of multilevel interconnection. Surface and Coating Technology 171 (2003), pp. 39-45 *
Rouxel et a. High Temperature Behavior of a Gel-Derived SiOC Glass: Elasticity and Viscosity. Journal of Sol-Gel Science and Technology 14, (1999), pp. 87-94 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258256A1 (en) * 2004-02-27 2008-10-23 Nobuaki Otsuka Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same
US8105886B2 (en) * 2004-02-27 2012-01-31 Kabushiki Kaisha Toshiba Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same
US20100252908A1 (en) * 2009-04-03 2010-10-07 Freescale Semiconductor, Inc. Electrically alterable circuit for use in an integrated circuit device
US8178942B2 (en) * 2009-04-03 2012-05-15 Freescale Semiconductor, Inc. Electrically alterable circuit for use in an integrated circuit device
US9064871B2 (en) 2012-07-18 2015-06-23 International Business Machines Corporation Vertical electronic fuse

Also Published As

Publication number Publication date Type
US20140021559A1 (en) 2014-01-23 application
CN101150113B (en) 2011-04-13 grant
KR101354389B1 (en) 2014-01-22 grant
CN101150113A (en) 2008-03-26 application
US9893013B2 (en) 2018-02-13 grant
JP4959267B2 (en) 2012-06-20 grant
US7745905B2 (en) 2010-06-29 grant
US9508641B2 (en) 2016-11-29 grant
US20180138121A1 (en) 2018-05-17 application
JP2007273940A (en) 2007-10-18 application
KR20070092161A (en) 2007-09-12 application
CN102157490A (en) 2011-08-17 application
US20150303144A1 (en) 2015-10-22 application
US20170040261A1 (en) 2017-02-09 application
US20070210414A1 (en) 2007-09-13 application

Similar Documents

Publication Publication Date Title
US6265778B1 (en) Semiconductor device with a multi-level interconnection structure
US4976200A (en) Tungsten bridge for the low energy ignition of explosive and energetic materials
US5557136A (en) Programmable interconnect structures and programmable integrated circuits
US6624499B2 (en) System for programming fuse structure by electromigration of silicide enhanced by creating temperature gradient
US5324681A (en) Method of making a 3-dimensional programmable antifuse for integrated circuits
US7394089B2 (en) Heat-shielded low power PCM-based reprogrammable EFUSE device
US6243283B1 (en) Impedance control using fuses
US5880512A (en) Programmable interconnect structures and programmable integrated circuits
US20080186788A1 (en) Electrical fuse and associated methods
US5866938A (en) Semiconductor device equipped with antifuse elements and a method for manufacturing an FPGA
US6242789B1 (en) Vertical fuse and method of fabrication
US7067902B2 (en) Building metal pillars in a chip for structure support
US20050023692A1 (en) Semiconductor apparatus including a radiator for diffusing the heat generated therein
US6677220B2 (en) Antifuse structure and method of making
US5625219A (en) Programmable semiconductor device using anti-fuse elements with floating electrode
US20080093703A1 (en) Electrical fuse and method of making
US5191405A (en) Three-dimensional stacked lsi
US20070210890A1 (en) Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US6252292B1 (en) Vertical electrical cavity-fuse
US6707156B2 (en) Semiconductor device with multilevel wiring layers
US8836141B2 (en) Conductor layout technique to reduce stress-induced void formations
US20060278895A1 (en) Reprogrammable fuse structure and method
US6498385B1 (en) Post-fuse blow corrosion prevention structure for copper fuses
US20070235708A1 (en) Programmable via structure for three dimensional integration technology
US20110031581A1 (en) Integrated circuit (ic) having tsvs with dielectric crack suppression structures