US20100200985A1 - Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process - Google Patents

Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process Download PDF

Info

Publication number
US20100200985A1
US20100200985A1 US12/763,378 US76337810A US2010200985A1 US 20100200985 A1 US20100200985 A1 US 20100200985A1 US 76337810 A US76337810 A US 76337810A US 2010200985 A1 US2010200985 A1 US 2010200985A1
Authority
US
United States
Prior art keywords
layer
formed over
adhesive layer
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/763,378
Other versions
US20120211881A9 (en
Inventor
Yaojian Lin
Haijing Cao
Qing Zhang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to US12/763,378 priority Critical patent/US20120211881A9/en
Publication of US20100200985A1 publication Critical patent/US20100200985A1/en
Publication of US20120211881A9 publication Critical patent/US20120211881A9/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05169—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Definitions

  • the present invention relates in general to semiconductor devices and, more particularly, to formation of solder bump structures on semiconductor devices.
  • Semiconductor devices are found in many products used in modern society. Semiconductors find applications in consumer items such as entertainment, communications, networks, computers, and household items markets. In the industrial or commercial market, semiconductors are found in military, aviation, automotive, industrial controllers, and office equipment.
  • Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer.
  • the finished wafer has an active side containing the transistors and other active and passive components.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
  • Flip chip packages or wafer level packages are ideally suited for ICs demanding high speed, high density, and greater pin count.
  • Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB).
  • PCB printed circuit board
  • the electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls.
  • the solder bumps are formed by a reflow process applied to solder material deposited on contact pads, which are disposed on the semiconductor substrate.
  • the solder bumps are then soldered to the carrier substrate.
  • the flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
  • the reliability and integrity of the interconnect structure is important to testing, manufacturing yield, and longevity of the product while in service.
  • a problem of cracking has been detected in the passivation layer surrounding the solder bump after solder reflow.
  • the cracking has been attributed to degradation of the passivation layer caused by the chemical processes used during formation of the solder bumps.
  • the cracking problem is especially noted during formation and removal of dry film used to create the solder bumps.
  • the present invention is a semiconductor device comprising a substrate having a plurality of semiconductor devices formed on a surface of the substrate.
  • a contact pad is formed over the substrate in electrical contact with the semiconductor devices.
  • An RDL is formed over the substrate in electrical contact with the contact pad.
  • a passivation layer is formed over the substrate and RDL. A portion of the passivation layer is removed to expose the RDL.
  • An adhesive layer is formed over the passivation layer and the exposed RDL.
  • a barrier layer is formed over a first portion of the adhesive layer which is over the exposed RDL. The barrier layer is not formed over a second portion of the adhesive layer.
  • a wetting layer is formed over the barrier layer which is over the first portion of the adhesive layer. The wetting layer is not formed over the second portion of the adhesive layer.
  • a bump is formed over the wetting layer and barrier layer.
  • the present invention is a semiconductor device comprising a substrate and passivation layer formed over the substrate.
  • An adhesive layer is formed over the passivation layer.
  • a barrier layer is formed over a first portion of the adhesive layer. The barrier layer not being formed over a second portion of the adhesive layer.
  • a wetting layer is formed over the barrier layer over the first portion of the adhesive layer. The wetting layer not being formed over the second portion of the adhesive layer.
  • An electrical interconnect is formed over the wetting layer and barrier layer.
  • the present invention is a semiconductor device comprising substrate and passivation layer formed over the substrate.
  • An adhesive layer is formed over the passivation layer.
  • a wetting layer is formed over a first portion of the adhesive layer. The wetting layer not being formed over a second portion of the adhesive layer.
  • An electrical interconnect is formed over the wetting layer.
  • the present invention is a semiconductor device comprising a substrate and passivation layer formed over the substrate.
  • An adhesive layer is formed over the passivation layer.
  • a barrier layer is formed over a first portion of the adhesive layer. The barrier layer not being formed over a second portion of the adhesive layer.
  • An electrical interconnect is formed over the barrier layer.
  • FIG. 1 is a flip chip semiconductor device with solder bumps providing electrical interconnect between an active area of the die and a chip carrier substrate;
  • FIG. 2 illustrates formation of an adhesive layer over the second passivation layer
  • FIG. 3 illustrates formation of a barrier layer and wetting layer over the adhesive layer
  • FIG. 4 illustrates patterning the UBM structure prior to etching portions of the barrier layer and wetting layer
  • FIG. 5 illustrates removing portions of the barrier layer and wetting layer in a region outside the UBM structure while leaving the adhesive layer intact over the passivation layer;
  • FIG. 6 illustrates formation of dry film layer over the adhesive layer, which protects the passivation layer and the deposition of solder material
  • FIG. 7 illustrates reflow of the solder material to form solder bumps and removal of dry film layer
  • FIG. 8 illustrates removal of the adhesive layer from the region outside the UBM structure.
  • Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer.
  • the finished wafer has an active side containing the transistors and other active and passive components.
  • Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
  • a semiconductor wafer generally includes an active front side surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon.
  • the active front side surface contains a plurality of semiconductor die.
  • the active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment.
  • semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Patterning involves use of photolithography to mask areas of the surface and etch away undesired material to form specific structures.
  • the doping process injects concentrations of dopant material by thermal diffusion or ion implantation.
  • the active surface is substantially planar and uniform with electrical interconnects, such as bond pads.
  • Flip chip semiconductor packages and wafer level packages are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count.
  • Flip chip style semiconductor device 10 involves mounting an active area 12 of die 14 facedown toward a chip carrier substrate or printed circuit board (PCB) 16 , as shown in FIG. 1 .
  • Active area 12 contains active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die.
  • the electrical and mechanical interconnect is achieved through a solder bump structure 20 comprising a large number of individual conductive solder bumps or balls 22 .
  • the solder bumps are formed on bump pads 24 , which are disposed on active area 12 .
  • the bump pads 24 connect to the active circuits by conduction tracks in active area 12 .
  • the solder bumps 22 are electrically and mechanically connected to contact pads 26 on carrier substrate 16 by a solder reflow process.
  • the flip chip semiconductor device provides a short electrical conduction path from the active devices on die 14 to conduction tracks on carrier substrate 16 in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
  • FIG. 2 illustrates a cross-sectional view of the formation of a support structure for a solder bump. Note that for FIGS. 2-8 the semiconductor device is oriented with its active surface facing up.
  • metal contact pad 32 is formed on silicon substrate 34 .
  • Contact pad 32 is made of aluminum (Al), copper (Cu), or aluminum/copper alloys.
  • Contact pad 32 is electrically connected to active and passive devices through conduction tracks or layers formed on substrate 34 .
  • a solder bump will later be formed to connect through an RDL to the metal contact pad.
  • a first passivation layer 36 is formed over substrate 34 with an opening to expose metal contact pad 32 . The opening is realized by removing a portion of passivation layer 36 through a photoresist mask defined etching process.
  • the first passivation layer 36 can be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material.
  • a first redistribution layer (RDL) 40 is formed over first passivation layer 36 , as shown in FIG. 2 .
  • RDL 40 provides electrical contact between pad 32 and solder bump area 48 which is provided for the first solder bump.
  • a second RDL 42 is also is formed over first passivation layer 36 .
  • RDL 42 provides electrical contact between other conduction tracks on substrate 34 and solder bump area 50 which is provided for the second solder bump.
  • the first and second RDLs can be made with Aluminum (Al), Aluminum Copper alloy (AlCu), Cu, or Cu alloy.
  • RDLs 40 and 42 operate as an intermediate conduction layer to route electrical signals to various areas of the die, including active and passive circuits, and provides various electrical interconnect options during package integration.
  • a second passivation layer 44 is formed over first passivation layer 36 and RDLs 40 and 42 .
  • the second passivation layer is thicker than RDLs 40 and 42 .
  • passivation layer 44 is about 5-15 ⁇ m in thickness and RDL 40 is about 1-3 ⁇ m in thickness.
  • Passivation layer 44 can be made using similar material as described for passivation layer 36 .
  • passivation layers 36 and 44 are formed by repassivation. A portion of second passivation layer 44 is removed by a photoresist mask defined etching process for the first and second solder bumps in areas 48 and 50 or the second passivation layer is photosensitive and can be patterned directly.
  • Adhesive layer 46 is formed on passivation layer 44 and RDLs 40 and 42 .
  • adhesive layer 46 is about 200-2000 angstroms in thickness.
  • Adhesive layer 46 can be titanium (Ti), Al, titanium tungsten (TiW), and chromium (Cr).
  • Adhesive layer 46 is patterned to follow the contour of passivation layer 44 and RDLs 40 and 42 . Accordingly, the formation of adhesive layer 46 is depressed in solder bump areas 48 and 50 and covers substantially the entire surface of passivation layer 44 , particularly in and around areas 48 and 50 , as seen in FIG. 2 .
  • FIG. 3 illustrates a barrier layer 52 formed over adhesive layer 46 , and wetting layer 54 formed over barrier layer 52 .
  • Barrier layer 52 and wetting layer 54 in combination with adhesive layer 46 , forms an under bump metallization (UBM) in areas 48 and 50 for the first and second solder bumps.
  • UBM under bump metallization
  • the adhesion layer 46 bonds to barrier layer 52 .
  • Barrier layer 42 inhibits the diffusion of materials destructive to silicon such as Cu into the active area of the die.
  • Barrier layer 52 is optional depending on the materials used and the application.
  • Wetting layer 52 electrically connects to contact pad 32 via RDL 40 .
  • barrier layer 52 is about 3000-4000 angstroms in thickness
  • wetting layer 54 is about 5000-10000 angstroms in thickness.
  • Barrier layer 52 can be made of nickel (Ni), Ni-alloy, platinum (Pt), palladium (Pd), TiW, and chromium copper (CrCu).
  • Wetting layer 54 can be made with Cu, gold (Au), or Al. Barrier layer 52 is patterned to follow the contour of adhesive layer 46 . Likewise, wetting layer 54 is patterned to follow the contour of barrier layer 52 and acts as an intermediate conduction layer formed between the first solder bump and RDL 40 .
  • the patterning barrier layer 52 and wetting layer 54 and adhesive layer 46 as described above, define the solder bump areas 48 and 50 for forming solder bumps.
  • the barrier layer 52 and wetting layer 54 and adhesive layer 46 enhance reliability of the bump support structure.
  • a photoresist layer is deposited over wetting layer 54 .
  • the photoresist layer is patterned to provide photoresist layers 56 and 58 over solder bump areas 48 and 50 , respectively.
  • the portions of barrier layer 52 and wetting layer 54 which are not protected by photoresist layers 56 and 58 , are removed using a wet etch process. That is, only the portions of wetting layer 54 and barrier layer 52 in the region outside the UBM structure are etched away.
  • the adhesive layer 46 in the region outside the UMB structure remains in place at this stage of the process.
  • the portion of adhesive layer 46 in the region outside solder bump areas 48 and 50 protects passivation layer 44 from chemical degradation during formation of the solder bumps in later stages of the process.
  • Photoresist layers 56 and 58 are then removed, leaving the UBM structure comprising adhesive layer 46 , barrier layer 52 , and wetting layer 54 only in solder bump areas 48 and 50 .
  • a dry film layer 60 is deposited over adhesive layer 46 and the UBM structure comprising adhesive layer 46 , barrier layer 52 , and wetting layer 54 .
  • the dry film layer is patterned, and the portion of the dry film over the UBM structure is removed.
  • Solder material 62 is deposited over the UBM structure between the patterned dry film layer through a screen printing, or electrolytic plating or electroless plating process.
  • the solder material can be any metal or electrically conductive material, e.g., tin (Sn), lead (Pb), Ni, Au, silver (Ag), Cu, bismuthinite (Bi) and alloys thereof, or mixtures of other electrically conductive material.
  • the solder material is 63 percent weight of Sn and 37 percent weight of Pb.
  • solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 64 and 66 over semiconductor substrate 34 .
  • solder bumps 64 and 66 are about 70 ⁇ 180 ⁇ m in height. In some applications, solder bumps 64 and 66 are reflowed a second time to improve electrical contact to the UBM structure.
  • the adhesive layer 46 in the region outside the UBM structure remains in place.
  • the previous step of removing the portion of wetting layer 54 and barrier layer 52 in the region outside the UBM structure did not involve adhesive layer 46 .
  • the adhesive layer 46 in the region outside the UBM structure remains in place and protects passivation layer 44 against chemical degradation during the formation of the solder bumps, in particular during deposition and remove of dry film layer 60 .
  • the adhesive layer over the passivation layer reduces cracking of the passivation layer 44 without incurring additional manufacturing costs.
  • solder bump 64 electrically contacts metal contact pad 32 by way of RDL 40 .
  • solder bump 66 electrically contacts RDL 42 .
  • semiconductor device 10 can be made with a direct contact between the solder bump and the contact pad, i.e., without RDLs or other conductive routing structure.
  • contact pad 32 is formed directly under the UBM structure.
  • the adhesive layer in the region outside the UBM structure protects the passivation layer against chemical degradation during formation of the solder bumps, particularly during deposition and removal of dry film layer. Again, the adhesive layer over the passivation layer reduces cracking of the passivation layer without incurring additional manufacturing costs.

Abstract

A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.

Description

    CLAIM TO DOMESTIC PRIORITY
  • The present application is a division of U.S. patent application Ser. No. 11/934,009, filed Nov. 1, 2007, and claims priority to the foregoing parent application pursuant to 35 U.S.C. §120.
    • FIELD OF THE INVENTION
  • The present invention relates in general to semiconductor devices and, more particularly, to formation of solder bump structures on semiconductor devices.
    • BACKGROUND OF THE INVENTION
  • Semiconductor devices are found in many products used in modern society. Semiconductors find applications in consumer items such as entertainment, communications, networks, computers, and household items markets. In the industrial or commercial market, semiconductors are found in military, aviation, automotive, industrial controllers, and office equipment.
  • The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
  • One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level packages (WLP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads, which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
  • The reliability and integrity of the interconnect structure is important to testing, manufacturing yield, and longevity of the product while in service. In some devices, a problem of cracking has been detected in the passivation layer surrounding the solder bump after solder reflow. The cracking has been attributed to degradation of the passivation layer caused by the chemical processes used during formation of the solder bumps. The cracking problem is especially noted during formation and removal of dry film used to create the solder bumps.
  • A need exists for a solder bump structure with enhanced strength and reliability.
    • SUMMARY OF THE INVENTION
  • In one embodiment, the present invention is a semiconductor device comprising a substrate having a plurality of semiconductor devices formed on a surface of the substrate. A contact pad is formed over the substrate in electrical contact with the semiconductor devices. An RDL is formed over the substrate in electrical contact with the contact pad. A passivation layer is formed over the substrate and RDL. A portion of the passivation layer is removed to expose the RDL. An adhesive layer is formed over the passivation layer and the exposed RDL. A barrier layer is formed over a first portion of the adhesive layer which is over the exposed RDL. The barrier layer is not formed over a second portion of the adhesive layer. A wetting layer is formed over the barrier layer which is over the first portion of the adhesive layer. The wetting layer is not formed over the second portion of the adhesive layer. A bump is formed over the wetting layer and barrier layer.
  • In another embodiment, the present invention is a semiconductor device comprising a substrate and passivation layer formed over the substrate. An adhesive layer is formed over the passivation layer. A barrier layer is formed over a first portion of the adhesive layer. The barrier layer not being formed over a second portion of the adhesive layer. A wetting layer is formed over the barrier layer over the first portion of the adhesive layer. The wetting layer not being formed over the second portion of the adhesive layer. An electrical interconnect is formed over the wetting layer and barrier layer.
  • In another embodiment, the present invention is a semiconductor device comprising substrate and passivation layer formed over the substrate. An adhesive layer is formed over the passivation layer. A wetting layer is formed over a first portion of the adhesive layer. The wetting layer not being formed over a second portion of the adhesive layer. An electrical interconnect is formed over the wetting layer.
  • In another embodiment, the present invention is a semiconductor device comprising a substrate and passivation layer formed over the substrate. An adhesive layer is formed over the passivation layer. A barrier layer is formed over a first portion of the adhesive layer. The barrier layer not being formed over a second portion of the adhesive layer. An electrical interconnect is formed over the barrier layer.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flip chip semiconductor device with solder bumps providing electrical interconnect between an active area of the die and a chip carrier substrate;
  • FIG. 2 illustrates formation of an adhesive layer over the second passivation layer;
  • FIG. 3 illustrates formation of a barrier layer and wetting layer over the adhesive layer;
  • FIG. 4 illustrates patterning the UBM structure prior to etching portions of the barrier layer and wetting layer;
  • FIG. 5 illustrates removing portions of the barrier layer and wetting layer in a region outside the UBM structure while leaving the adhesive layer intact over the passivation layer;
  • FIG. 6 illustrates formation of dry film layer over the adhesive layer, which protects the passivation layer and the deposition of solder material;
  • FIG. 7 illustrates reflow of the solder material to form solder bumps and removal of dry film layer; and
  • FIG. 8 illustrates removal of the adhesive layer from the region outside the UBM structure.
    •  DETAILED DESCRIPTION OF THE DRAWINGS
  • The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
  • The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
  • A semiconductor wafer generally includes an active front side surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active front side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Patterning involves use of photolithography to mask areas of the surface and etch away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation. The active surface is substantially planar and uniform with electrical interconnects, such as bond pads.
  • Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. Flip chip style semiconductor device 10 involves mounting an active area 12 of die 14 facedown toward a chip carrier substrate or printed circuit board (PCB) 16, as shown in FIG. 1. Active area 12 contains active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die. The electrical and mechanical interconnect is achieved through a solder bump structure 20 comprising a large number of individual conductive solder bumps or balls 22. The solder bumps are formed on bump pads 24, which are disposed on active area 12. The bump pads 24 connect to the active circuits by conduction tracks in active area 12. The solder bumps 22 are electrically and mechanically connected to contact pads 26 on carrier substrate 16 by a solder reflow process. The flip chip semiconductor device provides a short electrical conduction path from the active devices on die 14 to conduction tracks on carrier substrate 16 in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
  • FIG. 2 illustrates a cross-sectional view of the formation of a support structure for a solder bump. Note that for FIGS. 2-8 the semiconductor device is oriented with its active surface facing up. In FIG. 2, metal contact pad 32 is formed on silicon substrate 34. Contact pad 32 is made of aluminum (Al), copper (Cu), or aluminum/copper alloys. Contact pad 32 is electrically connected to active and passive devices through conduction tracks or layers formed on substrate 34. A solder bump will later be formed to connect through an RDL to the metal contact pad. A first passivation layer 36 is formed over substrate 34 with an opening to expose metal contact pad 32. The opening is realized by removing a portion of passivation layer 36 through a photoresist mask defined etching process. The first passivation layer 36 can be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material.
  • A first redistribution layer (RDL) 40 is formed over first passivation layer 36, as shown in FIG. 2. RDL 40 provides electrical contact between pad 32 and solder bump area 48 which is provided for the first solder bump. A second RDL 42 is also is formed over first passivation layer 36. RDL 42 provides electrical contact between other conduction tracks on substrate 34 and solder bump area 50 which is provided for the second solder bump. The first and second RDLs can be made with Aluminum (Al), Aluminum Copper alloy (AlCu), Cu, or Cu alloy. RDLs 40 and 42 operate as an intermediate conduction layer to route electrical signals to various areas of the die, including active and passive circuits, and provides various electrical interconnect options during package integration.
  • A second passivation layer 44 is formed over first passivation layer 36 and RDLs 40 and 42. The second passivation layer is thicker than RDLs 40 and 42. In one embodiment, passivation layer 44 is about 5-15 μm in thickness and RDL 40 is about 1-3 μm in thickness. Passivation layer 44 can be made using similar material as described for passivation layer 36. In another embodiment, passivation layers 36 and 44 are formed by repassivation. A portion of second passivation layer 44 is removed by a photoresist mask defined etching process for the first and second solder bumps in areas 48 and 50 or the second passivation layer is photosensitive and can be patterned directly.
  • An adhesive layer 46 is formed on passivation layer 44 and RDLs 40 and 42. In one embodiment, adhesive layer 46 is about 200-2000 angstroms in thickness. Adhesive layer 46 can be titanium (Ti), Al, titanium tungsten (TiW), and chromium (Cr). Adhesive layer 46 is patterned to follow the contour of passivation layer 44 and RDLs 40 and 42. Accordingly, the formation of adhesive layer 46 is depressed in solder bump areas 48 and 50 and covers substantially the entire surface of passivation layer 44, particularly in and around areas 48 and 50, as seen in FIG. 2.
  • FIG. 3 illustrates a barrier layer 52 formed over adhesive layer 46, and wetting layer 54 formed over barrier layer 52. Barrier layer 52 and wetting layer 54, in combination with adhesive layer 46, forms an under bump metallization (UBM) in areas 48 and 50 for the first and second solder bumps. The adhesion layer 46 bonds to barrier layer 52. Barrier layer 42 inhibits the diffusion of materials destructive to silicon such as Cu into the active area of the die. Barrier layer 52 is optional depending on the materials used and the application. Wetting layer 52 electrically connects to contact pad 32 via RDL 40. In one embodiment, barrier layer 52 is about 3000-4000 angstroms in thickness, and wetting layer 54 is about 5000-10000 angstroms in thickness. Barrier layer 52 can be made of nickel (Ni), Ni-alloy, platinum (Pt), palladium (Pd), TiW, and chromium copper (CrCu). Wetting layer 54 can be made with Cu, gold (Au), or Al. Barrier layer 52 is patterned to follow the contour of adhesive layer 46. Likewise, wetting layer 54 is patterned to follow the contour of barrier layer 52 and acts as an intermediate conduction layer formed between the first solder bump and RDL 40. The patterning barrier layer 52 and wetting layer 54 and adhesive layer 46, as described above, define the solder bump areas 48 and 50 for forming solder bumps. The barrier layer 52 and wetting layer 54 and adhesive layer 46 enhance reliability of the bump support structure.
  • In FIG. 4, a photoresist layer is deposited over wetting layer 54. The photoresist layer is patterned to provide photoresist layers 56 and 58 over solder bump areas 48 and 50, respectively. In FIG. 5, the portions of barrier layer 52 and wetting layer 54, which are not protected by photoresist layers 56 and 58, are removed using a wet etch process. That is, only the portions of wetting layer 54 and barrier layer 52 in the region outside the UBM structure are etched away. The adhesive layer 46 in the region outside the UMB structure remains in place at this stage of the process. As will be shown, the portion of adhesive layer 46 in the region outside solder bump areas 48 and 50 protects passivation layer 44 from chemical degradation during formation of the solder bumps in later stages of the process. Photoresist layers 56 and 58 are then removed, leaving the UBM structure comprising adhesive layer 46, barrier layer 52, and wetting layer 54 only in solder bump areas 48 and 50.
  • In FIG. 6, a dry film layer 60 is deposited over adhesive layer 46 and the UBM structure comprising adhesive layer 46, barrier layer 52, and wetting layer 54. The dry film layer is patterned, and the portion of the dry film over the UBM structure is removed. Solder material 62 is deposited over the UBM structure between the patterned dry film layer through a screen printing, or electrolytic plating or electroless plating process. The solder material can be any metal or electrically conductive material, e.g., tin (Sn), lead (Pb), Ni, Au, silver (Ag), Cu, bismuthinite (Bi) and alloys thereof, or mixtures of other electrically conductive material. In one embodiment, the solder material is 63 percent weight of Sn and 37 percent weight of Pb.
  • In FIG. 7, the solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 64 and 66 over semiconductor substrate 34. In one embodiment, solder bumps 64 and 66 are about 70˜180 μm in height. In some applications, solder bumps 64 and 66 are reflowed a second time to improve electrical contact to the UBM structure.
  • It is important to note that during the solder bump formation process, the adhesive layer 46 in the region outside the UBM structure remains in place. The previous step of removing the portion of wetting layer 54 and barrier layer 52 in the region outside the UBM structure did not involve adhesive layer 46. The adhesive layer 46 in the region outside the UBM structure remains in place and protects passivation layer 44 against chemical degradation during the formation of the solder bumps, in particular during deposition and remove of dry film layer 60. The adhesive layer over the passivation layer reduces cracking of the passivation layer 44 without incurring additional manufacturing costs.
  • In FIG. 8, a wet etching process applied to remove any portion of adhesion layer 46 in the region outside the region of the solder bump structure using solder bumps as the etching mask. Solder bump 64 electrically contacts metal contact pad 32 by way of RDL 40. Likewise, solder bump 66 electrically contacts RDL 42.
  • In another embodiment, semiconductor device 10 can be made with a direct contact between the solder bump and the contact pad, i.e., without RDLs or other conductive routing structure. In this case, contact pad 32 is formed directly under the UBM structure. A similar process, as described in FIGS. 2-8, would be used for the direct solder bump to contact pad embodiment. The adhesive layer in the region outside the UBM structure protects the passivation layer against chemical degradation during formation of the solder bumps, particularly during deposition and removal of dry film layer. Again, the adhesive layer over the passivation layer reduces cracking of the passivation layer without incurring additional manufacturing costs.
  • While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims (25)

1. A semiconductor device, comprising:
a substrate having a plurality of semiconductor devices formed on a surface of the substrate;
a contact pad formed over the substrate in electrical contact with the semiconductor devices;
a redistribution layer (RDL) formed over the substrate in electrical contact with the contact pad;
a passivation layer formed over the substrate and RDL, wherein a portion of the passivation layer is removed to expose the RDL;
an adhesive layer formed over the passivation layer and the exposed RDL;
a barrier layer formed over a first portion of the adhesive layer which is over the exposed RDL, the barrier layer not being formed over a second portion of the adhesive layer;
a wetting layer formed over the barrier layer which is over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer; and
a bump formed over the wetting layer and barrier layer.
2. The semiconductor device of claim 1, wherein the first portion of the adhesive layer is removed after the bump is formed.
3. The semiconductor device of claim 1, wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
4. The semiconductor device of claim 1, wherein the adhesive layer follows a contour of the passivation layer.
5. A semiconductor device, comprising:
a substrate;
a passivation layer formed over the substrate;
an adhesive layer formed over the passivation layer;
a barrier layer formed over a first portion of the adhesive layer, the barrier layer not being formed over a second portion of the adhesive layer;
a wetting layer formed over the barrier layer over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer; and
an electrical interconnect formed over the wetting layer and barrier layer.
6. The semiconductor device of claim 5, further including a plurality of semiconductor devices formed on a surface of the substrate.
7. The semiconductor device of claim 5, further including:
a contact pad formed over the substrate; and
a redistribution layer (RDL) formed over the substrate in electrical contact with the contact pad.
8. The semiconductor device of claim 7, wherein the passivation layer is formed over the RDL and a portion of the passivation layer is removed to expose the RDL.
9. The semiconductor device of claim 8, wherein the barrier layer is formed over the first portion of the adhesive layer which is over the exposed RDL.
10. The semiconductor device of claim 5, wherein the first portion of adhesive layer is removed after the bump is formed.
11. The semiconductor device of claim 5, wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
12. The semiconductor device of claim 5, wherein the adhesive layer follows a contour of the passivation layer.
13. The semiconductor device of claim 5, wherein the electrical interconnect includes a bump.
14. A semiconductor device, comprising:
a substrate;
a passivation layer formed over the substrate;
an adhesive layer formed over the passivation layer;
a wetting layer formed over a first portion of the adhesive layer, the wetting layer not being formed over a second portion of the adhesive layer; and
an electrical interconnect formed over the wetting layer.
15. The semiconductor device of claim 14, further including a barrier layer formed between the adhesive layer and the wetting layer.
16. The semiconductor device of claim 15, wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
17. The semiconductor device of claim 14, further including:
a contact pad formed over the substrate; and
a redistribution layer formed over the substrate in electrical contact with the contact pad.
18. The semiconductor device of claim 14, wherein the first portion of adhesive layer is removed after the bump is formed.
19. The semiconductor device of claim 14, wherein the electrical interconnect includes a bump.
20. A semiconductor device, comprising:
a substrate;
a passivation layer formed over the substrate;
an adhesive layer formed over the passivation layer;
a barrier layer formed over a first portion of the adhesive layer, the barrier layer not being formed over a second portion of the adhesive layer; and
an electrical interconnect formed over the barrier layer.
21. The semiconductor device of claim 20, further including a wetting layer formed over the barrier layer which is over the first portion of the adhesive layer, the wetting layer not being formed over the second portion of the adhesive layer.
22. The semiconductor device of claim 21, wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
23. The semiconductor device of claim 20, further including:
a contact pad formed over the substrate; and
a redistribution layer formed over the substrate in electrical contact with the contact pad.
24. The semiconductor device of claim 20, wherein the first portion of adhesive layer is removed after the bump is formed.
25. The semiconductor device of claim 20, wherein the electrical interconnect includes a bump.
US12/763,378 2006-12-21 2010-04-20 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process Abandoned US20120211881A9 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/763,378 US20120211881A9 (en) 2006-12-21 2010-04-20 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US87141006P 2006-12-21 2006-12-21
US11/934,009 US7727876B2 (en) 2006-12-21 2007-11-01 Semiconductor device and method of protecting passivation layer in a solder bump process
US12/763,378 US20120211881A9 (en) 2006-12-21 2010-04-20 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/934,009 Division US7727876B2 (en) 2006-12-21 2007-11-01 Semiconductor device and method of protecting passivation layer in a solder bump process

Publications (2)

Publication Number Publication Date
US20100200985A1 true US20100200985A1 (en) 2010-08-12
US20120211881A9 US20120211881A9 (en) 2012-08-23

Family

ID=39541682

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/934,009 Active 2028-04-24 US7727876B2 (en) 2006-12-21 2007-11-01 Semiconductor device and method of protecting passivation layer in a solder bump process
US12/763,378 Abandoned US20120211881A9 (en) 2006-12-21 2010-04-20 Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/934,009 Active 2028-04-24 US7727876B2 (en) 2006-12-21 2007-11-01 Semiconductor device and method of protecting passivation layer in a solder bump process

Country Status (1)

Country Link
US (2) US7727876B2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5162851B2 (en) * 2006-07-14 2013-03-13 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
US7727876B2 (en) * 2006-12-21 2010-06-01 Stats Chippac, Ltd. Semiconductor device and method of protecting passivation layer in a solder bump process
DE102007057689A1 (en) * 2007-11-30 2009-06-04 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device having a chip area, which is designed for an aluminum-free solder bump connection, and a test structure, which is designed for an aluminum-free wire connection
US9035459B2 (en) 2009-04-10 2015-05-19 International Business Machines Corporation Structures for improving current carrying capability of interconnects and methods of fabricating the same
TWI445147B (en) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng Semiconductor device
FR2952314B1 (en) * 2009-11-12 2012-02-10 Sagem Defense Securite BRAZING METHOD, GYROSCOPE AND BRAZED PART
KR101113501B1 (en) * 2009-11-12 2012-02-29 삼성전기주식회사 Manufacturing method of semiconductor package
US8269348B2 (en) * 2010-02-22 2012-09-18 Texas Instruments Incorporated IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch
KR20110124993A (en) * 2010-05-12 2011-11-18 삼성전자주식회사 Semiconductor chip and semiconductor package including the same and method of manufacturing the same
US8518815B2 (en) 2010-07-07 2013-08-27 Lam Research Corporation Methods, devices, and materials for metallization
TWI478303B (en) 2010-09-27 2015-03-21 Advanced Semiconductor Eng Chip having metal pillar and package having the same
TWI451546B (en) 2010-10-29 2014-09-01 Advanced Semiconductor Eng Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package
US8569886B2 (en) * 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8912087B2 (en) * 2012-08-01 2014-12-16 Infineon Technologies Ag Method of fabricating a chip package
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
KR20150073473A (en) * 2013-12-23 2015-07-01 에스케이하이닉스 주식회사 Semiconductor device and method for manufacturing the same
US9418951B2 (en) * 2014-05-15 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof
DE102014107018A1 (en) * 2014-05-19 2015-11-19 Infineon Technologies Ag Semiconductor device with solderable and bondable electrical contact plates
CN104538315B (en) * 2015-01-08 2017-12-01 电子科技大学 A kind of low-resistance high current DMOS device chips level CSP method for packing
US10008461B2 (en) * 2015-06-05 2018-06-26 Micron Technology, Inc. Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
US11024569B2 (en) * 2017-08-09 2021-06-01 Advanced Semiconducor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US20230145953A1 (en) * 2021-11-08 2023-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Reduction of cracks in passivation layer

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020180064A1 (en) * 2001-06-05 2002-12-05 Chipbond Technology Corporation Metallized surface wafer level package structure
US20030157438A1 (en) * 2002-02-20 2003-08-21 Ho-Ming Tong Bump forming process
US6716739B2 (en) * 2002-02-19 2004-04-06 Advanced Semiconductor Engineering, Inc. Bump manufacturing method
US6720243B2 (en) * 2002-01-07 2004-04-13 Advanced Semiconductor Engineering, Inc. Bump fabrication method
US20040188378A1 (en) * 2003-03-25 2004-09-30 Advanced Semiconductor Engineering, Inc. Bumping process
US20040256734A1 (en) * 2003-03-31 2004-12-23 Farnworth Warren M. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US20050250323A1 (en) * 2004-03-29 2005-11-10 Barnak John P Under bump metallization layer to enable use of high tin content solder bumps
US6989326B2 (en) * 2002-02-21 2006-01-24 Advanced Semiconductor Engineering, Inc. Bump manufacturing method
US20060046434A1 (en) * 2004-08-26 2006-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing lead precipitation during wafer processing
US7112523B2 (en) * 2003-06-30 2006-09-26 Advanced Semiconductor Engineering, Inc. Bumping process
US20080150161A1 (en) * 2006-12-21 2008-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020180064A1 (en) * 2001-06-05 2002-12-05 Chipbond Technology Corporation Metallized surface wafer level package structure
US6720243B2 (en) * 2002-01-07 2004-04-13 Advanced Semiconductor Engineering, Inc. Bump fabrication method
US6716739B2 (en) * 2002-02-19 2004-04-06 Advanced Semiconductor Engineering, Inc. Bump manufacturing method
US20030157438A1 (en) * 2002-02-20 2003-08-21 Ho-Ming Tong Bump forming process
US6989326B2 (en) * 2002-02-21 2006-01-24 Advanced Semiconductor Engineering, Inc. Bump manufacturing method
US20040188378A1 (en) * 2003-03-25 2004-09-30 Advanced Semiconductor Engineering, Inc. Bumping process
US20040256734A1 (en) * 2003-03-31 2004-12-23 Farnworth Warren M. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US7112523B2 (en) * 2003-06-30 2006-09-26 Advanced Semiconductor Engineering, Inc. Bumping process
US20050250323A1 (en) * 2004-03-29 2005-11-10 Barnak John P Under bump metallization layer to enable use of high tin content solder bumps
US20060046434A1 (en) * 2004-08-26 2006-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing lead precipitation during wafer processing
US20080150161A1 (en) * 2006-12-21 2008-06-26 Stats Chippac, Ltd. Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Also Published As

Publication number Publication date
US20080150161A1 (en) 2008-06-26
US7727876B2 (en) 2010-06-01
US20120211881A9 (en) 2012-08-23

Similar Documents

Publication Publication Date Title
US7727876B2 (en) Semiconductor device and method of protecting passivation layer in a solder bump process
US9177930B2 (en) Solder bump with inner core pillar in semiconductor package
US7667335B2 (en) Semiconductor package with passivation island for reducing stress on solder bumps
US10651139B2 (en) Semiconductor device and method of forming wafer level ground plane and power ring
US9142514B2 (en) Semiconductor device and method of forming wafer level die integration
US7772106B2 (en) Method of forming an inductor on a semiconductor wafer
US8921983B2 (en) Semiconductor package and method of forming similar structure for top and bottom bonding pads
US9659890B2 (en) Methods and apparatus of packaging semiconductor devices
US9349723B2 (en) Semiconductor device and method of forming passive devices
US20140159236A1 (en) Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating
US7723224B2 (en) Microelectronic assembly with back side metallization and method for forming the same
US20070138628A1 (en) Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US7176117B2 (en) Method for mounting passive components on wafer
US9466577B2 (en) Semiconductor interconnect structure with stacked vias separated by signal line and method therefor

Legal Events

Date Code Title Description
AS Assignment

Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT, HONG KONG

Free format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS CHIPPAC LTD.;REEL/FRAME:036288/0748

Effective date: 20150806

Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY

Free format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS CHIPPAC LTD.;REEL/FRAME:036288/0748

Effective date: 20150806

STCB Information on status: application discontinuation

Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION

AS Assignment

Owner name: STATS CHIPPAC PTE. LTE., SINGAPORE

Free format text: CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LD.;REEL/FRAME:038378/0442

Effective date: 20160329

AS Assignment

Owner name: STATS CHIPPAC PTE. LTD., SINGAPORE

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LTD.;REEL/FRAME:039980/0838

Effective date: 20160329

AS Assignment

Owner name: STATS CHIPPAC, INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT;REEL/FRAME:053476/0094

Effective date: 20190503

Owner name: STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD., SINGAPORE

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT;REEL/FRAME:053476/0094

Effective date: 20190503