US20100155881A1

US20100155881A1 - Forming Isolation Regions For Integrated Circuits

Info

Publication number: US20100155881A1
Application number: US12/342,312
Authority: US
Inventors: Roberto Colombo; Luca Di Piazza
Original assignee: Individual
Current assignee: US Bank NA
Priority date: 2008-12-23
Filing date: 2008-12-23
Publication date: 2010-06-24
Also published as: US8211778B2

Abstract

A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect.

Description

BACKGROUND

This relates generally to the formation of active areas in microelectronic devices.
Active areas are areas where transistors may be formed. Generally, active areas are isolated from the remainder of an integrated circuit using local oxidation (LOCOS). Within the active area of a memory there is an array and a periphery. The array is a matrix of memory elements and the periphery is the portion of the active area outside the array.
The LOCOS process does not form, for example, substrate areas of different heights. In charge trapping and phase change memories, array and peripheral areas may be at different heights to allow the right process integration.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged, cross-sectional view at an early stage of manufacture;

FIG. 2 is an enlarged, cross-sectional view at a subsequent stage;

FIG. 3 is an enlarged, cross-sectional view at a subsequent stage;

FIG. 4 is an enlarged, cross-sectional view at a subsequent stage;

FIG. 5 is an enlarged, cross-sectional view at a subsequent stage;

FIG. 6 is an enlarged, cross-sectional view at a subsequent stage; and

FIG. 7 is an enlarged, cross-sectional depiction after the formation of a two-level substrate.

DETAILED DESCRIPTION

In accordance with some embodiments, a stepped or two-level substrate may be formed in microelectronic wafers, such as silicon wafers. The different heights may be used to form memory array and periphery circuits in some embodiments. Particularly, the array may be formed at the higher level and the periphery may be formed at the lower level.
In some embodiments, an isolation region may be formed by integrating a shallow trench isolation and local oxidation of silicon or LOCOS. This integration may lead to a tunable transition between substrate areas of different heights, expanding the application of LOCOS, in some embodiments, without incurring substantial limitations related to substrate area consumption. By defining a trench that acts as a barrier to LOCOS oxidation, the adverse effects, known as the bird's beak effect, may be managed in some embodiments.
Initially, as shown in FIG. 1, a silicon substrate may be coated with a pad ox 12, a hard mask 14, and a resist patterning layer 16. The resist patterning layer 16 may include an opening 18 formed by photolithographic techniques and having a diameter W. In one embodiment, the opening 18 may be a closed geometric shape, such as a square, an oval, or a circle. It defines, within its confines, an active area. In one embodiment, the pad ox 12 may be silicon dioxide that is grown or deposited. The hard mask 14 may be silicon nitride.
The dimension W of the aperture 18 may be large enough to avoid diffusion in ensuing local oxidation of silicon (LOCOS) oxidation.
Using the opening 18 in the resist patterning layer 16 as a mask, an aperture 20 may be formed, as shown in FIG. 2. The aperture 20 extends through the hard mask 18, the pad ox 12 and into the underlying substrate 10. Its extent in silicon is indicated by the arrow D that indicates the depth of a conventional LOCOS process.
Then, referring to FIG. 3, the aperture 20 may be filled with a fill material 24, such as silicon dioxide, and the wafer may be planarized, for example, by etch back or chemical mechanical planarization to remove the overlying portion of the fill material 24. The fill material 24 may be formed pursuant to a shallow trench isolation technology.
Then, as shown in FIG. 4, the wafer is patterned in order to mask areas that will be higher. The mask 26, in this embodiment, covers the left side of FIG. 4 and the filled aperture 22. Thus, the right side will actually be the active area and is now ready for subsequent etching.
Referring to FIG. 5, the initial etching extends through the hard mask 14 and pad ox 12, on the right side, as indicated at 28, down to the surface of the microelectronic substrate 10. Dry or wet etching may be used, or a combination of both, to remove these layers. After resist etching, the wafer is ready for a LOCOS oxidation process.
Referring to FIG. 6, the LOCOS oxidation 36 has been formed to the depth D, consuming the portion of the silicon substrate 10 to the right of the fill material 24 and extending to a slightly greater depth indicated as D_LOCOS. The transition 32 in the bottom of the microelectronic substrate is tunable. In this case, an inclined ramp shape is depicted between the horizontal surfaces 38 and 30. The LOCOS oxide 36 fills the area above the transition 32 and surface 38. The transition 32 may avoid sharp ends at the trench bottom. Particularly where the oxidation depth D_LOCOSis slightly greater than the trench depth D, shown in FIG. 2, sharp corners may be desirably avoided in some embodiments.
The fill material 24, located alongside the pad ox 12 and hard mask 14, may reduce the effect of the bird's beak. Normally, the bird's beak effect involves an increased oxide growth in the region under the edge of the hard mask. Because of the imposition of the fill material 24, the diffusion of oxidants, such as O₂and H₂O, is reduced into the region under the hard mask 14 and pad oxide 12. Oxidant diffusion to the substrate 10 is reduced or blocked by the effective wall defined by the material 24. As a result, a gentle curved insulation transition region 32 may be formed, ideally, right at the bottom outside corner of the fill material 24. In some embodiments, the region 32 may hit further up on fill material 24, but it is most advantageous for it to hit right at the corner, as depicted in FIG. 6.
The production of the arrangement, shown in FIG. 6, where the LOCOS oxide 36 forms down to a point right at the corner of the fill material 24 may reduce dislocation formation in some embodiments. The transition region 32 is defined by the width of the fill material 24 because oxidation of substrate 10 under the pad oxide 12 and hard mask 14 is prevented or reduced by the blocking oxide wall defined by the fill material 24. Thus, to move the region 32 downwardly, the width of the fill material 24 may be reduced and to move the region 32 upwardly, the width of the fill material 24 may be increased to achieve the arrangement where the region 32 hits right at the outer, lower corner of the fill material 24, as depicted in FIG. 6.
The hard mask 14, the pad ox 12, and the LOCOS oxide 36 may be removed to create the substrate 10 shown in FIG. 7 with an upper surface 30, a transition 32, and a lower surface 38. The transition 32 and surface 30 between the upper level 40 and the lower surface 38 becomes a transition region such that some components may be formed on the level 40 of the FIG. 7 and others may be formed on the surface 38. These components will be isolated from one another because of the step or height difference.
The extent of the transition, in terms of its length, may be tunable by controlling the dimensions of the trench 20. The shape of its bottom may also be controllable based on the etching process that is utilized.
In some embodiments, a two level structure may be utilized for periphery and memory. The transition between the two level structures may be tunable by using a combination of a shallow trench isolation structure with a LOCOS structure. Tunability may be achieved, in some embodiments, by controlling the width of the shallow trench isolation structure. Because of the imposition of the shallow trench isolation between the nitride mask and pad ox and the area that will form the localized oxidation, the bird's beak effect may be controlled in some embodiments.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

1. A method comprising:

forming a mask on a substrate;

forming a trench isolation along said mask; and

oxidizing the substrate along said trench isolation.

2. The method of claim 1 including defining a higher and lower level of said substrate on opposite sides of said mask.

3. The method of claim 1 including forming a transition between said higher and lower levels.

4. The method of claim 3 including defining said transition by controlling the width of said trench isolation.

5. The method of claim 4 including causing said transition to intersect substantially at a lower corner of said trench isolation.

6. The method of claim 1 including forming said mask of a hard mask over a pad oxide.

7. The method of claim 6 wherein forming a trench isolation includes forming a shallow trench isolation.

8. A method comprising:

forming a local oxidation of silicon isolation by controlling diffusion of an oxidant under a mask.

9. The method of claim 8 including forming said mask of a hard mask over a pad oxide.

10. The method of claim 8 wherein controlling diffusion includes forming a trench along said mask and filling said trench with an insulator.

11. The method of claim 10 wherein forming a trench includes forming a shallow trench isolation.

12. The method of claim 8 including forming substrate surfaces of different levels on opposite sides of said mask.

13. An apparatus comprising:

a substrate;

a mask over said substrate;

a trench isolation next to said mask; and

an oxide isolation next to said trench isolation.

14. The apparatus of claim 13, said substrate including a first level on one side of said mask and a second level, higher than said first level, on the opposite side of said mask.

15. The apparatus of claim 13 including a transition in said substrate between said levels.

16. The apparatus of claim 15 wherein said LOCOS isolation intersects substantially at a lower corner of said shallow trench isolation.

17. The apparatus of claim 13 wherein said mask includes a hard mask and a pad oxide.

18. The apparatus of claim 13 wherein said trench isolation is a shallow trench isolation and said oxide isolation is a local oxidation of silicon isolation.

19. The apparatus of claim 18 wherein said oxide isolation extends below said shallow trench isolation.

20. The apparatus of claim 18 wherein said shallow trench isolation includes oxide.