US20100149013A1 - System And Method For Common Mode Translation - Google Patents
System And Method For Common Mode Translation Download PDFInfo
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- US20100149013A1 US20100149013A1 US12/710,856 US71085610A US2010149013A1 US 20100149013 A1 US20100149013 A1 US 20100149013A1 US 71085610 A US71085610 A US 71085610A US 2010149013 A1 US2010149013 A1 US 2010149013A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication
- H03M3/488—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication using automatic control
Abstract
System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
Description
- The present invention relates generally to a system and method for signal processing, and more particularly to a system and method for common mode translation in continuous-time sigma-delta analog-to-digital converters.
- A continuous-time sigma-delta analog-to-digital converter (continuous-time sigma-delta ADC) differs from a discrete-time sigma-delta ADC in that the continuous-time sigma-delta ADC makes use of a loop filter while the discrete-time sigma-delta ADC uses a switched-capacitor filter, which may require the use of fast settling circuits and an input buffer to eliminate sample glitches. The switched-capacitor filter may limit the signal bandwidth. Additionally, due to the thermal noise of the capacitors used in the switched-capacitor filters, large capacitors may be needed to obtain good signal-to-noise ratios.
- The loop filter may have a topology that is active-Gm-C, active-RC, a combination of active-Gm-C and active-RC, or a combination of active and passive networks. A diagram shown in
FIG. 1 illustrates a view of a typical prior art continuous-time sigma-delta ADC 100. The continuous-time sigma-delta ADC 100 includes aninput RC network 105 and an active-passive Gm-C/Quantizer/DAC circuit (GQD) 110. - The
RC network 105, which may provide passive filtering of the input signals to the continuous-time sigma-delta ADC, may include resistors (R), such asresistors capacitors delta ADC 100. The GQD 110 may include aloop filter 170, aquantizer 175, and afeedback loop 180 from a positive, and a negative output from thequantizer 175 back to the positive and the negative inputs to theloop filter 170. Summing points combine the signal from therespective feedback loop 180 and the respective input signal and provides it to theloop filter 170. TheGQD 110 may evaluate an input signal (provided by the RC network 105), measure an error signal present in the input signal, and provide compensation for the error signal. During normal operation of theGQD 110, a virtual short circuit may be maintained between the positive and the negative inputs of theloop filter 170 due to the GQD's high gain and its negative feedback loop. Thefeedback loop 180 may include a digital-to-analog converter (DAC) 185 to provide an analog version of the feedback of thequantizer 175 output. - Due to the nature of the
GQD 110, the input common mode level of theloop filter 170 may be identical to the common mode level of the input signal. However, if the input signal is to be provided by a separate integrated circuit (for example, an RF chip coupled to the continuous-time sigma-delta ADC 100), the common mode signal levels at the input to the continuous-time sigma-delta ADC 100 could be too high or too low for proper operation and reliability. Therefore, there may be a need to accommodate different common mode levels at the input to the continuous-time sigma-delta ADC 100 to enable reliable and optimal operation between the continuous-time sigma-delta ADC 100 and a variety of RF chips. The common mode level may be higher than a supply voltage of theloop filter 170 in theGQD 110. - If the continuous-time sigma-delta ADC 100 is fabricated using a low-voltage process, reliability issues may arise due to the high common mode level. Even with acceptable common mode levels, during start-up, overload conditions, or power supply loss, when the
GQD 110 loop may be incapable of maintaining the summing junction (at the input to theloop filter 170, for example) at the common mode level, the differential swing of the input signal appears at the summing junction and may cause a degradation in the reliability of the continuous-time sigma-delta ADC 100. - These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention which provide a system and a method for common mode translation in continuous-time sigma-delta analog-to-digital converters.
- In accordance with an embodiment, a continuous-time sigma-delta analog-to-digital converter (CT SD ADC) is provided. The continuous-time sigma-delta analog-to-digital converter includes a loop filter having an input resistor-capacitor (RC) network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and to the common mode level adjust circuit. The GQD evaluates an input signal provided by the input RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common mode level adjust circuit alters a common mode level of a differential input signal to be substantially equal to a desired common mode level, and the tuning circuit provides a compensation voltage to the common mode level adjust circuit based on a difference between the common mode level of the differential input signal and the desired common mode level.
- In accordance with another embodiment, a circuit for adjusting a common mode level of a second circuit is provided. The circuit includes a first current supply coupled between a first input of the second circuit and a power rail, and a second current supply coupled between a second input of the second circuit and the power rail. The first input and the second input make up a differential input, and the first current supply and the second current supply provide a current path between a respective input and the power rail based on a control signal provided to the respective current supply.
- In accordance with another embodiment, a method for tuning a circuit is provided. The method includes determining a difference between a common mode level of an input signal to the circuit and a desired common mode level, generating a compensation voltage based on the difference, and applying the compensation voltage.
- An advantage of an embodiment is that implementation of the embodiment is simple and may be readily added to existing continuous-time sigma-delta analog-to-digital converters without significant modification.
- A further advantage of an embodiment is that relatively little integrated circuit real estate is required, helping to keep the cost of the integrated circuit low.
- Yet another advantage of an embodiment is that the embodiment enables the tuning of the adjustments to the common mode level. This may allow the use of the embodiment in a wide variety of applications, further enhancing its appeal.
- The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
- For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
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FIG. 1 is a diagram of a typical continuous-time sigma-delta ADC; -
FIG. 2 is a diagram of a prior art technique for providing common mode level protection in a continuous-time sigma-delta ADC; -
FIGS. 3 a through 3 c are diagrams of common mode adjust circuits; -
FIG. 4 is a diagram of a schematic of an exemplary continuous-time sigma-delta ADC with a common mode adjust circuit; -
FIG. 5 is a diagram of a schematic of an exemplary continuous-time sigma-delta ADC with a common mode adjust circuit; and -
FIGS. 6 a through 6 c are diagrams of sequences of events used in adjusting a common mode adjust circuit of an exemplary continuous-time sigma-delta ADC. - The making and using of the embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
- The embodiments will be described in a specific context, namely a continuous-time sigma-delta ADC. The invention may also be applied, however, to other integrated circuits wherein there is a desire to provide common mode level protection, such as in a continuous-time sigma-delta DAC, and so on.
- With reference now to
FIG. 2 , there is shown a diagram illustrating a continuous-time sigma-delta ADC 200, wherein the continuous-time sigma-delta ADC 200 includes a prior art technique for providing common mode level protection. The common mode level protection comes in the form of a voltage clamp and aseries switch 190 for each input to the continuous-time sigma-delta ADC 200. The voltage clamp and theseries switch 190 however, only provides high voltage protection without stepping down the common mode level to an optimum value (e.g., about the same as, the common mode level produced by the output of the GQD 110). Furthermore, the voltage clamp and theseries switch 190 provides high voltage protection at the expense of large area and potentially significant signal distortion and clipping due to the presence of clamps and series switches in the signal path. Additionally, the voltage clamp and theseries switch 190 may not be able to be maintained in the event of power supply loss. - With reference now to
FIGS. 3 a through 3 c, there are shown diagrams illustrating embodiments of common mode level protection circuitry for a continuous-time sigma-delta ADC. In a majority of situations, a common mode level as provided to an input of the continuous-time sigma-delta ADC may be higher than a desired common mode level of the continuous-time sigma-delta ADC. Therefore, a current sink may be used to pull the common mode level down. The diagram shown inFIG. 3 a illustrates acircuit 300 containing two current sinks (NMOS transistors NMOS transistors resistors RC network 105. - The voltage drop may be determined by the value of the
resistors NMOS transistors example NMOS transistor 310, may be coupled to the positive signal input of a continuous-time sigma-delta ADC, and a second of the two NMOS transistors, forexample NMOS transistor 311, may be coupled to the negative signal input of a continuous-time sigma-delta ADC. Although shown to be NMOS transistors, other types of transistors, such as PMOS, BJT, DMOS, and so forth, may be used with modification to thecircuit 300. The illustration and discussion of NMOS transistors should not be construed as being limiting to either the scope or the spirit of the present invention. - Similarly, when the common mode level as provided to the input of the continuous-time sigma-delta ADC may be lower than the desired common mode level of the continuous-time sigma-delta ADC, a current source may be used to provide the current needed to pull the common mode level up. In this case the voltage rise at the positive signal input may be determined by the value of
resistors transistors FIG. 3 b illustrates. Similarly, the voltage rise at the negative signal input may be determined by the value of resistors coupled to the negative signal input and either of the PMOS pull-uptransistors PMOS transistors circuit 320. The illustration and discussion of PMOS transistors should not be construed as being limiting to either the scope or the spirit of the present invention. - The circuit(s) (
circuit 300 andcircuit 320 or a combination thereof) may be coupled to a continuous-time sigma-delta ADC at one of several locations. A first location may be at the inputs to the continuous-time sigma-delta ADC, such as the continuous-time sigma-delta ADC 100, (shown as plane A inFIG. 1 ). If the circuit 300 (orcircuit 320 or both) is coupled to the continuous-time sigma-delta ADC 100 at the inputs of the continuous-time sigma-delta ADC 100, then an additional resistor may have to be added to each signal input of the continuous-time sigma-delta ADC 100. The resistor may be needed to produce a voltage drop necessary to shift the common mode level. This may reduce the bandwidth of the input filter (the RC network 105), consume valuable integrated circuit real estate, and attenuate the input signal. Furthermore, the differential signal at the inputs of the continuous-time sigma-delta ADC 100 is a large signal, which may make matching thecircuit 300 very difficult due to the finite output resistance of the current sinks. - A second location may be at the RC network 105 (shown as plane B in
FIG. 1 ). If thecircuit 300 is coupled to the continuous-time sigma-delta ADC 100 at theRC network 105, then theresistor 155 may be used to realize the voltage drop needed to shift the common mode level. However, the value of theresistor 155 may typically be smaller than the value of the resistor 156 (normally the resistance of theresistor 155 is about one-half the resistance of the resistor 156), which may mean that thecircuit 300 may potentially need to contain high-current current sinks. The use of high-current current sinks to shift the common mode level may consume more power than necessary and may overload the common mode feedback circuit of an output stage of an RF circuit providing the input signal to the continuous-time sigma-delta ADC 100. Additionally, the differential signal at theRC network 105 may still be a large signal (the differential signal at theRC network 105 may be expressed as (resistor 156)/(resistor 155+resistor 156) of the differential signal at the inputs of the continuous-time sigma-delta ADC 100). This may make matching thecircuit 300 difficult and cascading may be necessary. - A third location may be the inputs to the GQD 110 (shown as plane C in
FIG. 1 ). If thecircuit 300 is coupled to the continuous-time sigma-delta ADC 100 at theGQD 110, then theresistors RC network 105 may be used to realize the voltage drop needed to shift the common mode level of the negative signal input, implying that the values of the current sinks in thecircuit 300 may be at a minimum. Additionally, the differential signal at the inputs to theGQD 110 may be small (due to the virtual short at the inputs to the GQD 110) due to the loop operation. This may eliminate the need for any cascoding of thecircuit 300, yielding large headroom. In turn, this may allow for larger overdrive (small transconductance) in the current sinks in thecircuit 300 and permit better matching and a negligible noise contribution. - The placement of the
circuit 300 at theGQD 110 of the continuous-time sigma-delta ADC 100 may typically be perceived as a source of noise performance degradation for the continuous-time sigma-delta ADC 100 since thecircuit 300 is located at a summing junction, where the feedback signal is added to the input signal. Since the noise from the current sinks (NMOS transistors ADC 100 may be dominated by quantization noise rather than flicker or thermal noise of the individual circuit components. Therefore, the addition of thecircuit 300 to the continuous-time sigma-delta ADC 100 may have little impact on the noise performance of the continuous-time sigma-delta ADC 100. - Since there is substantially no differential voltage swing present at the input to the
GQD 110, the current sinks added in thecircuit 300 may not introduce any distortion to the input signal. Any mismatch between the current sinks may appear simply as a DC offset without any harmonics. Additionally, since thecircuit 300 does not require any voltage clamps or series switches, significant area (integrated circuit real estate) may be saved and distortion problems associated with voltage clamps and series switches are eliminated. - In an alternative embodiment, the diagram shown in
FIG. 3 c illustrates acircuit 340 that includes two current sinks (NMOS transistors PMOS transistors FIG. 3 b, the two current sinks may be replaced with current sources if there is a need to pull the common mode level up to the desired common mode level instead of the need to pull the common mode level down to the desired common mode level. Alternatively, the current sources may be added in addition to the current sinks to provide both a pull up and a pull down capability to adjusting the common mode level. The two protection circuits,PMOS transistors loop filter 170 of theGQD 110 from any high voltage from the input signal in the case of a power supply loss, wherein the current sinks,NMOS transistors PMOS transistors GQD 110. - The two protection circuits, the
PMOS transistors resistors 150 and 156 to drop the level of the input signal to a low level to protect theloop filter 170. When the power supply is lost, the “CONTROL VOLTAGE C” may be at ground potential and thus the protection provided by the two protection circuits may still be in effect. Although shown to be PMOS transistors, other types of transistors, such as NMOS, BJT, DMOS, and so forth, may be used with modification to the protection circuits. The illustration and discussion of PMOS transistors should not be construed as being limiting to either the scope or the spirit of the present invention. - Although shown as single transistors, the current sinks (
NMOS transistors PMOS transistors PMOS transistors - The current sinks in the
circuit 300,NMOS transistors - With reference now to
FIG. 4 , there is shown a diagram illustrating a schematic of a continuous-time sigma-delta ADC 400 with atuning circuit 405 for setting a control voltage used to tune current sinks to set a common mode level. The continuous-time sigma-delta ADC 400 includes the continuous-time sigma-delta ADC 100 with thecircuit 340 for common mode level protection with additional supply loss protection. Thetuning circuit 405 may be coupled to the continuous-time sigma-delta ADC 400 at the inputs to theGQD 110 like thecircuit 340. Thetuning circuit 405 may compare both a positive input to theGQD 110 and a negative input to theGQD 110 to a reference signal “VREF,” which may represent the desired common mode level. The comparison between the positive input to theGQD 110 and the reference signal may take place in a first pair oftransistors 410, while a second pair oftransistors 415 may perform the comparison between the negative input to theGQD 110 and the reference signal. Current mirrors 420, 425, and 430 provide necessary current to assert a bias voltage to control the state of the current sinks (transistors circuit 340. - If there is no difference between the level of the positive input to the
GQD 110 and the negative input to the GQD 110 (collectively, the common mode level of the input signal) and the reference signal (the desired common mode level), then the applied bias voltage goes to zero and the current sinks of thecircuit 340 are turned off. If there is a positive difference between the level of the positive input to theGQD 110 and the negative input to the GQD 110 (the common mode level of the input signal) and the reference signal (the desired common mode level), then a positive bias voltage is applied to the current sinks of thecircuit 340 and the current sinks are turned on and the inputs (both the positive and the negative inputs) of theGQD 110 may be pulled down towards the desired common mode level. - The first pair of
transistors 410 and the second pair oftransistors 415 may become part of the capacitance needed at the input of theGQD 110 and combine with capacitors in theRC network 105 to help reduce the overall capacitance of the capacitors in theRC network 105, such as thecapacitor 161. The configuration as shown inFIG. 4 may have a reduced additional integrated circuit real estate requirement that includes the remaining transistors in thecurrent mirrors RC network 105 are referenced to ground and the transistors in the first pair oftransistors 410 and the second pair oftransistors 415 are reference to the supply (VDD), better capacitance linearity at the input of theGQD 110 may be achieved. The improved capacitance linearity may improve the overall performance of the continuous-time sigma-delta ADC 400. - With reference now to
FIG. 5 , there is shown a diagram illustrating a schematic of a continuous-time sigma-delta ADC 500 with a tuning circuit 505 (for setting a control voltage used to tune current sinks to set a common mode level. Thetuning circuit 505 includes a diode connectedtransistor 510 that may be used to generate a bias voltage to control the state of the current sinks (transistors circuit 340. The current sinks may be operated as current mirrors. - A reference current “IREF” of the diode connected
transistor 510 may be defined as VBG/RINT, where VBG is a band-gap voltage and RINT is a resistor similar (manufactured using the same manufacturing process) to the resistors in theRC network 105, such as theresistors RC network 105, it may be ensured that a voltage drop across the resistors in theRC network 105, such as theresistors resistors 155 and 156). - The setting of the voltage drop across the resistors in the RC network 105 (a measure of programmability) may be implemented digitally through switching additional current sinks (similar to
transistors 310 and 311) in thecircuit 340 by a control bus “CONTROL.” Depending upon the value of the voltage drop across the resistors in theRC network 105, a number of current sinks may be turned on or turned off as needed. This may require prior knowledge of the input signal's common mode level in order to turn on the required number of current sinks. - However, since there is a limited number of unique RF integrated circuits that may be attached to the continuous-time sigma-
delta ADC 500 and provide the input signals, it may be possible to determine a typical common mode level for each unique RF integrated circuit and store them in amemory 515 of the continuous-time sigma-delta ADC 500. This may occur during manufacture of the continuous-time sigma-delta ADC 500 or it may occur during manufacture of a system containing the continuous-time sigma-delta ADC 500. The manufacturer may specify the RF integrated circuit that may be coupled to the continuous-time sigma-delta ADC 500, and then based on a reference to thememory 515, acontrol circuit 520 may turn on a number of current sinks (via a control bus 525) that may need to be turned on to properly set the voltage drop across the resistors in theRC network 105. - With reference now to
FIGS. 6 a through 6 c, there are shown diagrams illustrating sequences of events in adjusting the common mode level of an input signal provided to a continuous-time sigma-delta ADC. The diagram shown inFIG. 6 a illustrates a high-level sequence ofevents 600 in adjusting the common mode level of an input signal provided to a continuous-time sigma-delta ADC. The adjusting of the common mode level may begin with a determining of a difference between the common mode level of the input signal and a desired common mode level (block 605). The difference between the common mode level and the desired common mode level may then be used to generate a compensation voltage (block 610) that may be applied to a tuning circuit to bring the common mode level to a level about equal to the desired common mode level (block 615). - The diagram shown in
FIG. 6 b illustrates a sequence ofevents 630 used in adjusting the common mode level of an input signal provided to a continuous-time sigma-delta ADC, wherein a tuning circuit similar to thetuning circuit 405 is utilized to perform the adjusting. The sequence ofevents 630 may be an implementation of the sequence ofevents 600 modified to meet the specific requirements of thetuning circuit 405. The tuning of the common mode level may begin with a comparison of the input signals to the continuous-time sigma-delta ADC with the desired common mode level (block 635). The comparison may be an implementation of the determining of the difference between the common mode level of the input signal and the desired common mode level (block 605). The comparison may be performed by the first pair oftransistors 410 and the second pair oftransistors 415, for example. Then, a bias voltage may be generated based on the comparison of the common mode level and the desired common mode level (block 640) and may be an implementation of the generating of the compensation voltage (block 610). Current mirrors 420, 425, and 430 may be used to generate the compensation voltage, for example. The bias voltage may then be provided to current sinks to change the common mode level (block 645). - The diagram shown in
FIG. 6 c illustrates a sequence ofevents 660 used in adjusting the common mode level of an input signal provided to a continuous-time sigma-delta ADC, wherein a tuning circuit similar to thetuning circuit 505 is utilized to perform the adjusting. The sequence ofevents 660 may be an implementation of the sequence ofevents 600 modified to meet the specific requirements of thetuning circuit 505. The tuning of the common mode level may begin with the specifying of the type and make of an integrated circuit, such as an RF chip, that may be providing the input signal to the continuous-time sigma-delta ADC (block 665). The specifying may be an implementation of the determining of the difference between the common mode level of the input signal and the desired common mode level (block 605) since each type and make of integrated circuit may be characterized by a typical common mode level for output signals provided. With the specified type and make of integrated circuit, it may be possible to retrieve a compensation voltage, from a memory, for example (block 670) and may be an implementation of the generating of the compensation voltage (block 610). With the compensation voltage, a number of current sinks may be turned on to provide a requisite voltage drop necessary to place a common mode level at the input of a GQD that is substantially equal to the desired common, mode level (block 675). The voltage drop may be realized across the resistors that are part of an RC network present in a loop filter of the continuous-time sigma-delta ADC. - Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly; the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (8)
1. A continuous-time sigma-delta analog-to-digital converter (CT SD ADC) comprising:
a loop filter having an input resistor-capacitor (RC) network coupled to a differential signal input;
a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, the GQD configured to evaluate an input signal provided by the input RC network, compute a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measure the error signal, and compensate for the error signal with sigma-delta noise-shaping;
a common mode level adjust circuit coupled to signal inputs of the GQD, the common mode level adjust circuit configured to alter a common mode level of a differential input signal to be substantially equal to a desired common mode level; and
a tuning circuit coupled to the GQD and to the common mode level adjust circuit, the tuning circuit configured to provide a compensation voltage to the common mode level adjust circuit based on a difference between the common mode level of the differential input signal and the desired common mode level.
2. The continuous-time sigma-delta analog-to-digital converter of claim 1 , wherein the GQD comprises:
a loop filter having a second input RC network, the loop filter configured to filter a continuous time signal at its input;
a quantizer coupled to the loop filter, the quantizer configured to sample and quantize the filtered continuous time signal from the loop filter;
a first feedback loop coupling a first output of the quantizer to a first input of the loop filter, the first feedback loop configured to provide a first error signal to the loop filter;
a second feedback loop coupling a second output of the quantizer to a second input of the loop filter, the second feedback loop configured to provide a second error signal to the loop filter;
a first summing point coupled to the first feedback loop and a first input of the loop filter, the first summing point configured to combine signals provided by the first feedback loop and a first signal input; and
a first summing point coupled to the first feedback loop and a second input of the loop filter, the first summing point configured to combine signals provided by the first feedback loop and a second signal input.
3. The continuous-time sigma-delta analog-to-digital converter of claim 1 , wherein the common mode level adjust comprises:
a first current sink coupled between the first signal input of the loop filter and an electrical ground, the first current sink configured to create a voltage drop across the RC network substantially equal to a difference between the common mode level of the differential input signal and the desired common mode level; and
a second current sink coupled between the second signal input of the loop filter and an electrical ground, the second current sink configured to create a voltage drop across the RC network substantially equal to the difference between the common mode level of the differential input signal and the desired common mode level.
4. The continuous-time sigma-delta analog-to-digital converter of claim 3 , wherein the tuning circuit comprises:
a first comparison circuit coupled to the first input of the loop filter, the first comparison circuit configured to compare a signal on the first input of the loop filter with the desired common mode level;
a second comparison circuit coupled to the second input of the loop filter, the second comparison circuit configured to compare a signal on the second input of the loop filter with the desired common mode level; and
a voltage generation circuit coupled to the first comparison circuit and the second generation circuit, the voltage generation circuit configured to generate the compensation voltage.
5. The continuous-time sigma-delta analog-to-digital converter of claim 3 , wherein the tuning circuit comprises:
a memory to store compensation voltage values;
a reference voltage generator coupled to a plurality of current sinks, the reference voltage generator configured to produce a bias voltage to turn on the current sinks; and
a control signal generator coupled to the memory and the plurality of current sinks, the control signal generator configured to selectively turn on a number of the current sinks based on a compensation voltage value retrieved from the memory.
6. The continuous-time sigma-delta analog-to-digital converter of claim 5 , wherein the reference voltage generator produces the bias voltage based on a band-gap voltage and a resistor created using the same manufacturing process used to create resistors in the RC network.
7. The continuous-time sigma-delta analog-to-digital converter of claim 3 , wherein the common mode adjust circuit further comprises:
a first protection circuit coupled to the first input of the loop filter and to the electrical ground, the first protection circuit configured to provide a current path to the electrical ground when there is a power supply failure; and
a second protection circuit coupled to the second input of the loop filter and to the electrical ground, the second protection circuit configured to provide a current path to the electrical ground when there is a power supply failure.
8-20. (canceled)
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US12/710,889 Active US8390496B2 (en) | 2006-08-31 | 2010-02-23 | System and method for common mode translation |
US12/711,035 Abandoned US20100148844A1 (en) | 2006-08-31 | 2010-02-23 | System And Method For Common Mode Translation |
US12/710,928 Active US8120425B2 (en) | 2006-08-31 | 2010-02-23 | System and method for common mode translation |
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US12/710,928 Active US8120425B2 (en) | 2006-08-31 | 2010-02-23 | System and method for common mode translation |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7936298B2 (en) * | 2009-09-18 | 2011-05-03 | Mediatek Singapore Pte. Ltd. | Integrated circuit and electronic device comprising threshold generation circuitry and method therefor |
JP2012060304A (en) * | 2010-09-07 | 2012-03-22 | Toshiba Corp | Digital/analog converter |
US20150244385A1 (en) * | 2014-02-27 | 2015-08-27 | Qualcomm Incorporated | Circuit interfacing single-ended input to an analog to digital converter |
US10128866B2 (en) * | 2015-10-16 | 2018-11-13 | Sony Semiconductor Solutions Corporation | Fast current mode sigma-delta analog-to-digital converter |
US9520891B1 (en) | 2015-11-17 | 2016-12-13 | International Business Machines Corporation | Successive approximation register converter |
EP3229372B1 (en) | 2016-04-06 | 2019-06-26 | NXP USA, Inc. | System and method to directly couple to analog to digital converter having lower voltage reference |
US11863205B2 (en) | 2021-11-30 | 2024-01-02 | Analog Devices International Unlimited Company | Adaptive bias techniques for amplifiers in sigma delta modulators |
Citations (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2927962A (en) * | 1954-04-26 | 1960-03-08 | Bell Telephone Labor Inc | Transmission systems employing quantization |
US5442352A (en) * | 1994-01-14 | 1995-08-15 | Motorola, Inc. | Linear attenuator for current-mode digital-to-analog converter (DAC) or the like |
US5838200A (en) * | 1997-06-06 | 1998-11-17 | National Semiconductor Corporation | Differential amplifier with switched capacitor common mode feedback |
US5917440A (en) * | 1996-12-31 | 1999-06-29 | Lucent Technologies Inc. | Implementing transmission zeroes in narrowband sigma-delta A/D converters |
US6252989B1 (en) * | 1997-01-07 | 2001-06-26 | Board Of The Regents, The University Of Texas System | Foveated image coding system and method for image bandwidth reduction |
US6351335B1 (en) * | 1999-04-08 | 2002-02-26 | New York University | Extremely high resolution foveated display |
US6459335B1 (en) * | 2000-09-29 | 2002-10-01 | Microchip Technology Incorporated | Auto-calibration circuit to minimize input offset voltage in an integrated circuit analog input device |
US20020175749A1 (en) * | 2001-05-11 | 2002-11-28 | Hedberg Mats Olof Joakim | Differential signal transfer circuit |
US6515464B1 (en) * | 2000-09-29 | 2003-02-04 | Microchip Technology Incorporated | Input voltage offset calibration of an analog device using a microcontroller |
US6693572B1 (en) * | 2003-02-04 | 2004-02-17 | Motorola, Inc. | Digital tuning scheme for continuous-time sigma delta modulation |
US6697001B1 (en) * | 2002-12-19 | 2004-02-24 | Motorola, Inc. | Continuous-time sigma-delta modulator with discrete time common-mode feedback |
US20040189388A1 (en) * | 2000-02-15 | 2004-09-30 | Broadcom Corporation | Variable transconductance variable gain amplifier utilizing a degenerated differential pair |
US20040189392A1 (en) * | 2003-03-28 | 2004-09-30 | Nec Electronics Corporation | Voltage control circuit for common mode voltage and method for controlling the same |
US6853323B1 (en) * | 2004-05-04 | 2005-02-08 | Integrated Programmable Communications, Inc. | Differential voltage output digital-to-analog converter |
US20050068213A1 (en) * | 2003-09-25 | 2005-03-31 | Paul-Aymeric Fontaine | Digital compensation of excess delay in continuous time sigma delta modulators |
US6876248B2 (en) * | 2002-02-14 | 2005-04-05 | Rambus Inc. | Signaling accommodation |
US6909543B2 (en) * | 2002-07-22 | 2005-06-21 | Spitz, Inc. | Foveated display system |
US20050179491A1 (en) * | 2002-01-23 | 2005-08-18 | Broadcom Corporation | System and method for a startup circuit for a differential CMOS amplifier |
US20050207596A1 (en) * | 2004-02-16 | 2005-09-22 | Stmicroelectronics S.R.L. | Packaged digital microphone device with auxiliary line-in function |
US6985158B2 (en) * | 2001-10-04 | 2006-01-10 | Eastman Kodak Company | Method and system for displaying an image |
US7009541B1 (en) * | 2004-10-21 | 2006-03-07 | Analog Devices, Inc. | Input common-mode voltage feedback circuit for continuous-time sigma-delta analog-to-digital converter |
US7024171B2 (en) * | 2003-02-25 | 2006-04-04 | Icom America, Incorporated | Fractional-N frequency synthesizer with cascaded sigma-delta converters |
US7042304B2 (en) * | 2002-11-28 | 2006-05-09 | Stmicroelectronics S.R.L. | Circuit device for realizing a non-linear reactive elements scale network |
US7053712B2 (en) * | 2004-07-30 | 2006-05-30 | International Business Machines Corporation | Method and apparatus for controlling common-mode output voltage in fully differential amplifiers |
US7075348B2 (en) * | 2001-12-07 | 2006-07-11 | Mediatek Inc. | Differential charge pump with common-mode feedback compensation |
US7129875B1 (en) * | 2003-10-31 | 2006-10-31 | Texas Instruments Incorporated | Tracking reference system for analog-to-digital converter systems |
US20060244532A1 (en) * | 2005-05-02 | 2006-11-02 | Texas Instruments Incorporated | Circuit and method for switching active loads of operational amplifier input stage |
US7233203B2 (en) * | 2005-08-05 | 2007-06-19 | Realtek Semiconductor Corp. | Differential amplifier |
US20070216557A1 (en) * | 2006-01-30 | 2007-09-20 | Christian Ebner | Delta-sigma analog digital converter with offset compensation |
US7295070B2 (en) * | 2005-06-21 | 2007-11-13 | Analog Devices, Inc. | Flip around switched capacitor amplifier |
US7348838B2 (en) * | 2004-04-27 | 2008-03-25 | Broadcom Corporation | Method and system for DC offset cancellation from a modulated signal |
US7405625B1 (en) * | 2007-04-25 | 2008-07-29 | Analog Devices, Inc. | Common-mode control structures and signal converter systems for use therewith |
US7414557B2 (en) * | 2006-12-15 | 2008-08-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for feedback signal generation in sigma-delta analog-to-digital converters |
US20100066577A1 (en) * | 2008-09-16 | 2010-03-18 | Sheng-Jui Huang | Delta-sigma analog-to-digital converter |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5226159A (en) | 1989-05-15 | 1993-07-06 | International Business Machines Corporation | File lock management in a distributed data processing system |
JPH0619771A (en) | 1992-04-20 | 1994-01-28 | Internatl Business Mach Corp <Ibm> | File management system of shared file by different kinds of clients |
DE69322057T2 (en) | 1992-10-24 | 1999-06-10 | Int Computers Ltd | Distributed data processing system |
US5615373A (en) | 1993-08-26 | 1997-03-25 | International Business Machines Corporation | Data lock management in a distributed file server system determines variable lock lifetime in response to request to access data object |
US5454108A (en) | 1994-01-26 | 1995-09-26 | International Business Machines Corporation | Distributed lock manager using a passive, state-full control-server |
US5692120A (en) | 1994-08-08 | 1997-11-25 | International Business Machines Corporation | Failure recovery apparatus and method for distributed processing shared resource control |
US5742813A (en) | 1994-11-10 | 1998-04-21 | Cadis, Inc. | Method and apparatus for concurrency in an object oriented database using lock inheritance based on class objects |
US5513314A (en) | 1995-01-27 | 1996-04-30 | Auspex Systems, Inc. | Fault tolerant NFS server system and mirroring protocol |
US5745747A (en) | 1995-02-06 | 1998-04-28 | International Business Machines Corporation | Method and system of lock request management in a data processing system having multiple processes per transaction |
US5682537A (en) | 1995-08-31 | 1997-10-28 | Unisys Corporation | Object lock management system with improved local lock management and global deadlock detection in a parallel data processing system |
US5845147A (en) | 1996-03-19 | 1998-12-01 | Emc Corporation | Single lock command for an I/O storage system that performs both locking and I/O data operation |
WO1999012264A2 (en) * | 1997-08-29 | 1999-03-11 | Koninklijke Philips Electronics N.V. | Sigma-delta modulator with improved gain accuracy |
US5963156A (en) * | 1997-10-22 | 1999-10-05 | National Semiconductor Corporation | Sample and hold circuit and method with common mode differential signal feedback for converting single-ended signals to differential signals |
US6529070B1 (en) * | 1999-10-25 | 2003-03-04 | Texas Instruments Incorporated | Low-voltage, broadband operational amplifier |
DE60105819T2 (en) * | 2000-07-05 | 2005-10-06 | Koninklijke Philips Electronics N.V. | A / D CONVERTER WITH INTEGRATED VOLTAGE FOR MICROPHONE |
US6559720B1 (en) * | 2001-10-26 | 2003-05-06 | Maxim Integrated Products, Inc. | GM-controlled current-isolated indirect-feedback instrumentation amplifier |
US6856195B2 (en) * | 2002-06-24 | 2005-02-15 | Texas Instruments Incorporated | Preamplifier system with selectable input impedance |
US6778119B2 (en) * | 2002-11-29 | 2004-08-17 | Sigmatel, Inc. | Method and apparatus for accurate digital-to-analog conversion |
KR100520299B1 (en) * | 2003-09-09 | 2005-10-13 | 삼성전자주식회사 | Current-added-type digital to analog converter and digital to analog converting method thereof |
US7227483B2 (en) * | 2004-09-22 | 2007-06-05 | Dongwon Seo | High-speed and high-accuracy digital-to-analog converter |
US7620121B1 (en) * | 2004-12-09 | 2009-11-17 | Xilinx, Inc. | DC balance compensation for AC-coupled circuits |
US7535258B1 (en) * | 2004-12-15 | 2009-05-19 | Lattice Semiconductor Corporation | Programmable current output and common-mode voltage buffer |
DE102005007632A1 (en) * | 2005-02-18 | 2006-08-24 | Infineon Technologies Ag | Amplifier arrangement and method for adjusting an offset |
US7532065B2 (en) * | 2005-07-12 | 2009-05-12 | Agere Systems Inc. | Analog amplifier having DC offset cancellation circuit and method of offset cancellation for analog amplifiers |
DE102005061813B4 (en) * | 2005-12-23 | 2012-10-11 | Intel Mobile Communications GmbH | receiver circuit |
US7450050B2 (en) * | 2006-04-05 | 2008-11-11 | Snowbush, Inc. | Switched-capacitor reset architecture for opamp |
TWI310264B (en) * | 2006-05-23 | 2009-05-21 | Ind Tech Res Inst | Fully differential sensing apparatus and input common mode feedback circuit thereof |
US7436216B1 (en) * | 2006-06-14 | 2008-10-14 | Xilinx, Inc. | Method and apparatus for a direct current (DC) coupled input buffer |
US7417463B1 (en) * | 2007-09-13 | 2008-08-26 | Gigle Semiconductor Limited | Wireline transmission circuit |
US7348911B2 (en) * | 2006-08-08 | 2008-03-25 | Atmel Corporation | Common mode management between a current-steering DAC and transconductance filter in a transmission system |
US7382192B2 (en) * | 2006-11-07 | 2008-06-03 | Aimtron Technology Corp. | Bias current compensation circuit for a differential input stage |
US7741981B1 (en) * | 2008-12-30 | 2010-06-22 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC |
US8264268B2 (en) * | 2009-07-27 | 2012-09-11 | Electronics And Telecommunications Research Institute | Offset-voltage calibration circuit |
-
2007
- 2007-03-29 US US11/729,487 patent/US7679443B2/en active Active
- 2007-08-31 WO PCT/US2007/077323 patent/WO2008028096A2/en active Application Filing
-
2010
- 2010-02-23 US US12/710,856 patent/US7796066B2/en active Active
- 2010-02-23 US US12/710,889 patent/US8390496B2/en active Active
- 2010-02-23 US US12/711,035 patent/US20100148844A1/en not_active Abandoned
- 2010-02-23 US US12/710,928 patent/US8120425B2/en active Active
Patent Citations (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2927962A (en) * | 1954-04-26 | 1960-03-08 | Bell Telephone Labor Inc | Transmission systems employing quantization |
US5442352A (en) * | 1994-01-14 | 1995-08-15 | Motorola, Inc. | Linear attenuator for current-mode digital-to-analog converter (DAC) or the like |
US5917440A (en) * | 1996-12-31 | 1999-06-29 | Lucent Technologies Inc. | Implementing transmission zeroes in narrowband sigma-delta A/D converters |
US6252989B1 (en) * | 1997-01-07 | 2001-06-26 | Board Of The Regents, The University Of Texas System | Foveated image coding system and method for image bandwidth reduction |
US5838200A (en) * | 1997-06-06 | 1998-11-17 | National Semiconductor Corporation | Differential amplifier with switched capacitor common mode feedback |
US6351335B1 (en) * | 1999-04-08 | 2002-02-26 | New York University | Extremely high resolution foveated display |
US20040189388A1 (en) * | 2000-02-15 | 2004-09-30 | Broadcom Corporation | Variable transconductance variable gain amplifier utilizing a degenerated differential pair |
US6459335B1 (en) * | 2000-09-29 | 2002-10-01 | Microchip Technology Incorporated | Auto-calibration circuit to minimize input offset voltage in an integrated circuit analog input device |
US6515464B1 (en) * | 2000-09-29 | 2003-02-04 | Microchip Technology Incorporated | Input voltage offset calibration of an analog device using a microcontroller |
US20020175749A1 (en) * | 2001-05-11 | 2002-11-28 | Hedberg Mats Olof Joakim | Differential signal transfer circuit |
US6985158B2 (en) * | 2001-10-04 | 2006-01-10 | Eastman Kodak Company | Method and system for displaying an image |
US7075348B2 (en) * | 2001-12-07 | 2006-07-11 | Mediatek Inc. | Differential charge pump with common-mode feedback compensation |
US20050179491A1 (en) * | 2002-01-23 | 2005-08-18 | Broadcom Corporation | System and method for a startup circuit for a differential CMOS amplifier |
US7099786B2 (en) * | 2002-02-14 | 2006-08-29 | Rambus Inc. | Signaling accommodation |
US6876248B2 (en) * | 2002-02-14 | 2005-04-05 | Rambus Inc. | Signaling accommodation |
US6909543B2 (en) * | 2002-07-22 | 2005-06-21 | Spitz, Inc. | Foveated display system |
US7042304B2 (en) * | 2002-11-28 | 2006-05-09 | Stmicroelectronics S.R.L. | Circuit device for realizing a non-linear reactive elements scale network |
US6697001B1 (en) * | 2002-12-19 | 2004-02-24 | Motorola, Inc. | Continuous-time sigma-delta modulator with discrete time common-mode feedback |
US6693572B1 (en) * | 2003-02-04 | 2004-02-17 | Motorola, Inc. | Digital tuning scheme for continuous-time sigma delta modulation |
US7024171B2 (en) * | 2003-02-25 | 2006-04-04 | Icom America, Incorporated | Fractional-N frequency synthesizer with cascaded sigma-delta converters |
US20040189392A1 (en) * | 2003-03-28 | 2004-09-30 | Nec Electronics Corporation | Voltage control circuit for common mode voltage and method for controlling the same |
US20050068213A1 (en) * | 2003-09-25 | 2005-03-31 | Paul-Aymeric Fontaine | Digital compensation of excess delay in continuous time sigma delta modulators |
US7129875B1 (en) * | 2003-10-31 | 2006-10-31 | Texas Instruments Incorporated | Tracking reference system for analog-to-digital converter systems |
US20050207596A1 (en) * | 2004-02-16 | 2005-09-22 | Stmicroelectronics S.R.L. | Packaged digital microphone device with auxiliary line-in function |
US7348838B2 (en) * | 2004-04-27 | 2008-03-25 | Broadcom Corporation | Method and system for DC offset cancellation from a modulated signal |
US6853323B1 (en) * | 2004-05-04 | 2005-02-08 | Integrated Programmable Communications, Inc. | Differential voltage output digital-to-analog converter |
US7053712B2 (en) * | 2004-07-30 | 2006-05-30 | International Business Machines Corporation | Method and apparatus for controlling common-mode output voltage in fully differential amplifiers |
US7009541B1 (en) * | 2004-10-21 | 2006-03-07 | Analog Devices, Inc. | Input common-mode voltage feedback circuit for continuous-time sigma-delta analog-to-digital converter |
US20060244532A1 (en) * | 2005-05-02 | 2006-11-02 | Texas Instruments Incorporated | Circuit and method for switching active loads of operational amplifier input stage |
US7295070B2 (en) * | 2005-06-21 | 2007-11-13 | Analog Devices, Inc. | Flip around switched capacitor amplifier |
US7233203B2 (en) * | 2005-08-05 | 2007-06-19 | Realtek Semiconductor Corp. | Differential amplifier |
US20070216557A1 (en) * | 2006-01-30 | 2007-09-20 | Christian Ebner | Delta-sigma analog digital converter with offset compensation |
US7414557B2 (en) * | 2006-12-15 | 2008-08-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for feedback signal generation in sigma-delta analog-to-digital converters |
US7405625B1 (en) * | 2007-04-25 | 2008-07-29 | Analog Devices, Inc. | Common-mode control structures and signal converter systems for use therewith |
US20100066577A1 (en) * | 2008-09-16 | 2010-03-18 | Sheng-Jui Huang | Delta-sigma analog-to-digital converter |
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US20100156497A1 (en) | 2010-06-24 |
US7796066B2 (en) | 2010-09-14 |
US8390496B2 (en) | 2013-03-05 |
US8120425B2 (en) | 2012-02-21 |
US20100148844A1 (en) | 2010-06-17 |
US20080238746A1 (en) | 2008-10-02 |
US20100148850A1 (en) | 2010-06-17 |
WO2008028096A2 (en) | 2008-03-06 |
WO2008028096A3 (en) | 2008-06-12 |
US7679443B2 (en) | 2010-03-16 |
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