US20100127775A1 - Amplifier for driving external capacitive loads - Google Patents
Amplifier for driving external capacitive loads Download PDFInfo
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- US20100127775A1 US20100127775A1 US12/323,813 US32381308A US2010127775A1 US 20100127775 A1 US20100127775 A1 US 20100127775A1 US 32381308 A US32381308 A US 32381308A US 2010127775 A1 US2010127775 A1 US 2010127775A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/50—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
- H03F3/505—Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/297—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a capacitor
Definitions
- the invention relates generally to an amplifier and, more particularly, to an amplifier having greater stability for driving external capacitive loads.
- Wide band amplifiers typically suffer from multi-pole response due to their topology.
- a very standard technique to improve stability in differential amplifiers is to intentionally add pole zero pairs and improve phase margin.
- Some examples of conventional circuits can be seen in U.S. Pat. Nos. 6,518,737; 7,432,693; and 7,235,959 and U.S. Patent Pre-Grant Pub. Nos. 2007/0241731 and 2006/0273771.
- An embodiment of the present invention accordingly, provides an apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load.
- the apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage has an output node, and wherein the amplifier stage includes a plurality of internal transistors; an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node; a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node; a power transistor coupled between a second input voltage and the intermediate node; a second capacitor coupled between the internal node and the power transistor, wherein the second capacitor provides a third input voltage to the power transistor, wherein the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole; and a feedback stage coupled to the intermediate node and to the amplifier stage, wherein the feedback stage is adapted to output an output voltage to a load
- the amplifier stage further comprises a plurality of differential amplifiers.
- the amplifier stage further comprises a first differential amplifier that receives the first input voltage and the feedback voltage; and a second differential amplifier that receives a plurality of inputs from the first differential amplifier, wherein the second differential amplifier includes the internal node.
- the intermediate stage further comprises a PMOS transistor coupled to the bias voltage at its drain and the output node of the amplifier stage at its gate; and a resistor coupled between the source of the PMOS transistor and the intermediate node.
- the feedback stage further comprises a feedback node coupled to the amplifier stage; an impedance coupled between the intermediate node and the output node; a voltage divider coupled to the output node to the feedback node; a third capacitor coupled between the intermediate node and the feedback node; and a fourth capacitor coupled between the output node and the feedback node.
- the second capacitor is about 150 fF.
- the first capacitor is about 10 pF.
- an apparatus having a zero-pole that is dependant on an ESR and a load.
- the apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage includes: a first current source coupled to the bias voltage; a first FET coupled at its drain to the first current source; a second FET coupled at its drain to the first current source; a second current source coupled to the bias voltage; a third FET coupled to the second current source at its drain and to the source of the first transistor at its gate; a fourth FET coupled to the second current source at its drain and to the source of the second transistor at its gate; a current mirror coupled to the bias voltage; and a transistor coupled to the current mirror at an output node and coupled to the source of the fourth FET at an internal node; an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node; a first capacitor coupled between at least one of the internal transistors at an internal node and
- the amplifier stage further comprises a fifth FET coupled to the source of the third FET at its drain; and a sixth FET coupled to internal node at its drain, wherein the gate of the fifth FET is coupled to the gate of the sixth FET.
- the intermediate stage further comprises a PMOS transistor coupled to the bias voltage at its drain and the output node of the amplifier stage at its gate; and a resistor coupled between the source of the PMOS transistor and the intermediate node.
- an apparatus having a zero-pole that is dependant on an ESR and a load.
- the apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage includes: a first current source coupled to the bias voltage; a first FET coupled at its drain to the first current source; a second FET coupled at its drain to the first current source; a second current source coupled to the bias voltage; a third FET coupled to the second current source at its drain and to the source of the first transistor at its gate; a fourth FET coupled to the second current source at its drain and to the source of the second transistor at its gate; a current mirror coupled to the bias voltage; a transistor coupled to the current mirror at an output node and coupled to the source of the fourth FET at an internal node; a fifth FET coupled to the source of the third FET at its drain; and a sixth FET coupled to internal node at its drain, wherein the gate of the fifth FET is coupled to the gate of the sixth FET;
- FIG. 1 is a block diagram of the amplifier in accordance with a preferred embodiment of the present invention.
- FIG. 2 is a more detailed block diagram of the amplifier of FIG. 1 .
- the reference numeral 100 generally depicts an amplifier in accordance with a preferred embodiment of the present invention.
- the amplifier 100 (which is coupled to load 108 ) is generally comprised of an amplifier stage 102 , an intermediate stage 112 , feedback stage 110 .
- the amplifier stage 102 is generally comprised of a pair of differential amplifiers 104 and 106 coupled to one another in a cascade arrangement.
- the first differential amplifier receives a first input voltage V BG and a feedback voltage through feedback node 118 .
- the outputs of the first differential amplifier are inputs to the second differential amplifier which outputs an output voltage to the intermediate stage at output node 124 .
- capacitors C 1 and C 2 are coupled to an internal node 120 within the second differential amplifier 106 .
- capacitors C 1 and C 2 operate as sense elements and provide a voltage to the node between transistors Q 1 and Q 2 (which are preferably a PMOS FET and an NMOS FET, respectively) and a voltage to intermediate node 122 .
- the first portion of the amplifier stage 102 is a portion of the first differential amplifier 102 .
- this first portion is comprised of a current source 114 , transistors Q 3 and Q 4 , and resistor R 5 , R 6 , and R 7 .
- the current source 114 is coupled to a bias voltage V BIAS and is coupled to the drains of transistors Q 3 and Q 4 (which are preferably PMOS FETs).
- the sources of transistors Q 3 and Q 4 are the coupled to resistors R 5 and R 6 , respectively, and each of resistors R 5 and R 6 is coupled to resistor R 7 .
- the control electrode of transistor Q 4 receives the first input voltage V BG while transistor Q 3 receives a feedback signal through feedback node 118 from the feedback stage 110 .
- the second portion of the amplifier stage 102 is a portion of the differential amplifier 106 .
- this second portion is comprised of a current source 116 , transistors Q 5 , Q 6 , Q 7 , and Q 8 , and resistor R 8 and R 9 .
- the current source 116 is coupled to the bias voltage V BIAS and is coupled to the drains of transistors Q 5 and Q 6 (which are preferably PMOS FETs).
- the sources of transistors Q 3 and Q 4 are the coupled to the drains of transistors Q 7 and Q 8 , which are preferably NMOS FETs and which are biased at their gates by a bias voltage N BIAS .
- the sources of transistors Q 7 and Q 8 are coupled to resistors R 8 and R 9 , respectively.
- the control electrode of transistor Q 5 is coupled to the source of transistor Q 3 while transistor Q 6 is coupled to the an electrode of transistor Q 4 .
- the third portion of the amplifier stage is portion of the differential amplifier 106 .
- this third portion is comprised of a current mirror Q 9 and Q 10 , capacitor C 5 , resistor R 10 , and transistors Q 11 , and Q 12 .
- current mirror Q 9 and Q 10 (which are preferably PMOS FETs) is coupled to the bias voltage V BIAS .
- Transistor Q 11 is coupled between the source of transistor Q 9 and the source of transistor Q 5 while transistor Q 12 is coupled to the source of transistor Q 10 and is coupled to the source of transistor Q 6 at internal node 120 .
- Each of these transistor Q 11 and Q 12 (which are preferably bipolar NPN transistors) receives an input voltage V b at its respective control node.
- capacitor C 5 and resistor R 10 are coupled between the bias voltage V BIAS and the source of transistor Q 10 (at the output node 124 ).
- the intermediate stage 112 is generally comprised of transistor Q 1 and resistor R 1 .
- Transistor Q 1 is coupled at one of its electrodes to the bias voltage V BIAS , its control electrode to the output node 124 , and to resistor R 1 (at control node 126 ) at its other electrode. Resistor R 1 is then coupled between the control node 126 and the intermediate node 122 .
- power transistor Q 2 preferably an NMOS FET
- the feedback circuit 110 is generally comprised of resistor R 2 , capacitors C 3 and C 4 , and voltage divider R 3 and R 4 .
- R 2 is generally described as the effective series resistance or ESR resistance, which is coupled to the intermediate node 122 and the load 108 (which is generally comprised of capacitor C LOAD and resistor R LOAD ) at output node 128 .
- Capacitor C 3 is coupled between the intermediate node 122 and the feedback node 118 while capacitor is coupled between the output node 128 and the feedback node 118 .
- the voltage divider R 3 and R 4 is coupled between the output node 128 and ground, and the feedback node 118 is coupled to the voltage divider between resistors R 3 and R 4 .
- capacitors C 1 and C 2 One difference between circuit 100 and other amplifier circuits is the use of capacitors C 1 and C 2 .
- Capacitor C 1 (which is preferably about 150 fF) is coupled between internal node 120 and control node 126
- capacitor C 2 (which is preferably about 10 pF) is coupled between internal node 120 and intermediate node 122 .
- One reason for employing these capacitors is to control the position of the zero-pole in the transfer function. In the s-domain, the output voltage V OUT at intermediate node 122 would be as follows:
- V GATE V OUT ⁇ ( 1 + sR EFF ⁇ C LOAD 1 + sR 2 ⁇ C LOAD ) ( 1 )
- the signal current ISIG would also be:
- Equation 2 can then be simplified as follows:
- Equation (3) the signal current I SIG has a zero which is not only dependent on the R 2 (ESR) but also on the value of the load resistance, and the ratio of capacitor C 1 to capacitor C 2 controls the location of zero-pole with respect to the pole created by capacitor C load and the effective resistance R eff of the feedback stage 110 and load 108 .
- the configuration of amplifier 100 thus, makes it possible to have a zero-pole that tracks the output pole.
- the design methodology employed can generate zeros in the transfer function, improving the phase loss.
- this design methodology several assumptions are made: there are two (possibly more) nodes with different gains and phase relations; and the two nodes are algebraically related to one another. With these assumptions, the following formula an be written:
- V 1 f ⁇ ( V 2 ) ( 6 )
- Equation (7) additional terms in the numerator of I SIG will generally be present.
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Abstract
Description
- The invention relates generally to an amplifier and, more particularly, to an amplifier having greater stability for driving external capacitive loads.
- Wide band amplifiers typically suffer from multi-pole response due to their topology. A very standard technique to improve stability in differential amplifiers is to intentionally add pole zero pairs and improve phase margin. Some examples of conventional circuits can be seen in U.S. Pat. Nos. 6,518,737; 7,432,693; and 7,235,959 and U.S. Patent Pre-Grant Pub. Nos. 2007/0241731 and 2006/0273771.
- An embodiment of the present invention, accordingly, provides an apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load. The apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage has an output node, and wherein the amplifier stage includes a plurality of internal transistors; an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node; a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node; a power transistor coupled between a second input voltage and the intermediate node; a second capacitor coupled between the internal node and the power transistor, wherein the second capacitor provides a third input voltage to the power transistor, wherein the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole; and a feedback stage coupled to the intermediate node and to the amplifier stage, wherein the feedback stage is adapted to output an output voltage to a load, and wherein the feedback stage provides a feedback voltage to the amplifier stage.
- In accordance with another embodiment of the present invention, the amplifier stage further comprises a plurality of differential amplifiers.
- In accordance with another embodiment of the present invention, the amplifier stage further comprises a first differential amplifier that receives the first input voltage and the feedback voltage; and a second differential amplifier that receives a plurality of inputs from the first differential amplifier, wherein the second differential amplifier includes the internal node.
- In accordance with another embodiment of the present invention, the intermediate stage further comprises a PMOS transistor coupled to the bias voltage at its drain and the output node of the amplifier stage at its gate; and a resistor coupled between the source of the PMOS transistor and the intermediate node.
- In accordance with another embodiment of the present invention, the feedback stage further comprises a feedback node coupled to the amplifier stage; an impedance coupled between the intermediate node and the output node; a voltage divider coupled to the output node to the feedback node; a third capacitor coupled between the intermediate node and the feedback node; and a fourth capacitor coupled between the output node and the feedback node.
- In accordance with another embodiment of the present invention, the second capacitor is about 150 fF.
- In accordance with another embodiment of the present invention, the first capacitor is about 10 pF.
- In accordance with another embodiment of the present invention, an apparatus having a zero-pole that is dependant on an ESR and a load. The apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage includes: a first current source coupled to the bias voltage; a first FET coupled at its drain to the first current source; a second FET coupled at its drain to the first current source; a second current source coupled to the bias voltage; a third FET coupled to the second current source at its drain and to the source of the first transistor at its gate; a fourth FET coupled to the second current source at its drain and to the source of the second transistor at its gate; a current mirror coupled to the bias voltage; and a transistor coupled to the current mirror at an output node and coupled to the source of the fourth FET at an internal node; an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node; a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node; a power transistor coupled between a second input voltage and the intermediate node; a second capacitor coupled between the internal node and the power transistor, wherein the second capacitor provides a third input voltage to the power transistor, wherein the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole; and a feedback stage coupled to the intermediate node and to the amplifier stage, wherein the feedback stage is adapted to output an output voltage to a load, and wherein the feedback stage provides a feedback voltage to the gate of the first FET.
- In accordance with another embodiment of the present invention, the amplifier stage further comprises a fifth FET coupled to the source of the third FET at its drain; and a sixth FET coupled to internal node at its drain, wherein the gate of the fifth FET is coupled to the gate of the sixth FET.
- In accordance with another embodiment of the present invention, the intermediate stage further comprises a PMOS transistor coupled to the bias voltage at its drain and the output node of the amplifier stage at its gate; and a resistor coupled between the source of the PMOS transistor and the intermediate node.
- In accordance with another embodiment of the present invention, an apparatus having a zero-pole that is dependant on an ESR and a load. The apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, wherein the amplifier stage includes: a first current source coupled to the bias voltage; a first FET coupled at its drain to the first current source; a second FET coupled at its drain to the first current source; a second current source coupled to the bias voltage; a third FET coupled to the second current source at its drain and to the source of the first transistor at its gate; a fourth FET coupled to the second current source at its drain and to the source of the second transistor at its gate; a current mirror coupled to the bias voltage; a transistor coupled to the current mirror at an output node and coupled to the source of the fourth FET at an internal node; a fifth FET coupled to the source of the third FET at its drain; and a sixth FET coupled to internal node at its drain, wherein the gate of the fifth FET is coupled to the gate of the sixth FET; an intermediate stage that is coupled to the output node of the amplifier stage, wherein the intermediate stage outputs an intermediate voltage to an intermediate node; a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node; a power transistor coupled between a second input voltage and the intermediate node; a second capacitor coupled between the intermediate node and the power transistor, wherein the second capacitor provides a third input voltage to the power transistor, wherein the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole; and a feedback stage coupled to the intermediate node and to the amplifier stage, wherein the feedback stage is adapted to output an output voltage to a load, and wherein the feedback stage includes: a feedback node coupled to the gate of the first FET; an impedance coupled between the intermediate node and the output node; a voltage divider coupled to the output node to the feedback node; a third capacitor coupled between the intermediate node and the feedback node; and a fourth capacitor coupled between the output node and the feedback node.
- The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a block diagram of the amplifier in accordance with a preferred embodiment of the present invention; and -
FIG. 2 is a more detailed block diagram of the amplifier ofFIG. 1 . - Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
- Referring now to
FIGS. 1 and 2 of the drawings, thereference numeral 100 generally depicts an amplifier in accordance with a preferred embodiment of the present invention. The amplifier 100 (which is coupled to load 108) is generally comprised of anamplifier stage 102, anintermediate stage 112,feedback stage 110. - As can be seen in
FIG. 1 , theamplifier stage 102 is generally comprised of a pair ofdifferential amplifiers feedback node 118. The outputs of the first differential amplifier are inputs to the second differential amplifier which outputs an output voltage to the intermediate stage atoutput node 124. Additionally, capacitors C1 and C2 are coupled to aninternal node 120 within the seconddifferential amplifier 106. Generally, capacitors C1 and C2 operate as sense elements and provide a voltage to the node between transistors Q1 and Q2 (which are preferably a PMOS FET and an NMOS FET, respectively) and a voltage tointermediate node 122. - Turning to
FIG. 2 , theamplifier stage 102 can be seen in greater detail. The first portion of theamplifier stage 102 is a portion of the firstdifferential amplifier 102. Preferably, this first portion is comprised of acurrent source 114, transistors Q3 and Q4, and resistor R5, R6, and R7. In this first portion, thecurrent source 114 is coupled to a bias voltage VBIAS and is coupled to the drains of transistors Q3 and Q4 (which are preferably PMOS FETs). The sources of transistors Q3 and Q4 are the coupled to resistors R5 and R6, respectively, and each of resistors R5 and R6 is coupled to resistor R7. Additionally, the control electrode of transistor Q4 receives the first input voltage VBG while transistor Q3 receives a feedback signal throughfeedback node 118 from thefeedback stage 110. - The second portion of the
amplifier stage 102 is a portion of thedifferential amplifier 106. Preferably, this second portion is comprised of acurrent source 116, transistors Q5, Q6, Q7, and Q8, and resistor R8 and R9. In this second portion, thecurrent source 116 is coupled to the bias voltage VBIAS and is coupled to the drains of transistors Q5 and Q6 (which are preferably PMOS FETs). The sources of transistors Q3 and Q4 are the coupled to the drains of transistors Q7 and Q8, which are preferably NMOS FETs and which are biased at their gates by a bias voltage NBIAS. The sources of transistors Q7 and Q8 are coupled to resistors R8 and R9, respectively. Additionally, the control electrode of transistor Q5 is coupled to the source of transistor Q3 while transistor Q6 is coupled to the an electrode of transistor Q4. - The third portion of the amplifier stage is portion of the
differential amplifier 106. Preferably, this third portion is comprised of a current mirror Q9 and Q10, capacitor C5, resistor R10, and transistors Q11, and Q12. In this third portion, current mirror Q9 and Q10 (which are preferably PMOS FETs) is coupled to the bias voltage VBIAS. Transistor Q11 is coupled between the source of transistor Q9 and the source of transistor Q5 while transistor Q12 is coupled to the source of transistor Q10 and is coupled to the source of transistor Q6 atinternal node 120. Each of these transistor Q11 and Q12 (which are preferably bipolar NPN transistors) receives an input voltage Vb at its respective control node. Additionally, capacitor C5 and resistor R10 are coupled between the bias voltage VBIAS and the source of transistor Q10 (at the output node 124). - As can be seen in both
FIGS. 1 and 2 , theintermediate stage 112 is generally comprised of transistor Q1 and resistor R1. Transistor Q1 is coupled at one of its electrodes to the bias voltage VBIAS, its control electrode to theoutput node 124, and to resistor R1 (at control node 126) at its other electrode. Resistor R1 is then coupled between thecontrol node 126 and theintermediate node 122. Additionally, power transistor Q2 (preferably an NMOS FET) is coupled at its control electrode to thecontrol node 126, and is coupled to an input voltage VIN and thefeedback circuit 110 at its other electrodes. - Also, as can be seen in
FIGS. 1 and 2 , thefeedback circuit 110 is generally comprised of resistor R2, capacitors C3 and C4, and voltage divider R3 and R4. R2 is generally described as the effective series resistance or ESR resistance, which is coupled to theintermediate node 122 and the load 108 (which is generally comprised of capacitor CLOAD and resistor RLOAD) atoutput node 128. Capacitor C3 is coupled between theintermediate node 122 and thefeedback node 118 while capacitor is coupled between theoutput node 128 and thefeedback node 118. Additionally, the voltage divider R3 and R4 is coupled between theoutput node 128 and ground, and thefeedback node 118 is coupled to the voltage divider between resistors R3 and R4. - One difference between
circuit 100 and other amplifier circuits is the use of capacitors C1 and C2. Capacitor C1 (which is preferably about 150 fF) is coupled betweeninternal node 120 andcontrol node 126, and capacitor C2 (which is preferably about 10 pF) is coupled betweeninternal node 120 andintermediate node 122. One reason for employing these capacitors is to control the position of the zero-pole in the transfer function. In the s-domain, the output voltage VOUT atintermediate node 122 would be as follows: -
- The signal current ISIG would also be:
-
- Equation 2 can then be simplified as follows:
-
- It is, therefore, clear from Equation (3) that the signal current ISIG has a zero which is not only dependent on the R2 (ESR) but also on the value of the load resistance, and the ratio of capacitor C1 to capacitor C2 controls the location of zero-pole with respect to the pole created by capacitor Cload and the effective resistance Reff of the
feedback stage 110 andload 108. The configuration ofamplifier 100, thus, makes it possible to have a zero-pole that tracks the output pole. - Preferably, the design methodology employed can generate zeros in the transfer function, improving the phase loss. In this design methodology, several assumptions are made: there are two (possibly more) nodes with different gains and phase relations; and the two nodes are algebraically related to one another. With these assumptions, the following formula an be written:
-
- Equations can then be incorporated as follows:
-
- As can be seen from Equation (7) additional terms in the numerator of ISIG will generally be present.
- Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
Claims (17)
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US20070188228A1 (en) * | 2006-01-09 | 2007-08-16 | Stmicroelectronics S.A. | Series voltage regulator with low dropout voltage |
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US20120049628A1 (en) * | 2010-08-24 | 2012-03-01 | Texas Instruments Incorporated | Apparatus for charging an external capacitor |
US8492925B2 (en) * | 2010-08-24 | 2013-07-23 | Texas Instruments Incorporated | Apparatus for charging an external capacitor |
EP3107209A3 (en) * | 2015-05-27 | 2017-04-05 | STMicroelectronics Srl | Voltage regulator with improved electrical properties and corresponding control method |
US9684324B2 (en) | 2015-05-27 | 2017-06-20 | Stmicroelectronics S.R.L. | Voltage regulator with improved electrical properties and corresponding control method |
US9964976B2 (en) | 2015-05-27 | 2018-05-08 | Stmicroelectronics S.R.L. | Voltage regulator with improved electrical properties and corresponding control method |
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