US20100059867A1 - Integrated circuit chip with seal ring structure - Google Patents

Integrated circuit chip with seal ring structure Download PDF

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Publication number
US20100059867A1
US20100059867A1 US12/207,490 US20749008A US2010059867A1 US 20100059867 A1 US20100059867 A1 US 20100059867A1 US 20749008 A US20749008 A US 20749008A US 2010059867 A1 US2010059867 A1 US 2010059867A1
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Prior art keywords
seal ring
integrated circuit
analog
circuit chip
ring structure
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Granted
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US12/207,490
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US7667302B1 (en
Inventor
Tien-Chang Chang
Shi-Bai Chen
Tao Cheng
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MediaTek Inc
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MediaTek Inc
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Application filed by MediaTek Inc filed Critical MediaTek Inc
Priority to US12/207,490 priority Critical patent/US7667302B1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, TIEN-CHANG, CHEN, SHI-BAI, CHENG, TAO
Priority to TW098100335A priority patent/TWI441306B/en
Priority to CN2009100002129A priority patent/CN101673733B/en
Priority to US12/650,549 priority patent/US8242586B2/en
Application granted granted Critical
Publication of US7667302B1 publication Critical patent/US7667302B1/en
Publication of US20100059867A1 publication Critical patent/US20100059867A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention related to integrated circuits and, more particularly, to a seal ring structure of an integrated circuit chip having both a digital circuit and an analog and/or RF circuit on one chip.
  • an integrated circuit chip includes a seal ring used to protect it from moisture degradation or ionic contamination.
  • the seal ring is made of a stack of metal and contact/via layers and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • an integrated circuit chip which includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block.
  • the seal ring structure comprises a continuous outer seal ring and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block.
  • FIG. 1 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with one preferred embodiment of this invention.
  • FIG. 2 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with another preferred embodiment of this invention.
  • the present invention pertains to an integrated circuit chip with a seal ring structure.
  • the seal ring structure includes an outer seal ring and an inner seal ring.
  • the outer seal ring is a continuous ring, while the inner seal ring is divided into at least two separated portions including a conductive rampart that is situated in front of a sensitive analog and/or RF circuit block of the integrated circuit chip.
  • the conductive rampart of the inner seal ring shields the analog and/or RF circuit from noise, which may propagate through the outer seal ring, thereby reducing the noise-coupling effects.
  • the continuous outer seal ring keeps the moisture and corrosive substances from entering the IC.
  • FIG. 1 is a schematic, planar view of an integrated circuit chip 10 with a seal ring structure 12 in accordance with one preferred embodiment of this invention.
  • the integrated circuit chip 10 comprises at least one analog and/or RF circuit block 14 , a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16 .
  • the integrated circuit chip 10 may further comprise a plurality of input/output (I/O) pads 20 .
  • I/O input/output
  • noise may originate from a digital power V DD signal line or a signal out pad 20 a of the digital circuit 16 , for example, propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit 14 .
  • a possible noise propagation path 30 is indicated in FIG. 1 .
  • the present invention aims to tackle this problem.
  • the seal ring structure 12 which is disposed along the periphery of the chip, includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124 .
  • the inner seal ring 124 is divided into two portions including a first portion 124 a and a second portion 124 b. Though the inner seal ring 124 is divided into two portions in this embodiment, it could be divided into more portions.
  • the first portion 124 a and a second portion 124 b may have substantially the same structure, which may be made of a stack of metal and contact/via layers and may be manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • the second portion 124 b serves as an isolated conductive rampart that is situated in front of the analog and/or RF circuit block 14 for shielding the noise propagating through the continuous outer seal ring 122 .
  • the length of the second portion 124 b is equal to or greater than the length of the shielded analog and/or RF circuit block 14 .
  • FIG. 2 is a schematic, planar view of an integrated circuit chip 10 a with a seal ring structure 12 in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like regions, layers or elements.
  • the integrated circuit chip 10 a comprises at least one analog and/or RF circuit block 14 , a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16 .
  • the integrated circuit chip 10 a may further comprises a plurality of input/output (I/O) pads 20 .
  • Noise which may originate from a digital power V DD signal line or a signal out pad 20 a of the digital circuit 16 , propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit block 14 .
  • the seal ring structure 12 includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124 .
  • the inner seal ring 124 is divided into two portions including a first portion 124 a and a second portion 124 b. Though the inner seal ring 124 is divided into two portions in this embodiment, it could be divided into more portions.
  • the first portion 124 a and a second portion 124 b may have substantially the same ring structure, which may be made of a stack of metal and contact/via layers and may be manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • the second portion 124 b serves as an isolated conductive rampart for shielding the noise propagating through the continuous outer seal ring 122 .
  • the length of the second portion 124 b is equal to or greater than the length of the shielded analog and/or RF circuit block 14 .
  • the second portion 124 b may be coupled to an independent ground or an independent supply voltage. According to this invention, the second portion 124 b may be coupled to the independent ground through an independent pad and an interconnection trace.
  • independent used herein means that the ground, pad or supply voltage is not commonly used by the analog circuit, RF circuit or digital circuit.
  • the second portion 124 b may be electrically coupled to an independent pad 20 b through an interconnection trace 124 c.
  • the interconnection trace 124 c may be comprised of a topmost metal layer of the integrated circuit chip 10 a and an aluminum layer (not shown). By doing this, the second portion 124 b could be coupled to an independent ground (not shown) or an independent supply voltage, such as V SS , and the noise coupling can be significantly reduced.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An integrated circuit chip includes an analog and/or RF circuit block, a digital circuit, and a seal ring structure surrounding and protecting the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring, and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention related to integrated circuits and, more particularly, to a seal ring structure of an integrated circuit chip having both a digital circuit and an analog and/or RF circuit on one chip.
  • 2. Description of the Prior Art
  • Advances in fabrication technology have enabled entire functional blocks, which previously had been implemented as plural chips on a circuit board, to be integrated onto a single IC. One particularly significant development is mixed-signal circuits, which combine analog circuitry and digital logic circuitry onto a single IC.
  • However, a major technical hurdle to implementing mixed-signal circuits has been the coupling of noise between different portions of the IC, for example, from the digital to the analog portions of the IC.
  • Ordinarily, an integrated circuit chip includes a seal ring used to protect it from moisture degradation or ionic contamination. Typically, the seal ring is made of a stack of metal and contact/via layers and is manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • It has been found that the noise, such as those come from a digital power signal line such as VDD or signal pad of a digital circuit, propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit.
    • SUMMARY OF THE INVENTION
  • It is one object of the present invention to provide an improved seal ring structure of an integrated circuit chip, which is capable of reducing a noise such as those coupling from a digital circuit.
  • To achieve the goals of the invention, an integrated circuit chip is provided, which includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
  • FIG. 1 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with one preferred embodiment of this invention; and
  • FIG. 2 is a schematic, planar view of an integrated circuit chip with a seal ring structure in accordance with another preferred embodiment of this invention.
    •  DETAILED DESCRIPTION
  • The present invention pertains to an integrated circuit chip with a seal ring structure. The seal ring structure includes an outer seal ring and an inner seal ring. The outer seal ring is a continuous ring, while the inner seal ring is divided into at least two separated portions including a conductive rampart that is situated in front of a sensitive analog and/or RF circuit block of the integrated circuit chip.
  • The conductive rampart of the inner seal ring shields the analog and/or RF circuit from noise, which may propagate through the outer seal ring, thereby reducing the noise-coupling effects. The continuous outer seal ring keeps the moisture and corrosive substances from entering the IC.
  • Please refer to FIG. 1. FIG. 1 is a schematic, planar view of an integrated circuit chip 10 with a seal ring structure 12 in accordance with one preferred embodiment of this invention. As shown in FIG. 1, the integrated circuit chip 10 comprises at least one analog and/or RF circuit block 14, a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16.
  • The integrated circuit chip 10 may further comprise a plurality of input/output (I/O) pads 20. As previously described, noise may originate from a digital power VDD signal line or a signal out pad 20a of the digital circuit 16, for example, propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit 14. A possible noise propagation path 30 is indicated in FIG. 1. The present invention aims to tackle this problem.
  • According to the present invention, the seal ring structure 12, which is disposed along the periphery of the chip, includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124. The inner seal ring 124 is divided into two portions including a first portion 124 a and a second portion 124 b. Though the inner seal ring 124 is divided into two portions in this embodiment, it could be divided into more portions.
  • The first portion 124 a and a second portion 124 b may have substantially the same structure, which may be made of a stack of metal and contact/via layers and may be manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • The second portion 124 b serves as an isolated conductive rampart that is situated in front of the analog and/or RF circuit block 14 for shielding the noise propagating through the continuous outer seal ring 122. Preferably, the length of the second portion 124 b is equal to or greater than the length of the shielded analog and/or RF circuit block 14.
  • FIG. 2 is a schematic, planar view of an integrated circuit chip 10 a with a seal ring structure 12 in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like regions, layers or elements. As shown in FIG. 2, likewise, the integrated circuit chip 10 a comprises at least one analog and/or RF circuit block 14, a digital circuit 16 and a seal ring structure 12 surrounding and protecting the analog and/or RF circuit block 14 and digital circuit 16.
  • The integrated circuit chip 10 a may further comprises a plurality of input/output (I/O) pads 20. Noise, which may originate from a digital power VDD signal line or a signal out pad 20 a of the digital circuit 16, propagates through the seal ring and adversely affects the performance of the sensitive analog and/or RF circuit block 14.
  • The seal ring structure 12 includes a continuous outer seal ring 122 and a discontinuous inner seal ring 124. The inner seal ring 124 is divided into two portions including a first portion 124 a and a second portion 124 b. Though the inner seal ring 124 is divided into two portions in this embodiment, it could be divided into more portions.
  • The first portion 124 a and a second portion 124 b may have substantially the same ring structure, which may be made of a stack of metal and contact/via layers and may be manufactured step by step as sequential depositions of insulators and metals in conjunction together with the fabrication of the integrated circuit elements.
  • The second portion 124 b serves as an isolated conductive rampart for shielding the noise propagating through the continuous outer seal ring 122. Preferably, the length of the second portion 124 b is equal to or greater than the length of the shielded analog and/or RF circuit block 14.
  • According to this invention, the second portion 124 b may be coupled to an independent ground or an independent supply voltage. According to this invention, the second portion 124 b may be coupled to the independent ground through an independent pad and an interconnection trace. The term “independent” used herein means that the ground, pad or supply voltage is not commonly used by the analog circuit, RF circuit or digital circuit.
  • The second portion 124 b may be electrically coupled to an independent pad 20 b through an interconnection trace 124 c. The interconnection trace 124 c may be comprised of a topmost metal layer of the integrated circuit chip 10 a and an aluminum layer (not shown). By doing this, the second portion 124 b could be coupled to an independent ground (not shown) or an independent supply voltage, such as VSS, and the noise coupling can be significantly reduced.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (14)

1. An integrated circuit chip comprising:
an analog and/or RF circuit block;
a seal ring structure surrounding said analog and/or RF circuit block; said seal ring structure comprises:
a continuous outer seal ring; and
a discontinuous inner seal ring divided into at least a first portion and a second portion;
wherein said second portion is situated in front of said analog and/or RF circuit block for shielding a noise from interfering said analog and/or RF circuit block.
2. The integrated circuit chip according to claim 1 wherein said noise is originated from a digital circuit in the integrated circuit chip.
3. The integrated circuit chip according to claim 1 wherein said second portion is coupled to an independent ground.
4. The integrated circuit chip according to claim 3 wherein said second portion is coupled to the independent ground through a pad and an interconnection trace.
5. The integrated circuit chip according to claim 4 wherein said interconnection trace is comprised of a topmost metal layer of said integrated circuit chip and an aluminum layer.
6. The integrated circuit chip according to claim 1 wherein said second portion is coupled to an independent supply voltage.
7. The integrated circuit chip according to claim 1 wherein a length of said second portion is equal to or greater than that of said analog and/or RF circuit block.
8. A seal ring structure of an integrated circuit chip, comprising:
a continuous outer seal ring; and
a discontinuous inner seal ring divided into at least a first portion and a second portion, wherein said second portion is situated in front of an analog and/or RF circuit block of said integrated circuit chip for shielding a noise from interfering said analog and/or RF circuit block.
9. The seal ring structure according to claim 8 wherein said noise is originated from a digital circuit in said integrated circuit chip.
10. The seal ring structure according to claim 8 wherein said second portion is coupled to an independent ground.
11. The seal ring structure according to claim 10 wherein said second portion is coupled to said independent ground through a pad and an interconnection trace.
12. The seal ring structure according to claim 11 wherein said interconnection trace is comprised of a topmost metal layer of said integrated circuit chip and an aluminum layer.
13. The seal ring structure according to claim 8 wherein said second portion is coupled to an independent supply voltage.
14. The seal ring structure according to claim 8 wherein a length of said second portion is equal to or greater than that of said analog and/or RF circuit block.
US12/207,490 2008-09-09 2008-09-09 Integrated circuit chip with seal ring structure Active US7667302B1 (en)

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Application Number Priority Date Filing Date Title
US12/207,490 US7667302B1 (en) 2008-09-09 2008-09-09 Integrated circuit chip with seal ring structure
TW098100335A TWI441306B (en) 2008-09-09 2009-01-07 Integrated circuit chip and seal ring structure of an integrated circuit chip
CN2009100002129A CN101673733B (en) 2008-09-09 2009-01-13 Integrated circuit chip and seal ring structure of same
US12/650,549 US8242586B2 (en) 2008-09-09 2009-12-31 Integrated circuit chip with seal ring structure

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US20100059867A1 true US20100059867A1 (en) 2010-03-11

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JP2015092607A (en) * 2011-09-27 2015-05-14 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Semiconductor structure having guard ring
DE102015111848A1 (en) * 2015-06-10 2016-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method
CN107851635A (en) * 2015-07-24 2018-03-27 高通股份有限公司 Conductive seal ring for distribution
US10546822B2 (en) 2017-08-30 2020-01-28 Globalfoundries Inc. Seal ring structure of integrated circuit and method of forming same
WO2020030931A1 (en) 2018-08-09 2020-02-13 Datalase Ltd. Functionalising diacetylene compounds
US11740418B2 (en) 2021-03-23 2023-08-29 Globalfoundries U.S. Inc. Barrier structure with passage for waveguide in photonic integrated circuit

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US9295157B2 (en) * 2012-07-13 2016-03-22 Skyworks Solutions, Inc. Racetrack design in radio frequency shielding applications
CN102832178A (en) * 2012-09-18 2012-12-19 上海工程技术大学 Sealing ring structure used for integrated circuit chip
JP6478395B2 (en) * 2015-03-06 2019-03-06 住友電工デバイス・イノベーション株式会社 Semiconductor device
US10128047B2 (en) 2015-07-19 2018-11-13 Vq Research, Inc. Methods and systems for increasing surface area of multilayer ceramic capacitors
US10236123B2 (en) 2015-07-19 2019-03-19 Vq Research, Inc. Methods and systems to minimize delamination of multilayer ceramic capacitors
US10431508B2 (en) 2015-07-19 2019-10-01 Vq Research, Inc. Methods and systems to improve printed electrical components and for integration in circuits
US10332684B2 (en) 2015-07-19 2019-06-25 Vq Research, Inc. Methods and systems for material cladding of multilayer ceramic capacitors
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US11309412B1 (en) * 2017-05-17 2022-04-19 Northrop Grumman Systems Corporation Shifting the pinch-off voltage of an InP high electron mobility transistor with a metal ring
CN108281421A (en) * 2018-02-12 2018-07-13 上海矽杰微电子有限公司 A kind of domain structure of radio frequency chip

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JP2015092607A (en) * 2011-09-27 2015-05-14 インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ Semiconductor structure having guard ring
DE102015111848A1 (en) * 2015-06-10 2016-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method
DE102015111848B4 (en) * 2015-06-10 2020-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method
CN107851635A (en) * 2015-07-24 2018-03-27 高通股份有限公司 Conductive seal ring for distribution
US10546822B2 (en) 2017-08-30 2020-01-28 Globalfoundries Inc. Seal ring structure of integrated circuit and method of forming same
WO2020030931A1 (en) 2018-08-09 2020-02-13 Datalase Ltd. Functionalising diacetylene compounds
US11740418B2 (en) 2021-03-23 2023-08-29 Globalfoundries U.S. Inc. Barrier structure with passage for waveguide in photonic integrated circuit

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US7667302B1 (en) 2010-02-23
TW201011887A (en) 2010-03-16
CN101673733A (en) 2010-03-17
TWI441306B (en) 2014-06-11
CN101673733B (en) 2012-07-04

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