US20090267641A1 - I/O Driver For Integrated Circuit With Output Impedance Control - Google Patents
I/O Driver For Integrated Circuit With Output Impedance Control Download PDFInfo
- Publication number
- US20090267641A1 US20090267641A1 US12/258,704 US25870408A US2009267641A1 US 20090267641 A1 US20090267641 A1 US 20090267641A1 US 25870408 A US25870408 A US 25870408A US 2009267641 A1 US2009267641 A1 US 2009267641A1
- Authority
- US
- United States
- Prior art keywords
- pull
- array
- nfet
- output
- pfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004044 response Effects 0.000 claims abstract description 17
- 230000007704 transition Effects 0.000 claims abstract description 8
- 230000000295 complement effect Effects 0.000 claims description 26
- 230000004913 activation Effects 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 abstract description 6
- 101000972637 Homo sapiens Protein kintoun Proteins 0.000 description 5
- 102100022660 Protein kintoun Human genes 0.000 description 5
- 238000003491 array Methods 0.000 description 5
- 101150044039 PF12 gene Proteins 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
Definitions
- the present invention relates broadly to I/O drivers for integrated circuits (ICs), and more directly to I/O drivers for improving output impedance response during switching.
- Integrated circuits send signals outside of the IC circuitry using output driver circuits or drivers.
- Input/output (I/O) drivers present signals to output signal pads, which connect to a pin, the set of pins referred to as the packaging.
- the pin or packaging connects to a trace or bus.
- the signal pad displays inherent parasitic resistance, inductance, and capacitance (sometimes referred to as the characteristic package impedance).
- the characteristic package impedance affects transmission of the output signal from the signal pad (i.e., the IC).
- the trace in receipt of the output signal displays transmission line characteristics: resistance, capacitance and inductance (sometimes referred to as the characteristic impedance).
- the characteristic impedance also affects transmission of the output signal from the signal pad.
- Maintaining the output impedance of I/Os is extremely important for maintaining signal integrity of the data being transmitted.
- Various conditions affect signal quality. For example, where the characteristic package impedance at the I/O pad or pin, and the characteristic impedance of the transmission line (i.e., a trace to which the package is connected) are mismatched, signal reflections occur during voltage level switching of (data) signals. The signal reflections result in undesirable signal degradation. Mismatched impedance can occur for any number of reasons. For example, as the manufacturing process, operating temperature, and voltage supply rails vary, the output impedance of the I/O also tends to vary. The problem is acute at switching, where the output impedance response can vary significantly as the output signal (at the pad) transitions between voltage levels.
- Calibrated I/O drivers have been developed to overcome fluctuating I/O output impedance at switching. Calibrated I/Os continually adjust the strength of the output driver stage in an attempt to maintain a constant output impedance at switching. Unfortunately, the output impedance is often linear only over a small range of the output voltage, so a calibrated output does not overcome the problem of fluctuating output impedance for the entire voltage switching range. Switching between logical voltage levels, for example, from a low voltage level to a high voltage level, takes a fixed time period. The initial portion of such a fixed time requires a much larger amount of current than the latter portions of this switching period.
- U.S. Pat. No. 6,268,750 (“the '750 patent”), incorporated by reference, discloses a circuit for flattening the I/O output impedance response at switching, which improved the then-known calibrated I/Os.
- the flattening circuit of the '750 patent includes a combination of pull-up PFETs arranged in a pull-up PFET array.
- the pull-up PFETs are programmatically enabled by a pull-up calibration word pu_n [5:0], and a pull_up signal to drive an I/O output pad high.
- the flattening circuit also includes a combination of pull-down NFETs arranged in a pull-down NFET array.
- the pull-down NFETs are programmatically enabled by a pull-down calibration word pd [5:0], and a pulldown signal to drive the I/O output pad low.
- the FET arrays are sized such that they exhibit conductance values corresponding to their binary weighted bit position in their respective calibration word pu_n[n:0] or pd[n:0]. Each FET has a conductance value about equal to 2 bit position G. Thus, if bit 0 of the calibration word controls a FET with conductance G, bit 1 of the calibration word controls a FET with a conductance 2 G, bit 2 of the calibration word controls a FET with a conductance 4 G, and so on.
- the pull-up PFET array includes an NFET, and included in the pull-down NFET array is a PFET.
- Including the complementary NFET with the pull-up PFETs, and the complementary PFET with the pull-down NFETs enables the output driver to supply more current in the initial stages of voltage transitions in attempt to better control the voltage to current ratio and therefore the output signal integrity at switching. Supplying more current through the complementary NFET results in a flatter overall output resistance response during the voltage transition. For example, during a low-to-high transition, the pull-up NFET is conducting. As the output voltage V o approaches V DD -V t from 0V, the pull-up NFET enters the cut-off region.
- the pull-up NFET is cutoff where (V DD ⁇ Vt) ⁇ V 0 ⁇ V DD , and the pull-up PFET array then determines the driver output impedance.
- the pull-down PFET behaves in a similar fashion during a high-to-low transition.
- the present invention provides an I/O driver circuit that overcomes the shortcomings of conventional I/O drivers.
- the I/O driver circuit of the invention controls I/O output impedances using a combination of FET pull-up and pull-down stages in series with a linear resistive element.
- the pull-up and pull-down stages include respective PFET and NFET arrays, which are controlled to exhibit predefined conductances by a logical circuit and respective pull-up and pull-down calibration words.
- the combined programmed conductance values in the active PFET and NFET devices operate to better maintain output impedance or voltage/current (v/i) output characteristic linearity for the entire switching period, whether transitioning from a first to a second voltage level, or transitioning from the second to the first voltage level.
- the NFETS are arranged in a stack of at least two NFETs in order to provide enhanced ESD protection.
- the I/O driver circuit of the invention may be described as a configuration formed with the active FET-based pull-up and pull-down stages in series with a resistive element that exhibits a large linear resistance.
- the resistive element is included so that its linear resistance value is always a significant portion of the magnitude of the v/i output characteristic at the pad, to better stabilize the output v/i characteristic than known I/O drivers controlled with active FET devices that produce a v/i output characteristic that is not balanced with a substantial conventional resistive element.
- the resistive element should have a magnitude at least as large, and preferably 4 times as large as the active matching element comprising the pull-up and pull-down FET arrays.
- the total series impedance at each pad output includes an eighty-percent contribution from the linear resistive element.
- FIG. 1 is a schematic circuit diagram depicting one embodiment of an I/O driver with v/i output characteristic control of the invention.
- FIG. 2 is a second embodiment of the I/O driver with v/i output characteristic control of the invention.
- FIG. 1 shows one embodiment of an I/O driver with output impedance control for maintaining a substantially flat output impedance response.
- the I/O driver may be described as a transmission gate configuration.
- the configuration comprises a resistive element (R), connected between an active impedance matching element and an I/O output pad (PAD).
- the active impedance matching element is controlled by a logical control circuit (LCC).
- the logical control circuit (LCC) receives a data signal A comprising a time series of voltage state transitions, e.g., between logic one and logic zero, representative of digital I/O data, enable signals EN and PNDRIVE and calibration control words PCW and NCW.
- Calibration control words PCW and NCW control respective PFET pull-up (e.g., to VDD) and NFET pull-down arrays (e.g., to ground) as explained below.
- the logical control circuit utilizes these signals to generate logical control signals to control operation of the individual FET devices comprising pull-up and pull-down stages in the active impedance matching element.
- the active impedance matching element output impedance is therefore controlled by controlling the pull-up and pull-down stages. It is this controlled active output impedance in series combination with the fixed linear resistive element or resistor that defines the pad output response at switching.
- the linear resistive element R may be configured to provide a major portion of the pad output impedance such as 50% to 80%, where the remaining output impedance is provided by the active impedance matching element.
- the combination provides for improved control and linearity in the pad output impedance.
- the linear resistive element R may contribute at least twenty-five (25) ohms of the controlled output impedance response, and preferably about forty (40) ohms.
- the overall linearity of the output driver would likely benefit from improving the linearity of the active impedance matching element.
- Such a calibration analysis may be done on a case by case basis. The designer should determine the bits and corresponding binary weighted v/i response contribution that should be augmented for the extra current at switching.
- the PFET pull-up stage ( 110 ) also comprises a base PFET device PF 1 that is activated by signal PBASE as shown.
- Complementary NFET devices NF 2 (base), NF 4 , NF 6 , NF 8 , NF 10 , NF 12 and NF 14 are connected in parallel with the base PFET (the base bit), and with each PFET device PF 3 , PF 5 , PF 7 , PF 9 , PF 11 , PF 13 in the PFET array (the pull-up stage; 110 ), respectively.
- the complementary base NFET device is activated by a signal PBASEBAR.
- Complementary PFET devices PF 2 (base), PF 4 , PF 6 , PF 8 , PF 10 , PF 12 and PF 14 are connected in parallel with the base NFET (NF 1 ), and with each NFET device in the NFET array (the pull-down stage).
- the complementary base PFET device is activated by a signal NBASEBAR.
- Complementary PFETs: PF 4 , PF 6 , PF 8 , PF 10 , PF 12 and PF 14 are activated by respective signals NB 0 BAR, NB 1 BAR, NB 2 BAR, NB 3 BAR, NB 4 BAR and NB 5 BAR.
- the logical control section LCC includes NAND-based control logic ( 130 ) for generating the signals to control the pull-up stage, and NOR-based control logic ( 140 ) for generating the signals to control the pull-down stage.
- a first NAND GATE 1 In the NAND-based control logic ( 130 ) for controlling the pull-up stage, a first NAND GATE 1 generates control signal PBASE by NAND-ing data input signal (A), enable signal EN (for enabling output I/O driver operation) and a base device activate signal PNDRIVE.
- An inverter element IN 1 connected to the first NAND GATE 1 output inverts signal PBASE to generate signal PBASEBAR.
- PBASEBAR controls the complementary NFET (NF 2 ) connected in parallel with the PFET base device (PF 1 ), as mentioned.
- the 6-bit size of the pull-up array is arbitrary, and defined herein for explanatory purposes only.
- the number of PFETs comprising a pull-up stage ( 110 ), as well as the number of NFETs in the pull-down stage ( 120 ), and corresponding control and calibration logic and calibration words PCW, NCW may be modified to any number of active pull-up PFET (and pull-down NFET) devices arranged in parallel, and in parallel with a complementary NFET device (or a complementary PFET device in the pull-down stage) to accommodate various v/i requirements.
- NOR-based control logic ( 140 ) for controlling the pull-down stage ( 120 ) a first NOR GATE 1 generates control signal NBASE that is applied as a gate input to the NFET base device NF 1 (in the base bit position).
- control signal NBASE data input signal A
- ENBAR for enabling output I/O driver operation
- base device activate signal PNDRIVEBAR are NOR-ed by a first NOR GATE 1 .
- An inverter element IN 8 connected to the first NOR GATE 1 output inverts signal NBASE to generate signal NBASEBAR.
- NBASEBAR controls the complementary PFET PF 2 connected in parallel with the NFET base device NF 1 .
- the NOR-based control logic ( 140 ) includes six other NOR gates: NOR GATE 2 , NOR GATE 3 , NOR GATE 4 , NOR GATE 5 , NOR GATE 6 and NOR GATE 7 , with NOR outputs for generating activation signals NB 0 , NB 1 , NB 2 , NB 3 , NB 4 and NB 5 . These signals are for activating NFET devices NF 3 , NF 5 , NF 7 , NF 9 , NF 11 and NF 13 , comprising the NFET pull-down array ( 120 ).
- the 6-bit size of the pull-down array is arbitrary and defined herein for explanatory purposes only.
- the number of NFETs comprising a pull-down stage and corresponding control and calibration logic may be modified to any number of active NFET devices arranged in parallel, and individually in parallel with a complementary PFET device to accommodate various v/i requirements.
- FIG. 2 A second embodiment of the I/O driver with output impedance control is shown in FIG. 2 .
- the FIG. 2 embodiment of the inventive I/O driver with a matched/flat output impedance response control is different in a number of respects to the FIG. 1 embodiment.
- the base PFET device PF 1 in the base bit position is the only PFET in the PFET pull-up array ( 210 ) having a complementary NFET device NF 2 connected in parallel.
- the base PFET device PF 1 in the base bit position is the only PFET in the PFET pull-up array ( 210 ) having a complementary NFET device NF 2 connected in parallel.
- the base PFET device PF 1 is activated by the signal PBASE generated by the first NAND Gate 1
- the complementary NFET NF 2 is activated by signal PBASEBAR generated by signal PBASE inverted by inverter IN 1 .
- Each of the six PFET devices PF 3 , PF 5 , PF 7 , PF 9 , PF 11 and PF 13 comprising the PFET pull-up array ( 210 ) are activated by signals PB 0 , PB 1 , PB 2 , P 133 , PB 4 and PB 5 (pull-up calibration word PCW).
- these signals are generated by other six NAND gates of the NAND-based control logic ( 230 ) of the logical control section LCC which are: NAND GATE 2 , NAND GATE 3 , NAND GATE 4 , NAND GATE 5 , NAND GATE 6 and NAND GATE 7 .
- the base NFET device NF 1 in the base bit position is the only NFET in the NFET pull-down NFET array having a complementary PFET device PF 2 connected in parallel.
- the base NFET device NF 1 is activated by the signal NBASE generated by the first NOR Gate 1
- the complementary PFET PF 2 is activated by signal NBASEBAR generated by signal NBASE inverted by inverter IN 2 .
- Each of the six NFET devices NF 3 , NF 5 , NF 7 , NF 9 , NF 11 and NF 13 comprising the NFET pull-down array are activated by signals NB 0 , NB 1 , NB 2 , NB 3 , NB 4 and NB 5 (pull-down calibration word NCW).
- these signals are generated by other six NOR gates of the NOR-based control logic ( 240 ) of the logical control section LCC which are: NOR GATE 2 , NOR GATE 3 , NOR GATE 4 , NOR GATE 5 , NOR GATE 6 and NOR GATE 7 .
- each of NFETs NF 1 , NF 2 , NF 3 , NF 5 , NF 7 , NF 9 , NF 1 1 and NF 13 which are driven by signals NBASE, PBASEBAR, NB 0 , NB 1 , NB 2 , NB 3 , NB 4 and NB 5 , respectively, are stacked in series with NFETs NF 15 , NF 16 , NF 17 , NF 18 , NF 19 , NF 20 , NF 21 and NF 22 , respectively.
- NFETs NF 15 , NF 16 , NF 17 , NF 18 , NF 19 , NF 20 , NF 21 and NF 22 are activated by signal EN.
- the stacked NFETs are included in the FIG. 2 pull-down stage ( 220 ) for additional electrostatic discharge (ESD) protection, for example.
- the use of the comparative large series resistor R provides the appropriate balance with the FET array responses at switching. If 80% of the I/O output impedance at the pad (PAD) comprises the linear resistor R, then only 20% of the output impedance will exhibit variations in linearity due to the source to drain voltage on the PFET and NFET devices comprising the respective pull-up and pull-down stages. Using complementary devices to improve the linearity of that portion of the output impedance derived from the FET devices allows for the reduction in the percentage the series resistor contributes to the overall output impedance while still maintaining output impedance linearity.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
- The present invention relates broadly to I/O drivers for integrated circuits (ICs), and more directly to I/O drivers for improving output impedance response during switching.
- Integrated circuits (ICs) send signals outside of the IC circuitry using output driver circuits or drivers. Input/output (I/O) drivers present signals to output signal pads, which connect to a pin, the set of pins referred to as the packaging. The pin or packaging connects to a trace or bus. The signal pad displays inherent parasitic resistance, inductance, and capacitance (sometimes referred to as the characteristic package impedance). The characteristic package impedance affects transmission of the output signal from the signal pad (i.e., the IC). The trace in receipt of the output signal displays transmission line characteristics: resistance, capacitance and inductance (sometimes referred to as the characteristic impedance). The characteristic impedance also affects transmission of the output signal from the signal pad.
- Maintaining the output impedance of I/Os is extremely important for maintaining signal integrity of the data being transmitted. Various conditions affect signal quality. For example, where the characteristic package impedance at the I/O pad or pin, and the characteristic impedance of the transmission line (i.e., a trace to which the package is connected) are mismatched, signal reflections occur during voltage level switching of (data) signals. The signal reflections result in undesirable signal degradation. Mismatched impedance can occur for any number of reasons. For example, as the manufacturing process, operating temperature, and voltage supply rails vary, the output impedance of the I/O also tends to vary. The problem is acute at switching, where the output impedance response can vary significantly as the output signal (at the pad) transitions between voltage levels.
- Calibrated I/O drivers have been developed to overcome fluctuating I/O output impedance at switching. Calibrated I/Os continually adjust the strength of the output driver stage in an attempt to maintain a constant output impedance at switching. Unfortunately, the output impedance is often linear only over a small range of the output voltage, so a calibrated output does not overcome the problem of fluctuating output impedance for the entire voltage switching range. Switching between logical voltage levels, for example, from a low voltage level to a high voltage level, takes a fixed time period. The initial portion of such a fixed time requires a much larger amount of current than the latter portions of this switching period. U.S. Pat. No. 6,268,750 (“the '750 patent”), incorporated by reference, discloses a circuit for flattening the I/O output impedance response at switching, which improved the then-known calibrated I/Os.
- The flattening circuit of the '750 patent includes a combination of pull-up PFETs arranged in a pull-up PFET array. The pull-up PFETs are programmatically enabled by a pull-up calibration word pu_n [5:0], and a pull_up signal to drive an I/O output pad high. The flattening circuit also includes a combination of pull-down NFETs arranged in a pull-down NFET array. The pull-down NFETs are programmatically enabled by a pull-down calibration word pd [5:0], and a pulldown signal to drive the I/O output pad low. The FET arrays are sized such that they exhibit conductance values corresponding to their binary weighted bit position in their respective calibration word pu_n[n:0] or pd[n:0]. Each FET has a conductance value about equal to 2bit positionG. Thus, if
bit 0 of the calibration word controls a FET with conductance G,bit 1 of the calibration word controls a FET with a conductance 2 G,bit 2 of the calibration word controls a FET with a conductance 4 G, and so on. - In effect, as the calibration word binary count increments, more resistors are added in parallel in the driver FET array, and reflected in the output impedance response. The construction of the '750 patent flattening circuit requires separate and independent calibration words for each of the pull-up PFET and pull-down NFET arrays. For that matter, due to the non-linear nature of the FET array operation at the time of switching, the output impedance over the different stages of the switching period can still vary undesirably.
- Included in the pull-up PFET array is an NFET, and included in the pull-down NFET array is a PFET. Including the complementary NFET with the pull-up PFETs, and the complementary PFET with the pull-down NFETs enables the output driver to supply more current in the initial stages of voltage transitions in attempt to better control the voltage to current ratio and therefore the output signal integrity at switching. Supplying more current through the complementary NFET results in a flatter overall output resistance response during the voltage transition. For example, during a low-to-high transition, the pull-up NFET is conducting. As the output voltage Vo approaches VDD-Vt from 0V, the pull-up NFET enters the cut-off region. The pull-up NFET is cutoff where (VDD−Vt)≦V0≦VDD, and the pull-up PFET array then determines the driver output impedance. The pull-down PFET behaves in a similar fashion during a high-to-low transition.
- The present invention provides an I/O driver circuit that overcomes the shortcomings of conventional I/O drivers.
- The I/O driver circuit of the invention controls I/O output impedances using a combination of FET pull-up and pull-down stages in series with a linear resistive element. The pull-up and pull-down stages include respective PFET and NFET arrays, which are controlled to exhibit predefined conductances by a logical circuit and respective pull-up and pull-down calibration words. The combined programmed conductance values in the active PFET and NFET devices operate to better maintain output impedance or voltage/current (v/i) output characteristic linearity for the entire switching period, whether transitioning from a first to a second voltage level, or transitioning from the second to the first voltage level. For that matters the NFETS are arranged in a stack of at least two NFETs in order to provide enhanced ESD protection.
- The I/O driver circuit of the invention may be described as a configuration formed with the active FET-based pull-up and pull-down stages in series with a resistive element that exhibits a large linear resistance. The resistive element is included so that its linear resistance value is always a significant portion of the magnitude of the v/i output characteristic at the pad, to better stabilize the output v/i characteristic than known I/O drivers controlled with active FET devices that produce a v/i output characteristic that is not balanced with a substantial conventional resistive element. As such the resistive element should have a magnitude at least as large, and preferably 4 times as large as the active matching element comprising the pull-up and pull-down FET arrays. As preferred, the total series impedance at each pad output includes an eighty-percent contribution from the linear resistive element.
- In order that the manner in which the above recited and other advantages of the invention may be obtained, a more particular description of the invention briefly described above is rendered by reference to specific embodiments thereof that are illustrated in the appended drawings. Understanding that these drawings depict typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention is described and explained with additional specificity and detail through use of the accompanying drawings in which:
-
FIG. 1 is a schematic circuit diagram depicting one embodiment of an I/O driver with v/i output characteristic control of the invention; and -
FIG. 2 is a second embodiment of the I/O driver with v/i output characteristic control of the invention. - Reference will now be made in detail to the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
-
FIG. 1 shows one embodiment of an I/O driver with output impedance control for maintaining a substantially flat output impedance response. The I/O driver may be described as a transmission gate configuration. The configuration comprises a resistive element (R), connected between an active impedance matching element and an I/O output pad (PAD). The active impedance matching element is controlled by a logical control circuit (LCC). The logical control circuit (LCC) receives a data signal A comprising a time series of voltage state transitions, e.g., between logic one and logic zero, representative of digital I/O data, enable signals EN and PNDRIVE and calibration control words PCW and NCW. Calibration control words PCW and NCW control respective PFET pull-up (e.g., to VDD) and NFET pull-down arrays (e.g., to ground) as explained below. - The logical control circuit (LCC) utilizes these signals to generate logical control signals to control operation of the individual FET devices comprising pull-up and pull-down stages in the active impedance matching element. The active impedance matching element output impedance is therefore controlled by controlling the pull-up and pull-down stages. It is this controlled active output impedance in series combination with the fixed linear resistive element or resistor that defines the pad output response at switching.
- The linear resistive element R may be configured to provide a major portion of the pad output impedance such as 50% to 80%, where the remaining output impedance is provided by the active impedance matching element. The combination provides for improved control and linearity in the pad output impedance. For example, when the desired output impedance is fifty (50) ohms, the linear resistive element R may contribute at least twenty-five (25) ohms of the controlled output impedance response, and preferably about forty (40) ohms. As such, the overall linearity of the output driver would likely benefit from improving the linearity of the active impedance matching element. Such a calibration analysis may be done on a case by case basis. The designer should determine the bits and corresponding binary weighted v/i response contribution that should be augmented for the extra current at switching.
- The active impedance matching element comprises a PFET pull-up stage (110) and an NFET pull down stage (120). The PFET pull-up stage comprises an array of pull-up PFETs. PF3, PF5, PF7, PF9, PF11 and PF13. The six PFETs exhibit conductance values when activated by the pull-up calibration word (PCW) that corresponds to multiples of their bit weighted positions in the array, as is known. The bits comprising the pull-up calibration word are shown individually as signals PB0, PB1, PB2, PB3, PB4 and PB5. The PFET pull-up stage (110) also comprises a base PFET device PF1 that is activated by signal PBASE as shown. Complementary NFET devices NF2 (base), NF4, NF6, NF8, NF10, NF12 and NF14 are connected in parallel with the base PFET (the base bit), and with each PFET device PF3, PF5, PF7, PF9, PF11, PF13 in the PFET array (the pull-up stage; 110), respectively. The complementary base NFET device is activated by a signal PBASEBAR. Complementary NFETs: NF4, NF6, NF8, NF10, NF12 and NF14 are activated by respective signals PB0BAR, PB1BAR, PB2BAR, PB3BAR, PB4BAR and PB5BAR.
- The NFET pull-down stage (120) comprises an array of pull-down NFETs: NF3, NF5, NF7, NF9, NF11 and NF13. The six NFETs exhibit conductance values when activated by the pull-down calibration word (NCW) that corresponds to multiples of their bit weighted positions in the array, as is known. The bits comprising the pull-down calibration word NCW are shown individually as signals NB0, NB1, NB2, NB3, NB4 and NB5. The pull-down stage also comprises a base NFET device NF1 that is activated by signal NBASE as shown. Complementary PFET devices PF2 (base), PF4, PF6, PF8, PF10, PF12 and PF14 are connected in parallel with the base NFET (NF1), and with each NFET device in the NFET array (the pull-down stage). The complementary base PFET device is activated by a signal NBASEBAR. Complementary PFETs: PF4, PF6, PF8, PF 10, PF12 and PF14 are activated by respective signals NB0BAR, NB1BAR, NB2BAR, NB3BAR, NB4BAR and NB5BAR.
- The logical control section LCC includes NAND-based control logic (130) for generating the signals to control the pull-up stage, and NOR-based control logic (140) for generating the signals to control the pull-down stage.
- In the NAND-based control logic (130) for controlling the pull-up stage, a
first NAND GATE 1 generates control signal PBASE by NAND-ing data input signal (A), enable signal EN (for enabling output I/O driver operation) and a base device activate signal PNDRIVE. An inverter element IN1 connected to thefirst NAND GATE 1 output inverts signal PBASE to generate signal PBASEBAR. PBASEBAR controls the complementary NFET (NF2) connected in parallel with the PFET base device (PF1), as mentioned. The NAND-based control logic includes six other NAND gates:NAND GATE 2,NAND GATE 3,NAND GATE 4,NAND GATE 5, NAND GATE 6 andNAND GATE 7. The six other NAND gates generate NAND-ed outputs that are the activation signals for the PFET devices PF3, PF5, PF7, PF9, PF11, PF13 comprising the pull-up PFET array (110). The six other NAND gates are activated by the data signal A, enable signal EN and the state of the 6 calibration signals B0-B5. As described, the LCC takes B0-B5 and B0BAR-B5BAR to create the NCW and PCW. The combined effect of the PFET array with the impedance contribution of the linear resistive element R improves the v/i output response during data transitioning, e.g., from logic low to logic high. - Inverter elements IN2, IN3, IN4, INS, IN6 and IN7 are connected at the NAND gate outputs to generate signals PB0BAR, PB1BAR, PB2BAR, PB3BAR, PB4BAR and PB5BAR. These inverted NAND output signals control activation of the six complementary NFETs: NF4, NF6, NF8, NF10, NF12 and NF14 of the pull-up array (110), each connected in parallel to ones of the six PFETs PF3, PF5, PF7, PF9, PF11, PF13 comprising the pull-up array 110 (at each PFET respective binary weighted bit position). The reader should note that the 6-bit size of the pull-up array is arbitrary, and defined herein for explanatory purposes only. The number of PFETs comprising a pull-up stage (110), as well as the number of NFETs in the pull-down stage (120), and corresponding control and calibration logic and calibration words PCW, NCW may be modified to any number of active pull-up PFET (and pull-down NFET) devices arranged in parallel, and in parallel with a complementary NFET device (or a complementary PFET device in the pull-down stage) to accommodate various v/i requirements.
- In the NOR-based control logic (140) for controlling the pull-down stage (120), a first NOR
GATE 1 generates control signal NBASE that is applied as a gate input to the NFET base device NF1 (in the base bit position). To generate signal NBASE, data input signal A, an enable signal ENBAR (for enabling output I/O driver operation) and base device activate signal PNDRIVEBAR are NOR-ed by a first NORGATE 1. An inverter element IN8 connected to the first NORGATE 1 output inverts signal NBASE to generate signal NBASEBAR. NBASEBAR controls the complementary PFET PF2 connected in parallel with the NFET base device NF1. - The NOR-based control logic (140) includes six other NOR gates: NOR
GATE 2, NORGATE 3, NORGATE 4, NORGATE 5, NOR GATE 6 and NORGATE 7, with NOR outputs for generating activation signals NB0, NB1, NB2, NB3, NB4 and NB5. These signals are for activating NFET devices NF3, NF5, NF7, NF9, NF11 and NF13, comprising the NFET pull-down array (120). The NOR outputs are enabled by data signal A, NFET enable signal ENBAR and impedance calibration signals B0BAR, B1BAR, B2BAR, B3BAR, B4BAR and B5BAR, respectively. Depending on the state of the signals B0BAR-B5BAR, the various NFETs comprising the array are activated. An active impedance generated by the NFET devices combined with the impedance contribution from the linear resistive element R improves v/i output response at data transitioning, e.g., from logic high to logic low. - Like the first NOR
GATE 1, the other six NOR gates include inverter elements IN8, IN9, IN10 IN11, IN12, IN13 and IN14. The inverter elements invert the NOR outputs to generate signals NB0BAR, NB1BAR, NB2BAR, NB3BAR, NB4BAR and NB5BAR. These (inverted) activation signals are provided as gate inputs to respective ones of the six complementary PFETS: PF4, PF6, PF8, PF10, PF12 and PF14, connected in parallel the NFETs comprising the pull-down array (120), at each NFET respective binary weighted bit position. The reader should note that the 6-bit size of the pull-down array is arbitrary and defined herein for explanatory purposes only. The number of NFETs comprising a pull-down stage and corresponding control and calibration logic may be modified to any number of active NFET devices arranged in parallel, and individually in parallel with a complementary PFET device to accommodate various v/i requirements. - A second embodiment of the I/O driver with output impedance control is shown in
FIG. 2 . TheFIG. 2 embodiment of the inventive I/O driver with a matched/flat output impedance response control is different in a number of respects to theFIG. 1 embodiment. When compared to the pull-up stage (110) of the active matching element in theFIG. 1 embodiment, in the pull-up stage (210) of the matching element in theFIG. 2 embodiment, the base PFET device PF1 in the base bit position is the only PFET in the PFET pull-up array (210) having a complementary NFET device NF2 connected in parallel. Like theFIG. 1 embodiment, the base PFET device PF1 is activated by the signal PBASE generated by thefirst NAND Gate 1, and the complementary NFET NF2 is activated by signal PBASEBAR generated by signal PBASE inverted by inverter IN1. - Each of the six PFET devices PF3, PF5, PF7, PF9, PF11 and PF13 comprising the PFET pull-up array (210) are activated by signals PB0, PB1, PB2, P133, PB4 and PB5 (pull-up calibration word PCW). Like the
FIG. 1 embodiment, these signals are generated by other six NAND gates of the NAND-based control logic (230) of the logical control section LCC which are:NAND GATE 2,NAND GATE 3,NAND GATE 4,NAND GATE 5, NAND GATE 6 andNAND GATE 7. There are no inverted outputs of the PFET pull-up array activation signals in view of the fact that the PFET array does not include the complementary NFETS (NF4, NF6, NF8, NF10, NF12, NF14) included in theFIG. 1 embodiment. - When compared to the pull-down stage (120) of the active matching element in the
FIG. 1 embodiment, in the pull-down stage (220) of the active matching element in theFIG. 2 embodiment, the base NFET device NF1 in the base bit position is the only NFET in the NFET pull-down NFET array having a complementary PFET device PF2 connected in parallel. Like theFIG. 1 embodiment, the base NFET device NF1 is activated by the signal NBASE generated by the first NORGate 1, and the complementary PFET PF2 is activated by signal NBASEBAR generated by signal NBASE inverted by inverter IN2. - Each of the six NFET devices NF3, NF5, NF7, NF9, NF11 and NF13 comprising the NFET pull-down array are activated by signals NB0, NB1, NB2, NB3, NB4 and NB5 (pull-down calibration word NCW). Like the
FIG. 1 embodiment, these signals are generated by other six NOR gates of the NOR-based control logic (240) of the logical control section LCC which are: NORGATE 2, NORGATE 3, NORGATE 4, NORGATE 5, NOR GATE 6 and NORGATE 7. There are no inverted outputs of the NFET pull-up array activation signals in view of the fact that the PFET array does not include the complementary PFETS included in theFIG. 1 embodiment. Significantly, each of NFETs NF1, NF2, NF3, NF5, NF7, NF9,NF1 1 and NF13, which are driven by signals NBASE, PBASEBAR, NB0, NB1, NB2, NB3, NB4 and NB5, respectively, are stacked in series with NFETs NF15, NF16, NF17, NF18, NF19, NF20, NF21 and NF22, respectively. NFETs NF15, NF16, NF17, NF 18, NF19, NF20, NF21 and NF22 are activated by signal EN. The stacked NFETs are included in theFIG. 2 pull-down stage (220) for additional electrostatic discharge (ESD) protection, for example. - As stated, while the complementary FETs improve linearity of the output impedance at switching, e.g., between logic high and low levels, the use of the comparative large series resistor R provides the appropriate balance with the FET array responses at switching. If 80% of the I/O output impedance at the pad (PAD) comprises the linear resistor R, then only 20% of the output impedance will exhibit variations in linearity due to the source to drain voltage on the PFET and NFET devices comprising the respective pull-up and pull-down stages. Using complementary devices to improve the linearity of that portion of the output impedance derived from the FET devices allows for the reduction in the percentage the series resistor contributes to the overall output impedance while still maintaining output impedance linearity. Reducing the percentage of the output impedance contributed by a linear resistive element, or the resistor shown to 50%-60% allows for smaller output devices while maintaining the linearity and the same desired output impedance, as well as less chip area consumed, and lowered output pin capacitance.
- Although a few examples of the present invention are shown and described, it would be appreciated by those skilled in the art that changes might be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/258,704 US8149014B2 (en) | 2008-04-24 | 2008-10-27 | I/O driver for integrated circuit with output impedance control |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/109,285 US7443194B1 (en) | 2008-04-24 | 2008-04-24 | I/O driver for integrated circuit with output impedance control |
US12/258,704 US8149014B2 (en) | 2008-04-24 | 2008-10-27 | I/O driver for integrated circuit with output impedance control |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/109,285 Continuation US7443194B1 (en) | 2008-04-24 | 2008-04-24 | I/O driver for integrated circuit with output impedance control |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090267641A1 true US20090267641A1 (en) | 2009-10-29 |
US8149014B2 US8149014B2 (en) | 2012-04-03 |
Family
ID=39874315
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/109,285 Expired - Fee Related US7443194B1 (en) | 2008-04-24 | 2008-04-24 | I/O driver for integrated circuit with output impedance control |
US12/258,704 Expired - Fee Related US8149014B2 (en) | 2008-04-24 | 2008-10-27 | I/O driver for integrated circuit with output impedance control |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/109,285 Expired - Fee Related US7443194B1 (en) | 2008-04-24 | 2008-04-24 | I/O driver for integrated circuit with output impedance control |
Country Status (1)
Country | Link |
---|---|
US (2) | US7443194B1 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100265622A1 (en) * | 2009-04-15 | 2010-10-21 | International Business Machines Corporation | Robust esd protection circuit, method and design structure for tolerant and failsafe designs |
US20110163608A1 (en) * | 2009-07-21 | 2011-07-07 | Texas Instruments Incorporated | Reducing Corruption of Communication in a Wireless Power Transmission System |
US9911469B1 (en) | 2016-11-10 | 2018-03-06 | Micron Technology, Inc. | Apparatuses and methods for power efficient driver circuits |
US10015027B2 (en) | 2014-10-22 | 2018-07-03 | Micron Technology, Inc. | Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures |
CN109313917A (en) * | 2016-06-01 | 2019-02-05 | 美光科技公司 | Semiconductor device comprising buffer circuits |
US20210391023A1 (en) * | 2017-11-08 | 2021-12-16 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US11386940B2 (en) | 2019-05-30 | 2022-07-12 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8766663B2 (en) * | 2012-06-18 | 2014-07-01 | International Business Machines Corporation | Implementing linearly weighted thermal coded I/O driver output stage calibration |
US10333497B1 (en) | 2018-04-04 | 2019-06-25 | Globalfoundries Inc. | Calibration devices for I/O driver circuits having switches biased differently for different temperatures |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087847A (en) * | 1997-07-29 | 2000-07-11 | Intel Corporation | Impedance control circuit |
US6894529B1 (en) * | 2003-07-09 | 2005-05-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5097148A (en) | 1990-04-25 | 1992-03-17 | At&T Bell Laboratories | Integrated circuit buffer with improved drive capability |
US5134311A (en) | 1990-06-07 | 1992-07-28 | International Business Machines Corporation | Self-adjusting impedance matching driver |
US5430404A (en) | 1992-10-28 | 1995-07-04 | Integrated Device Technology, Inc. | Output driver circuits with enhanced supply-line bounce control and improved VOH characteristic |
US5594373A (en) | 1994-12-20 | 1997-01-14 | Sgs-Thomson Microelectronics, Inc. | Output driver circuitry with selective limited output high voltage |
EP0735687A3 (en) | 1995-03-31 | 1998-03-25 | STMicroelectronics, Inc. | Output driver with programmable drive characteristics |
US5581197A (en) | 1995-05-31 | 1996-12-03 | Hewlett-Packard Co. | Method of programming a desired source resistance for a driver stage |
US5811997A (en) | 1996-04-26 | 1998-09-22 | Silicon Graphics, Inc. | Multi-configurable push-pull/open-drain driver circuit |
US6087853A (en) | 1998-06-22 | 2000-07-11 | Lucent Technologies, Inc. | Controlled output impedance buffer using CMOS technology |
US6118310A (en) | 1998-11-04 | 2000-09-12 | Agilent Technologies | Digitally controlled output driver and method for impedance matching |
US6177817B1 (en) | 1999-04-01 | 2001-01-23 | International Business Machines Corporation | Compensated-current mirror off-chip driver |
US6184730B1 (en) | 1999-11-03 | 2001-02-06 | Pericom Semiconductor Corp. | CMOS output buffer with negative feedback dynamic-drive control and dual P,N active-termination transmission gates |
US6268750B1 (en) | 2000-01-11 | 2001-07-31 | Agilent Technologies, Inc. | Flattened resistance response for an electrical output driver |
US6624671B2 (en) | 2000-05-04 | 2003-09-23 | Exar Corporation | Wide-band replica output current sensing circuit |
US6759868B2 (en) | 2001-02-27 | 2004-07-06 | Agilent Technologies, Inc. | Circuit and method for compensation if high-frequency signal loss on a transmission line |
EP1286469A1 (en) | 2001-07-31 | 2003-02-26 | Infineon Technologies AG | An output driver for integrated circuits and a method for controlling the output impedance of an integrated circuit |
US6437611B1 (en) | 2001-10-30 | 2002-08-20 | Silicon Integrated Systems Corporation | MOS output driver circuit with linear I/V characteristics |
US6812734B1 (en) * | 2001-12-11 | 2004-11-02 | Altera Corporation | Programmable termination with DC voltage level control |
US6949949B2 (en) | 2002-12-17 | 2005-09-27 | Ip-First, Llc | Apparatus and method for adjusting the impedance of an output driver |
US6847235B2 (en) | 2002-12-18 | 2005-01-25 | Texas Instruments Incorporated | Bus driver |
JP4428504B2 (en) * | 2003-04-23 | 2010-03-10 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
US7088127B2 (en) | 2003-09-12 | 2006-08-08 | Rambus, Inc. | Adaptive impedance output driver circuit |
US6943588B1 (en) | 2003-09-24 | 2005-09-13 | Altera Corporation | Dynamically-adjustable differential output drivers |
US7095246B2 (en) | 2004-08-25 | 2006-08-22 | Freescale Semiconductor, Inc. | Variable impedance output buffer |
-
2008
- 2008-04-24 US US12/109,285 patent/US7443194B1/en not_active Expired - Fee Related
- 2008-10-27 US US12/258,704 patent/US8149014B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6087847A (en) * | 1997-07-29 | 2000-07-11 | Intel Corporation | Impedance control circuit |
US6894529B1 (en) * | 2003-07-09 | 2005-05-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8760827B2 (en) * | 2009-04-15 | 2014-06-24 | International Business Machines Corporation | Robust ESD protection circuit, method and design structure for tolerant and failsafe designs |
US20100265622A1 (en) * | 2009-04-15 | 2010-10-21 | International Business Machines Corporation | Robust esd protection circuit, method and design structure for tolerant and failsafe designs |
US20110163608A1 (en) * | 2009-07-21 | 2011-07-07 | Texas Instruments Incorporated | Reducing Corruption of Communication in a Wireless Power Transmission System |
US9318897B2 (en) * | 2009-07-21 | 2016-04-19 | Texas Instruments Incorporated | Reducing corruption of communication in a wireless power transmission system |
US20160308400A1 (en) * | 2009-07-21 | 2016-10-20 | Texas Instruments Incorporated | Reducing corruption of communication in a wireless power transmission system |
US11569673B2 (en) | 2009-07-21 | 2023-01-31 | Texas Instruments Incorporated | Charge control circuitry in a wireless power receiver |
US9954402B2 (en) * | 2009-07-21 | 2018-04-24 | Texas Instruments Incorporated | Reducing corruption of communication in a wireless power transmission system |
US10348537B2 (en) | 2014-10-22 | 2019-07-09 | Micron Technology, Inc. | Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures |
US10015027B2 (en) | 2014-10-22 | 2018-07-03 | Micron Technology, Inc. | Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures |
CN109313917A (en) * | 2016-06-01 | 2019-02-05 | 美光科技公司 | Semiconductor device comprising buffer circuits |
US10381050B2 (en) | 2016-11-10 | 2019-08-13 | Micron Technology, Inc. | Apparatuses and methods for power efficient driver circuits |
US9911469B1 (en) | 2016-11-10 | 2018-03-06 | Micron Technology, Inc. | Apparatuses and methods for power efficient driver circuits |
WO2018089064A1 (en) * | 2016-11-10 | 2018-05-17 | Micron Technology, Inc. | Apparatuses and methods for power efficient driver circuits |
US10825485B2 (en) | 2016-11-10 | 2020-11-03 | Micron Technology, Inc. | Apparatuses and methods for power efficient driver circuits |
TWI659613B (en) * | 2016-11-10 | 2019-05-11 | 美商美光科技公司 | Apparatuses and methods for power efficient driver circuits |
US11804270B2 (en) * | 2017-11-08 | 2023-10-31 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US20210391023A1 (en) * | 2017-11-08 | 2021-12-16 | Samsung Electronics Co., Ltd. | Non-volatile memory device |
US11386940B2 (en) | 2019-05-30 | 2022-07-12 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
US11830575B2 (en) | 2019-05-30 | 2023-11-28 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
US11842791B2 (en) | 2019-05-30 | 2023-12-12 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
US11923039B2 (en) | 2019-05-30 | 2024-03-05 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
US11923038B2 (en) | 2019-05-30 | 2024-03-05 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
US11923040B2 (en) | 2019-05-30 | 2024-03-05 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
US11996161B2 (en) | 2019-05-30 | 2024-05-28 | Micron Technology, Inc. | Apparatuses and methods including multilevel command and address signals |
Also Published As
Publication number | Publication date |
---|---|
US8149014B2 (en) | 2012-04-03 |
US7443194B1 (en) | 2008-10-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8149014B2 (en) | I/O driver for integrated circuit with output impedance control | |
US9300291B2 (en) | Dynamic impedance control for input/output buffers | |
US9391612B2 (en) | Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit | |
US7893710B2 (en) | Termination circuit and impedance matching device including the same | |
KR100780646B1 (en) | On die termination device and semiconductor device which the on die termination device | |
US7683657B2 (en) | Calibration circuit of on-die termination device | |
US7884637B2 (en) | Calibration circuit and semiconductor memory device with the same | |
CN107919148B (en) | Output circuit using calibration circuit, and semiconductor device and system including the same | |
US6667633B2 (en) | Multiple finger off chip driver (OCD) with single level translator | |
US6268750B1 (en) | Flattened resistance response for an electrical output driver | |
US10491216B2 (en) | Termination circuit, semiconductor device and operating method thereof | |
KR100568875B1 (en) | Output driver for use in semiconductor device | |
US10985757B2 (en) | Dynamic impedance control for input/output buffers | |
KR100838366B1 (en) | Calibration circuit of on die termination device that can compensate offset | |
Esch et al. | Design of CMOS IO drivers with less sensitivity to process, voltage, and temperature variations | |
KR20090061313A (en) | Termination circuit of on die termination device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ZAAA | Notice of allowance and fees due |
Free format text: ORIGINAL CODE: NOA |
|
ZAAB | Notice of allowance mailed |
Free format text: ORIGINAL CODE: MN/=. |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:050122/0001 Effective date: 20190821 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
AS | Assignment |
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:051070/0625 Effective date: 20191105 |
|
AS | Assignment |
Owner name: CAVIUM INTERNATIONAL, CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL INTERNATIONAL LTD.;REEL/FRAME:052918/0001 Effective date: 20191231 |
|
AS | Assignment |
Owner name: MARVELL ASIA PTE, LTD., SINGAPORE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CAVIUM INTERNATIONAL;REEL/FRAME:053475/0001 Effective date: 20191231 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20240403 |