US20090224839A1 - Lock loop circuit and method having improved lock time - Google Patents
Lock loop circuit and method having improved lock time Download PDFInfo
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- US20090224839A1 US20090224839A1 US12/042,228 US4222808A US2009224839A1 US 20090224839 A1 US20090224839 A1 US 20090224839A1 US 4222808 A US4222808 A US 4222808A US 2009224839 A1 US2009224839 A1 US 2009224839A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
Definitions
- the present disclosure generally relates to lock loop circuits, and more particularly, to lock loop circuits having a reduced time required to lock frequency and phase.
- Lock loop circuits such as phase lock loop (PLL) circuits provide an output signal having a frequency and phase that is locked to a reference signal. More specifically, PLL circuits use feedback to adjust the output signal so that the frequency and phase of the output signal match the reference signal.
- PLL phase lock loop
- PLL circuits are used in many applications such as radio, telecommunications, computers, and other suitable applications.
- the circuits can be used to, among other things, generate stable frequencies, recover signals from noisy communication signals, and provide clock timing for applications requiring a stable clock.
- Some mobile devices include power management systems that disable phase lock loop circuits when not in use in order to reduce power consumption and increase battery life. Since PLL circuits are used for timing in many devices, it is desirable for the circuit to quickly lock frequency and phase when the power management system re-enables the circuit.
- a typical PLL circuit 100 includes an error detector 102 , a loop filter 104 , a voltage controlled oscillator (VCO) 106 , and a feedback divider 108 .
- the loop filter 104 includes a resistor 110 , a first capacitor 112 , and a second capacitor 114 .
- the resistor 110 is operatively coupled to the error detector 102 and the VCO 106 at one end and the first capacitor 112 at the other end.
- the first capacitor 112 is operatively coupled to the resistor 110 at one end and to ground 116 at the other end.
- the second capacitor 114 is operatively coupled to the error detector 102 and the VCO 106 at one end and ground 116 at the other end.
- the error detector 102 provides an unfiltered VCO control voltage 116 in response to a reference frequency signal 118 and feedback frequency signal 120 . More specifically, the error detector 102 adjusts the unfiltered VCO control voltage 116 to reduce a frequency and phase difference between the reference frequency signal 118 and the feedback frequency signal 120 .
- the loop filter 104 filters the unfiltered VCO control voltage 116 to remove any imperfections and provides a VCO control voltage 122 (e.g., a steering voltage) based thereon.
- the VCO 106 provides an output frequency signal 124 in response to the VCO control voltage 122 .
- the feedback divider 108 provides the feedback frequency signal 120 in response to the output frequency signal 124 .
- the PLL circuit 100 includes a loop precharger 126 to reduce time required for the PLL circuit 100 to lock frequency and phase.
- the loop precharger 108 provides the unfiltered VCO control voltage 116 , which precharges the first and second capacitors 112 , 114 . In this manner, the VCO control voltage signal 122 is adjusted to a desired value faster than PLL circuits without the loop precharger 126 .
- loop precharger 126 reduces time for the PLL circuit 100 to lock the frequency and phase of the output frequency signal 124 , it is desirable to further reduce the time required to lock the frequency and phase.
- first and second capacitors 112 , 114 are known to leak current to ground, which increases power consumption and noise of the PLL circuit 100 . Therefore, it desirable to provide a PLL circuit having a loop filter with reduced current leakage to ground.
- FIG. 1 is an exemplary block diagram of a prior art lock loop circuit
- FIG. 2 is an exemplary block diagram of a mobile device using a reduced lock time lock loop circuit in accordance with one embodiment of the present disclosure
- FIG. 3 is an exemplary block diagram of the reduced lock time lock loop circuit
- FIG. 4 is a flowchart depicting exemplary steps that can be taken by the reduced lock time lock loop circuit
- FIG. 5 is a flowchart depicting additional exemplary steps that can be taken by the reduced lock time lock loop circuit
- FIG. 6 is an exemplary timing diagram of various signals during operation of the reduced lock time lock loop circuit.
- FIG. 7 is an additional exemplary timing diagram of various signals during operation of the reduced lock time lock loop circuit.
- a lock loop circuit includes a floating ground loop filter circuit and a precharge circuit.
- the floating ground loop filter circuit includes at least one capacitive element.
- the floating ground loop filter circuit provides a steering signal for a controllable oscillator circuit in response to a precharge signal.
- the precharge circuit provides the precharge signal in response to lock loop enable information.
- the precharge circuit controls the floating ground loop filter to bypass the capacitive element for a period of time in response to the lock loop enable information.
- the circuit and method provide, among other advantages, an output signal having a frequency and phase that is locked to a reference signal faster than conventional lock loop circuits and methods.
- the floating loop ground filter reduces leakage current to ground, which reduces power consumption and noise of the lock loop circuit.
- the lock loop circuit includes a synchronized feedback divider circuit.
- the synchronized feedback divider circuit After a second period of time, the synchronized feedback divider circuit provides feedback frequency information based on output frequency information provided by the controllable oscillator circuit in response to the steering signal. In one example, the feedback frequency information is provided in response to a rising edge of reference frequency information. In one example, the second period of time is greater than the period of time.
- the floating ground loop filter circuit includes at least one bypass switch circuit operatively coupled in parallel to the capacitive element.
- the bypass switch circuit bypasses the capacitive element in response to a bypass control signal received from the precharge circuit.
- the lock loop circuit includes an error detection circuit.
- the error detection circuit provides an unfiltered steering signal based on the frequency feedback information and the reference frequency information.
- the precharge circuit includes a first delay circuit, a second delay circuit, a third delay circuit, and a voltage regulator circuit.
- the first delay circuit After a third period of time that is less than the period of time, the first delay circuit provides a voltage regulator enable signal in response to the lock loop enable information.
- the second delay circuit In response to the lock loop enable information, the second delay circuit enables the floating ground loop filter to bypass the capacitive element for the period of time.
- the third delay circuit enables the synchronized feedback divider.
- the voltage regulator circuit provides the precharge signal in response to the voltage regulator enable signal.
- a mobile device e.g., a wireless phone, a mobile computer, a media player, and/or any other suitable mobile device that is operative by a battery
- a mobile device includes a battery supply circuit, a switching converter circuit, and the lock loop circuit.
- the battery supply circuit provides a first voltage value.
- the switching converter circuit which includes at least one switching element, converts the first voltage value into a second voltage value.
- the lock loop circuit provides a switching control signal to the switching element in response to the steering signal.
- circuit can include one or more processors (e.g., shared, dedicated, or group of processors such as but not limited to microprocessors, DSPs, or central processing units) and memory that execute one or more software or firmware programs, electronic circuits, integrated circuits, combinational logic circuits, FPGAs, ASICs, state machines, and/or other suitable components that provide the described functionality.
- processors e.g., shared, dedicated, or group of processors such as but not limited to microprocessors, DSPs, or central processing units
- memory execute one or more software or firmware programs
- electronic circuits integrated circuits, combinational logic circuits, FPGAs, ASICs, state machines, and/or other suitable components that provide the described functionality.
- signal may refer to analog or digital information.
- FIG. 2 an exemplary functional block diagram of a mobile device 200 such as a wireless phone, a mobile computer, a media player, or any other suitable mobile device that is operative by a battery supply circuit 202 .
- the mobile device includes a switching power supply circuit 204 and other mobile device circuits 206 required to provide the desired functionality of the mobile device 200 .
- the switching power supply circuit 204 receives a battery supply voltage 208 and provides a suitable supply voltage 210 to the other mobile device circuits 206 .
- the switching power supply circuit 204 can be a buck switching supply circuit to convert the suitable supply voltage 210 to a lower voltage value than the battery supply voltage 208 .
- the switching power supply circuit 204 can be a boost switching supply circuit to convert the suitable supply voltage 210 to a higher voltage value than the battery supply voltage 208 .
- the switching power supply circuit 204 includes a switching converter circuit 212 , a pulse frequency modulation (PFM) circuit 214 , a lock loop circuit 216 such as a phase lock loop (PLL) circuit having a reduced lock time, and a power management circuit 218 .
- PFM pulse frequency modulation
- lock loop circuit 216 such as a phase lock loop (PLL) circuit having a reduced lock time
- PLL phase lock loop
- the power management circuit 218 monitors a load 220 of the mobile device circuits 206 and determines whether to operate the switching converter circuit 212 in a PFM mode or a pulse width modulation (PWM) mode based on the load 220 .
- PFM pulse frequency modulation
- PWM pulse width modulation
- the power management circuit 218 provides a PFM enable signal 222 when the load is operating in at light load condition such as, for example, less than or equal to 50 mA.
- the PFM circuit 214 provides a PFM control signal 224 to the switching converter circuit 212 , which controls internal switching of the circuit as known in the art.
- the power management circuit 218 provides a lock loop enable signal 226 when the load is operating at a load greater than the light load (e.g., greater than or equal to 50 mA) so that the switching converter circuit 212 can operate in the PWM mode.
- the lock loop circuit 216 provides a control signal 228 (e.g., a PWM control signal) having a stable frequency and phase to the switching converter circuit 212 , which controls internal switching of the circuit as known in the art.
- the lock loop circuit 216 requires less time to lock frequency and phase than known lock loop circuits. As such, the lock loop circuit 216 can provide the control signal 228 having a stable frequency and phase faster than known PLL circuits.
- the reduced lock time lock loop circuit 216 is used to control switching of a switching converter circuit in this example, skilled artisans will appreciate that the lock loop circuit 216 can be used in any application where a signal having a stable frequency and phase is desired.
- the lock loop circuit 216 includes an error detection circuit 300 , a floating ground loop filter circuit 302 , a precharge circuit 304 , a controllable oscillator circuit 306 , and a synchronized feedback divider circuit 308 .
- the error detection circuit 300 is operatively coupled to the floating ground loop filter circuit 302 , the synchronized feedback divider circuit 308 , and the precharge circuit 304 .
- the controllable oscillator circuit 306 is operatively coupled to the synchronized feedback divider circuit 308 and the floating ground loop filter circuit 302 .
- the floating ground loop filter circuit 302 is operatively coupled to the error detection circuit 300 , the controllable oscillator circuit 306 , and the precharge circuit 304 .
- the floating ground loop filter circuit 302 is not coupled to ground 116 like the loop filter 104 depicted in FIG. 1 . Therefore, the floating ground loop filter circuit 302 has a floating (or virtual) ground unlike the loop filter 104 in FIG. 1 .
- the error detection circuit 300 includes a phase-frequency detection (PFD) circuit 310 and a charge pump circuit 312 .
- the PFD circuit 310 compares a reference frequency signal 314 , which can be provided by a crystal oscillator circuit 316 for example, to a feedback frequency signal 318 .
- the PFD circuit 310 provides error information 320 based on a difference (e.g., frequency and phase difference) between the reference frequency signal 314 and the feedback frequency signal 318 .
- the charge pump circuit 312 provides a unfiltered steering signal 322 in response to the error information 320 . In some embodiments, the unfiltered steering signal 322 is proportional to the error information 320 .
- the floating ground loop filter circuit 302 includes a resistive element 324 (e.g., a resistor), a first capacitive element 326 (e.g., a capacitor), a second capacitive element 328 (e.g., a capacitor), a first bypass switch circuit 330 , and a second bypass switch circuit 332 .
- the resistive element 324 and the first capacitive element 326 are operatively coupled in series between node 331 and node 333 .
- the second capacitive element 328 is operatively coupled in parallel to the resistive element 324 and the first capacitive element 326 .
- the first bypass switch circuit 330 is operatively coupled in parallel to the first capacitive element 326 .
- the second bypass switch circuit 332 is operatively coupled in parallel to the second capacitive element 328 .
- the precharge circuit 304 selectively controls the bypass switch circuits 330 , 332 to bypass the respective capacitive element 326 , 328 in order to provide a steering signal 334 faster than known PLL circuits 100 . More specifically, the precharge circuit 304 provides a precharge signal 347 and controls the floating ground loop filter 302 to bypass the capacitive elements 326 , 328 in response to the enable signal 226 . In response to the precharge signal 347 , the floating ground loop filter circuit 302 provides a steering signal 334 (e.g., an oscillator control signal) for the controllable oscillator circuit 306 .
- a steering signal 334 e.g., an oscillator control signal
- the precharge circuit 304 includes a first delay circuit 336 , a second delay circuit 338 , a third delay circuit 340 , a bias circuit 342 , and a voltage regulator circuit 344 .
- the bias circuit 342 provides a bias signal 343 (e.g., a bias current) to the voltage regulator circuit 344 as known in the art.
- the voltage regulator circuit 344 can be any known voltage regulator circuit such as, for example, a low dropout (LDO) regulator circuit or other suitable regulator circuit.
- LDO low dropout
- the voltage regulator circuit 344 provides a precharge signal 347 in response to the bias signal 343 .
- the first delay circuit 336 provides a voltage regulator enable signal 346
- the second delay circuit 338 provides a capacitive element bypass signal 348
- the third delay circuit 340 provides an error detection enable signal 350 .
- the first delay circuit 366 provides the voltage regulator enable signal 346 after a first period of time
- the second delay circuit 338 provides the capacitive element bypass signal 348 for a second period of time
- the third delay circuit 340 provides the error detection enable signal 350 after a third period of time.
- the third period of time can be greater than the second period of time, which can be greater than the first period of time.
- the first, second, and third periods of time can be predetermined.
- the first period of time can be 0.690 ⁇ s
- the second period of time can be 3.75 ⁇ s
- the third period of time can be 4.25 ⁇ s, although other period of times are contemplated.
- the switch circuits 330 , 332 initially bypass the respective capacitive elements 326 , 328 for the second period of time, which allows the steering signal 334 to rise quicker since the capacitors 326 , 328 do not need to be charged and are not coupled to ground.
- the bypass switch circuits 326 , 328 are disabled allowing the floating ground loop filter circuit 302 to filter the unfiltered steering signal 322 to remove any imperfections.
- the synchronized feedback divider circuit 308 includes a synchronization circuit 352 and a divider circuit 354 .
- the synchronization circuit 352 provides the feedback frequency signal 318 , which is based on the control signal 228 , in response to the error detection enable signal 350 and the reference frequency signal 314 . More specifically, the synchronization circuit 352 provides the feedback frequency signal 318 in response to the error detection enable signal 350 and after a desired edge of the reference frequency signal 314 .
- the desired edge can be a first rising edge of reference frequency signal 314 after the error detection enable signal 350 is provided.
- the feedback frequency signal 318 is based on an initial feedback frequency signal 356 .
- the divider circuit 354 provides the initial feedback frequency signal 356 by dividing (or in some cases multiplying) the output frequency signal 124 by a determined value such as 128 or other suitable value.
- step 400 exemplary steps that can be taken by the lock loop circuit 216 to lock frequency and phase of the PWM control signal 228 to the reference frequency signal 314 are generally identified at 400 .
- the process starts in step 402 when the lock loop enable signal 226 is received by the precharge circuit 304 .
- step 404 the floating ground loop filter circuit 302 controls the bypass switch circuits 330 , 332 to bypass capacitive elements 326 , 328 , respectively, for the second period of time provided by the second delay circuit 338 .
- the synchronized feedback divider circuit 308 After the third period of time provided by the third delay circuit 340 , the synchronized feedback divider circuit 308 provides the feedback information 318 to the error detection circuit 300 , which subsequently locks the frequency and phase of the control signal 228 to the reference frequency signal 314 .
- the feedback information is provided to the error detection circuit 300 after the third period of time and a rising edge (e.g., the first rising edge after the third period of time) of the reference frequency signal 314 .
- the process ends in step 408 .
- exemplary steps that can be taken by the lock loop circuit 216 to bypass the capacitive elements 326 , 328 of step 404 are generally identified.
- the process starts in step 500 .
- the precharge circuit 304 controls the bypass switch circuits 330 , 332 of the floating ground loop filter circuit 302 to bypass the capacitive elements 326 , 328 for the period of time provided by the second delay circuit 338 in response to the lock loop enable signal 226 .
- bypassing respective capacitive elements 326 , 328 provides the steering signal 334 faster than known PLL circuits because the capacitive elements 326 , 328 do not have to charge.
- step 504 the floating ground loop filter circuit 302 provides the steering signal 334 to the controllable oscillator circuit 306 in response to the precharge signal 347 .
- the controllable oscillator circuit 306 provides the control signal 228 in response to the steering signal 334 .
- the process ends in step 508 .
- the bypass switches 330 , 332 can be controlled to discontinue bypassing the capacitive elements 326 , 328 after the period of time provided by the second delay circuit 338 so that the floating ground loop filter 302 can filter the unfiltered signal 322 .
- an exemplary timing diagram of the lock loop circuit 216 adjusting the frequency of the control signal 228 is generally identified at 600 .
- the precharge circuit 304 receives the lock loop enable signal 226 .
- the capacitive element bypass signal 348 is provided in order to bypass the capacitive elements 326 , 328 at start.
- the controllable oscillator 306 may provide some spurious frequencies in the control signal 228 due to voltage regulator circuit 344 settling time.
- the frequency of the control signal 228 is adjusted faster than conventional PLL circuits 100 due to bypassing the capacitive elements 326 , 328 and the floating ground nature of the floating ground loop filter circuit 302 .
- the precharge circuit 304 discontinues providing the capacitive element bypass signal 348 , which disables the bypass switch circuits 330 , 332 so that the floating ground loop filter circuit 302 can filter imperfections from the steering signal 334 .
- the error detection enable signal 350 is provided to enable the error detection circuit 300 so that the frequency and phase of the control signal 228 can be locked to the reference frequency signal 314 .
- an exemplary timing diagram of the lock loop circuit 216 locking the frequency and phase of the control signal 228 is generally identified at 700 .
- the precharge circuit 304 receives the lock loop enable signal 226 at time 602 .
- the frequency of the control signal 228 is adjusted while the capacitive elements 326 , 328 are bypassed.
- the precharge circuit 304 disables the bypass switch circuits 330 , 332 so that the floating ground loop filter circuit 302 can filter imperfections from the steering signal 334 .
- the error detection enable signal 350 is provided to enable the error detection circuit 300 .
- a first rising edge of the reference frequency signal 314 is received by the error detection circuit 300 .
- a second rising edge of the control signal 228 is generated by the controllable oscillator 306 and the synchronized feedback divider circuit 308 provides the feedback frequency signal 318 to the error detection circuit so that the frequency and phase of the control signal 228 can be locked to the reference frequency signal 314 .
- the reduced lock time lock loop circuit 216 provides an output signal having a frequency and phase that is locked to a reference signal faster than conventional PLL circuits.
- the floating loop ground filter 302 reduces leakage current to ground, which reduces power consumption and noise of the lock loop circuit 216 .
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Abstract
Description
- This application is related to co-pending application entitled “AUTOMATIC CALIBRATION LOCK LOOP CIRCUIT AND METHOD HAVING IMPROVED LOCK TIME,” filed on even date, having docket number 36600.07.1631, inventors David M. Schlueter and Michael C. Doll, owned by instant Assignee and is incorporated herein by reference in its entirety.
- 1. Field
- The present disclosure generally relates to lock loop circuits, and more particularly, to lock loop circuits having a reduced time required to lock frequency and phase.
- 2. Related Art
- Lock loop circuits such as phase lock loop (PLL) circuits provide an output signal having a frequency and phase that is locked to a reference signal. More specifically, PLL circuits use feedback to adjust the output signal so that the frequency and phase of the output signal match the reference signal.
- As known in the art, PLL circuits are used in many applications such as radio, telecommunications, computers, and other suitable applications. For example, the circuits can be used to, among other things, generate stable frequencies, recover signals from noisy communication signals, and provide clock timing for applications requiring a stable clock.
- Some mobile devices include power management systems that disable phase lock loop circuits when not in use in order to reduce power consumption and increase battery life. Since PLL circuits are used for timing in many devices, it is desirable for the circuit to quickly lock frequency and phase when the power management system re-enables the circuit.
- As shown in
FIG. 1 , atypical PLL circuit 100 includes anerror detector 102, aloop filter 104, a voltage controlled oscillator (VCO) 106, and afeedback divider 108. Theloop filter 104 includes aresistor 110, afirst capacitor 112, and asecond capacitor 114. Theresistor 110 is operatively coupled to theerror detector 102 and theVCO 106 at one end and thefirst capacitor 112 at the other end. Thefirst capacitor 112 is operatively coupled to theresistor 110 at one end and toground 116 at the other end. Thesecond capacitor 114 is operatively coupled to theerror detector 102 and theVCO 106 at one end and ground 116 at the other end. - During operation, the
error detector 102 provides an unfilteredVCO control voltage 116 in response to areference frequency signal 118 andfeedback frequency signal 120. More specifically, theerror detector 102 adjusts the unfilteredVCO control voltage 116 to reduce a frequency and phase difference between thereference frequency signal 118 and thefeedback frequency signal 120. - The
loop filter 104 filters the unfilteredVCO control voltage 116 to remove any imperfections and provides a VCO control voltage 122 (e.g., a steering voltage) based thereon. TheVCO 106 provides anoutput frequency signal 124 in response to theVCO control voltage 122. Thefeedback divider 108 provides thefeedback frequency signal 120 in response to theoutput frequency signal 124. - In some embodiments, the
PLL circuit 100 includes a loop precharger 126 to reduce time required for thePLL circuit 100 to lock frequency and phase. In response to a PLL enablesignal 128, theloop precharger 108 provides the unfilteredVCO control voltage 116, which precharges the first andsecond capacitors control voltage signal 122 is adjusted to a desired value faster than PLL circuits without the loop precharger 126. - Although the loop precharger 126 reduces time for the
PLL circuit 100 to lock the frequency and phase of theoutput frequency signal 124, it is desirable to further reduce the time required to lock the frequency and phase. - In addition, the first and
second capacitors PLL circuit 100. Therefore, it desirable to provide a PLL circuit having a loop filter with reduced current leakage to ground. - The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
-
FIG. 1 is an exemplary block diagram of a prior art lock loop circuit; -
FIG. 2 is an exemplary block diagram of a mobile device using a reduced lock time lock loop circuit in accordance with one embodiment of the present disclosure; -
FIG. 3 is an exemplary block diagram of the reduced lock time lock loop circuit; -
FIG. 4 is a flowchart depicting exemplary steps that can be taken by the reduced lock time lock loop circuit; -
FIG. 5 is a flowchart depicting additional exemplary steps that can be taken by the reduced lock time lock loop circuit; -
FIG. 6 is an exemplary timing diagram of various signals during operation of the reduced lock time lock loop circuit; and -
FIG. 7 is an additional exemplary timing diagram of various signals during operation of the reduced lock time lock loop circuit. - In one example, a lock loop circuit includes a floating ground loop filter circuit and a precharge circuit. The floating ground loop filter circuit includes at least one capacitive element. The floating ground loop filter circuit provides a steering signal for a controllable oscillator circuit in response to a precharge signal. The precharge circuit provides the precharge signal in response to lock loop enable information. The precharge circuit controls the floating ground loop filter to bypass the capacitive element for a period of time in response to the lock loop enable information. A related method is also disclosed.
- The circuit and method provide, among other advantages, an output signal having a frequency and phase that is locked to a reference signal faster than conventional lock loop circuits and methods. In addition, the floating loop ground filter reduces leakage current to ground, which reduces power consumption and noise of the lock loop circuit. Other advantages will be recognized by those of ordinary skill in the art.
- In one example, the lock loop circuit includes a synchronized feedback divider circuit. After a second period of time, the synchronized feedback divider circuit provides feedback frequency information based on output frequency information provided by the controllable oscillator circuit in response to the steering signal. In one example, the feedback frequency information is provided in response to a rising edge of reference frequency information. In one example, the second period of time is greater than the period of time.
- In one example, the floating ground loop filter circuit includes at least one bypass switch circuit operatively coupled in parallel to the capacitive element. The bypass switch circuit bypasses the capacitive element in response to a bypass control signal received from the precharge circuit.
- In one example, the lock loop circuit includes an error detection circuit. The error detection circuit provides an unfiltered steering signal based on the frequency feedback information and the reference frequency information.
- In one example, the precharge circuit includes a first delay circuit, a second delay circuit, a third delay circuit, and a voltage regulator circuit. After a third period of time that is less than the period of time, the first delay circuit provides a voltage regulator enable signal in response to the lock loop enable information. In response to the lock loop enable information, the second delay circuit enables the floating ground loop filter to bypass the capacitive element for the period of time. After the second period of time, the third delay circuit enables the synchronized feedback divider. The voltage regulator circuit provides the precharge signal in response to the voltage regulator enable signal.
- In one example, a mobile device (e.g., a wireless phone, a mobile computer, a media player, and/or any other suitable mobile device that is operative by a battery) includes a battery supply circuit, a switching converter circuit, and the lock loop circuit. The battery supply circuit provides a first voltage value. The switching converter circuit, which includes at least one switching element, converts the first voltage value into a second voltage value. The lock loop circuit provides a switching control signal to the switching element in response to the steering signal.
- As used herein, the term “circuit” can include one or more processors (e.g., shared, dedicated, or group of processors such as but not limited to microprocessors, DSPs, or central processing units) and memory that execute one or more software or firmware programs, electronic circuits, integrated circuits, combinational logic circuits, FPGAs, ASICs, state machines, and/or other suitable components that provide the described functionality. In addition, the term “signal” may refer to analog or digital information.
- Referring now to
FIG. 2 , an exemplary functional block diagram of amobile device 200 such as a wireless phone, a mobile computer, a media player, or any other suitable mobile device that is operative by abattery supply circuit 202. The mobile device includes a switchingpower supply circuit 204 and othermobile device circuits 206 required to provide the desired functionality of themobile device 200. The switchingpower supply circuit 204 receives abattery supply voltage 208 and provides asuitable supply voltage 210 to the othermobile device circuits 206. In some embodiments, the switchingpower supply circuit 204 can be a buck switching supply circuit to convert thesuitable supply voltage 210 to a lower voltage value than thebattery supply voltage 208. In other embodiments, the switchingpower supply circuit 204 can be a boost switching supply circuit to convert thesuitable supply voltage 210 to a higher voltage value than thebattery supply voltage 208. - The switching
power supply circuit 204 includes a switchingconverter circuit 212, a pulse frequency modulation (PFM)circuit 214, alock loop circuit 216 such as a phase lock loop (PLL) circuit having a reduced lock time, and a power management circuit 218. Although thelock loop circuit 216 is discussed as a phase lock loop (PLL) circuit herein, skilled artisans will appreciate that thelock loop circuit 216 can be implemented as any other suitable lock loop circuit such as, for example, a delay lock loop circuit. The power management circuit 218 monitors aload 220 of themobile device circuits 206 and determines whether to operate the switchingconverter circuit 212 in a PFM mode or a pulse width modulation (PWM) mode based on theload 220. In some embodiments, the power management circuit 218 provides a PFM enable signal 222 when the load is operating in at light load condition such as, for example, less than or equal to 50 mA. In response to the PFM enablesignal 222, thePFM circuit 214 provides aPFM control signal 224 to the switchingconverter circuit 212, which controls internal switching of the circuit as known in the art. - In addition, in some embodiments, the power management circuit 218 provides a lock loop enable
signal 226 when the load is operating at a load greater than the light load (e.g., greater than or equal to 50 mA) so that the switchingconverter circuit 212 can operate in the PWM mode. In response to the lock loop enablesignal 226, thelock loop circuit 216 provides a control signal 228 (e.g., a PWM control signal) having a stable frequency and phase to the switchingconverter circuit 212, which controls internal switching of the circuit as known in the art. As will be discussed in more detail, thelock loop circuit 216 requires less time to lock frequency and phase than known lock loop circuits. As such, thelock loop circuit 216 can provide thecontrol signal 228 having a stable frequency and phase faster than known PLL circuits. - Although, the reduced lock time
lock loop circuit 216 is used to control switching of a switching converter circuit in this example, skilled artisans will appreciate that thelock loop circuit 216 can be used in any application where a signal having a stable frequency and phase is desired. - Referring now to
FIG. 3 , thelock loop circuit 216 includes anerror detection circuit 300, a floating groundloop filter circuit 302, aprecharge circuit 304, acontrollable oscillator circuit 306, and a synchronizedfeedback divider circuit 308. Theerror detection circuit 300 is operatively coupled to the floating groundloop filter circuit 302, the synchronizedfeedback divider circuit 308, and theprecharge circuit 304. Thecontrollable oscillator circuit 306 is operatively coupled to the synchronizedfeedback divider circuit 308 and the floating groundloop filter circuit 302. The floating groundloop filter circuit 302 is operatively coupled to theerror detection circuit 300, thecontrollable oscillator circuit 306, and theprecharge circuit 304. As shown, the floating groundloop filter circuit 302 is not coupled to ground 116 like theloop filter 104 depicted inFIG. 1 . Therefore, the floating groundloop filter circuit 302 has a floating (or virtual) ground unlike theloop filter 104 inFIG. 1 . - The
error detection circuit 300 includes a phase-frequency detection (PFD)circuit 310 and acharge pump circuit 312. ThePFD circuit 310 compares areference frequency signal 314, which can be provided by acrystal oscillator circuit 316 for example, to afeedback frequency signal 318. ThePFD circuit 310 provideserror information 320 based on a difference (e.g., frequency and phase difference) between thereference frequency signal 314 and thefeedback frequency signal 318. Thecharge pump circuit 312 provides aunfiltered steering signal 322 in response to theerror information 320. In some embodiments, theunfiltered steering signal 322 is proportional to theerror information 320. - The floating ground
loop filter circuit 302 includes a resistive element 324 (e.g., a resistor), a first capacitive element 326 (e.g., a capacitor), a second capacitive element 328 (e.g., a capacitor), a firstbypass switch circuit 330, and a secondbypass switch circuit 332. Theresistive element 324 and the firstcapacitive element 326 are operatively coupled in series betweennode 331 andnode 333. The secondcapacitive element 328 is operatively coupled in parallel to theresistive element 324 and the firstcapacitive element 326. The firstbypass switch circuit 330 is operatively coupled in parallel to the firstcapacitive element 326. The secondbypass switch circuit 332 is operatively coupled in parallel to the secondcapacitive element 328. - The
precharge circuit 304 selectively controls thebypass switch circuits respective capacitive element steering signal 334 faster than knownPLL circuits 100. More specifically, theprecharge circuit 304 provides aprecharge signal 347 and controls the floatingground loop filter 302 to bypass thecapacitive elements signal 226. In response to theprecharge signal 347, the floating groundloop filter circuit 302 provides a steering signal 334 (e.g., an oscillator control signal) for thecontrollable oscillator circuit 306. - The
precharge circuit 304 includes afirst delay circuit 336, a second delay circuit 338, athird delay circuit 340, abias circuit 342, and avoltage regulator circuit 344. Thebias circuit 342 provides a bias signal 343 (e.g., a bias current) to thevoltage regulator circuit 344 as known in the art. Thevoltage regulator circuit 344 can be any known voltage regulator circuit such as, for example, a low dropout (LDO) regulator circuit or other suitable regulator circuit. Thevoltage regulator circuit 344 provides aprecharge signal 347 in response to thebias signal 343. - In response to the enable
signal 226, thefirst delay circuit 336 provides a voltage regulator enablesignal 346, the second delay circuit 338 provides a capacitiveelement bypass signal 348, and thethird delay circuit 340 provides an error detection enablesignal 350. More specifically, the first delay circuit 366 provides the voltage regulator enablesignal 346 after a first period of time, the second delay circuit 338 provides the capacitiveelement bypass signal 348 for a second period of time, and thethird delay circuit 340 provides the error detection enablesignal 350 after a third period of time. In some embodiments, the third period of time can be greater than the second period of time, which can be greater than the first period of time. In addition, the first, second, and third periods of time can be predetermined. For example, the first period of time can be 0.690 μs, the second period of time can be 3.75 μs, and the third period of time can be 4.25 μs, although other period of times are contemplated. - As such, when the
lock loop circuit 216 is enabled, theswitch circuits capacitive elements steering signal 334 to rise quicker since thecapacitors bypass switch circuits loop filter circuit 302 to filter theunfiltered steering signal 322 to remove any imperfections. - The synchronized
feedback divider circuit 308 includes asynchronization circuit 352 and adivider circuit 354. Thesynchronization circuit 352 provides thefeedback frequency signal 318, which is based on thecontrol signal 228, in response to the error detection enablesignal 350 and thereference frequency signal 314. More specifically, thesynchronization circuit 352 provides thefeedback frequency signal 318 in response to the error detection enablesignal 350 and after a desired edge of thereference frequency signal 314. In some embodiments, the desired edge can be a first rising edge ofreference frequency signal 314 after the error detection enablesignal 350 is provided. - The
feedback frequency signal 318 is based on an initialfeedback frequency signal 356. Thedivider circuit 354 provides the initialfeedback frequency signal 356 by dividing (or in some cases multiplying) theoutput frequency signal 124 by a determined value such as 128 or other suitable value. - Referring now to
FIG. 4 , exemplary steps that can be taken by thelock loop circuit 216 to lock frequency and phase of thePWM control signal 228 to thereference frequency signal 314 are generally identified at 400. The process starts instep 402 when the lock loop enablesignal 226 is received by theprecharge circuit 304. Instep 404, the floating groundloop filter circuit 302 controls thebypass switch circuits capacitive elements third delay circuit 340, the synchronizedfeedback divider circuit 308 provides thefeedback information 318 to theerror detection circuit 300, which subsequently locks the frequency and phase of thecontrol signal 228 to thereference frequency signal 314. In some embodiments, the feedback information is provided to theerror detection circuit 300 after the third period of time and a rising edge (e.g., the first rising edge after the third period of time) of thereference frequency signal 314. The process ends instep 408. - Referring to
FIG. 5 , exemplary steps that can be taken by thelock loop circuit 216 to bypass thecapacitive elements step 404 are generally identified. The process starts instep 500. Instep 502, theprecharge circuit 304 controls thebypass switch circuits loop filter circuit 302 to bypass thecapacitive elements signal 226. As noted above, bypassing respectivecapacitive elements steering signal 334 faster than known PLL circuits because thecapacitive elements step 504, the floating groundloop filter circuit 302 provides thesteering signal 334 to thecontrollable oscillator circuit 306 in response to theprecharge signal 347. Thecontrollable oscillator circuit 306 provides thecontrol signal 228 in response to thesteering signal 334. The process ends instep 508. If desired, the bypass switches 330, 332 can be controlled to discontinue bypassing thecapacitive elements ground loop filter 302 can filter theunfiltered signal 322. - Referring now to
FIG. 6 , an exemplary timing diagram of thelock loop circuit 216 adjusting the frequency of thecontrol signal 228 is generally identified at 600. At afirst time 602, theprecharge circuit 304 receives the lock loop enablesignal 226. As shown, the capacitiveelement bypass signal 348 is provided in order to bypass thecapacitive elements time 604, which is provided by thefirst delay circuit 336, thecontrollable oscillator 306 may provide some spurious frequencies in thecontrol signal 228 due tovoltage regulator circuit 344 settling time. - During the second period of
time 606, which is provided by the second delay circuit 338, the frequency of thecontrol signal 228 is adjusted faster thanconventional PLL circuits 100 due to bypassing thecapacitive elements loop filter circuit 302. Attime 608, theprecharge circuit 304 discontinues providing the capacitiveelement bypass signal 348, which disables thebypass switch circuits loop filter circuit 302 can filter imperfections from thesteering signal 334. After the third period oftime 610, which is provided by thethird delay circuit 340, the error detection enablesignal 350 is provided to enable theerror detection circuit 300 so that the frequency and phase of thecontrol signal 228 can be locked to thereference frequency signal 314. - Referring now to
FIG. 7 , an exemplary timing diagram of thelock loop circuit 216 locking the frequency and phase of thecontrol signal 228 is generally identified at 700. As shown, theprecharge circuit 304 receives the lock loop enablesignal 226 attime 602. During the second period oftime 606, the frequency of thecontrol signal 228 is adjusted while thecapacitive elements time 608, theprecharge circuit 304 disables thebypass switch circuits loop filter circuit 302 can filter imperfections from thesteering signal 334. After the third period oftime 610, the error detection enablesignal 350 is provided to enable theerror detection circuit 300. Attime 702, a first rising edge of thereference frequency signal 314 is received by theerror detection circuit 300. Attime 704, a second rising edge of thecontrol signal 228 is generated by thecontrollable oscillator 306 and the synchronizedfeedback divider circuit 308 provides thefeedback frequency signal 318 to the error detection circuit so that the frequency and phase of thecontrol signal 228 can be locked to thereference frequency signal 314. - As noted above, among other advantages, the reduced lock time
lock loop circuit 216 provides an output signal having a frequency and phase that is locked to a reference signal faster than conventional PLL circuits. In addition, the floatingloop ground filter 302 reduces leakage current to ground, which reduces power consumption and noise of thelock loop circuit 216. Other advantages will be recognized by those of ordinary skill in the art. - Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. In addition, unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Claims (20)
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US10693474B1 (en) | 2019-02-14 | 2020-06-23 | Infineon Technologies Ag | PLL filter having a capacitive voltage divider |
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JP6222356B2 (en) * | 2014-11-07 | 2017-11-01 | 株式会社ソシオネクスト | Semiconductor integrated circuit and processing circuit |
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