US20080316813A1 - Multi-level cell serial-parallel sense scheme for non-volatile flash memory - Google Patents
Multi-level cell serial-parallel sense scheme for non-volatile flash memory Download PDFInfo
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- US20080316813A1 US20080316813A1 US11/766,248 US76624807A US2008316813A1 US 20080316813 A1 US20080316813 A1 US 20080316813A1 US 76624807 A US76624807 A US 76624807A US 2008316813 A1 US2008316813 A1 US 2008316813A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5633—Mixed concurrent serial multilevel reading
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5645—Multilevel memory with current-mirror arrangements
Definitions
- Flash memory data is stored as a variable amount of charge on a secondary gate that floats between a conventional gate and a channel.
- the amount of charge on this floating secondary gate changes the effective threshold voltage (Vt) of the cell and results in a variable current for a fixed top gate voltage (Vg).
- Vt effective threshold voltage
- Vg fixed top gate voltage
- Ids a fixed current
- the wordline (WL) ramps through three different levels to sense the four possible combinations of two bits in cell states 00, 01, 10, 11. Ramping to each level consumes time in the sensing process.
- FIG. 1 is a sensing scheme used in 90 nm and 65 nm process technology products.
- FIG. 2 is a sensing scheme according to one embodiment of the present invention.
- FIG. 3 is a flowchart of a method of sensing memory data according to one embodiment.
- FIG. 4 is a circuit diagram according to one embodiment.
- FIG. 5 is a circuit diagram of a sense amplifier of FIG. 4 .
- a conventional sense scheme used in 90 nm and 65 nm process technology is shown at 10 .
- the gate voltage 12 of a flash cell steps up from a starting cell level L 0 through different cell levels L 1 , L 2 , and L 3 , cell levels collectively shown as 14 .
- cell levels L 0 , L 1 , L 2 , and L 3 correspond to cell states 11, 10, 00, and 01, respectively.
- a sense operation occurs at each level for determination of the cell data.
- conventional steps 18 include equalization (A), amplification (B), comparison (C), and data out (D).
- a first sense operation 20 the WL ramps from L 0 to L 1 and goes through steps A and B.
- a second sense operation 22 begins with the WL ramping up from L 1 to L 2 .
- the first sense operation completes with steps C and D as step A begins in the second sense operation 22 .
- a third sense operation 24 the WL ramps up from L 2 to L 3 as steps A and B occur.
- the second sense operation 22 finishes during step A of the third sense operation 24 .
- the third sense operation is completed as the WL returns to L 0 .
- the gate voltage 12 may ramp down to a different voltage 12 a in the third sense operation 24 .
- a sense amplifier In sensing operations, a sense amplifier is used for determination of the value of cell data and the output from the sense amplifier would input data into a bus.
- the sense amplifier is initially set to a known state at the beginning of the sense operations.
- FIG. 1 further shows sense amplifier output at the various cell levels at 26 , corresponding in time with steps in the sense operations 20 , 22 , 24 .
- a serial-parallel sense scheme in accordance with one embodiment of the present invention is shown at 50 .
- a wordline (WL) 51 of a flash cell would directly ramp to cell level L 2 at the beginning of a first sense operation 52 , and obviating the need for a sense operation at cell level L 1 .
- the WL need only ramp up to two different cell levels, namely L 2 and L 3 in contrast to the scheme of FIG. 1 which required WL to go through three different cell levels.
- a first sense operation 52 the WL ramps from L 0 to L 2 and goes through steps A and B.
- a second sense operation 54 begins with the WL ramping up to L 3 .
- the first sense operation completes with steps C and D as step A begins in the second sense operation 54 .
- the voltage ramps back down, and a third sense operation is not needed.
- FIG. 2 further shows sense amplifier output at the various cell levels at 56 , corresponding in time with steps in the sense operations 52 , 54 .
- Method 100 includes, at 102 , a step of ramping a wordline (WL) of a multi-level cell (MLC) flash memory to a first cell level L 2 .
- the method includes performing a first sense operation at I REF1 , which may be defined as the equivalent reference current at the threshold voltage Vt of the flash cell. In one embodiment, the first sense operation is performed at 7.5 ⁇ A of reference current.
- the method 100 includes determining a value of most significant bit (MSB) data at step 106 .
- the MSB data may be determined and captured at the end of the first sense operation when the WL is at cell level L 2 . Thus, the MSB data is resolved at the first sense operation.
- the method further includes step 108 of ramping the WL to a second cell level L 3 .
- the WL is at L 3 .
- Method 100 further includes, at 110 , performing a second sense operation at I REF2 , where I REF2 is greater than I REF1 .
- I REF2 is equivalent to a reference current for an erased flash cell having L 3 at its gate.
- I REF2 may be approximately 25 ⁇ A of reference current.
- method 100 includes adjusting the column load of a sense circuit for sensing data in the MLC memory.
- the column load may be reconfigured in the second sense operation based on a selected reference current or based on MSB data.
- the method may include a step of determining whether column load adjustment is needed.
- Method 100 further includes step 114 where cell states 10 and 11 can be differentiated.
- the state of the output of the sense amplifier which may have been previously placed at an initial known state, differentiates the cell states between cell levels L 1 and L 0 . Hence, the data of the MLC memory is resolved.
- step 106 after determining a value of MSB data, if MSB is determined to equal 0, the output from the sense amplifier trips a bus at 116 .
- This bus may include a READ/VerifyBUS, or other bus suitable to receive output from the sense amplifier.
- the MSB data is resolved and the wordline ramps to L 3 .
- the method includes, at 120 , performing a second sense operation at I REF1 and, at 122 , differentiating between the cell states 01 (L 3 ) or 00 (L 2 ).
- the data of the MLC memory is resolved.
- cell states and cell levels as used herein subscribe to one convention. Other conventions may be used and are considered to fall within the scope of this invention. For example, in a different convention, cell level L 2 may correspond to cell state 01.
- Sensing circuit 200 for implementation of an MLC serial-parallel sense scheme according to one embodiment is shown.
- Sensing circuit 200 has an array side 202 including a flash cell 204 , a decoding device 206 , and a cascode device 208 .
- the flash cell may be any non-volatile memory that can be electrically erased and reprogrammed.
- the control gate of the flash cell is tied to a wordline (WL) where voltage may be controlled.
- Sensing circuit 200 further includes a reference side 210 including a decoding device 212 and a cascode device 214 .
- the decoding devices 206 , 212 may include a number of transistors as global and local bitline selection devices. As such, each transistor may receive a selection signal at 216 . These signals may or may not be tied and varies depending on the controller (not shown) that is coupled to the transistors.
- the cascode devices 208 , 214 may be referenced to a drain bias or cascode reference node 218 .
- a sense line 220 on the array side 202 provides input to a positive terminal of a sense amplifier 222 .
- a sense line 224 on the reference side 210 provides input to a negative terminal of the sense amplifier.
- the cascode devices 208 and 214 may hold voltages steady on the array side and the reference side sense line input, respectively.
- the sensing circuit 200 uses multiple mirror devices 224 to provide different reference currents. As shown, for example, when I REF1 is the selected current for use in a sense operation (selected current), a switch 226 at the array side of the sensing circuit is closed, while a switch 228 for I REF2 , parallel to switch for I REF1 , is open. Generally, a corresponding switch, for example, switch 230 , at the reference side of the sensing circuit is closed for I REF1 to be selected. When I REF2 is the selected current, switches 228 and 232 , at the array side and the reference side, respectively, are closed, while switches 226 and 230 are open.
- the multiple mirror devices are coupled to a separate reference current or signal as indicated at 234 , which may or may not be tied to each other.
- separate reference current generators may be used instead of the multiple mirror devices.
- the reference current generators may give design flexibility in controlling different levels in an MLC sense scheme.
- the sense amplifier 222 takes the input from sense lines 220 and 224 , and outputs a signal. Depending on the value of the output, the signal may trip a bus 236 .
- a bus may include a READ/VerifyBUS, or other bus suitable to receive output from the sense amplifier.
- the sense amplifier 222 may include a column load adjuster 300 , a comparator device 302 , and a data propagation device 304 .
- the column load adjuster 300 may include a variable resistor 306 coupled to a kicker device 308 .
- the kicker device may be switched on by a controller (not shown) when it is determined that the charge in a decoding device 206 is insufficient. When the kicker device is on, the resistor 306 effectively adjusts the column load through the decoding device 206 .
- the column load adjuster 300 may include a variable resistor 310 coupled to a kicker device 312 . Alternatively, it is not necessary for the resistance of the resistors to be variable.
- the kicker devices 308 and 312 receive signals at 314 from the controller.
- the signals may be tied to the same controller signal.
- the signal to kicker device 308 may be different from the signal to kicker device 12 , depending on the column loads in the array side 202 and the reference side 210 .
- the additional resistance provided to each sense line may vary depending on the needs of each decoding device 206 and decoding device 212 .
- the comparator device 302 receives input from sense lines 220 and 224 . Within the comparator device, which includes a circuit (not shown) with transistors and comparators, determinations may be made from the input. In one embodiment, the output generated by the comparator device 302 enters the data propagation device 304 , which also includes a circuit (not shown) with transistors and comparators. The data propagation device may manipulate or enhance the input that it receives from the comparator device and generates output that may enter a bus. Depending on the value of the output, the bus may trip. In another embodiment, more than one output signal may be generated by the comparator device and may enter the data propagation device via a different circuit path. As a result, multiple signals may exit the data propagation device and fed to a bus.
- sensing circuit and sense amplifier may be used to implement an MLC serial-parallel scheme and obtain characteristics and/or results similar to those shown and/or described above.
- the MLC serial-parallel sense scheme would eliminate the need of a third sense operation required for current MLC sense scheme which could be used for faster access time (projected to reduce access time by 10 ns) or improved Read Window Budget (RWB) for 45 nm/30 nm technology timeframe.
- RWB Read Window Budget
- the serial-parallel sense scheme allows performing sense operation using two stages instead of three stages of operation and also gain from the present reduction of 1/f noise by utilizing common reference current.
- the sense operation is reduced by approximately 20% (10-15 ns) which translates to a savings of read window budget (RWB) in the range between 100 mV to 400 mV.
- RWB read window budget
- MLC sense operation in 30 nm and 45 nm process technology may be feasible.
- Any reference to device may include a component, circuit, module, or any such mechanism in which the device can achieve the purpose or description as indicated by the modifier preceding the device.
- the component, circuit, module, or any such mechanism is not necessarily a specific limitation to the device.
Abstract
Description
- Flash memory data is stored as a variable amount of charge on a secondary gate that floats between a conventional gate and a channel. The amount of charge on this floating secondary gate changes the effective threshold voltage (Vt) of the cell and results in a variable current for a fixed top gate voltage (Vg). In conventional flash sensing schemes used in 90 nm and 65 nm process technology, a fixed current (Ids) is applied to measure the cell threshold voltage Vt and the gate voltage Vg determines a cell state.
- In a multi-level cell (MLC) approach utilizing two-bit cell memory, the wordline (WL) ramps through three different levels to sense the four possible combinations of two bits in
cell states - It is desirable to have an improved scheme for faster access time. At the same time, having a better reference for sensing by reduction of 1/f or Random Telegraph Signal (RTS) noise is also desired.
- The invention will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the invention which, however, should not be taken to limit the invention to the specific embodiment(s) described, but are for explanation and understanding only.
-
FIG. 1 is a sensing scheme used in 90 nm and 65 nm process technology products. -
FIG. 2 is a sensing scheme according to one embodiment of the present invention. -
FIG. 3 is a flowchart of a method of sensing memory data according to one embodiment. -
FIG. 4 is a circuit diagram according to one embodiment. -
FIG. 5 is a circuit diagram of a sense amplifier ofFIG. 4 . - Referring to
FIG. 1 , a conventional sense scheme used in 90 nm and 65 nm process technology is shown at 10. In multi-level cell sensing, thegate voltage 12 of a flash cell steps up from a starting cell level L0 through different cell levels L1, L2, and L3, cell levels collectively shown as 14. As shown at 16, cell levels L0, L1, L2, and L3 correspond tocell states gate voltage 12 at a wordline (WL) ramps up, a sense operation occurs at each level for determination of the cell data. Within each sense operation,conventional steps 18 include equalization (A), amplification (B), comparison (C), and data out (D). - In a first sense operation 20, the WL ramps from L0 to L1 and goes through steps A and B. Before the first sense operation is completed, a second sense operation 22 begins with the WL ramping up from L1 to L2. The first sense operation completes with steps C and D as step A begins in the second sense operation 22. In a
third sense operation 24, the WL ramps up from L2 to L3 as steps A and B occur. The second sense operation 22 finishes during step A of thethird sense operation 24. The third sense operation is completed as the WL returns to L0. Depending on the sense scheme and the Vt of the flash cell, thegate voltage 12 may ramp down to adifferent voltage 12a in thethird sense operation 24. - In sensing operations, a sense amplifier is used for determination of the value of cell data and the output from the sense amplifier would input data into a bus. The sense amplifier is initially set to a known state at the beginning of the sense operations.
FIG. 1 further shows sense amplifier output at the various cell levels at 26, corresponding in time with steps in thesense operations 20, 22, 24. - Referring to
FIG. 2 , a serial-parallel sense scheme in accordance with one embodiment of the present invention is shown at 50. A wordline (WL) 51 of a flash cell would directly ramp to cell level L2 at the beginning of afirst sense operation 52, and obviating the need for a sense operation at cell level L1. The WL need only ramp up to two different cell levels, namely L2 and L3 in contrast to the scheme ofFIG. 1 which required WL to go through three different cell levels. - In a
first sense operation 52, the WL ramps from L0 to L2 and goes through steps A and B. Before the first sense operation is completed, asecond sense operation 54 begins with the WL ramping up to L3. The first sense operation completes with steps C and D as step A begins in thesecond sense operation 54. As the second sense operation goes through steps C and D, the voltage ramps back down, and a third sense operation is not needed.FIG. 2 further shows sense amplifier output at the various cell levels at 56, corresponding in time with steps in thesense operations - It is noteworthy that a most significant bit is resolved during the step C of the
first sense operation 52, in contrast to the conventional sense scheme ofFIG. 1 . It is also noted that the gate voltage and time increments as represented inFIGS. 1 and 2 are not necessarily drawn to scale. Further, the voltage may vary from one level to another. - Turning to
FIG. 3 , a method of sensing data in a multi-level cell memory according to one embodiment of the present invention is indicated at 100.Method 100 includes, at 102, a step of ramping a wordline (WL) of a multi-level cell (MLC) flash memory to a first cell level L2. Atstep 104, the method includes performing a first sense operation at IREF1, which may be defined as the equivalent reference current at the threshold voltage Vt of the flash cell. In one embodiment, the first sense operation is performed at 7.5 μA of reference current. - The
method 100 includes determining a value of most significant bit (MSB) data atstep 106. The MSB data may be determined and captured at the end of the first sense operation when the WL is at cell level L2. Thus, the MSB data is resolved at the first sense operation. - If MSB data is determined to equal 1, the method further includes
step 108 of ramping the WL to a second cell level L3. At the end of the first sense operation, the WL is at L3.Method 100 further includes, at 110, performing a second sense operation at IREF2, where IREF2 is greater than IREF1. In one embodiment, IREF2 is equivalent to a reference current for an erased flash cell having L3 at its gate. For example, IREF2 may be approximately 25 μA of reference current. - At 112,
method 100 includes adjusting the column load of a sense circuit for sensing data in the MLC memory. The column load may be reconfigured in the second sense operation based on a selected reference current or based on MSB data. In one embodiment, the method may include a step of determining whether column load adjustment is needed. -
Method 100 further includesstep 114 wherecell states - Returning to
step 106, after determining a value of MSB data, if MSB is determined to equal 0, the output from the sense amplifier trips a bus at 116. This bus may include a READ/VerifyBUS, or other bus suitable to receive output from the sense amplifier. - At
step 118 ofmethod 100, the MSB data is resolved and the wordline ramps to L3. The method includes, at 120, performing a second sense operation at IREF1 and, at 122, differentiating between the cell states 01 (L3) or 00 (L2). The data of the MLC memory is resolved. - It is noted that the cell states and cell levels as used herein subscribe to one convention. Other conventions may be used and are considered to fall within the scope of this invention. For example, in a different convention, cell level L2 may correspond to
cell state 01. - Referring to
FIG. 4 , asensing circuit 200 for implementation of an MLC serial-parallel sense scheme according to one embodiment is shown.Sensing circuit 200 has anarray side 202 including aflash cell 204, adecoding device 206, and acascode device 208. The flash cell may be any non-volatile memory that can be electrically erased and reprogrammed. The control gate of the flash cell is tied to a wordline (WL) where voltage may be controlled. -
Sensing circuit 200 further includes areference side 210 including adecoding device 212 and acascode device 214. Thedecoding devices cascode devices cascode reference node 218. - A
sense line 220 on thearray side 202 provides input to a positive terminal of asense amplifier 222. Asense line 224 on thereference side 210 provides input to a negative terminal of the sense amplifier. Thecascode devices - In one embodiment, the
sensing circuit 200 usesmultiple mirror devices 224 to provide different reference currents. As shown, for example, when IREF1 is the selected current for use in a sense operation (selected current), aswitch 226 at the array side of the sensing circuit is closed, while aswitch 228 for IREF2, parallel to switch for IREF1, is open. Generally, a corresponding switch, for example,switch 230, at the reference side of the sensing circuit is closed for IREF1 to be selected. When IREF2 is the selected current, switches 228 and 232, at the array side and the reference side, respectively, are closed, whileswitches - In an alternate embodiment, separate reference current generators may be used instead of the multiple mirror devices. The reference current generators may give design flexibility in controlling different levels in an MLC sense scheme.
- The
sense amplifier 222 takes the input fromsense lines bus 236. As mentioned above, a bus may include a READ/VerifyBUS, or other bus suitable to receive output from the sense amplifier. - Referring to
FIG. 5 , one embodiment of the sense amplifier ofFIG. 4 is shown in detail. Thesense amplifier 222 may include acolumn load adjuster 300, acomparator device 302, and adata propagation device 304. - On the array side where the input to the
sense amplifier 222 is coming from thesense line 220, thecolumn load adjuster 300 may include avariable resistor 306 coupled to akicker device 308. The kicker device may be switched on by a controller (not shown) when it is determined that the charge in adecoding device 206 is insufficient. When the kicker device is on, theresistor 306 effectively adjusts the column load through thedecoding device 206. Similarly, on the reference side where the input to thesense amplifier 222 is coming from thesense line 224, thecolumn load adjuster 300 may include avariable resistor 310 coupled to akicker device 312. Alternatively, it is not necessary for the resistance of the resistors to be variable. - The
kicker devices kicker device 308 may be different from the signal tokicker device 12, depending on the column loads in thearray side 202 and thereference side 210. The additional resistance provided to each sense line may vary depending on the needs of eachdecoding device 206 anddecoding device 212. - The
comparator device 302 receives input fromsense lines comparator device 302 enters thedata propagation device 304, which also includes a circuit (not shown) with transistors and comparators. The data propagation device may manipulate or enhance the input that it receives from the comparator device and generates output that may enter a bus. Depending on the value of the output, the bus may trip. In another embodiment, more than one output signal may be generated by the comparator device and may enter the data propagation device via a different circuit path. As a result, multiple signals may exit the data propagation device and fed to a bus. - It should be noted that other configurations of a sensing circuit and sense amplifier may be used to implement an MLC serial-parallel scheme and obtain characteristics and/or results similar to those shown and/or described above.
- As seen throughout the disclosure, the MLC serial-parallel sense scheme would eliminate the need of a third sense operation required for current MLC sense scheme which could be used for faster access time (projected to reduce access time by 10 ns) or improved Read Window Budget (RWB) for 45 nm/30 nm technology timeframe. At the same time, dynamic adjustment of the column load in the circuit implementation is available.
- According to one embodiment, the serial-parallel sense scheme allows performing sense operation using two stages instead of three stages of operation and also gain from the present reduction of 1/f noise by utilizing common reference current. The sense operation is reduced by approximately 20% (10-15 ns) which translates to a savings of read window budget (RWB) in the range between 100 mV to 400 mV. In turn, MLC sense operation in 30 nm and 45 nm process technology may be feasible.
- It is appreciated that the invention has been explained with reference to one exemplary embodiment, and that the invention is not limited to the specific details given above. References in the specification made to other embodiments fall into the scope of the present invention.
- The steps as presented in one embodiment of a method according to the present invention do not necessarily follow the particular order in which they were presented. For example, consecutive steps may occur simultaneously.
- Any reference to device may include a component, circuit, module, or any such mechanism in which the device can achieve the purpose or description as indicated by the modifier preceding the device. However, the component, circuit, module, or any such mechanism is not necessarily a specific limitation to the device.
- Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the invention. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
- If the specification states a component, feature, structure, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
- Those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present invention. Indeed, the invention is not limited to the details described above. Rather, it is the following claims including any amendments thereto that define the scope of the invention.
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KR20120011642A (en) | 2010-07-29 | 2012-02-08 | 삼성전자주식회사 | Non-volatile memory device having reference cells and reference current setting method thereof |
US9076547B2 (en) | 2012-04-05 | 2015-07-07 | Micron Technology, Inc. | Level compensation in multilevel memory |
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US7057934B2 (en) * | 2004-06-29 | 2006-06-06 | Intel Corporation | Flash memory with coarse/fine gate step programming |
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