US20080286925A1 - Nonvolatile memory with backplate - Google Patents

Nonvolatile memory with backplate Download PDF

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Publication number
US20080286925A1
US20080286925A1 US12/127,561 US12756108A US2008286925A1 US 20080286925 A1 US20080286925 A1 US 20080286925A1 US 12756108 A US12756108 A US 12756108A US 2008286925 A1 US2008286925 A1 US 2008286925A1
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gate
dielectric layer
dual
gate electrode
tungsten
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US12/127,561
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Andrew J. Walker
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

  • the present invention relates to semiconductor devices.
  • the present invention relates to serially-connected dual-gate devices used in non-volatile memory strings.
  • a NAND-type memory string consists of a number of serially connected storage transistors.
  • the source terminal of the storage transistor to be programmed is connected to a predetermined low voltage at one end of the memory string through inversion channels of all the intermediate storage transistors situated in between that end of the memory string and the storage transistor to be programmed.
  • the inversion channel of each of the intermediate storage transistors is made conducting by applying a “program pass voltage” at the gate electrode of the intermediate storage transistor.
  • a programming voltage is then applied to the storage transistor to be programmed.
  • the programming voltage is much higher than the program pass voltage.
  • a common problem with such a NAND-type flash memory string is “program disturb,” which occurs during programming of a memory cell in a NAND-type memory string.
  • program disturb By applying a program pass voltage at the gate electrode, electrons in the inversion layer associated with an intermediate storage transistor may inadvertently be introduced into the charge storage gate dielectric layer of the intermediate storage transistor, thereby disturbing the programmed state of the intermediate storage transistor.
  • the present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common.
  • the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.
  • FIG. 1 shows NAND-type non-volatile memory string 100 , including serially connected dual-gate devices 101 - 1 to 101 - 6 , in accordance with one embodiment of the present invention.
  • the present invention provides a NAND-type non-volatile memory string using dual-gate devices that share a common back gate.
  • Dual-gate devices have been used in non-volatile memory strings (e.g., NAND-type flash memory strings).
  • non-volatile memory strings e.g., NAND-type flash memory strings.
  • Such non-volatile memory strings are described, for example, in copending U.S. patent application (“Copending Application”), entitled “DUAL-GATE DEVICE AND METHOD,” Ser. No. 11/197,462, filed on Aug. 3, 2005, describes various configurations of dual-gate devices that can be used to form NAND memory strings to achieve very high storage densities.
  • the disclosure of the Copending Application is hereby incorporated by reference in its entirety to provide background information regarding dual-gate memory devices.
  • FIG. 1 shows NAND-type non-volatile memory string 100 , including serially connected dual-gate devices 101 - 1 to 101 - 6 , in accordance with one embodiment of the present invention.
  • each dual-gate device e.g., dual-gate device 101 - 1
  • first gate electrode 109 also referred to as “front gate electrode”
  • storage gate dielectric layer 108 N + source-drain diffusion regions 110
  • lightly doped channel region 107 e.g., second gate dielectric layer 106 and common gate electrode 102
  • Second gate dielectric layer 106 and common gate electrode 102 are shared among dual-gate devices 101 - 1 to 101 - 6 .
  • second gate dielectric layer 106 is not charge-storing.
  • Common gate electrode 102 also referred to as the “backplate”, allows inversion to take place within channel region 107 adjacent second gate dielectric layer 106 and coincident with backplate gate electrode 102 .
  • any of dual-gate devices 101 - 1 to 101 - 6 may be programmed by applying a programming voltage to the corresponding front gate electrode 109 , with the connection to the low voltage reference provided by inversion layers in the lightly doped channel regions 107 induced by the backplate. Accordingly, no program pass voltage is applied to the front gate electrode in any of the intermediate storage transistors, thereby avoiding possible program disturb.
  • common electrode 102 may be implemented by a suitable conductor, such as doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.
  • Second gate dielectric layer 106 may be implemented by an insulator oxide, e.g., silicon dioxide, or a high dielectric constant (“High-K”) material.
  • Lightly doped channel region 107 may be provided by amorphous silicon, germanium, a combination of amorphous silicon and germanium, polycrystalline silicon, or a combination of polycrystalline silicon and germanium.
  • the dopant concentration may be either p-type or n-type, at a concentration between 10 14 cm ⁇ 3 to 10 19 cm ⁇ 3 .
  • Source-drain diffusion regions 110 may be provided by heavily-doped amorphous silicon, germanium, a combination of heavily-doped amorphous silicon and germanium, polycrystalline silicon, or a combination of polycrystalline silicon and germanium.
  • the dopant concentration may be either p-type or n-type, at a concentration between 10 19 cm ⁇ 3 to 10 21 cm ⁇ 3 .
  • First charge storage gate dielectric layer 108 may include stacked layers of materials, such as a silicon dioxide-silicon nitride-silicon dioxide stack.
  • the silicon nitride in the stack may be provided instead by a silicon oxynitride layer or a graded layer of silicon nitride with spatial variations in oxygen content.
  • nanocrystals of silicon, germanium or a metal e.g., tungsten
  • Other possible materials for first charge storage gate dielectric layer 108 include aluminum oxide or another High-K material.
  • first charge storage gate dielectric layer 106 may include, in order from first gate electrode 109 to lightly doped channel region 107 , a 50-200 ⁇ thick layer of aluminum oxide, a 50-150 ⁇ thick silicon nitride, and a 15-60 ⁇ thick silicon dioxide.
  • First gate electrode 109 may be provided by a suitable conductor (e.g., doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more these materials).
  • a suitable conductor e.g., doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more these materials.

Abstract

The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common. In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • The present application is a division of U.S. patent application Ser. No. 11/749,060 filed on May 15, 2007, which is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to semiconductor devices. In particular, the present invention relates to serially-connected dual-gate devices used in non-volatile memory strings.
  • 2. Discussion of the Related Art
  • A NAND-type memory string consists of a number of serially connected storage transistors. During programming of a NAND-type memory string, the source terminal of the storage transistor to be programmed is connected to a predetermined low voltage at one end of the memory string through inversion channels of all the intermediate storage transistors situated in between that end of the memory string and the storage transistor to be programmed. To provide that connection, the inversion channel of each of the intermediate storage transistors is made conducting by applying a “program pass voltage” at the gate electrode of the intermediate storage transistor. A programming voltage is then applied to the storage transistor to be programmed. Typically, the programming voltage is much higher than the program pass voltage.
  • A common problem with such a NAND-type flash memory string is “program disturb,” which occurs during programming of a memory cell in a NAND-type memory string. By applying a program pass voltage at the gate electrode, electrons in the inversion layer associated with an intermediate storage transistor may inadvertently be introduced into the charge storage gate dielectric layer of the intermediate storage transistor, thereby disturbing the programmed state of the intermediate storage transistor.
    • SUMMARY
  • The present invention provides a non-volatile memory string having serially connected dual-gate devices, in which a first gate dielectric layer adjacent a first gate electrode layer in each dual-gate device is charge-storing and in which the second gate electrode adjacent a non-charge storing gate dielectric layer are connected in common.
  • In one implementation, the second gate electrodes of the dual-gate devices in the memory string are provided by a continuous layer of doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors.
  • The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawing.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows NAND-type non-volatile memory string 100, including serially connected dual-gate devices 101-1 to 101-6, in accordance with one embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The present invention provides a NAND-type non-volatile memory string using dual-gate devices that share a common back gate. Dual-gate devices have been used in non-volatile memory strings (e.g., NAND-type flash memory strings). Such non-volatile memory strings are described, for example, in copending U.S. patent application (“Copending Application”), entitled “DUAL-GATE DEVICE AND METHOD,” Ser. No. 11/197,462, filed on Aug. 3, 2005, describes various configurations of dual-gate devices that can be used to form NAND memory strings to achieve very high storage densities. The disclosure of the Copending Application is hereby incorporated by reference in its entirety to provide background information regarding dual-gate memory devices.
  • FIG. 1 shows NAND-type non-volatile memory string 100, including serially connected dual-gate devices 101-1 to 101-6, in accordance with one embodiment of the present invention. As shown in FIG. 1, each dual-gate device (e.g., dual-gate device 101-1) includes first gate electrode 109 (also referred to as “front gate electrode”), storage gate dielectric layer 108, N+ source-drain diffusion regions 110, lightly doped channel region 107, second gate dielectric layer 106 and common gate electrode 102. Second gate dielectric layer 106 and common gate electrode 102 are shared among dual-gate devices 101-1 to 101-6. In this embodiment, second gate dielectric layer 106 is not charge-storing.
  • Common gate electrode 102, also referred to as the “backplate”, allows inversion to take place within channel region 107 adjacent second gate dielectric layer 106 and coincident with backplate gate electrode 102. Under this configuration, any of dual-gate devices 101-1 to 101-6 may be programmed by applying a programming voltage to the corresponding front gate electrode 109, with the connection to the low voltage reference provided by inversion layers in the lightly doped channel regions 107 induced by the backplate. Accordingly, no program pass voltage is applied to the front gate electrode in any of the intermediate storage transistors, thereby avoiding possible program disturb.
  • According to one embodiment of the present invention, common electrode 102 may be implemented by a suitable conductor, such as doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more of these conductors. Second gate dielectric layer 106 may be implemented by an insulator oxide, e.g., silicon dioxide, or a high dielectric constant (“High-K”) material. Lightly doped channel region 107 may be provided by amorphous silicon, germanium, a combination of amorphous silicon and germanium, polycrystalline silicon, or a combination of polycrystalline silicon and germanium. The dopant concentration may be either p-type or n-type, at a concentration between 1014 cm−3 to 1019 cm−3. Source-drain diffusion regions 110 may be provided by heavily-doped amorphous silicon, germanium, a combination of heavily-doped amorphous silicon and germanium, polycrystalline silicon, or a combination of polycrystalline silicon and germanium. The dopant concentration may be either p-type or n-type, at a concentration between 1019 cm−3 to 1021 cm−3.
  • First charge storage gate dielectric layer 108 may include stacked layers of materials, such as a silicon dioxide-silicon nitride-silicon dioxide stack. Alternatively, the silicon nitride in the stack may be provided instead by a silicon oxynitride layer or a graded layer of silicon nitride with spatial variations in oxygen content. In another alternative implementation, instead of silicon nitride, nanocrystals of silicon, germanium or a metal (e.g., tungsten) may be provided. Other possible materials for first charge storage gate dielectric layer 108 include aluminum oxide or another High-K material. In one embodiment, first charge storage gate dielectric layer 106 may include, in order from first gate electrode 109 to lightly doped channel region 107, a 50-200 Å thick layer of aluminum oxide, a 50-150 Å thick silicon nitride, and a 15-60 Å thick silicon dioxide.
  • First gate electrode 109 may be provided by a suitable conductor (e.g., doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more these materials).
  • The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.

Claims (5)

1. A method in a NAND-type non-volatile memory string, comprising:
Serially connecting a plurality of dual-gate devices, wherein each dual-gate device having a first gate dielectric layer provided between a first gate electrode and a lightly doped channel region and a second gate dielectric layer provided between the lightly doped channel region and a second gate electrode and wherein the first gate dielectric layer is charge-storing; and
providing the second gate electrodes as a continuous layer conducting material.
2. A method as in claim 1, further comprising providing the first gate dielectric layer as stacked layers of materials.
3. A method as in claim 2 wherein the materials comprise a selected charge-storing material between silicon oxide layers.
4. A method as in claim 3 wherein the charge-storing material comprises one or more of: silicon nitride, silicon oxynitride, a graded layer of silicon nitride with spatial variations in oxygen content, nanocrystals of silicon, germanium, tungsten or another metal, aluminum oxide, or a High-K material.
5. A method as in claim 1, wherein the first gate electrode comprises doped polysilicon, tungsten, tantalum nitride, tungsten nitride or any combination of two or more these conductors.
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