US20080252355A1 - Super-Symmetric Multiplier - Google Patents
Super-Symmetric Multiplier Download PDFInfo
- Publication number
- US20080252355A1 US20080252355A1 US11/768,142 US76814207A US2008252355A1 US 20080252355 A1 US20080252355 A1 US 20080252355A1 US 76814207 A US76814207 A US 76814207A US 2008252355 A1 US2008252355 A1 US 2008252355A1
- Authority
- US
- United States
- Prior art keywords
- coupled
- transistor
- input
- tanh
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
Definitions
- the collectors of Q 1 and Q 4 are connected together to provide a first output current I M , and the connectors of Q 2 and Q 3 are connected together to provide a second output current I P which, in combination with I M , provides a differential output signal I OUT .
- the scaling of the multiplier is set by the value of I T which determines the transconductance of the entire multiplier.
- the bias current may be utilized as a third multiplying input.
- I OUT exp ⁇ ( X + Y ) + exp ⁇ ( - X - Y ) - exp ⁇ ( - X + Y ) - exp ⁇ ( - X - Y ) exp ⁇ ( X + Y ) + exp ⁇ ( - X + Y ) + exp ⁇ ( - X + Y ) + exp ⁇ ( - X - Y ) ⁇ I T ( Eq . ⁇ 2 ) ⁇
- the output from a multiplier cell may be obtained by using nothing more than low-value resistive loads at the summed collector outputs.
- cascodes may be included between the core collectors and the system outputs to minimize the Miller multiplication of the parasitic capacitance that the summing nodes are burdened with.
- a broadband transimpedance output stage may be utilized, such as the triple Darlington-type arrangement shown in FIGS. 17 and 18 of U.S. Patent Application Publication No. 2005/0030121 by the same inventor as the present patent disclosure, which is incorporated by reference.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
Abstract
Description
- This application claims priority from U.S. Provisional Patent Application Ser. No. 60/912,158 having the same title and filed Apr. 16, 2007 which is incorporated by reference.
-
FIG. 1 illustrates a prior art four-quadrant multiplier based on a common-emitter multi-tanh transistor cell. The circuit ofFIG. 1 includes a core of four transistors Q1-Q4 having their emitters connected together at a common node N1. A current source IT is connected to N1 to provide a bias current (or “tail current”) for transistors Q1-Q4. The X and Y inputs are applied to a network of input resistors R1-R8 as differential voltages ±VX and ±VY. The collectors of Q1 and Q4 are connected together to provide a first output current IM, and the connectors of Q2 and Q3 are connected together to provide a second output current IP which, in combination with IM, provides a differential output signal IOUT. The scaling of the multiplier is set by the value of IT which determines the transconductance of the entire multiplier. Thus, the bias current may be utilized as a third multiplying input. - The signals at the bases of Q1-Q4 are designated as X+Y, X−Y, Y−X and −X−Y, respectively. The variables X and Y are defined as X=VX/2VT and Y=VY/2VT, where VT is the thermal voltage kT/q. Thus, X and Y are normalized dimensionless variables. The need for the factor 2 in the denominator is apparent from
FIG. 1 ; for example, if +VX is held constant and +VY is increased by some amount, one-half of the increase is applied to the base of Q1. - For a generalized common-emitter multi-tanh transistor cell having N transistors, the collector currents bear the following relationships:
-
- Inserting the base voltages and adding the collector currents with the appropriate phasing as shown in
FIG. 1 , we have -
- Using the truncated expansion exp(u)≈1+u+u2/2 for the exponential functions of the individual transistors it can be shown that the differential output current IOUT may be approximated as follows:
-
- The product term (X2+Y2) diminishes when X and Y are relatively small, and thus the equation collapses to IOUT≈XYIT which provides a useful multiplication function at low input signal levels. As the magnitude of the X or Y input increases, however, the product term (X2+Y2) in the denominator of Eq. 3 increases to the point that the approximation breaks down. In a typical implementation, the multiplier of
FIG. 1 has an acceptably linear input range of about ±40 mV, beyond which, the behavior starts to enter a limiting domain of operation. -
FIG. 1 illustrates a prior art four-quadrant multiplier based on a common-emitter multi-tanh transistor cell. -
FIG. 2 illustrates an embodiment of a multi-tanh circuit according to some of the inventive principles of this patent disclosure. -
FIG. 3 illustrates an embodiment of a four-quadrant multiplier according to some of the inventive principles of this patent disclosure. -
FIG. 4 illustrates an embodiment of a four-quadrant multiplier having a multi-tanh cell with additional series-connected junctions according to some of the inventive principles of this patent disclosure. -
FIG. 5 illustrates an embodiment of a circuit having dual multipliers according to some of the inventive principles of this patent disclosure. -
FIG. 6 illustrates another embodiment of a circuit having dual multipliers according to some of the inventive principles of this patent disclosure. - To gain a better understanding of the inventive principles of this patent disclosure, some of the salient aspects of the prior art will first be discussed with reference to
FIG. 1 . One possible approach to increasing the linear input range of the circuit ofFIG. 1 would be to utilize larger input signals, and then scale the inputs down to operate within the linear range of the multiplier. However, there are at least two disadvantages to such an approach. First, mismatches in the transistors become increasingly important at low signal levels. Thus, operating with only a few millivolts of swing would be problematic. Second, the noise floor, which is determined predominantly by the emitter current and the input resistors R1-R8, does not change as the input signals are scaled down. This sets a practical limit on the lower end of the useful input signal range. - Another possible approach to increasing the linear input range of a multi-tanh cell involves the use of transistors having different emitter areas. However, in the circuit of
FIG. 1 , any variation in transistor sizes would destroy the symmetry and balance which are important in a multiplier. Likewise, any variation in the resistor ratios in the input resistor matrix would upset the function of the circuit which is fundamentally a matter of balancing and sharing the various input voltages. -
FIG. 2 is a conceptual illustration of a multi-tanh circuit that may overcome some of these problems according to the inventive principles of this patent disclosure. The circuit ofFIG. 2 includes a common-emittermulti-tanh cell 10 having any suitable number of transistors arranged in an appropriate topology. Although a particularly useful embodiment with a four-transistor multi-tanh cell will be described below, the inventive principles are not limited to any particular type of multi-tanh cell. See, e.g., The Multi-tanh Principle: A Tutorial Overview, IEEE Journal of Solid-State Circuits, Vol. 33, No. 1, January 1998, by the inventor of the present patent disclosure. - A tail current IT is coupled to the common emitter node N1 to bias the
multi-tanh cell 10, thereby setting the initial (or nominal) transconductance of the cell. However, an extra transistor Q is coupled to the common emitter node and arranged to dynamically divert a portion of the tail current from the multi-tanh cell. In this example, the emitter of Q is coupled to common emitter node, the collector is attached to a point such a power supply where the diverted tail current may be routed, and the base is anchored to any suitable point that may, for example, be responsive to the inputs of the multi-tanh cell. - By diverting a portion of the tail current at low input signal levels, the extra transistor may increase the compliance of the common emitter node. For example, a conventional multi-tanh cell may be designed to operate with a certain amount of tail current IT1. By adding the extra transistor Q, the value of IT may be increased to provide an additional amount of tail current IT2 which is normally diverted by Q. Thus, the tail current is normally split between the multi-tanh cell and the extra transistor Q. However, when the magnitude of one or more of the input signals increases to a level that would exceed the linear input range of the multi-tanh cell, some of the additional tail current IT2 may be redirected back from Q to the multi-tanh cell, thereby extending the linear input range. Moreover, this increase in linear range may be obtained without increasing the noise floor as discussed below.
-
FIG. 3 illustrates an embodiment of a four-quadrant multiplier according to some of the inventive principles of this patent disclosure. The circuit ofFIG. 3 includes a common-emitter multi-tanh core Q1-Q4 and input network R1-R8 arranged as in a conventional multiplier. However, the circuit includes an extra transistor Q5 having an emitter coupled to the common emitter node N1, a collector coupled to supply voltage +VS and a base anchored to a point VA which is driven by a signal representing the mean of the input signals. In this example, the mean is provided by coupling the base of Q5 back to the inputs +VX, −VX, +VY and −VY through resistors R10-R13, respectively. - Because the extra transistor Q5 is outside of the multi-tanh core, its size may be varied relative to the other transistors without destroying the symmetry of the core. A variable K may be defined as the emitter area of Q5 relative to the emitter areas of transistors Q1-Q4. Eq. 2 may then be modified as follows:
-
- The linearity of this function with respect to either X or Y may be considerably enhanced for K>0 which may be implemented by the extra transistor Q5.
- The expansion of exp(u) used to generate the approximation for Eq. 3 is less accurate here, but as a rough guide, the result is
-
- Although the approximation of Eq. 5 is not as analytically rigorous as the approximation of Eq. 3, it is still useful for conceptualizing the effect of the emitter area ratio K on the operation of the circuit. The output may be described as being “diluted” in a sense by the factor (1+K). That is, K works by diluting the nonlinearity of X2+Y2 in the denominator. As K increases, more of the tail current under quiescent conditions is diverted by Q5. Increasing the value of K enables the circuit to accommodate large input signal swings.
- To better illustrate these effects, some example vales will be assigned to the variables. For purposes of illustration and computational simplicity, Q5 will be assumed to have an emitter area of 9 units, while Q1-Q4 are assumed to have emitter areas of 1 unit each. Thus, K=9 in this example, and all 5 transistors have a combined emitter area of 13 unites. Also, the tail current IT is assumed to have a nominal value of 13 milliamps. Under quiescent conditions, 1/13th of the total tail current, or 1 mA, flows through each of Q1-Q4, and 9/13ths of the total tail current, or 9 mA, flows through Q5. Therefore, the total common mode current coming out of the multiplier core is 4/13ths of the total tail current. This might initially seem to indicate worse noise performance because the output is reduced, but the noise would seem to be worsened by partition noise. However, the partition effect only affects the common node noise which is related to the total current coming out of Q1-Q4. Thus, the presence of Q5 extends the upper end of the linear input range without increasing the noise floor at the lower end.
-
FIG. 4 illustrates another embodiment of a four-quadrant multiplier having a multi-tanh cell with additional series-connected junctions according to some of the inventive principles of this patent disclosure. The embodiment ofFIG. 4 includes a common-emitter multi-tanh core Q1-Q4 having an extra transistor Q5 as inFIG. 3 , but the input resistors are omitted for simplicity. - The embodiment of
FIG. 4 also includes one or more additional ranks of junctions (Q1A-Q1C, Q2A-Q2C, etc.) in the form of diode-connected transistors connected between the emitters of transistors Q1-Q5 and the common-emitter node N1. The junctions in series with Q5 are scaled in the same way as Q5. The inclusion of extra junctions extends the input voltage range over which the multiplier exhibits linear behavior. Although there is a noise penalty associated with the additional ranks of junctions, the extension of linear input range has a greater impact than the increased noise. For example, for a given tail current, doubling the number of junctions in each leg from one to two doubles the voltage range over which the input voltages exert a certain effect in terms of current densities. However, assuming the noise in each junction is en, the RMS sum of the noise from the two junctions is √{square root over (2)}en. Therefore, the linear input range is increased by a factor of two, but the noise only increases by a factor of √{square root over (2)}. Doubling the number of junctions in each leg increases the dynamic range by 3 dB, and thus, including a total of four junctions in each leg as shown inFIG. 4 provides a 6 dB improvement in signal-to-noise ratio (SNR). Moreover, in addition to improving the SNR, the quadrupling of the input voltage range may result in a circuit that can directly accept user-level signals, e.g., ±500 mV. - Although the increased number of transistors may initially seem to introduce a possibility of device mismatches, the large number of devices may actually result in self-canceling deviations and thus, there may be no performance penalty from a device matching point of view. Moreover, the increased number of devices may enable more robust cross-quadding arrangements. Note that the effective area of the combination of Q5, Q5A, etc. is the geometric mean of the emitter areas, and thus, may be achieved through various combinations of devices sizes.
-
FIG. 5 illustrates an embodiment of a circuit having dual multipliers according to some of the inventive principles of this patent disclosure. The circuit ofFIG. 5 includes twoidentical multipliers first multiplier 12 receives X and Y inputs, and thesecond multiplier 14 receives a U input and a feedback input. The outputs of the multipliers are combined at the input to abuffer 16 which provides a final output signal W. The output is fed back to the second multiplier through an attenuator having an attenuation factor K. The final output may be expressed as follows: -
- where X and Y are multiplier inputs and U is a scaling input.
- An advantage of the arrangement of
FIG. 5 is that nonlinearities in the multipliers may be canceled through the use of identical multipliers. If a reference signal is applied as the U input, and an integrating buffer is used, the feedback loop servos the system to force the outputs of the two multiplier cells to be equal. Changing the attenuation factor in the feedback path changes the gain of the system without affecting the linearity. - The inventive principles relating to multi-tanh cells having extra transistors may be utilized in a dual multiplier feedback arrangement as illustrated in
FIG. 5 to provide a robust and versatile multiplier system with synergistic properties.FIG. 6 illustrates an embodiment of such a system according to some of the inventive principles of this patent disclosure. - The system of
FIG. 6 includes twoidentical multipliers FIGS. 2-4 . The X and Y inputs are applied to the first multiplier as differential voltage signals ±VX and ±VY. A scaling signal U is applied to the second multiplier as a differential voltage signal ±VU. The other input to the second multiplier is provided by a summingcircuit 24 which combines the final output signal W with an offset signal Z. The output of thefirst multiplier 18 may be expressed as α1XY where α1 is a scaling factor determined by the tail current through the first multiplier. The output of the second multiplier may be expressed as α2U(W+Z) where α2 is the scaling factor of the second multiplier. - The outputs of the first and second multipliers are combined as an integrating node N2 which may be a simple summing node or, in the case of a differential embodiment, a pair of summing nodes. A
buffer 22 provides the final output W as a differential voltage ±VW. The integrating action of the buffer forces the outputs of multipliers to be equal. Assuming the scaling factors of the two multipliers are made equal, α1=α2, and the output may be expressed as follows: -
- Thus, the architecture of
FIG. 6 enables multiplication through the X and Y inputs and division through the U input, and also provides an offset through the Z input. The U input may alternatively be referenced to a high-accuracy reference signal. Themultipliers - The inventive principles of this patent disclosure have been described above with reference to some specific example embodiments, but these embodiments can be modified in arrangement and detail without departing from the inventive concepts. For example, some transistors have been illustrated as bipolar junction transistors (BJTs) of specific polarities, but MOS and other types and polarities of devices may be used as well. Thus, the terms base, emitter and collector are understood to refer to the corresponding terminals of other types of transistors. Area ratios may be realized with actual device sizes, or they may be realized as synthesized area ratios, collective unit devices, etc. Thus, emitter area refers to effective emitter area. Likewise, the emitters of the transistors in a common-emitter multi-tanh cell may be connected directly to the common-emitter node, which itself may include multiple nodes, or coupled indirectly through other components, e.g., emitter resistors.
- As a further elaboration, according to some inventive principles of this patent disclosure, four resistors may be tied from the emitters of Q1-Q4 to a common dangling node. Such resistors would exert an expansion of the transfer function to work against the compression at high inputs, albeit at the expense of some temperature sensitivity which may be minimized by choosing an appropriate temperature shape for the tail currents.
- The output from a multiplier cell according to some inventive principles of this patent disclosure may be obtained by using nothing more than low-value resistive loads at the summed collector outputs. In other embodiments, cascodes may be included between the core collectors and the system outputs to minimize the Miller multiplication of the parasitic capacitance that the summing nodes are burdened with. In more demanding applications, a broadband transimpedance output stage may be utilized, such as the triple Darlington-type arrangement shown in
FIGS. 17 and 18 of U.S. Patent Application Publication No. 2005/0030121 by the same inventor as the present patent disclosure, which is incorporated by reference. - Since the embodiments described above can be modified in arrangement and detail without departing from the inventive concepts, such changes and modifications are considered to fall within the scope of the following claims.
Claims (25)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/768,142 US7795948B2 (en) | 2007-04-16 | 2007-06-25 | Super-symmetric multiplier |
PCT/US2008/060341 WO2008128223A1 (en) | 2007-04-16 | 2008-04-15 | Super-symmetric multiplier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US91215807P | 2007-04-16 | 2007-04-16 | |
US11/768,142 US7795948B2 (en) | 2007-04-16 | 2007-06-25 | Super-symmetric multiplier |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080252355A1 true US20080252355A1 (en) | 2008-10-16 |
US7795948B2 US7795948B2 (en) | 2010-09-14 |
Family
ID=39853159
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/768,142 Active US7795948B2 (en) | 2007-04-16 | 2007-06-25 | Super-symmetric multiplier |
Country Status (2)
Country | Link |
---|---|
US (1) | US7795948B2 (en) |
WO (1) | WO2008128223A1 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5589791A (en) * | 1995-06-09 | 1996-12-31 | Analog Devices, Inc. | Variable gain mixer having improved linearity and lower switching noise |
US5926408A (en) * | 1995-07-28 | 1999-07-20 | Nec Corporation | Bipolar multiplier with wide input voltage range using multitail cell |
US5986494A (en) * | 1994-03-09 | 1999-11-16 | Nec Corporation | Analog multiplier using multitail cell |
US6204719B1 (en) * | 1999-02-04 | 2001-03-20 | Analog Devices, Inc. | RMS-to-DC converter with balanced multi-tanh triplet squaring cells |
US6437630B1 (en) * | 1999-12-28 | 2002-08-20 | Analog Devices, Inc. | RMS-DC converter having gain stages with variable weighting coefficients |
US6456142B1 (en) * | 2000-11-28 | 2002-09-24 | Analog Devices, Inc. | Circuit having dual feedback multipliers |
US20040164784A1 (en) * | 2000-09-29 | 2004-08-26 | Toshiyuki Umeda | Amplifier circuit |
-
2007
- 2007-06-25 US US11/768,142 patent/US7795948B2/en active Active
-
2008
- 2008-04-15 WO PCT/US2008/060341 patent/WO2008128223A1/en active Application Filing
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5986494A (en) * | 1994-03-09 | 1999-11-16 | Nec Corporation | Analog multiplier using multitail cell |
US5589791A (en) * | 1995-06-09 | 1996-12-31 | Analog Devices, Inc. | Variable gain mixer having improved linearity and lower switching noise |
US5926408A (en) * | 1995-07-28 | 1999-07-20 | Nec Corporation | Bipolar multiplier with wide input voltage range using multitail cell |
US6204719B1 (en) * | 1999-02-04 | 2001-03-20 | Analog Devices, Inc. | RMS-to-DC converter with balanced multi-tanh triplet squaring cells |
US6549057B1 (en) * | 1999-02-04 | 2003-04-15 | Analog Devices, Inc. | RMS-to-DC converter with balanced multi-tanh triplet squaring cells |
US6437630B1 (en) * | 1999-12-28 | 2002-08-20 | Analog Devices, Inc. | RMS-DC converter having gain stages with variable weighting coefficients |
US20030030478A1 (en) * | 1999-12-28 | 2003-02-13 | Analog Devices, Inc. | RMS-DC converter having gain stages with variable weighting coefficients |
US20040164784A1 (en) * | 2000-09-29 | 2004-08-26 | Toshiyuki Umeda | Amplifier circuit |
US6456142B1 (en) * | 2000-11-28 | 2002-09-24 | Analog Devices, Inc. | Circuit having dual feedback multipliers |
Also Published As
Publication number | Publication date |
---|---|
US7795948B2 (en) | 2010-09-14 |
WO2008128223A1 (en) | 2008-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7327183B2 (en) | Squaring cells and multipliers using summed exponentials | |
KR100214456B1 (en) | Differential pair based transconductance element with improved linearity and signal to noise ratio | |
US8089309B2 (en) | Transimpedance amplifier input stage mixer | |
Holdenried et al. | A DC-4-GHz true logarithmic amplifier: theory and implementation | |
JPH04506286A (en) | logarithmic amplifier | |
JPH06326536A (en) | Variable gain amplifier for low supply voltage system | |
CA2289212C (en) | Active phase splitter | |
JP2606599B2 (en) | Logarithmic amplifier circuit | |
US4268759A (en) | Signal-processing circuitry with intrinsic temperature insensitivity | |
US6456142B1 (en) | Circuit having dual feedback multipliers | |
US6590454B2 (en) | System and method for current splitting for variable gain control | |
US5444648A (en) | Analog multiplier using quadritail circuits | |
KR860001018B1 (en) | Gain control circuit | |
US7795948B2 (en) | Super-symmetric multiplier | |
JPH02295209A (en) | Fr doubler differential amplifier | |
EP0447980B1 (en) | Logarithmic amplifier with gain control | |
US6456161B2 (en) | Enhanced slew rate in amplifier circuits | |
Camenzind et al. | An outline of design techniques for linear integrated circuits | |
US6710657B2 (en) | Gain control circuit with well-defined gain states | |
US20030110199A1 (en) | Multiplier | |
NL8004844A (en) | THERMALLY COMPENSATED DIFFERENCE AMPLIFIER WITH VARIABLE GAIN. | |
GB2100541A (en) | Buffer amplifier | |
US4385364A (en) | Electronic gain control circuit | |
JPS6252488B2 (en) | ||
US6486735B1 (en) | Adaptive equalizer filter with variable gain control |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: ANALOG DEVICES, INC., MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GILBERT, BARRIE;REEL/FRAME:019675/0043 Effective date: 20070730 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |