US20080185575A1 - Manufacture method of multilevel phase-change memory and operating method thereof - Google Patents
Manufacture method of multilevel phase-change memory and operating method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000011017 operating method Methods 0.000 title abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 87
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- 239000013078 crystal Substances 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims description 17
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- 238000005530 etching Methods 0.000 claims description 9
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000010009 beating Methods 0.000 claims description 2
- 238000002425 crystallisation Methods 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000763 AgInSbTe Inorganic materials 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
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- 229910052682 stishovite Inorganic materials 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
Definitions
- the present invention relates to a semi-conductor memory, and more particular, to a multilevel phase-change memory.
- Most electronic equipment uses different types of memories, such as a DRAM, SRAM and Flash memory or the combination of these different types' memories based on the requirements of the application, the operating speed, the memory size and the cost consideration of the equipment.
- the current new developments in the memory field include FeRAM, MRAM and phase-change memory.
- a Phase-change memory records data by changing the material of the semi-conductor circuit to different phase states due to the resistance changes inside of the circuit.
- Many materials such as Ge 2 Sb 2 Te 5 and others, have the characteristics of changing to different crystallization states with different temperatures and different crystallization states have different resistance. Therefore, a phase-change memory using electrical heating can change materials, such as Ge 2 Sb 2 Te 5 , into different crystallization states, each having different resistance, where each different state can represent a different recording state, i.e., 0 or 1.
- a phase-change memory is non-volatile, it will retain data recorded even if the power is off. Therefore, during a data writing operation in a phase-change memory, the electrical current has to be supplied to the selected memory cells, which will cause phase transition after being heated up by heating electrodes.
- phase-change memory technology uses contact to make a phase area method, such as a structure combining phase-change memory and a CMOS transistor disclosed by Samsung Electronics Co., Ltd in IEDM 2003, which connects heating electrodes to the phase-change layer and uses the contact as a phase-change area.
- a phase area method such as a structure combining phase-change memory and a CMOS transistor disclosed by Samsung Electronics Co., Ltd in IEDM 2003, which connects heating electrodes to the phase-change layer and uses the contact as a phase-change area.
- STMicroelectronics & Ovonyx Inc. recommended another structure using the via as phase-change region, which fills the phase-change layer in the via to obtain a smaller switching current.
- the present invention provides a multilevel phase-change memory and its associated manufacture method, which will solve several existing problems in the prior art.
- the multilevel phase-change memory of the present invention includes a first phase-change layer, a second phase-change layer, a first heating layer formed on a first surface of the first phase-change layer, a second heating layer formed between the first phase-change layer and the second phase-change layer, a first top electrode formed on a second surface of the first phase-change layer, a second top electrode formed on a second surface of the second phase-change layer, and a bottom electrode formed on a second surface of the first heating layer opposite to the second heating layer.
- the multilevel phase-change memory further includes a substrate with a transistor, and the bottom electrode is formed on the substrate.
- the manufacture method of a multilevel phase-change memory includes providing a substrate with a transistor formed thereon, forming a bottom electrode on the substrate, forming a first heating layer on top of the bottom electrode, forming a second heating layer on top of the first heating layer, forming a phase-change layer on top of the second heating layer, etching the phase-change layer to form a first phase-change layer and a second phase-change layer, and forming a first top electrode and a second electrode on top of the second phase-change layer opposite to the first phase-change layer.
- the present invention provides an operating method of a multilevel phase-change memory including grounding the first top electrode and the second top electrode, and applying a pulse current to the bottom electrode, to make the first phase-change layer and the second phase-change layer change states thereof according to the pulse current.
- the operation method further includes converting the first phase-change layer and the second phase-change layer into a non-crystal state before applying the pulse current.
- Another operating method of a multilevel phase-change memory includes grounding the first top electrode and the second top electrode, and applying a pulse current to one of the first top electrodes and the second top electrodes.
- the present invention utilizes a single transistor to control two different contact regions of phase-change area, which can achieve a higher recording density by realizing multiple recordings in a single memory cell, and increases the density of the memory and reduces the power consumption.
- FIG. 1 is a structure of phase-change memory of the present invention.
- FIGS. 2A-2J illustrate different structures of the phase-change memory of the present invention during the manufacture process.
- FIGS. 3A-3B illustrate other different structures of the phase-change memory of the present invention during the manufacture process.
- FIG. 4 is the writing operation of the phase-change memory of the present invention.
- FIG. 5 is the reading operation of the phase-change memory of the present invention.
- the present invention multilevel phase-change memory comprises a first phase-change layer 10 , a second phase-change layer 20 , a bottom electrode 30 , a first top electrode 41 and a second top electrode 42 , a first heating layer 51 and a second heating layer 52 .
- the bottom electrode is formed on a substrate 100 .
- a transistor 70 formed on the substrate 100 using a compatible manufacturing process.
- the transistor can be either a P-type or an N-type MOSFET. If it is a P-type MOSFET, a P-type substrate is formed with the Group III element added in the substrate 100 and an N-type region formed with the Group V element is added in the transistor, which is connected to the bottom electrode 30 for signal transmitting.
- an N-type MOSFET an N-type substrate formed with a Group V element is added in the substrate 100 , while a P-type region (P-well) formed with a Group III element is added in the transistor which is connected to the bottom electrode 30 .
- a first heating layer 51 is formed, and then a second heating layer 52 is formed above.
- the area size of the first heating layer 51 is different from the area size of the second heating layer 52 .
- the area size between the first heating layer 51 and the second heating layer 52 can be the same.
- the material used for making the heating layer it can be poly-Si, SiC, TiW, TiN and/or TiAlN.
- the first phase-change layer 10 contacts the first heating layer 51 , and the second phase-change layer 20 is formed on the second heating layer.
- On top of the first phase-change layer 10 is the first top electrode 41 , and the second top electrode 42 is on top of the second phase-change layer 20 .
- the first phase-change layer 10 and the second phase-change layer can be made in the same step with similar material.
- different material can be used in different steps, so each phase-change layers and the selections of different materials can be GeSbTe, AgInSbTe, or GeInSbTe, etc.
- the bottom electrode 30 , the first top electrode 41 and the second top electrode 42 can be made from a metal material.
- an insulation layer 60 such as, SiO 2 , Si 3 N 4 , polymer etc
- each phase-change layer has two states: crystal and non-crystal, and each phase-change layer can change its state by heating, therefore, two phase-change layers can form a multilevel phase-change memory.
- FIG. 2A-2J they is a manufacture process for multilevel phase-change memory of the present invention.
- a transistor may be formed if chosen; then an insulation layer 101 is laid on the top of the substrate 100 ; next, a guiding hole is etched on the insulation layer 101 and metal is filled into the hole to form the bottom electrode 102 as shown in FIG. 2A .
- the first heating layer 103 is formed above the bottom electrode 102 , and an insulation layer 104 is placed on top of the heating layer 103 , as shown in FIG. 2B .
- a guiding hole 105 is etched on the insulation layer 104 which is also aligned with the bottom electrode 102 ; then the second heating layer 106 is formed on top of the insulation layer 104 , as shown in FIGS. 2C and 2D ; through the guiding hole, the first heating layer 103 makes contact with the second heating layer 106 to be able to heat the phase-change layer in various degrees.
- the first heating layer 103 and the insulation layer 104 are etched into a form shown in 2 E and 2 F.
- phase-change layer 107 is formed on top of the second heating layer 106 as shown in FIG. 2F and then it is etched into the first phase-change layer 107 A and the second phase-change layer 107 B; Then, an insulation layer 108 is formed and two guiding holes 109 , 110 are etched, as shown in FIGS. 2G-2I .
- first phase-change layer and the second phase-change layer are made from the same material. In other embodiments, they can be made from different material.
- first electrode 111 and second electrode 112 are formed as shown in FIG. 2J .
- the second heating layer 113 is formed by depositing and etching into a specified size, as shown in FIGS. 3A and 3B . Then, an insulation layer 114 is formed after etching above the second heating layer 114 , as shown in FIG. 2E .
- the resistance ratio between two corresponding conductors are: An electrical current path is from the bottom electrode 30 via the first heating layer 51 and then to the first phase-change layer 10 . Another electrical current path is from the bottom electrode 30 , via the first heating layer 51 and the second heating layer 52 and then to the second phase-change layer 20 ) at non-crystal states are:
- the first phase-change layer and the second phase-change layer shall be set to a non-crystal state, then by applying with different writing current pulses, it produces different beating resistances at the contact areas, having different phase changes of the first and the second phase-change layers, therefore, it achieves a multilevel recording operation.
- the two phase-change layers are connected in parallel; and when in a memory reading operation, the two layer's resistances are read in serial.
- the operation of a writing signal for the phase-change memory is shown.
- the phase-change layers are changed to different crystal states by the pulse current provided by the transistor, which will generate four different levels.
- the data is written through state changes in the first phase-change layer 10 and the phase-change layer 20 .
- a first control signal is applied to change both the states of the first phase-change layer 10 and the phase-change layer 20 to a non-crystal state; then the writing signal is applied.
- the operation of a reading signal for the phase-change memory is shown, and the area resistance states of two phase-change layers are taken in serial. That is, the first top electrode 41 is grounded and the pulses current is applied through the second top electrode 42 , by measuring the current passing through the first phase-change layer 10 and the phase-change layer 20 , the crystal states of the first phase-change layer 10 and the phase-change layer 20 will be revealed.
- the detailed comparison is shown in Table 3, according to the TSMC manufacturing standard of 0.18 ⁇ m CMOS.
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Abstract
A manufacture method of a multilevel phase-change memory and operating method thereof are provided. The method includes providing a substrate, forming a bottom electrode on the substrate, forming a first heating layer on top of the bottom electrode, forming a second heating layer on top of the first heating layer, forming a first phase-change layer and a second phase-change layer respectively on the first heating layer and the second heating layer, and forming a first top electrode and a second electrode respectively on the first phase-change layer and the second phase-change layer. Hence, the bottom electrode, the first heating layer and the first phase-change layer constitute an electrical current path, the bottom electrode, the first heating layer, the second heating layer and the second phase-change layer constitute another electrical current path, and the resistances of the two electrical current path are different, thereby increasing the memory density.
Description
- This application is a Divisional of co-pending application Ser. No. 11/104,429 filed or Apr. 13, 2005, and for which priority is claimed under 35 U.S.C. § 120; and this application claims priority benefit of Taiwan Patent Application No. 93134142, filed on Nov. 9, 2004 under 35 U.S.C. § 119; the entire contents of all are hereby incorporated by reference.
- 1. Field of Invention
- The present invention relates to a semi-conductor memory, and more particular, to a multilevel phase-change memory.
- 2. Background of the Invention
- Most electronic equipment uses different types of memories, such as a DRAM, SRAM and Flash memory or the combination of these different types' memories based on the requirements of the application, the operating speed, the memory size and the cost consideration of the equipment. The current new developments in the memory field include FeRAM, MRAM and phase-change memory.
- A Phase-change memory records data by changing the material of the semi-conductor circuit to different phase states due to the resistance changes inside of the circuit. Many materials, such as Ge2Sb2Te5 and others, have the characteristics of changing to different crystallization states with different temperatures and different crystallization states have different resistance. Therefore, a phase-change memory using electrical heating can change materials, such as Ge2Sb2Te5, into different crystallization states, each having different resistance, where each different state can represent a different recording state, i.e., 0 or 1. Moreover, a phase-change memory is non-volatile, it will retain data recorded even if the power is off. Therefore, during a data writing operation in a phase-change memory, the electrical current has to be supplied to the selected memory cells, which will cause phase transition after being heated up by heating electrodes.
- The current phase-change memory technology uses contact to make a phase area method, such as a structure combining phase-change memory and a CMOS transistor disclosed by Samsung Electronics Co., Ltd in IEDM 2003, which connects heating electrodes to the phase-change layer and uses the contact as a phase-change area. Also in IEDM 2003, STMicroelectronics & Ovonyx Inc. recommended another structure using the via as phase-change region, which fills the phase-change layer in the via to obtain a smaller switching current.
- The above-referenced technology using the via to connect a heating electrode to a phase-change region will prevent making a high capacity memory. Therefore, the increase of a phase-change memory density is one key focus in the current memory technology development.
- The present invention provides a multilevel phase-change memory and its associated manufacture method, which will solve several existing problems in the prior art.
- Accordingly, the multilevel phase-change memory of the present invention includes a first phase-change layer, a second phase-change layer, a first heating layer formed on a first surface of the first phase-change layer, a second heating layer formed between the first phase-change layer and the second phase-change layer, a first top electrode formed on a second surface of the first phase-change layer, a second top electrode formed on a second surface of the second phase-change layer, and a bottom electrode formed on a second surface of the first heating layer opposite to the second heating layer.
- The multilevel phase-change memory further includes a substrate with a transistor, and the bottom electrode is formed on the substrate.
- Further, the manufacture method of a multilevel phase-change memory includes providing a substrate with a transistor formed thereon, forming a bottom electrode on the substrate, forming a first heating layer on top of the bottom electrode, forming a second heating layer on top of the first heating layer, forming a phase-change layer on top of the second heating layer, etching the phase-change layer to form a first phase-change layer and a second phase-change layer, and forming a first top electrode and a second electrode on top of the second phase-change layer opposite to the first phase-change layer.
- Furthermore, the present invention provides an operating method of a multilevel phase-change memory including grounding the first top electrode and the second top electrode, and applying a pulse current to the bottom electrode, to make the first phase-change layer and the second phase-change layer change states thereof according to the pulse current. Moreover, the operation method further includes converting the first phase-change layer and the second phase-change layer into a non-crystal state before applying the pulse current.
- Another operating method of a multilevel phase-change memory according to the present invention includes grounding the first top electrode and the second top electrode, and applying a pulse current to one of the first top electrodes and the second top electrodes.
- The present invention utilizes a single transistor to control two different contact regions of phase-change area, which can achieve a higher recording density by realizing multiple recordings in a single memory cell, and increases the density of the memory and reduces the power consumption.
- Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
- The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
-
FIG. 1 is a structure of phase-change memory of the present invention. -
FIGS. 2A-2J illustrate different structures of the phase-change memory of the present invention during the manufacture process. -
FIGS. 3A-3B illustrate other different structures of the phase-change memory of the present invention during the manufacture process. -
FIG. 4 is the writing operation of the phase-change memory of the present invention. -
FIG. 5 is the reading operation of the phase-change memory of the present invention. - The present invention will now be described in detail with reference to the accompanying drawings, wherein the same reference numerals will be used to identify the same or similar elements throughout the several views. It should be noted that the drawings should be viewed in the direction of orientation of the reference numerals.
- With reference to
FIG. 1 , the present invention multilevel phase-change memory comprises a first phase-change layer 10, a second phase-change layer 20, abottom electrode 30, a firsttop electrode 41 and asecond top electrode 42, afirst heating layer 51 and asecond heating layer 52. - As shown in
FIG. 1 , the bottom electrode is formed on asubstrate 100. There is atransistor 70 formed on thesubstrate 100 using a compatible manufacturing process. For example, the transistor can be either a P-type or an N-type MOSFET. If it is a P-type MOSFET, a P-type substrate is formed with the Group III element added in thesubstrate 100 and an N-type region formed with the Group V element is added in the transistor, which is connected to thebottom electrode 30 for signal transmitting. On the other hand, for an N-type MOSFET, an N-type substrate formed with a Group V element is added in thesubstrate 100, while a P-type region (P-well) formed with a Group III element is added in the transistor which is connected to thebottom electrode 30. - Furthermore, on top of the
bottom electrode 30, afirst heating layer 51 is formed, and then asecond heating layer 52 is formed above. In the example shown in theFIG. 1 , the area size of thefirst heating layer 51 is different from the area size of thesecond heating layer 52. However, in the other examples, the area size between thefirst heating layer 51 and thesecond heating layer 52 can be the same. As far as the material used for making the heating layer, it can be poly-Si, SiC, TiW, TiN and/or TiAlN. - The first phase-
change layer 10 contacts thefirst heating layer 51, and the second phase-change layer 20 is formed on the second heating layer. On top of the first phase-change layer 10 is the firsttop electrode 41, and the secondtop electrode 42 is on top of the second phase-change layer 20. In one embodiment, the first phase-change layer 10 and the second phase-change layer can be made in the same step with similar material. In another embodiment, different material can be used in different steps, so each phase-change layers and the selections of different materials can be GeSbTe, AgInSbTe, or GeInSbTe, etc. Thebottom electrode 30, the firsttop electrode 41 and thesecond top electrode 42 can be made from a metal material. In addition, between each layer, there is an insulation layer 60 (such as, SiO2, Si3N4, polymer etc) to separate them. - As the structure shown in the examples, when the memory is chosen by an outside control circuit through the transistor, the first phase-
change layer 10 is heated by thefirst heating layer 51, and the second phase-change layer 20 is heated by thefirst heating layer 51 and thesecond heating layer 52 such, that due to characteristic of the material used in them, the heating will induce phase changes both in the first phase-change layer 10 and the second phase-change layer 20. According to the principle of the present invention, using two phase-change layers and a transistor form a memory cell, each phase-change layer has two states: crystal and non-crystal, and each phase-change layer can change its state by heating, therefore, two phase-change layers can form a multilevel phase-change memory. - Referring to
FIG. 2A-2J , they is a manufacture process for multilevel phase-change memory of the present invention. - First, in a
substrate 100, preferably a silicon substrate, a transistor may be formed if chosen; then aninsulation layer 101 is laid on the top of thesubstrate 100; next, a guiding hole is etched on theinsulation layer 101 and metal is filled into the hole to form thebottom electrode 102 as shown inFIG. 2A . - Then the
first heating layer 103 is formed above thebottom electrode 102, and aninsulation layer 104 is placed on top of theheating layer 103, as shown inFIG. 2B . - Next, a guiding
hole 105 is etched on theinsulation layer 104 which is also aligned with thebottom electrode 102; then thesecond heating layer 106 is formed on top of theinsulation layer 104, as shown inFIGS. 2C and 2D ; through the guiding hole, thefirst heating layer 103 makes contact with thesecond heating layer 106 to be able to heat the phase-change layer in various degrees. - Then, after etching the
second heating layer 106, thefirst heating layer 103 and theinsulation layer 104 are etched into a form shown in 2E and 2F. - Next, a phase-
change layer 107 is formed on top of thesecond heating layer 106 as shown inFIG. 2F and then it is etched into the first phase-change layer 107A and the second phase-change layer 107B; Then, aninsulation layer 108 is formed and two guidingholes FIGS. 2G-2I . - In this embodiment, the first phase-change layer and the second phase-change layer are made from the same material. In other embodiments, they can be made from different material. Finally, the
first electrode 111 andsecond electrode 112 are formed as shown inFIG. 2J . - With reference to
FIGS. 3A and 3B , another example of forming the second heating layer. Thesecond heating layer 113 is formed by depositing and etching into a specified size, as shown inFIGS. 3A and 3B . Then, aninsulation layer 114 is formed after etching above thesecond heating layer 114, as shown inFIG. 2E . - Assuming the phase-change ratios of two different phase-change layers (represented by PC1 and PC2) are PC1= 1/10, PC2=⅕, and assuming the phase-change material is Ge2Sb2Te5, its resistance in the crystal state is 10−2 Ω-cm, and its resistance in the non-crystal state is 100 Ω-cm; the resistances in crystal and non-crystal state of two different regions of phase-change layers during operation are shown in Table 1, where the component sizes are evaluated according to the TSMC manufacturing standard of 0.18 μm CMOS.
-
TABLE 1 Resistances Crystal Non-Crystal PC1 714.3 Ω 7.14 × 105 Ω PC2 148 Ω 2.96 × 105 Ω - Also, assuming the electrode material of the first heating layer is TiN and its resistance is 28.6Ω, and the electrode material of the second heating layer is SiC and its resistance is 2.4×104Ω, then the resistance ratio between two corresponding conductors (two electrical current paths: An electrical current path is from the
bottom electrode 30 via thefirst heating layer 51 and then to the first phase-change layer 10. Another electrical current path is from thebottom electrode 30, via thefirst heating layer 51 and thesecond heating layer 52 and then to the second phase-change layer 20) at non-crystal states are: -
PC1: PC2=(7.14×105+28.6):(2.96×105+2.4×104)=2.23:1 - Based on this resistance ratio, four different operation currents can be obtained; the phase-change relationship between the first phase-change layer and the second phase-change layer is as shown in Table 2:
-
TABLE 2 Operation current and phase-change Current(mA), Current Pulse interval Phase-change layer Density(mA/μm2) States 0.42, 50 nS First PC Layer 30 Crystal Second PC Layer 13.8 No Change 0.7, 30 nS First PC Layer 50 Non-Crystal Second PC Layer 23 No Change 2.0, 50 nS First PC Layer 64 Crystal Second PC Layer 30 Crystal 3.38, 30 nS First PC Layer 108 Non-Crystal Second PC Layer 50 Non-Crystal - Therefore, by applying different current pulse signals, four kinds of recording states can be achieved via the structure of two different phase-change layers.
- According to the principle of the present invention, the first phase-change layer and the second phase-change layer shall be set to a non-crystal state, then by applying with different writing current pulses, it produces different beating resistances at the contact areas, having different phase changes of the first and the second phase-change layers, therefore, it achieves a multilevel recording operation. When in a memory writing operation, the two phase-change layers are connected in parallel; and when in a memory reading operation, the two layer's resistances are read in serial.
- Referring to
FIG. 4 , the operation of a writing signal for the phase-change memory is shown. To write, the phase-change layers are changed to different crystal states by the pulse current provided by the transistor, which will generate four different levels. While writing, by grounding the firsttop electrode 41 and the secondtop electrode 42, and then applying the writing signal through thebottom electrode 30, the data is written through state changes in the first phase-change layer 10 and the phase-change layer 20. In one embodiment, before writing data, a first control signal is applied to change both the states of the first phase-change layer 10 and the phase-change layer 20 to a non-crystal state; then the writing signal is applied. - Referring to
FIG. 5 , the operation of a reading signal for the phase-change memory is shown, and the area resistance states of two phase-change layers are taken in serial. That is, the firsttop electrode 41 is grounded and the pulses current is applied through the secondtop electrode 42, by measuring the current passing through the first phase-change layer 10 and the phase-change layer 20, the crystal states of the first phase-change layer 10 and the phase-change layer 20 will be revealed. - The structure, using one transistor and two phase-change layers of the present invention, takes much less space and power consumption in each cell than the prior art does. The detailed comparison is shown in Table 3, according to the TSMC manufacturing standard of 0.18 μm CMOS.
-
TABLE 3 Previous Technology Present Invention Reset current (mA) 3.38 4.89 Reset current per cell (mA) 3.38 2.45 Reset current ratio 1 0.723 Transistor width and length 14/0.18 20/0.18 ratio Memory cell area (μm2) 0.56 × 0.56 = 0.31 1.18 × 0.56 = 0.66 Memory cell area per cell 0.31 0.33 (μm2) Transistor area (μm2) 3.5 × 2.81 = 9.84 4.0 × 3.36 = 13.44 Transistor area per cell 9.84 6.72 (μm2) Area ratio 1 0.683 - The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Claims (11)
1. A method of manufacturing a multilevel phase-change memory, comprising:
providing a substrate;
forming a bottom electrode on the substrate;
forming a first heating layer on top of the bottom electrode;
forming a second heating layer on top of the first heating layer;
forming a first phase-change layer and a second phase-change layer respectively on the first heating layer and the second heating layer; and
forming a first top electrode and a second electrode respectively on the first phase-change layer and the second phase-change layer.
2. The method of claim 1 , wherein the step of forming the second heating layer comprises:
depositing an insulation layer on top of the first heating layer;
etching a guiding hole on the insulation layer at a position where the bottom electrode is located;
depositing a second heating layer in the guiding hole and on top of the insulation layer; and
etching the second heating layer to remove the second heating layer on the insulation layer.
3. The method of claim 1 , wherein the step of forming the second heating layer comprises:
depositing the second beating layer on the first heating layer corresponding to the bottom electrode;
depositing an insulation layer on top of the first heating layer and the second heating layer; and
etching the insulation layer above the second heating layer.
4. The method of claim 1 , wherein the step of forming the first phase-change layer and the second phase-change layer comprises:
forming a phase-change layer on the second heating layer, and
etching the phase-change layer to form the first phase-change layer and the second phase-change layer.
5. The method of claim 1 , wherein the step of forming the first top electrode and the second top electrode comprises:
depositing an insulation layer on top of the first phase-change layer and the second phase-change layer;
forming guiding holes by etching the insulation layer at positions where the first phase-change layer and the second phase-change layer are located; and
forming the first top electrode and the second top electrode in the guiding holes.
6. The method of claim 1 , wherein the phase-change ratios of the first phase-change layer and the second phase-change layer are different, and the resistance of the first heating layer and the second heating layer are different.
7. The method of claim 6 , wherein the material of the first phase-change layer and the second phase-change layer is Ge2Sb2Te5, the material of the first heating layer is TiN and the material of the second heating layer is SiC.
8. The method of claim 1 , wherein the bottom electrode, the first heating layer and the first phase-change layer constitute an electrical current path, the bottom electrode, the first heating layer, the second heating layer and the second phase-change layer constitute another electrical current path, and the resistances of the two electrical current path are different.
9. A method of operating a multilevel phase-change memory, wherein the phase-change memory comprises a first phase-change layer, a second phase-change layer, a first heating layer formed on a first surface of the first phase-change layer, a second heating layer formed between the first heating layer and the second phase-change layer, a first top electrode formed on a second surface of the first phase-change layer, a second top electrode formed on the second surface of the second phase-change layer opposite to the second heating layer, and a bottom electrode formed on the second surface of the first heating layer opposite of the second heating layer, the method comprising:
grounding the first top electrode and the second top electrode; and
applying a pulse current to the bottom electrode to make the first phase-change layer and the second phase-change layer to change states thereof according to the pulse current.
10. The method of claim 9 , further comprising, before applying the pulse current, converting the first phase-change layer and the second phase-change layer into a non-crystal state.
11. A method of operating a multilevel phase-change memory, wherein the phase-change memory comprises a first phase-change layer, a second phase-change layer, a first heating layer formed on a first surface of the first phase-change layer, a second heating layer formed between the first heating layer and the second phase-change layer, a first top electrode formed on a second surface of the first phase-change layer, a second top electrode formed on the second surface of the second phase-change layer opposite to the second heating layer, and a bottom electrode formed on the second surface of the first heating layer opposite of the second heating layer, the method comprising:
grounding the first top electrode and the second top electrode; and
applying a pulse current to one of the first top electrode and the second top electrode.
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US11/104,429 US7375365B2 (en) | 2004-11-09 | 2005-04-13 | Multilevel phase-change memory, manufacture method and operating method thereof |
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US7375365B2 (en) | 2008-05-20 |
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US20060097239A1 (en) | 2006-05-11 |
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