US20080172529A1 - Novel context instruction cache architecture for a digital signal processor - Google Patents

Novel context instruction cache architecture for a digital signal processor Download PDF

Info

Publication number
US20080172529A1
US20080172529A1 US11/623,760 US62376007A US2008172529A1 US 20080172529 A1 US20080172529 A1 US 20080172529A1 US 62376007 A US62376007 A US 62376007A US 2008172529 A1 US2008172529 A1 US 2008172529A1
Authority
US
United States
Prior art keywords
cache
instruction
instructions
memory
frequently executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/623,760
Inventor
Tushar Prakash Ringe
Abhijit Giri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Priority to US11/623,760 priority Critical patent/US20080172529A1/en
Assigned to ANALOG DEVICES, INC. reassignment ANALOG DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GIRI, ABHIJIT, RINGE, TUSHAR P
Publication of US20080172529A1 publication Critical patent/US20080172529A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3808Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381Loop buffering
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/13Access, addressing or allocation within memory systems or architectures, e.g. to reduce power consumption or heat production or to increase battery life

Abstract

Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, that is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.

Description

    TECHNICAL FIELD OF THE INVENTION
  • The present invention relates to digital signal processors, and more particularly to real-time memory management for digital signal processors.
  • BACKGROUND OF THE INVENTION
  • A digital signal computer or digital signal processor (DSP) is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, fast Fourier transforms, digital filters, image processing and speech recognition. DSP applications are characterized by real-time operation, high interrupt rates, and intensive numeric computations. In addition, DSP applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Thus, designs of DSPs may be quite different from those of general purpose processors.
  • One approach that has been used in the architecture of DSPs is the Harvard architecture, which utilizes separate, independent program and data memories so that two memories may be accessed simultaneously. This permits instructions and data to be accessed in a single clock cycle. Frequently, the program occupies less memory space than data. To achieve full memory utilization, a modified Harvard architecture utilizes the program memory for storing both instructions and data. Typically, the program and data memories are interconnected to the core processor by separate program and data buses.
  • When instructions and data are stored in the program memory, conflicts may arise in the fetching of instructions. Further, in the case of Harvard architecture, the instruction fetch and the data access can take place in the same clock cycle, which can lead to a conflict on the program memory bus. In this scenario, instructions which can generally be fetched in a single clock cycle for a case can stall a cycle due to conflict. This happens when the instructions fetch phase coincides with the memory access phase of a preceding load or store instruction on the program memory bus. Such instructions are cached in conflict cache so that next time when the same instructions are encountered, it can be fetched from the conflict cache to avoid the instruction fetch phase stalls. In addition to the conflict cache, traditional instruction cache is also required for fetching instructions from the external main memory. This results in requiring two different cache architectures.
  • Further, conventional instruction cache architectures exploit the locality of code to maximize cache-hits. Most of the cache architectures suffer from performance degradation due to cache thrashing, i.e., loading the cache with instruction and then removing it while it is still needed before it can be used by the computer system. Cache thrashing is, of course, undesirable, as it reduces the performance gains.
  • Conventional techniques reduce cache thrashing by increasing the cache size, increasing cache-associatively, having a victim cache, and so on. However, these techniques come with overheads like extra hardware, increased cache hit access time, and/or higher software overhead. Another conventional technique identifies frequently executed instructions after code-profiling and locking the cache through software to minimize cache thrashing. However, this technique requires additional overheads in terms of requiring profiling of code by user and extra instructions in the code to lock the cache. Further, this can make the code very cumbersome.
  • SUMMARY OF THE INVENTION
  • According to an aspect of the subject matter, there is provided a method for reducing cache thrashing in a DSP, comprising the steps of dynamically enabling caching of instructions upon encountering current frequently executed instructions in a program, and dynamically disabling the caching of the instructions upon encountering an exit point associated with the frequently executed instructions.
  • According to another aspect of the subject matter, there is provided a method for self configuring a cache memory in a digital signal processor, comprising determining during run-time execution of a program whether a current instruction is coming from an external main memory or internal memory, outputting an execution-space control signal based on the determination that code is executed from internal memory, determining whether a fetch phase of the current instruction coincides with the memory access phase of a preceding load or store instruction on program memory bus, if so, outputting a conflict instruction load enable signal so that the cache memory behaves like a conflict cache and store the current instruction in the cache memory upon receiving the execution-space control signal, and if the code is executed from external memory then enable a traditional instruction load enable signal so that the cache memory behaves likes a traditional cache and then store the current instruction in the cache memory upon receiving the execution-space control signal.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:
  • FIG. 1 is a flowchart illustrating a method for reducing cache thrashing in a DSP according to an embodiment of the present subject matter.
  • FIG. 2 illustrates a block diagram of a DSP cache memory according to an embodiment of the present subject matter, such as those shown in FIG. 1.
  • FIG. 3 is a flowchart illustrating a method for self configuring an instruction cache memory in a DSP according to an embodiment of the present subject matter.
  • FIG. 4 illustrates a block diagram of a DSP cache memory according to an embodiment of the present subject matter, such as FIG. 3.
  • DETAILED DESCRIPTION OF THE INVENTION
  • In the following detailed description of the various embodiments of the invention, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
  • The terms “cache”, “cache memory”, “instruction cache memory”, “conflict cache memory” are used interchangeably throughout the document. Also, the terms “thrashing” and “cache thrashing” are used interchangeably throughout the document. In addition, the terms “code”, “instructions”, and “program” are used interchangeably throughout the document. In addition, the term “current frequently executed instructions” means first encountered one or more frequently executed instructions in the program during run-time.
  • FIG. 1 illustrates an example method 100 for reducing cache thrashing in a digital signal processor (DSP). At step 110, this example method 100 begins by dynamically identifying frequently executed instructions in a program during run-time. Exemplary frequently executed instructions in the program include a hardware loop, a nested hardware loop, a call, a backward jump, and the like. In some embodiments, the frequently executed instructions include instructions having higher probability of reoccurrence during run-time of the program.
  • At step 120, current instructions are cached upon encountering the current frequently executed instructions in the program by dynamically enabling instruction cache memory. Generally, instruction cache memory is useful if same instruction is required again before the instruction is thrashed during run-time of the program. In some embodiments, the instruction cache is enabled only for those instructions which have higher probability of reoccurrence to reduce thrashing.
  • In some embodiments, caching of the instructions is dynamically disabled upon encountering an exit point in the current frequently executed instructions. The exit point refers to an exit found in frequently executed instructions, such as loop termination, call return, and the like. At step 130, an N-bit up-counter is incremented upon caching each instruction in the current frequently executed instructions in the instruction cache memory. In these embodiments, the N-bit up-counter has a number of states that is equal to number of entries available in the instruction cache memory.
  • At step 140, the method 100 determines whether the exit point in the current frequently executed instructions before the N-bit up-counter reaching saturation. Based on the determination at step 140, the method 100 goes to step 150. At step 150, the method 100 determines whether the N-bit up-counter has reached saturation. Based on the determination at step 150, the method 100 goes step 120 if the N-bit up-counter has not reached the saturation and repeats steps 120-150. Based on the determination at step 150 the method 100 goes to step 160 and dynamically disables caching of the current frequently executed instructions if the N-bit up-counter has reached the saturation. In these embodiments, the N-bit up-counter saturation can signify that instruction cache memory is saturated with instructions.
  • Based on the determination at step 140 the method 100 goes to step 160 and dynamically disables caching of the current frequently executed instructions if the exit point in the current frequently executed instructions is before the N-bit up-counter reaches saturation.
  • At step 170, the method 100 determines if there is a next frequently executed instructions. Based on the determination at step 170 the method 100 goes to step 120 and repeats steps 120-170 if there is a next frequently executed instructions in the program. In these embodiments, the instruction cache memory is dynamically re-enabled upon encountering next frequently executed instructions. Based on the determination at step 170 the method 100 goes to step 110 and repeats steps 110-170 if there is no other frequently executed set of instructions in the program.
  • In the case of a hardware loop or other such frequently occurring code including instructions that are greater than the length of the instruction cache memory, thrashing can occur causing a performance loss. As described above the proposed thrashing-aware scheme dynamically disables caching of the current frequently executed instructions once the instruction cache memory reaches saturation. The instruction cache memory is re-enabled when either the loop including the frequently executed instructions is terminated or a nested loop starts executing during run-time. This technique improves performance by reducing thrashing and increasing hit-ratio during run-time of the program. The above-described thrashing-aware technique is generally suitable for small instruction cache memories.
  • For example, in the case of a DSP having a small cache memory of 32 entries, the cache memory is very susceptible to thrashing if every instruction is cached during run-time. In the case of big loops, thrashing can lead to performance loss (i.e., for loop-sizes approximately greater than about 32) or for calls/Cjumps based subroutines which are greater than about 32 instruction. In order to avoid this problem, using a 5-bit up-counter to count 32 ACAM (address content addressable memory) loads in conjunction with instruction-based caching including a decoder logic circuit which decodes the frequently executed instructions, such as loops, calls, nested loops, negative jumps and the like as described above can increase cache hit-ratio. In this scenario, the 5 bit up-counter starts incrementing, upon encountering frequently executed instructions, with every instruction load to the instruction cache memory until the 5-bit up-counter reaches saturation at 32 loads. The instruction cache memory is disabled for that particular loop/call upon reaching saturation of the 5 bit up-counter.
  • The following equation illustrates the benefits of using the above-described technique to reduce thrashing and increase hit-ratio during run-time of a program:
  • Considering a case where an instruction cache memory has “X” entries and a frequently occurring set of instructions or code segment has a length of “Y” that occurs “N” times.
  • For Conventional Cache Architecture:
  • If “Y”<“X”, then the hit-ratio=N−/N
  • If “X”<“Y”<“2X”, then the hit-ratio=(Y−(Y−X)*2)(N−1)/NY
  • If “Y”>“2X”, then the Hit-ratio=0
  • For Thrashing-Aware Cache Architecture:
  • If “Y”<“X”, then the hit-ratio=N−1/N
  • If “Y”>“X”, then the hit-ratio=X(N−1)/NY
  • Now for “X”<Y”<“2X”,
  • The cache-hit advantage factor for thrashing aware cache architecture over the conventional cache architecture

  • =X/(Y−(Y−X)*2)

  • =X/(2X−Y)
  • It can be seen that for “X”<“Y”<“2X”, the cache-hit advantage factor (X)/(2X−Y) can be always greater than 1. This confirms that the hit-ratio for thrashing-aware cache architecture can be always greater than the conventional cache architecture.
  • Similarly, for cases where “Y”>“2X”, conventional cache architecture returns 0 hits, whereas the thrashing aware cache architecture can continue to return “X” hits per iterations.
  • The above example clearly illustrates that the thrashing-aware cache architecture gives a better hit-ratio when compared with the conventional cache architecture when deploying a combination of caching the frequently executed instructions and exiting upon the cache counter saturation, without increasing cache-size or degrading cache-hit access time. In some embodiments, the current frequently executed instructions is held in the instructions cache memory until identifying and enabling caching of a next frequently executed instructions in the program. In these embodiments, caching of instructions is dynamically re-enabled upon encountering next frequently executed instructions.
  • Referring now to FIG. 2, there is illustrated an example block diagram 200 of DSP thrashing-aware cache architecture. As shown in FIG. 2, the block diagram 200 includes an instruction cache memory 210, an external memory 230, and a computational unit 240. Further as shown in FIG. 2, the computational unit 240 includes a decoder logic circuit 250, an N-bit up-counter 260, an enabler/disabler logic circuit 270, and a cache controller 280. Furthermore, the instruction cache memory 210 is shown including SET 0 to SET 15, wherein each SET includes two entries making it a total of 32 entries in the instruction cache memory 210.
  • In operation, the computational unit 240 coupled to the instruction cache memory 210 dynamically enables loading of instructions upon encountering frequently executed instructions. Further, the computational unit 240 dynamically disables loading the instructions upon encountering an exit point associated with the frequently executed instructions in a program.
  • In some embodiments, the N-bit up-counter 260 has a number of states that is equal to a predetermined number of entries in the instruction cache memory 210. In these embodiments, the decoder logic circuit 250 locates the current frequently executed instructions in the program. Also, in these embodiments, the enabler/disabler logic circuit 270 enables storing of the instructions associated with the located frequently executed instructions via the cache controller 280. The N-bit up-counter 260 then increments upon storing each instruction in the instruction cache memory 210. The enabler/disabler logic circuit 270 then disables the storing of the instructions in the instruction cache memory 210 via the cache controller 280 upon the N-bit up-counter 260 reaching a saturation point or upon encountering the exit point in the instructions associated with the frequently executed instructions before reaching the saturation point.
  • In some embodiments, the instruction cache memory 210 has a predetermined number of entries 205. Also, in these embodiments, the N-bit up-counter 260 has a number of states that is equal to the predetermined number of entries in the internal cache memory 210. The N-bit up-counter 260 then increments a counter value for each instruction that is stored in the instruction cache memory 210. The enabler/disabler logic circuit 270 then disables the storing of the instructions in the frequently executed instructions via the cache controller 280 upon the N-bit up-counter 260 reaching a counter value equal to the number of states in the N-bit up-counter 260 or upon encountering the exit point in the instructions before the counter value in the N-bit up-counter 260 becomes equal to the number of states in the N-bit up-counter 260.
  • The operation of the thrashing-aware cache architecture shown in FIG. 2 is described above in more detail with reference to the flowchart 100 shown in FIG. 1.
  • FIG. 3 illustrates an example method 300 for a self-configuring cache in a digital signal processor (DSP). At step 310, this example method 300 begins by dynamically determining whether a current instruction in an executable program is coming from an external memory or an internal memory. Based on the determination at step 310, the method 300 goes to step 320 and outputs an external execution-space control signal if the current instruction is coming from the external memory. At step 340, a traditional instruction load enable signal is outputted so that the cache memory behaves like a traditional cache.
  • Based on the determination at step 310, the method 300 goes to step 330 and outputs an internal execution-space control signal if the current instruction is coming from the internal memory. At step 350, the method determines whether the fetch phase of the current instruction coincides with the memory access of a preceding load or a store instruction. Based on the determination at step 350 the method 300 goes to step 360 if the fetch phase of the current instruction coincides with the memory access of the preceding load of the store instruction and outputs a conflict instruction load enable signal so that the cache memory behaves like a conflict cache. This generally indicates a conflict condition. Based on the determination at step 350 the method 300 goes to step 310 via step 355 to fetch a next current instruction and repeats steps 310-360 if the fetch phase of the current instruction does not coincide with the memory access of the preceding load or the store instruction.
  • Referring now to FIG. 4, there is illustrated an example block diagram 400 of DSP self-configuring cache architecture. As shown in FIG. 4, the block diagram 400 includes a cache memory 410, an internal memory 420, an external memory 430, and a computational unit 440. As shown in FIG. 4, the computational unit 440 further comprises an execution-space decode logic circuit 450 and a cache control logic circuit 460. Further as shown in FIG. 4, the cache control logic circuit 460 includes a conflict instruction cache enabler 470, a traditional instruction cache enabler 480, a MUX 490, and a cache controller 495.
  • In operation, the execution-space decode logic circuit 450 dynamically determines whether a current instruction in an executable program is coming from the external memory 430 or the internal memory 420. The cache control logic circuit 460 then configures the cache memory 410 to behave like a traditional cache or a conflict cache based on an outcome of the determination by the execution-space decode logic circuit 450. The cache control logic circuit 460 then transfers the current instruction to and between the cache memory 410, the internal memory 420 and the external memory 430 based on the configured cache memory.
  • In some embodiments, the execution-space decode logic circuit 450 determines during run-time execution of the executable instructions whether a current instruction in the executable instructions in the executable program is coming from the external memory 430 or the internal memory 420. The execution-space decode logic circuit 450 then outputs an external execution-space control signal if the current instruction is coming from the external memory 430 and outputs an internal execution-space control signal if the current instruction is coming from the internal memory 420.
  • In some embodiments, the conflict instruction cache enabler 470 determines whether the current instruction in the executable program has a memory conflict condition and then outputs a conflict instruction load enable signal upon finding the memory conflict condition. The traditional instruction cache enabler 480 then enables a traditional instruction load enable signal for the current instruction in the executable program upon receiving the current instruction from the external memory 430. The MUX 490 then outputs an instruction load enable signal via the cache controller 495 and configures the cache memory 410 to behave like a traditional cache or a conflict cache based on the instruction load enable signal. The instruction load enable signal then transfers the current instruction to and between the cache memory 410, the internal memory 420, and the external memory 430 based on the configuration of the cache memory 410.
  • In some embodiments, the MUX 490 outputs the instruction load enable signal and enables the cache memory 410 to behave like a conflict cache via the cache controller 495 and transfers the current instruction to and between the internal memory 420, the cache memory 410 and the computational unit 440 upon finding a memory conflict condition and receiving the internal execution-space control signal from the conflict instruction cache enabler 470. In these embodiments, the MUX 490 outputs the instruction load enable signal and enables the cache memory 410 to behave like a traditional cache via the cache controller 495 and transfers the current instruction, coming from the external memory 430, to and between the cache memory 410 and the computation unit 440 upon receiving the current instruction from the external memory 430 and the traditional instruction load enable signal from the traditional instruction cache enabler 480.
  • Although the flowcharts 100 and 300 shown in FIGS. 1 and 3 include steps 110-170 and 310-360 that are arranged serially in the exemplary embodiments, other embodiments of the subject matter may execute two or more steps in parallel, using multiple processors or a single processor organized as two or more virtual machines or sub-processors. Moreover, still other embodiments may implement the steps as two or more specific interconnected hardware modules with related control and data signals communicated between and through the modules, or as portions of an application-specific integrated circuit. Thus, the exemplary process flow diagrams are applicable to software, firmware, and/or hardware implementations.
  • The above thrashing-aware architecture increases the digital signal processor performance by reducing cache thrashing and increasing hit-ratio. Further, the above process lowers power dissipation by reducing loading of unwanted instructions into cache memory. Further, the above thrashing-aware process is suitable for caches of small sizes used in digital signal processors.
  • The above-described self-configuring cache architecture is facilitates in significantly improving the cache functionality by using the same cache hardware as a traditional cache and conflict cache thereby eliminating the need for having two physically different cache in a DSP. The above described context switching self-configuring cache seamlessly switches between conflict cache to traditional cache and vice-versa without any user intervention. The above process uses same cache hardware as conflict cache to avoid resource-conflict during code execution from internal memory and as traditional instruction cache to improve performance during code execution from external memory where there is no resource-conflict.
  • The above techniques can be implemented using an apparatus controlled by a processor where the processor is provided with instructions in the form of a computer program constituting an aspect of the above technique. Such a computer program may be stored in storage medium as computer readable instructions so that the storage medium constitutes a further aspect of the present subject matter.
  • Although the flowchart shown in FIG. 1 depicts a simple case of caching the frequently executed instructions which are not nested to improve hit ratio, one can envision implementing the above-described process for nested loops and other such frequently executed instructions as well.
  • The above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those skilled in the art. The scope of the subject matter should therefore be determined by the appended claims, along with the full scope of equivalents to which such claims are entitled.
  • As shown herein, the present subject matter can be implemented in a number of different embodiments, including various methods, a circuit, an I/O device, a system, and an article comprising a machine-accessible medium having associated instructions.
  • Other embodiments will be readily apparent to those of ordinary skill in the art. The elements, algorithms, and sequence of operations can all be varied to suit particular requirements. The operations described-above with respect to the methods illustrated in FIGS. 1, 2, and 4 can be performed in a different order from those shown and described herein.
  • FIGS. 1-4 are merely representational and are not drawn to scale. Certain proportions thereof may be exaggerated, while others may be minimized. FIGS. 1-4 illustrate various embodiments of the subject matter that can be understood and appropriately carried out by those of ordinary skill in the art.
  • In the foregoing detailed description of the embodiments of the invention, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive invention lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description of the embodiments of the invention, with each claim standing on its own as a separate preferred embodiment.

Claims (21)

1. A method for reducing cache thrashing in a digital signal processor (DSP), comprising:
dynamically enabling caching of instructions upon encountering current frequently executed instructions in a program; and
dynamically disabling the caching of the instructions upon encountering an exit point in the frequently executed instructions.
2. The method of claim 1, further comprising:
dynamically identifying the current frequently executed instructions during run-time of the program.
3. The method of claim 2, further comprising:
holding the current frequently executed instructions in instruction cache memory until identifying and enabling caching of the instructions in next frequently executed instructions.
4. The method of claim 1, wherein the frequently executed instructions comprises instructions selected from the group consisting of a hardware loop, a nested hardware loop, a call, and a backward jump.
5. The method of claim 1, wherein disabling the caching of the instructions upon encountering an exit point associated with the frequently executed instructions comprises:
incrementing an N-bit up-counter upon caching each of the instructions associated with the current frequently executed instructions into the instruction cache memory, wherein the N-bit up-counter has a number of states equal to number of entries available in the instruction cache memory; and
dynamically disabling the caching of the instructions associated with the current frequently executed instructions into the instruction cache memory upon the N-bit up-counter reaching a counter value equal to the number of states in the N-bit up-counter or upon encountering an exit point, associated with the frequently executed instructions, before the counter value becomes equal to the number of states in the N-bit up-counter.
6. The method of claim 1, further comprising:
dynamically re-enabling caching of instructions upon encountering next frequently execute instructions.
7. An article comprising:
a storage medium having instructions, that when executed by a computing platform, result in execution of a method for reducing cache thrashing comprising:
dynamically enabling caching of instructions upon encountering current frequently executed instructions in a program; and
dynamically disabling the caching of the instructions upon encountering an exit point in the frequently executed instructions.
8. The article of claim 7, further comprising:
dynamically identifying the current frequently executed instructions during run-time.
9. The article of claim 8, further comprising:
holding the instructions in instruction cache memory until identifying a next frequently executed instructions and enabling caching of the instructions in the next frequently executed instructions.
10. The article of claim 7, wherein the frequently executed instructions comprises instructions selected from the group consisting of a hardware loop, a nested hardware loop, a call, and a backward jump.
11. The article of claim 7, wherein disabling the caching of the instructions upon encountering an exit point associated with the frequently executed instructions comprises:
incrementing an N-bit up-counter upon caching each of the instructions into the instruction cache memory, wherein the N-bit up-counter has a number of states equal to number of entries available in the instruction cache memory; and
dynamically disabling the caching of the instructions into the instruction cache memory upon the N-bit up-counter reaching a counter value equal to the number of states in the N-bit up-counter or upon encountering an exit point, associated with the frequently executed instructions, before the counter value becomes equal to the number of states in the N-bit up-counter.
12. A digital signal processor, comprising:
an instruction cache memory; and
a computational unit coupled to the instruction cache memory to dynamically enable loading of instructions upon encountering frequently executed instructions in a program and to dynamically disable loading of instructions upon encountering an exit point associated with the frequently executed instructions.
13. The digital signal processor of claim 12, wherein the computational unit comprises:
an N-bit up-counter having a number of states that is equal to a predetermined number of entries in the instruction cache memory;
a decoder logic circuit that locates the current frequently executed instructions in the program;
a cache controller; and
an enabler/disabler logic circuit that enables caching of the instructions associated with the located current frequently executed instructions via the cache controller, wherein the N-bit up-counter increments upon storing each instruction in the instruction cache memory, and wherein the enabler/disabler circuit disables the caching of the instructions in the instruction cache memory via the cache controller upon the N-bit up-counter reaching a saturation point or upon encountering an exit point in the instructions associated with the frequently executed instructions before reaching the saturation point.
14. The digital signal processor of claim 13, wherein the instruction cache memory has a predetermined number of entries, wherein the N-bit up-counter has a number of states that is equal to the predetermined number of entries in the internal cache memory, wherein the N-bit up-counter increments a counter value for each instruction stored in the instruction cache memory, and wherein the enabler/disabler logic circuit disables the storing of the instructions via the cache controller upon the N-bit up-counter reaching a counter value equal to the number of states in the N-bit up-counter or upon encountering an exit point, associated with the frequently executed instructions, before the counter value becomes equal to the number of states in the N-bit up-counter.
15. The digital signal processor of claim 12, wherein the frequently executed instructions comprises instructions selected from the group consisting of a hardware loop, a nested hardware loop, a call, and a backward jump.
16. A self-configuring cache architecture for a digital signal processor, comprising:
cache memory;
an internal memory;
an external memory; and
a computational unit comprising:
an execution-space decode logic circuit that dynamically determines whether a current instruction in an executable program that is coming from an external memory or an internal memory; and
a cache control logic circuit that configures the cache memory to behave like a traditional cache or a conflict cache based on the outcome of the determination, wherein the cache control logic circuit transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory.
17. The self-configuring cache architecture of claim 16, wherein the execution-space decode logic circuit determines, during run-time execution of the executable program, whether a instruction is coming from the external memory or the internal memory and then outputs an external execution-space control signal if the current instruction is coming from the external memory and outputs an internal execution-space control signal if the current instruction is coming from the internal memory.
18. The self-configuring cache architecture of claim 17, wherein the cache control logic circuit comprises:
a cache controller;
a conflict instruction cache enabler that determines whether the current instruction in the executable program has a memory conflict condition and then outputs a conflict instruction load enable signal upon finding the memory conflict condition;
a traditional instruction cache enabler that enables a traditional instruction load enable signal for the current instruction in the executable program upon receiving the current instruction from the external memory; and
a MUX coupled to the execution-space decode logic circuit, the conflict instruction cache enabler and the traditional instruction cache enabler outputs an instruction load enable signal via the cache controller to configure the cache memory to behave like a traditional cache or a conflict cache based on the instruction load enable signal, wherein the instruction load enable signal transfers the current instruction to and between the cache memory, the internal memory, and the external memory based on the configuration of the cache memory.
19. The self-configuring cache architecture of claim 18, wherein the MUX outputs the instruction load enable signal and enables the cache memory to behave like a conflict cache via the cache controller and transfers the current instruction to and between the internal memory, cache memory and the computational unit upon finding the memory conflict condition and receiving the internal execution-space control signal.
20. The self-configuring cache architecture of claim 19, wherein the MUX outputs the instruction load enable signal and enables the cache memory to behave like a traditional cache via the cache controller and transfers the current instruction, coming from the external memory, to and between the cache memory and the computation unit upon receiving the current instruction from the external memory and the traditional instruction load enable signal from the traditional instruction cache enabler.
21. A method for self configuring a cache memory in a digital signal processor, comprising:
determining during run-time execution of a program whether a current instruction is coming from an external memory or an internal memory;
outputting an external execution-space control signal or an internal execution-space control signal based on the determination;
determining whether a fetch phase of the current instruction coincides with the memory access phase of a preceding load or store instruction on program memory bus;
if so, outputting a conflict instruction load enable signal so that the cache memory behaves like a conflict cache and stores the current instruction in the cache memory upon receiving the internal execution-space control signal; and
outputting a traditional instruction load enable signal so that the cache memory behaves like a traditional cache and then stores the current instruction in the cache memory upon receiving the external execution-space control signal.
US11/623,760 2007-01-17 2007-01-17 Novel context instruction cache architecture for a digital signal processor Abandoned US20080172529A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/623,760 US20080172529A1 (en) 2007-01-17 2007-01-17 Novel context instruction cache architecture for a digital signal processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/623,760 US20080172529A1 (en) 2007-01-17 2007-01-17 Novel context instruction cache architecture for a digital signal processor
US12/835,319 US8219754B2 (en) 2007-01-17 2010-07-13 Context instruction cache architecture for a digital signal processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/835,319 Division US8219754B2 (en) 2007-01-17 2010-07-13 Context instruction cache architecture for a digital signal processor

Publications (1)

Publication Number Publication Date
US20080172529A1 true US20080172529A1 (en) 2008-07-17

Family

ID=39618651

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/623,760 Abandoned US20080172529A1 (en) 2007-01-17 2007-01-17 Novel context instruction cache architecture for a digital signal processor
US12/835,319 Active US8219754B2 (en) 2007-01-17 2010-07-13 Context instruction cache architecture for a digital signal processor

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/835,319 Active US8219754B2 (en) 2007-01-17 2010-07-13 Context instruction cache architecture for a digital signal processor

Country Status (1)

Country Link
US (2) US20080172529A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120179954A1 (en) * 2007-03-22 2012-07-12 Research In Motion Limited Device and method for improved lost frame concealment
US8767501B2 (en) 2012-07-17 2014-07-01 International Business Machines Corporation Self-reconfigurable address decoder for associative index extended caches
CN104699624A (en) * 2015-03-26 2015-06-10 中国人民解放军国防科学技术大学 FFT (fast Fourier transform) parallel computing-oriented conflict-free storage access method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8600317B2 (en) * 2012-03-15 2013-12-03 Broadcom Corporation Linearization signal processing with context switching

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272599B1 (en) * 1998-10-30 2001-08-07 Lucent Technologies Inc. Cache structure and method for improving worst case execution time
US20060195573A1 (en) * 2003-02-28 2006-08-31 Bea Systems, Inc. System and method for creating resources in a connection pool
US20060206874A1 (en) * 2000-08-30 2006-09-14 Klein Dean A System and method for determining the cacheability of code at the time of compiling

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710907A (en) * 1995-12-22 1998-01-20 Sun Microsystems, Inc. Hybrid NUMA COMA caching system and methods for selecting between the caching modes
US6173371B1 (en) * 1997-04-14 2001-01-09 International Business Machines Corporation Demand-based issuance of cache operations to a processor bus
US7039756B2 (en) * 2003-04-28 2006-05-02 Lsi Logic Corporation Method for use of ternary CAM to implement software programmable cache policies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272599B1 (en) * 1998-10-30 2001-08-07 Lucent Technologies Inc. Cache structure and method for improving worst case execution time
US20060206874A1 (en) * 2000-08-30 2006-09-14 Klein Dean A System and method for determining the cacheability of code at the time of compiling
US20060195573A1 (en) * 2003-02-28 2006-08-31 Bea Systems, Inc. System and method for creating resources in a connection pool

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120179954A1 (en) * 2007-03-22 2012-07-12 Research In Motion Limited Device and method for improved lost frame concealment
US8848806B2 (en) * 2007-03-22 2014-09-30 Blackberry Limited Device and method for improved lost frame concealment
US9542253B2 (en) 2007-03-22 2017-01-10 Blackberry Limited Device and method for improved lost frame concealment
US8767501B2 (en) 2012-07-17 2014-07-01 International Business Machines Corporation Self-reconfigurable address decoder for associative index extended caches
CN104699624A (en) * 2015-03-26 2015-06-10 中国人民解放军国防科学技术大学 FFT (fast Fourier transform) parallel computing-oriented conflict-free storage access method

Also Published As

Publication number Publication date
US8219754B2 (en) 2012-07-10
US20110010500A1 (en) 2011-01-13

Similar Documents

Publication Publication Date Title
US10133569B2 (en) Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture
JP5889986B2 (en) System and method for selectively committing the results of executed instructions
US9690581B2 (en) Computer processor with deferred operations
US7836289B2 (en) Branch predictor for setting predicate flag to skip predicated branch instruction execution in last iteration of loop processing
US9519484B1 (en) Picoengine instruction that controls an intelligent packet data register file prefetch function
EP0747816B1 (en) Method and system for high performance multithread operation in a data processing system
US20170003965A1 (en) Efficient instruction fusion by fusing instructions that fall within a counter-tracked amount of cycles apart
US7251737B2 (en) Convergence device with dynamic program throttling that replaces noncritical programs with alternate capacity programs based on power indicator
US8713286B2 (en) Register files for a digital signal processor operating in an interleaved multi-threaded environment
US6978350B2 (en) Methods and apparatus for improving throughput of cache-based embedded processors
JP4837305B2 (en) Microprocessor and control method of microprocessor
US8832350B2 (en) Method and apparatus for efficient memory bank utilization in multi-threaded packet processors
KR101183849B1 (en) System and method of executing program threads in a multi-threaded processor
US7062606B2 (en) Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events
KR100274268B1 (en) Method and apparatus for decreasing thread switch latency in a multithread processor
US7590830B2 (en) Method and structure for concurrent branch prediction in a processor
KR100980536B1 (en) Method and apparatus for thread-based memory access in a multithreaded processor
US6636945B2 (en) Hardware prefetch system based on transfer request address of cache miss load requests
JP3358996B2 (en) Parallel Arithmetic Logic Processor with Automatic Viterbi Traceback Bit Storage Function
US20130185792A1 (en) Dynamic execution prevention to inhibit return-oriented programming
KR101081662B1 (en) Method and apparatus for prefetching non-sequential instruction addresses
US6678807B2 (en) System and method for multiple store buffer forwarding in a system with a restrictive memory model
DE69636416T2 (en) Microprocessor designed to recognize a sub-program reception of a dsp routine and to drive a dsp to perform this routine
US6971103B2 (en) Inter-thread communications using shared interrupt register
US6918010B1 (en) Method and system for prefetching data

Legal Events

Date Code Title Description
AS Assignment

Owner name: ANALOG DEVICES, INC., MASSACHUSETTS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RINGE, TUSHAR P;GIRI, ABHIJIT;REEL/FRAME:018762/0929;SIGNING DATES FROM 20070105 TO 20070109

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION