US20080163008A1 - Speculative cache tag evaluation - Google Patents

Speculative cache tag evaluation Download PDF

Info

Publication number
US20080163008A1
US20080163008A1 US11/616,558 US61655806A US2008163008A1 US 20080163008 A1 US20080163008 A1 US 20080163008A1 US 61655806 A US61655806 A US 61655806A US 2008163008 A1 US2008163008 A1 US 2008163008A1
Authority
US
United States
Prior art keywords
cache
tag
data
error
adapted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/616,558
Other versions
US7840874B2 (en
Inventor
Rojit Jacob
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arm Finance Overseas Ltd
Original Assignee
MIPS Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MIPS Technologies Inc filed Critical MIPS Technologies Inc
Priority to US11/616,558 priority Critical patent/US7840874B2/en
Assigned to MIPS TECHNOLOGIES, INC. reassignment MIPS TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JACOB, ROJIT
Assigned to JEFFERIES FINANCE LLC, AS COLLATERAL AGENT reassignment JEFFERIES FINANCE LLC, AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: MIPS TECHNOLOGIES, INC.
Publication of US20080163008A1 publication Critical patent/US20080163008A1/en
Assigned to MIPS TECHNOLOGIES, INC. reassignment MIPS TECHNOLOGIES, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Publication of US7840874B2 publication Critical patent/US7840874B2/en
Application granted granted Critical
Assigned to BRIDGE CROSSING, LLC reassignment BRIDGE CROSSING, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIPS TECHNOLOGIES, INC.
Assigned to ARM FINANCE OVERSEAS LIMITED reassignment ARM FINANCE OVERSEAS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BRIDGE CROSSING, LLC
Application status is Active legal-status Critical
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • G06F12/0895Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories

Abstract

A cache tag comparison unit in a cache controller evaluates tag data and error correction codes to determine if there is a cache hit or miss. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error correction. The error correction code verifies whether this initial comparison is correct and provides a confirmed cache hit or miss signal. The tag data is compared with the request tag to determine a provisional cache hit or miss, and in parallel, the error correction code is evaluated. If the error code evaluation indicates errors in the tag data, a provisional cache hit is converted into a cache miss if errors are responsible for a false match. If the error code evaluation identifies the locations of errors, a provisional cache miss is converted into a cache hit if the errors are responsible for the mismatch.

Description

    BACKGROUND OF THE INVENTION
  • This application relates to the field of microprocessor architectures, and specifically to cache memory control logic. Processors often use one or more cache memories to reduce memory access time and minimize or eliminate periods when the microprocessor is idle and waiting for data. Cache memories typically store a temporary copies of program instructions and data. Cache memory can be integrated within the same integrated circuit die or same integrated circuit package as the processor, or be an external device interfaced with the processor.
  • Cache memories are comprised of many cache memory locations, referred to as cache lines. Each cache line typically includes space for storing cached data or instructions (generally referred to as cache data) and a cache tag that uniquely identifies the cache data stored in the cache line. Typically, the cache tag is comprised of all or a portion of the system memory address associated with the original copy of the cache data. Cache lines can also include other data fields to store cache coherency information, which is used to maintain the integrity of the data stored in system memory and any copies stored in the cache memory.
  • When a processor reads data from memory or writes data to memory, a cache controller identifies one or more cache lines that potentially include a copy of the data. The cache controller compares the tag data of the identified cache lines with all or a portion of the address of the data specified by the processor to determine if one of these identified cache lines actually includes the data specified by the processor. If the cache tag matches the address of the data, a cache hit occurs and the cache controller can retrieve the requested data from the cache memory (if the processor is reading data) or can write the data to cache memory (if the processor is writing data). If the cache tag does not match the address of the data, a cache miss occurs and the processor must read or write the specified data to system memory or a higher level cache memory, if any.
  • Data stored in cache memories can become corrupted. Data corruption can cause erroneous output data and crash programs and microprocessor systems. To mitigate against data corruption, some cache memories include error detection and/or correction codes. Error detection codes can detect the presence of data errors of one and sometimes more bits in the cache line. Typically, any part of the cache line can become corrupted, including the cache data, the cache tag, and/or cache coherency data. Error correction codes can detect and sometimes correct data errors of one or more bits in the cache lines.
  • When a processor reads data and the cache memory includes error detection and/or correction codes, the cache controller retrieves the cache tag, the cache data, and the error detection and/or correction code for a cache line. In prior systems, the cache memory controller evaluates the error detection and/or correction code for the cache line to determine if the cache data and cache tag in the cache line is valid or corrupted. If the cache data and cache tag are valid (or if the error correction code can correct any data errors to make the cache data and cache tag valid), then the cache controller compares the cache tag with all or a portion of the address of the specified data to determine if there is a cache hit or a cache miss.
  • Typically, cache controllers and other part of microprocessors are pipelined to improve performance. Pipelined processors divide data processing into a sequence of pipeline stages connected in series. Each pipeline stage operates independently, allowing different portions of multiple sequential instructions to be processed in parallel, much like an assembly line manufactures multiple items at the same time. Pipelining increases the throughput of data processing operations.
  • Because evaluating error detection and correction codes and comparing cache tags with addresses requires a substantial amount of time to complete, prior cache controllers implement the error detection and correction evaluation and the cache tag comparison in separate pipeline stages. Because of the need for at least two pipeline stages to implement cache hit/miss evaluation with error detection and correction, performance is degraded as compared with cache controllers that do not include error detection and correction.
  • It is therefore desirable for a cache controller to provide improved performance with cache memory having error detection and correction. It is also desirable for the cache controller to use error correction codes to minimize the number of cache misses resulting from cache tag data errors. It is further desirable for the cache controller to require minimal additional resources as compared with cache controllers without error detection and/or correction capabilities. It is also desirable for the cache controller to be adaptable to cache memories with error detection only or with error detection and correction.
  • BRIEF SUMMARY OF THE INVENTION
  • An embodiment of the invention includes a cache tag comparison unit in a cache memory controller adapted to evaluate cache tag data and error correction code to determine if there is a cache hit or cache miss in response to a cache request. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error detection and/or correction to determine if there might be a cache hit or cache miss. After this initial comparison, the error detection and/or correction data is used to verify whether this initial comparison is correct, because there are no detectable bit errors, or incorrect, because there are detectable bit errors. The cache tag comparison unit then provides a confirmed cache hit or cache miss output signal based on the initial comparison and the error detection and/or correction data.
  • In an embodiment, the cache tag comparison unit compares the tag data of a selected cache line with the request tag to determine if there is a provisional cache hit or cache miss. In an embodiment, the cache tag comparison unit evaluates the error correction code and the tag data in parallel with this comparison. If the results of the error correction code evaluation indicate that there are no errors in the tag data, the cache tag comparison unit confirms the provisional cache hit or cache miss. Conversely, if the results of the error correction code evaluation indicate that there are errors in the tag data, a provisional cache hit can be converted into a cache miss if the errors are responsible for a false match between the tag data and the request tag. If the error correction code evaluation can identify the locations of the errors, a provisional cache miss can be converted into a cache hit if the errors are responsible for the mismatch between the tag data and the request data.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be described with reference to the drawings, in which:
  • FIG. 1 illustrates a cache controller according to an embodiment of the invention;
  • FIG. 2 illustrates the portions of a cache line suitable for use with an embodiment of the invention;
  • FIG. 3 illustrates a cache tag comparison pipeline stage logic according to an embodiment of the invention;
  • FIG. 4 illustrates an example microprocessor including an embodiment of the invention; and
  • FIG. 5 illustrates a computer system suitable for use with an embodiment of the invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 illustrates a cache controller 100 according to an embodiment of the invention. Cache controller 100 includes a cache interface 105 adapted to receive requests from one or more processor cores. Requests can be read or write requests for instructions and/or data. Each request includes a memory address or other information identifying the location of the information pertaining to the request, such as the location in system memory or elsewhere in the system (for example if the system includes memory-mapped I/O) from where the instruction and/or data should be retrieved or the location in system memory or a location in system memory or elsewhere in the system where instructions and/or data should be stored.
  • For each request, a cache line selector 110 selects one or more cache lines potentially storing a copy of the instructions or data specified by the request. If the cache line selector 110 initially determines that the cache memory does not store the instructions or data corresponding with the request, such as if the request corresponds to a memory address range that is not cached, then the request is forwarded to the external system interface 115, so that the data can be fetched from memory or another part of the microprocessor system.
  • If the cache line selector 110 selects one or more cache lines for the data request, then cache tag data corresponding with the selected cache lines is retrieved from the cache tag memory 115. An embodiment of the invention includes a cache tag comparator 120 that compares cache tag data with tag data from the request to determine if one of the selected cache lines includes a copy of the requested data, referred to as a cache hit. As described in detail below, the cache tag comparator 120 also evaluates error detection and/or correction codes associated with the cache tag data to ensure that the cache tag is valid and to minimize false cache hits or misses due to corrupt cache tag data.
  • If the cache tag comparator 120 determines that there is a cache hit and the request is a read request, then the requested instructions and/or data is retrieved from the cache data memory 125 and provided to the cache interface 105 for return to the requesting processor core. If the cache tag comparator 120 determines that there is a cache hit and the request is a write request, then the instructions and/or data specified by the request is stored in the appropriate cache line in the cache data memory 125. Additionally, the cache controller 100 will update cache coherency data associated with this cache line to ensure that the instructions and/or data stored in the cache data memory 125 will eventually be written back to the system memory.
  • Conversely, if the cache tag comparator 120 determines that none of the selected cache lines include a copy of the requested instructions and/or data, referred to as a cache miss, then the request is provided to the external system interface 115, so that the data can be fetched from system memory or another part of the system.
  • Cache controller 100 can include numerous other portions omitted for clarity in FIG. 1, such as portions for caching instructions and data retrieved from the system and forwarding this information to one or more processor cores; portions for evicting instructions and data from the cache memory to make room for more important data; portions for arbitrating access to the cache memory between the system and one or more processor cores; portions for updating the system with changes to instructions and/or data in the cache memory; and portions for verifying the integrity of cached instructions and data. The function and implementation of these omitted portions are well understood to those of ordinary skill in the art.
  • An embodiment of the cache controller is divided into a set of pipeline stages, including tag address stage 130, tag data access stage 135, tag comparison stage 140, and one or more cache data access stages 145. Each stage is capable of processing a different request in parallel with the other pipeline stages. Thus, the cache data access stages 145 can retrieve cache data associated with a first request at the same time that the tag comparison stage 140 evaluates the cache tag data associated with a second request, the tag data access stage 135 retrieves cache tag data associated with a third request, and the tag address stage 130 processes a fourth request.
  • FIG. 2 illustrates the portions of a cache line 200 suitable for use with an embodiment of the invention. Cache line 200 includes a cache tag field 205 for storing tag data, a valid bit 210 to indicate whether the data stored by the cache line is valid, a lock bit 215 to indicate whether the data stored by the cache line is locked, and a tag error detection and/or correction code field 220. Cache line 200 also includes a cache data field 225 for storing cache data, cache coherency data field 230 for synchronizing the cache data with system memory, and optional cache data error detection and/or correction code 235.
  • Field 220 is adapted to store an error detection and/or correction code for all or a portion of the data of the cache line 200, such as the entire cache line or portion 240 of the cache line. In an embodiment, field 220 stores an error detection and/or correction code for portion 240 of the cache line 200, which includes fields 205, 210, 215, and 220. In this embodiment, field 220 can detect and/or correct errors in fields 205, 210, 215, and 220. Embodiments of the invention can use any error detection and/or correction scheme known in the art, such as parity schemes, cyclic redundancy checks, hashing functions, Hamming codes, and Reed-Solomon codes. For example, a parity scheme can detect a single bit error in portion 240 of cache line 200. A Hamming code can detect and correct a single bit error or detect a two bit error in portion 240 of cache line 200.
  • Similarly, field 235 stores an error detection and/or correction code for portion 245 of the cache line 200, which includes fields 225, 230, and 235. In an embodiment, the field 235 can also use any type of error detection and/or correction scheme known in the art. The scheme used in field 235 can be the same or different than the scheme used in field 220.
  • In an embodiment, portion 240 of the cache line 200 is located in a cache tag memory, such as cache tag memory 117 discussed above, and portion 245 of the cache line 200 is located in a cache data memory, such as cache data memory 125. In another embodiment, field 235 can be omitted if portions 240 and 245 of cache line 200 are in the same memory or are retrieved at the same time. In this case, field 220 can be used for error detection and/or correction of fields 205, 210, 215, 220, 225, and 230. In still other embodiments, field 235 can be omitted if error detection and/or correction is not required for portion 245 of the cache line 200.
  • FIG. 3 illustrates a cache tag comparison unit 300 according to an embodiment of the invention. In a sense, the cache tag comparison unit 300 speculatively compares the tag data with the request tag without regard to error detection and/or correction to determine if there might be a cache hit or cache miss. After this initial comparison, the error detection and/or correction data is used to verify whether this initial comparison is correct, because there are no detectable bit errors, or incorrect, because there are detectable bit errors. The cache tag comparison unit 300 then provides a confirmed cache hit or cache miss output signal based on the initial comparison and the error detection and/or correction data.
  • An embodiment of the cache tag comparison unit 300 corresponds with cache tag comparison unit 120 implemented in cache tag comparison pipeline stage 140 discussed above. Cache tag comparison unit 300 receives cache tag data 305 from a selected cache line. In an embodiment, cache tag data 305 corresponds with the cache tag stored in field 205 of cache line 200. In an embodiment, the cache tag data 305 is retrieved from cache tag memory 117.
  • Cache tag comparison unit 300 also receives an error detection and/or correction code 310. In an embodiment, the tag error detection and/or correction code 310 is retrieved from field 220 of a cache line 200. Similarly, the cache tag comparison unit 300 receives a valid bit 317. In an embodiment, valid bit 317 is retrieved from field 210 of cache line 200.
  • Additionally, cache tag comparison unit 300 receives a request tag 315. Request tag 315 identifies the instructions and/or data of the request received by the cache memory controller. As discussed above, the request tag 315 can correspond with all or a portion of the memory address specified by the request.
  • A tag data comparator 320 compares the request tag 315 with the tag data 305. Output 322 provides a true value to hit/miss processing logic 335 if the request tag 315 is equal to the tag data 305 and a false value to hit/miss processing logic 335 if the request tag 315 is not equal to the tag data 305. In this embodiment, a true value on output 322 indicates a provisional cache hit and a false value indicates a provision cache miss. These provisional cache hit and miss signals will be validated or invalidated based on the error detection and/or correction code.
  • Error detection and correction logic 325 receives the tag error detection and/or correction code 310, the tag data 305, and the valid bit 317. Error detection and correction logic 325 uses an error detection and/or correction algorithm, such as a Hamming code error correction scheme, to determine if there are one or more errors within the tag error detection and/or correction code 310, the tag data 305, and the valid bit 317. If there are no detectable errors, the error detection and correction logic 325 provides a signal indicating this via output 327 to the hit/miss processing logic 335. Output 327 also provides the valid bit or, if the valid bit includes a correctable error, a corrected valid bit to the hit/miss processing logic 335.
  • In an embodiment using a Hamming code or similar error correction scheme, if there is only a single bit error, the error detection and correction logic 325 output 327 provides the location of the error within this data to the hit/miss processing logic 335. If there is a two bit error, the error detection and correction logic 325 output 327 provides an indicator of an error to the hit/miss processing logic 335. This indicator specifies that there is at least a two bits error somewhere within the tag error detection and/or correction code 310, the tag data 305, and the valid bit 317, but does not specified the locations of these errors.
  • A single bit difference detector 330 receives the tag data 305 and the request tag 315. The single bit different detector 330 determines if the tag data 305 and the request tag 315 differ, if at all, by only a single bit or by more than one bit. If the tag data 305 and the request tag differ by a single bit, then single bit difference detector 330 provides signals via output 332 to the hit/miss processing logic 335 to indicate the location of the non-matching bit. Otherwise, the single bit difference detector 330 provides a signal via output 332 to the hit/miss processing logic to indicate that the tag data 305 and the request tag 315 either differ by more than a single bit or are identical.
  • Based on the signals provided by the tag data comparator 320, the error detection and correction logic 325, and the single bit difference detector 330, the hit/miss processing logic 335 determines whether there has been a cache hit or a cache miss. A cache hit will occur if the tag data 305 matches the request tag 315, after any error correction (if necessary), and if the cache line includes valid data, which is indicated by the valid bit 317. If these conditions are not satisfied, then a cache miss occurs. In an embodiment, the hit/miss processing logic provides either a hit signal via hit signal output 340 or a miss signal via miss signal output 345. The cache memory controller responds to a hit or miss signal as described above.
  • Table 1 enumerates the behavior of an embodiment of the hit/miss processing logic 335.
  • TABLE 1 Hit/Miss Processing Logic Tag Comparison After Error Status Tag Comparison Before Error Correction Error Correction No Error Provisional Hit - Tag Data matches Request Cache Hit Tag. Provisional Miss - Tag Data does not match Cache Miss Request Tag. Single Error Provisional Hit - - Tag Data matches Request Cache Hit - Lock bit does in Lock Bit Tag. not affect tag comparison. Provisional Miss - Tag Data does not match Cache Miss - Lock bit does Request Tag. not affect tag comparison. Single Error Provisional Hit - Tag Data matches Request Cache Miss - Valid bit in Valid Bit Tag and Valid bit is true. should have been false and therefore cached data is not valid. Provisional Miss - Tag Data matches Cache Hit - Valid bit should Request Tag, but Valid bit is false, indicating have been true and therefore that cached data is invalid. cached data is valid. Single Error Provisional Hit - Tag Data matches Request Cache Miss - Single bit error in Tag Data Tag. resulted in a false match between the Tag Data and the Request Tag. Provisional Miss - One bit difference Cache Hit - Single bit error between Tag Data and Request Tag and the resulted in a false mismatch detected error is on the differing bit. between the Tag Data and the Request Tag. Provisional Miss - One bit difference Cache Miss - After between Tag Data and Request Tag and the correcting for the single bit detected error is not on the differing bit. error, the Tag Data and the Request Tag will differ by two bits. Provisional Miss - Tag Data and Request Cache Miss - After Tag differ by multiple bits. correcting for the single bit error, the Tag Data and the Request Tag will still differ by at least one bit. Single Error Provisional Hit - Tag Data matches Request Cache Hit - an error in the in Tag Error Tag. error correction code does Correction not affect the cache tag Code comparison. Provisional Miss - Tag Data does not match Cache Miss - an error in the Request Tag. error correction code does not affect the cache tag comparison. Two Bit Provisional Hit - Tag Data matches Request Cache Miss - Code can detect Error Tag. but cannot locate the two erroneous bits, so to be safe it must be assumed that the errors are in the Tag Data and/or the valid bit. Provisional Miss - Tag Data does not match Cache Miss - Code can detect Request Tag. but cannot locate the two erroneous bits, so to be safe it must be assumed that the Tag Data and Request Tag do not match.
  • In a further embodiment, the cache tag comparison unit 300 can update all or portion of a cache line to correct for a detected error. For example, if the error detection and correction logic 325 detects a single bit error in the tag data 205, the valid bit 210, the lock bit 215, or the tag error detection/correction code 220 of a cache line, the cache tag comparison unit 300 will provide the corrected data to the cache memory to be stored.
  • In another embodiment, the cache tag comparison unit 300 can be simplified to detect, but not correct, errors of one or more bits in the tag data. In this embodiment, the cache tag comparison unit 300 generates a cache miss whenever an error in the tag data or any other part of the cache line is detected.
  • In an embodiment, the tag data comparator 320, the error detection and correction logic 325, and the single bit difference detector 330 are configured to operate in parallel. The outputs of the tag data comparator 320, the error detection and correction logic 325, and the single bit difference detector 330 are then provided roughly simultaneously to the hit/miss processing logic 335. As a result, an embodiment of the cache tag comparison unit 300 can evaluate error detection and correction data and determine if there is a cache hit or miss within a single clock cycle. This allows the cache tag comparison unit 300 to operate within a single pipeline stage.
  • Embodiments of the cache tag comparison unit 300, as well as other portions of the cache controller 100, can be implemented using standard logic gates, registers, and other logic circuits known in the art. Alternate embodiments of the invention can be implemented using programmable device hardware, such as FPGAs, or as part of ASICs architectures.
  • FIG. 4 illustrates an example microprocessor 400 including an embodiment of the invention. Processor 400 includes an L2 cache memory 410 to improve processor performance. In an embodiment, the L2 cache memory 410 includes a cache controller such as cache controller 100 described above. Embodiments of example processor 400 include two or more processor core units 405, such as processor core units 405A, 4055B, and 405C. Additionally, processor core units 405 are connected via at least one data bus 425 with each other and with external interface 430.
  • In an embodiment, L2 cache memory 410 is connected to processor core units 405 via data bus 425. In this embodiment, L2 cache memory 410 is shared with two or more of the processor core units 405. L2 cache memory 410 can store data potentially needed by one or more of the processor core units 405.
  • In an embodiment, the processor core units 405 each include L1 cache memories and associated cache control logic 430, such as L1 cache memories 430A, 430B, and 430C. An embodiment of the L1 cache memories and associated cache control logic 430 includes cache tag comparison units similar to cache tag comparison unit 300 discussed above. In this embodiment, errors in cache tag data or elsewhere in a cache line can be detected and potentially corrected in parallel with the cache tag comparison, allowing the cache tag comparison to be performed in a single pipeline stage. In another embodiment, the L1 cache memories and associated cache control logic 430 include a simplified cache tag comparison unit that can detect, but not correct, errors in cache tag data or elsewhere in a cache line. In this embodiment, the cache tag comparison unit generates a cache miss whenever an error is detected in the cache tag data.
  • FIG. 5 illustrates a computer system 1000 suitable for use with an embodiment of the invention. Computer system 1000 typically includes one or more output devices 1100, including display devices such as a CRT, LCD, OLED, LED, gas plasma, electronic ink, or other types of displays, speakers and other audio output devices; and haptic output devices such as vibrating actuators; computer 1200; a keyboard 1300; input devices 1400; and a network interface 1500. Input devices 1400 can include a computer mouse, a trackball, joystick, track pad, graphics tablet, touch screen, microphone, various sensors, and/or other wired or wireless input devices that allow a user or the environment to interact with computer system 1000. Embodiments of network interface 1500 typically provides wired or wireless communication with an electronic communications network, such as a local area network, a wide area network, for example the Internet, and/or virtual networks, for example a virtual private network (VPN). Network interface 1500 can implement one or more wired or wireless networking technologies, including Ethernet, one or more of the 802.11 standards, Bluetooth, and ultra-wideband networking technologies.
  • Computer 1200 typically includes components such as one or more general purpose processors 1600, and memory storage devices, such as a random access memory (RAM) 1700 and non-volatile memory 1800. Non-volatile memory 1800 can include floppy disks; fixed or removable hard disks; optical storage media such as DVD-ROM, CD-ROM, and bar codes; non-volatile semiconductor memory devices such as flash memories; read-only-memories (ROMS); battery-backed volatile memories; paper or other printing mediums; and networked storage devices. System bus 1900 interconnects the above components. Processors 1600 can include embodiments of the above described processors, such as processors 100 and 400.
  • RAM 1700 and non-volatile memory 1800 are examples of tangible media for storage of data, audio/video files, computer programs, applet interpreters or compilers, virtual machines, and embodiments of the herein described invention. For example, embodiments of the above described processors may be represented as human-readable or computer-usable programs and data files that enable the design, description, modeling, simulation, testing, integration, and/or fabrication of integrated circuits and/or computer systems including embodiments of the invention. Such programs and data files may be used to implement embodiments of the invention as separate integrated circuits or used to integrate embodiments of the invention with other components to form combined integrated circuits, such as microprocessors, microcontrollers, system on a chip (SoC), digital signal processors, embedded processors, or application specific integrated circuits (ASICs).
  • Programs and data files expressing embodiments of the invention can use general-purpose programming or scripting languages, such as C or C++; hardware description languages, such as VHDL or Verilog; and/or standard or proprietary format data files suitable for use with electronic design automation software applications known in the art. Programs and data files can express embodiments of the invention at various levels of abstraction, including as a functional description, as a synthesized netlist of logic gates and other circuit components, and as an integrated circuit layout or set of masks suitable for use with semiconductor fabrication processes.
  • Further embodiments of computer 1200 can include specialized input, output, and communications subsystems for configuring, operating, simulating, testing, and communicating with specialized hardware and software used in the design, testing, and fabrication of integrated circuits.
  • Further embodiments can be envisioned to one of ordinary skill in the art from the specification and figures. In other embodiments, combinations or sub-combinations of the above disclosed invention can be advantageously made. The block diagrams of the architecture and flow charts are grouped for ease of understanding. However it should be understood that combinations of blocks, additions of new blocks, re-arrangement of blocks, and the like are contemplated in alternative embodiments of the present invention.
  • It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g. expressed as a hardware description language description or a synthesized netlist) and transformed to hardware in the production of integrated circuits. Additionally, embodiments of the invention may be implemented using combinations of hardware and software, including micro-code suitable for execution within a processor. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims.

Claims (44)

1. A processor comprising:
a first processor core including logic adapted to retrieve and store instructions and data from a system memory and logic adapted to execute the instructions to process the data;
a first cache memory connected with the first processor core and with the system memory and adapted to store a copy of at least a subset of the instructions and the data, wherein the first cache memory includes a plurality of cache lines, each cache line including at least a tag data field adapted to store tag data, a cache data field adapted to store a portion of the subset of the instructions and data, and a tag error data field adapted to store an error detection and/or correction code for at least a portion of the cache line including the tag data field; and
a cache controller including cache tag comparison logic adapted to determine if at least one selected cache line matches a cache request received from the first processor core, wherein the cache tag comparison logic comprises:
a cache tag comparator unit adapted to compare a first tag data in the tag data field of the selected cache line with a request tag associated with the cache request and to output a provisional cache hit or provisional cache miss signal;
an error code processing logic adapted to evaluate at least the first tag data and a first error detection and/or correction code in the tag error data field of the selected cache line to output an error signal in response to the presence of at least one bit error in at least a portion of the selected cache line including the first tag data; and
tag comparison logic connected with the cache tag comparator unit and the error code processing logic and adapted to output a cache hit signal in response to the provisional cache hit signal and the absence of the error signal and to output the cache miss signal in response to the error signal.
2. The processor of claim 1, further comprising:
a single bit difference detector adapted to determine if the first tag data and the request tag differ by a single bit and to output a bit difference signal indicating the presence of a single bit difference and the location of the single bit difference; and
wherein the error signal further identifies a location of at least one bit error in the portion of the selected cache line; and
wherein the tag comparison logic is adapted to output a cache hit signal in response to the provisional miss signal if the location of the bit error matches the location of the single bit difference provided by the bit difference signal.
3. The processor of claim 2, wherein each cache line further includes a valid field adapted to store validation data that indicates if the cache data field is valid.
4. The processor of claim 3, wherein the error code processing logic is further adapted to evaluate validation data in the valid field of the selected cache line and the first error detection and/or correction code and to output the error signal in response to the presence of at least one bit error in at least the portion of the selected cache line including the first tag data and the validation data; and
wherein the tag comparison logic is adapted to output a cache miss signal in response to the validation data indicating that the cache data field is valid and the error signal indicating that the valid field of the selected cache line includes a bit error.
5. The processor of claim 4, wherein the tag comparison logic is adapted to output a cache miss signal in response to the validation data indicating that the cache data field is valid and the error signal indicating that the valid field of the selected cache line includes a bit error.
6. The processor of claim 2, wherein the tag comparison logic is adapted to further output a corrected first tag data in response to the error signal and wherein the cache controller further includes logic adapted to store the corrected first tag data in the tag data field of the selected cache line.
7. The processor of claim 1, wherein the error detection and/or correction code is a Hamming code.
8. The processor of claim 1, wherein the error detection and/or correction code is adapted to detect a single bit error.
9. The processor of claim 8, wherein the error detection and/or correction code is adapted to correct a single bit error.
10. The processor of claim 1, wherein the error detection and/or correction code is adapted to detect a two bit error.
11. The processor of claim 1, wherein the first cache memory is a first level cache memory.
12. The processor of claim 1, wherein the first cache memory is a second level cache memory.
13. The processor of claim 12, wherein the first cache memory is shared between the first processor core and a second processor core.
14. The processor of claim 1, wherein the cache tag comparator unit and the error code processing logic are adapted to operate in parallel.
15. A cache controller adapted to receive a cache request from at least a first processor core, the cache request comprising:
a first pipeline stage including logic adapted to select at least one cache line of a cache memory based on the request;
a second pipeline stage including logic adapted to access tag data and an error detection and/or correction code from the selected cache line;
a third pipeline stage including first logic adapted to compare the tag data with a request tag associated with the cache request to determine if the tag data provisionally matches the request tag, second logic adapted to evaluate the tag data and the error detection and/or correction code to determine if at least a portion of the selected cache line including the tag data includes at least one error, and third logic adapted to determine if the selected cache line includes cache data specified by the cache request based on the first and second logic, wherein the first and second logic are adapted to operate in parallel; and
a fourth pipeline stage adapted to access cache data in the selected cache line in response to the determination in the third pipeline stage that the selected cache line includes cache data specified by the cache request.
16. The cache controller of claim 15, wherein the third logic is adapted to determine that the selected cache line includes the cache data specified by the cache request in response to the tag data provisionally matching the request tag and the second logic determining that the portion of the selected cache line including the tag data does not include any errors.
17. The cache controller of claim 15, wherein the third logic is adapted to determine that the selected cache line includes the cache data specified by the cache request in response to the tag data not provisionally matching the request tag and the second logic determining that the portion of the selected cache line including the tag data includes at least one error responsible for the tag data not provisionally matching the request tag.
18. The cache controller of claim 17, further comprising fourth logic adapted to determine if the tag data and the request tag differ by a single bit and to determine a first location of the differing bit.
19. The cache controller of claim 18, wherein the third logic is adapted to determine that the selected cache line includes the cache data specified by the cache request in response to the tag data not provisionally matching the request tag, the second logic specifying a second location of an error in the portion of the selected cache line including the tag data, and the second location of the error matching the first location of the differing bit.
20. The cache controller of claim 15, wherein the second pipeline stage further includes logic adapted to access a valid bit indicating whether the cache data of the selected cache line is valid and the second logic is further adapted to evaluate the valid bit and the error detection and/or correction code to determine if a portion of the selected cache line including the valid bit and the tag data includes at least one error.
21. The cache controller of claim 20, wherein the third logic is adapted to determine that the selected cache line includes the cache data specified by the cache request in response to the tag data provisionally matching the request tag, the valid bit specifying that the cache data is valid, and the second logic further determining that the portion of the selected cache line including the valid bit and the tag data does not include any errors.
22. The cache controller of claim 20, wherein the third logic is adapted to determine that the selected cache line includes the cache data specified by the cache request in response to the tag data provisionally matching the request tag, the valid bit specifying that the cache data is invalid, and the second logic further determining that the portion of the selected cache line including the valid bit includes an error.
23. The cache controller of claim 15, wherein the error detection and/or correction code is a Hamming code.
24. The cache controller of claim 15, wherein the error detection and/or correction code is adapted to detect a single bit error.
25. The cache controller of claim 25, wherein the error detection and/or correction code is adapted to correct a single bit error.
26. The cache controller of claim 15, wherein the error detection and/or correction code is adapted to detect a two bit error.
27. The cache controller of claim 15, wherein the cache memory is a first level cache memory.
28. The cache controller of claim 15, wherein the cache memory is a second level cache memory.
29. The cache controller of claim 15, wherein the cache memory is shared between the first processor core and a second processor core.
30. The cache controller of claim 15, wherein the third pipeline stage further includes fourth logic adapted to output corrected tag data in response to the second logic determining that the portion of the selected cache line including the tag data includes at least one error; and wherein the cache controller further includes logic adapted to store the corrected tag data in the selected cache line.
31. A cache tag comparison unit adapted to determine if there is a cache hit or a cache miss in response to a cache request, the cache tag comparison unit comprising:
a first input adapted to receive a request tag identifying instructions and/or data specified by a cache request;
a second input adapted to receive tag data identifying the contents of at least one selected cache line;
a third input adapted to receive a tag error correction code for at least a portion of the selected cache line including at least the tag data;
tag data comparator logic connected with the first and second inputs and adapted to output a first signal indicating that the tag data matches the request tag;
single bit difference detector logic connected with the first and second inputs and adapted to output a second signal indicating if the tag data and the request tag differ by a single differing bit and to indicate a location of the single differing bit within the selected cache line;
error correction logic connected with the second and third inputs and adapted to output a third signal indicating an existence and a location of an error in the portion of the selected cache line including the tag data; and
cache hit and miss processing logic adapted to receive the first, second, and third signals and to output a cache hit signal in response to the first output signal indicating that the tag data does not match the request tag, the second signal indicating that the tag data and the request tag differ by a single differing bit, the third signal indicating the existence and the location of the error in the portion of the selected cache line including the tag data, and the location of the single differing bit being the same as the location of the error in the portion of the selected cache line.
32. A method of determining a cache hit or a cache miss in response to a cache request, the method comprising:
receiving a request tag identifying instructions and/or data specified by a cache request, tag data identifying the contents of at least one selected cache line; and a tag error correction code for at least a portion of the selected cache line including at least the tag data;
comparing the tag data with the request tag to determine if the tag data matches the request tag;
determining if the tag data and the request tag differ by one or more differing bits;
determining a location of at least one differing bit in response to the determination that the tag data and the request tag differ by at least one differing bit;
determining from the error correction code if a portion of the selected cache line including at least the tag data includes one or more bit errors;
determining a location of at least one bit error in the portion of the selected cache line in response to the determination that the selected cache line includes at least one bit error; and
outputting a cache hit signal if the tag data does not match the request tag and the location of the differing bit matches the location of the bit error.
33. The method of claim 32, further comprising:
outputting a cache hit signal if the tag data matches the request tag and if the portion of the selected cache line does not include any errors; and
outputting a cache miss signal if the tag data does not match the request tag and if the portion of the selected cache line does not include any errors.
34. The method of claim 32, further comprising:
outputting a cache miss signal if the tag data does match the request tag and if the portion of the selected cache line includes an error.
35. The method of claim 32, further comprising:
receiving a valid bit specifying if the selected cache line includes valid data, wherein the valid bit is included in the portion of the selected cache line also including the tag data; and
outputting a cache miss signal if the tag data does match the request tag, the valid bit indicates that the selected cache line is valid, and the location of the bit error corresponds with the valid bit.
36. The method of claim 35, further comprising:
outputting a cache hit signal if the tag data does match the request tag, the valid bit indicates that the selected cache line is invalid, and the location of the bit error corresponds with the valid bit.
37. The method of claim 32, further comprising:
outputting a cache miss signal in response to the determination that the portion of the selected cache line including at least the tag data includes one or more bit errors and the location of the bit error is indeterminate.
38. The method of claim 32, wherein the error correction code is a Hamming code.
39. The method of claim 32, wherein the error correction code is adapted to detect and correct a single bit error and to detect a double bit error.
40. The method of claim 32, wherein the steps of determining if the tag data and the request tag differ, determining a location of at least one differing bit, determining from the error correction code, and determining the location of at least one bit error are performed in parallel.
41. A computer readable medium including a hardware description of a processor, the computer readable medium comprising:
a first hardware description of a first input adapted to receive a request tag identifying instructions and/or data specified by a cache request;
a second hardware description of a second input adapted to receive tag data identifying the contents of at least one selected cache line;
a third hardware description of a third input adapted to receive a tag error correction code for at least a portion of the selected cache line including at least the tag data;
a fourth hardware description of a tag data comparator logic connected with the first and second inputs and adapted to output a first signal indicating that the tag data matches the request tag;
a fifth hardware description of single bit difference detector logic connected with the first and second inputs and adapted to output a second signal indicating if the tag data and the request tag differ by a single differing bit and to indicate a location of the single differing bit within the selected cache line;
a sixth hardware description of error correction logic connected with the second and third inputs and adapted to output a third signal indicating an existence and a location of an error in the portion of the selected cache line including the tag data; and
a seventh hardware description of cache hit and miss processing logic adapted to receive the first, second, and third signals and to output a cache hit signal in response to the first output signal indicating that the tag data does not match the request tag, the second signal indicating that the tag data and the request tag differ by a single differing bit, the third signal indicating the existence and the location of the error in the portion of the selected cache line including the tag data, and the location of the single differing bit being the same as the location of the error in the portion of the selected cache line.
42. The computer readable medium of claim 41, wherein the description of the processor is expressed using a general purpose programming language.
43. The computer readable medium of claim 41, wherein the description of the processor is expressed using a hardware description language.
44. The computer readable medium of claim 41, wherein the description of the processor is expressed using a netlist.
US11/616,558 2006-12-27 2006-12-27 Speculative cache tag evaluation Active 2029-08-16 US7840874B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/616,558 US7840874B2 (en) 2006-12-27 2006-12-27 Speculative cache tag evaluation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/616,558 US7840874B2 (en) 2006-12-27 2006-12-27 Speculative cache tag evaluation
PCT/US2007/087632 WO2008082919A1 (en) 2006-12-27 2007-12-14 Speculative cache tag evaluation

Publications (2)

Publication Number Publication Date
US20080163008A1 true US20080163008A1 (en) 2008-07-03
US7840874B2 US7840874B2 (en) 2010-11-23

Family

ID=39585786

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/616,558 Active 2029-08-16 US7840874B2 (en) 2006-12-27 2006-12-27 Speculative cache tag evaluation

Country Status (2)

Country Link
US (1) US7840874B2 (en)
WO (1) WO2008082919A1 (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090019306A1 (en) * 2007-07-11 2009-01-15 Herbert Hum Protecting tag information in a multi-level cache hierarchy
US20100306173A1 (en) * 2009-05-31 2010-12-02 Shahar Frank Handling temporary files of a virtual machine
US20100306770A1 (en) * 2009-05-31 2010-12-02 Shahar Frank Method and apparatus for swapping virtual machine memory
WO2011072500A1 (en) 2009-12-16 2011-06-23 品牌亚太有限公司 Organic acid composition and membrane containing such composition for exfoliating dead skin and horny layers on hands and feet
US20110231710A1 (en) * 2010-03-18 2011-09-22 Dor Laor Mechanism for Saving Crash Dump Files of a Virtual Machine on a Designated Disk
US20120079348A1 (en) * 2010-09-24 2012-03-29 Helia Naeimi Data with appended crc and residue value and encoder/decoder for same
US20120079342A1 (en) * 2010-09-24 2012-03-29 Shih-Lien Lu Error Correcting Code Logic for Processor Caches That Uses a Common Set of Check Bits
US20120110396A1 (en) * 2010-10-27 2012-05-03 Arm Limited Error handling mechanism for a tag memory within coherency control circuitry
US8181035B1 (en) 2011-06-22 2012-05-15 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US8261085B1 (en) * 2011-06-22 2012-09-04 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
WO2012135431A2 (en) * 2011-04-01 2012-10-04 Intel Corporation Mechanisms and techniques for providing cache tags in dynamic random access memory
EP2510624A2 (en) * 2009-12-10 2012-10-17 Intel Corporation Data line storage and transmission utilizing both error correcting code and synchronization information
WO2013095508A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Speculative cache modification
US8595510B2 (en) 2011-06-22 2013-11-26 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US20140062674A1 (en) * 2012-08-30 2014-03-06 Seiko Epson Corporation Media processing device, printing device and control method of a media processing device
WO2015016880A1 (en) * 2013-07-31 2015-02-05 Hewlett-Packard Development Company, L.P. Global error correction
US20150149864A1 (en) * 2013-11-25 2015-05-28 Qualcomm Incorporated Bit recovery system
US20150242274A1 (en) * 2014-02-25 2015-08-27 Imagination Technologies Limited Pipelined ecc-protected memory access
US10261909B2 (en) 2011-12-22 2019-04-16 Intel Corporation Speculative cache modification
US10303904B2 (en) 2012-08-30 2019-05-28 Seiko Epson Corporation Media processing device, printing device, and control method of a media processing device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8806294B2 (en) * 2012-04-20 2014-08-12 Freescale Semiconductor, Inc. Error detection within a memory
KR20170002053A (en) 2015-06-29 2017-01-06 삼성전자주식회사 Error correction circuit, semiconductor memory device and memory system including the same

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6502218B1 (en) * 1999-12-16 2002-12-31 Intel Corporation Deferred correction of a single bit storage error in a cache tag array
US20030129208A1 (en) * 2002-01-07 2003-07-10 Alberts David S. Topical application of alpha-DFMO and anti-inflammatory drug for treatment of actinic keratoses
US20040117558A1 (en) * 2002-12-13 2004-06-17 Krick Robert F System for and method of operating a cache
US6832294B2 (en) * 2002-04-22 2004-12-14 Sun Microsystems, Inc. Interleaved n-way set-associative external cache
US6868484B2 (en) * 2001-05-01 2005-03-15 Broadcom Corporation Replacement data error detector
US6912628B2 (en) * 2002-04-22 2005-06-28 Sun Microsystems Inc. N-way set-associative external cache with standard DDR memory devices
US20060010354A1 (en) * 2004-07-12 2006-01-12 Azevedo Michael J Self-healing cache system
US7120836B1 (en) * 2000-11-07 2006-10-10 Unisys Corporation System and method for increasing cache hit detection performance
US7127643B2 (en) * 2001-11-09 2006-10-24 Sun Microsystems, Inc Method and apparatus for fixing bit errors encountered during cache references without blocking
US7373466B1 (en) * 2004-04-07 2008-05-13 Advanced Micro Devices, Inc. Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
US7376877B2 (en) * 1999-05-27 2008-05-20 Intel Corporation Combined tag and data ECC for enhanced soft error recovery from cache tag errors
US7395489B2 (en) * 2002-06-28 2008-07-01 Fujitsu Limited Control system and memory control method executing a detection of an error in a formation in parallel with reading operation

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6636949B2 (en) 2000-06-10 2003-10-21 Hewlett-Packard Development Company, L.P. System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7376877B2 (en) * 1999-05-27 2008-05-20 Intel Corporation Combined tag and data ECC for enhanced soft error recovery from cache tag errors
US6502218B1 (en) * 1999-12-16 2002-12-31 Intel Corporation Deferred correction of a single bit storage error in a cache tag array
US7120836B1 (en) * 2000-11-07 2006-10-10 Unisys Corporation System and method for increasing cache hit detection performance
US6868484B2 (en) * 2001-05-01 2005-03-15 Broadcom Corporation Replacement data error detector
US7127643B2 (en) * 2001-11-09 2006-10-24 Sun Microsystems, Inc Method and apparatus for fixing bit errors encountered during cache references without blocking
US20030129208A1 (en) * 2002-01-07 2003-07-10 Alberts David S. Topical application of alpha-DFMO and anti-inflammatory drug for treatment of actinic keratoses
US6832294B2 (en) * 2002-04-22 2004-12-14 Sun Microsystems, Inc. Interleaved n-way set-associative external cache
US6912628B2 (en) * 2002-04-22 2005-06-28 Sun Microsystems Inc. N-way set-associative external cache with standard DDR memory devices
US7395489B2 (en) * 2002-06-28 2008-07-01 Fujitsu Limited Control system and memory control method executing a detection of an error in a formation in parallel with reading operation
US20040117558A1 (en) * 2002-12-13 2004-06-17 Krick Robert F System for and method of operating a cache
US7373466B1 (en) * 2004-04-07 2008-05-13 Advanced Micro Devices, Inc. Method and apparatus for filtering memory write snoop activity in a distributed shared memory computer
US20060010354A1 (en) * 2004-07-12 2006-01-12 Azevedo Michael J Self-healing cache system

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090019306A1 (en) * 2007-07-11 2009-01-15 Herbert Hum Protecting tag information in a multi-level cache hierarchy
US20100306173A1 (en) * 2009-05-31 2010-12-02 Shahar Frank Handling temporary files of a virtual machine
US20100306770A1 (en) * 2009-05-31 2010-12-02 Shahar Frank Method and apparatus for swapping virtual machine memory
US8527466B2 (en) 2009-05-31 2013-09-03 Red Hat Israel, Ltd. Handling temporary files of a virtual machine
US8943498B2 (en) * 2009-05-31 2015-01-27 Red Hat Israel, Ltd. Method and apparatus for swapping virtual machine memory
EP2510624A2 (en) * 2009-12-10 2012-10-17 Intel Corporation Data line storage and transmission utilizing both error correcting code and synchronization information
WO2011072500A1 (en) 2009-12-16 2011-06-23 品牌亚太有限公司 Organic acid composition and membrane containing such composition for exfoliating dead skin and horny layers on hands and feet
US8365020B2 (en) 2010-03-18 2013-01-29 Red Hat Israel, Ltd. Mechanism for saving crash dump files of a virtual machine on a designated disk
US8719642B2 (en) 2010-03-18 2014-05-06 Red Hat Israel, Ltd. Saving crash dump files of a virtual machine on a designated disk
US20110231710A1 (en) * 2010-03-18 2011-09-22 Dor Laor Mechanism for Saving Crash Dump Files of a Virtual Machine on a Designated Disk
US20120079342A1 (en) * 2010-09-24 2012-03-29 Shih-Lien Lu Error Correcting Code Logic for Processor Caches That Uses a Common Set of Check Bits
US20120079348A1 (en) * 2010-09-24 2012-03-29 Helia Naeimi Data with appended crc and residue value and encoder/decoder for same
US8533572B2 (en) * 2010-09-24 2013-09-10 Intel Corporation Error correcting code logic for processor caches that uses a common set of check bits
US8458532B2 (en) * 2010-10-27 2013-06-04 Arm Limited Error handling mechanism for a tag memory within coherency control circuitry
US20120110396A1 (en) * 2010-10-27 2012-05-03 Arm Limited Error handling mechanism for a tag memory within coherency control circuitry
CN103562885A (en) * 2011-04-01 2014-02-05 英特尔公司 Mechanisms and techniques for providing cache tags in dynamic random access memory
WO2012135431A2 (en) * 2011-04-01 2012-10-04 Intel Corporation Mechanisms and techniques for providing cache tags in dynamic random access memory
WO2012135431A3 (en) * 2011-04-01 2012-12-27 Intel Corporation Mechanisms and techniques for providing cache tags in dynamic random access memory
US8261085B1 (en) * 2011-06-22 2012-09-04 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US8595510B2 (en) 2011-06-22 2013-11-26 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US8181035B1 (en) 2011-06-22 2012-05-15 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US9092346B2 (en) 2011-12-22 2015-07-28 Intel Corporation Speculative cache modification
WO2013095508A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Speculative cache modification
US10261909B2 (en) 2011-12-22 2019-04-16 Intel Corporation Speculative cache modification
US20140062674A1 (en) * 2012-08-30 2014-03-06 Seiko Epson Corporation Media processing device, printing device and control method of a media processing device
US9984259B2 (en) * 2012-08-30 2018-05-29 Seiko Epson Corporation Media processing device, printing device and control method of a media processing device
US10303904B2 (en) 2012-08-30 2019-05-28 Seiko Epson Corporation Media processing device, printing device, and control method of a media processing device
WO2015016880A1 (en) * 2013-07-31 2015-02-05 Hewlett-Packard Development Company, L.P. Global error correction
US9898365B2 (en) 2013-07-31 2018-02-20 Hewlett Packard Enterprise Development Lp Global error correction
US9262263B2 (en) * 2013-11-25 2016-02-16 Qualcomm Incorporated Bit recovery system
US20150149864A1 (en) * 2013-11-25 2015-05-28 Qualcomm Incorporated Bit recovery system
GB2525715B (en) * 2014-02-25 2017-03-22 Imagination Tech Ltd Pipelined ECC-protected memory access
US9740557B2 (en) * 2014-02-25 2017-08-22 Imagination Technologies Limited Pipelined ECC-protected memory access
US20150242274A1 (en) * 2014-02-25 2015-08-27 Imagination Technologies Limited Pipelined ecc-protected memory access
GB2525715A (en) * 2014-02-25 2015-11-04 Imagination Tech Ltd Pipelined ECC-protected memory access

Also Published As

Publication number Publication date
WO2008082919A1 (en) 2008-07-10
US7840874B2 (en) 2010-11-23

Similar Documents

Publication Publication Date Title
US7917699B2 (en) Apparatus and method for controlling the exclusivity mode of a level-two cache
US5832250A (en) Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits
US6961824B2 (en) Deterministic setting of replacement policy in a cache
US7069494B2 (en) Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
US7873776B2 (en) Multiple-core processor with support for multiple virtual processors
US6594728B1 (en) Cache memory with dual-way arrays and multiplexed parallel output
US7739477B2 (en) Multiple page size address translation incorporating page size prediction
DE60223023T2 (en) Using type bit to track the storage of ecc and vordekodierungsbit in a level 2 cache
JP4567789B2 (en) TLB lock indicator
US7328371B1 (en) Core redundancy in a chip multiprocessor for highly reliable systems
Lucia et al. Atom-aid: Detecting and surviving atomicity violations
US6006311A (en) Dynamic updating of repair mask used for cache defect avoidance
US5509119A (en) Fast comparison method and apparatus for error corrected cache tags
US6539503B1 (en) Method and apparatus for testing error detection
US6725343B2 (en) System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
US20070174750A1 (en) Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability
US7043679B1 (en) Piggybacking of ECC corrections behind loads
DE60222402T2 (en) Method and system for the specular inadmissibility declaration of lines in a cache memory
US6963964B2 (en) Method and apparatus for detecting pipeline address conflict using parallel compares of multiple real addresses
US6732234B1 (en) Direct access mode for a cache
US7272773B2 (en) Cache directory array recovery mechanism to support special ECC stuck bit matrix
US6480975B1 (en) ECC mechanism for set associative cache array
US7219185B2 (en) Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache
US5913043A (en) State machine based bus bridge performance and resource usage monitoring in a bus bridge verification system
JP4920156B2 (en) Store-load transfer predictor with untraining

Legal Events

Date Code Title Description
AS Assignment

Owner name: MIPS TECHNOLOGIES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JACOB, ROJIT;REEL/FRAME:018956/0725

Effective date: 20070129

AS Assignment

Owner name: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT, NEW YO

Free format text: SECURITY AGREEMENT;ASSIGNOR:MIPS TECHNOLOGIES, INC.;REEL/FRAME:019744/0001

Effective date: 20070824

Owner name: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT,NEW YOR

Free format text: SECURITY AGREEMENT;ASSIGNOR:MIPS TECHNOLOGIES, INC.;REEL/FRAME:019744/0001

Effective date: 20070824

AS Assignment

Owner name: MIPS TECHNOLOGIES, INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC, AS COLLATERAL AGENT;REEL/FRAME:021985/0015

Effective date: 20081205

Owner name: MIPS TECHNOLOGIES, INC.,CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JEFFERIES FINANCE LLC, AS COLLATERAL AGENT;REEL/FRAME:021985/0015

Effective date: 20081205

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: BRIDGE CROSSING, LLC, NEW JERSEY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MIPS TECHNOLOGIES, INC.;REEL/FRAME:030202/0440

Effective date: 20130206

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: ARM FINANCE OVERSEAS LIMITED, GREAT BRITAIN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BRIDGE CROSSING, LLC;REEL/FRAME:033074/0058

Effective date: 20140131

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8