US20080158947A1 - System for controlling voltage in non-volatile memory systems - Google Patents
System for controlling voltage in non-volatile memory systems Download PDFInfo
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- US20080158947A1 US20080158947A1 US11/618,544 US61854406A US2008158947A1 US 20080158947 A1 US20080158947 A1 US 20080158947A1 US 61854406 A US61854406 A US 61854406A US 2008158947 A1 US2008158947 A1 US 2008158947A1
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
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- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Definitions
- a system for generating a voltage for a non-volatile memory system includes a voltage generator system including a temperature dependent voltage generator for generating a temperature-dependent component of a voltage, and a temperature independent voltage generator for generating a temperature independent component of the voltage, the voltage generator system configured to operate in one of a plurality of modes to generate a voltage applied to a memory cell; and a time multiplexing system for selecting a first input value and a second input value for one of the plurality of modes of operation of the voltage generator system; the first input value controlling a temperature dependent component of the voltage applied to the memory cell, and the second input value controlling a temperature independent component of the voltage applied to the memory cell.
- Temporal coefficient or “T CO ” is a multiplication factor operating on a temperature dependent variable for controlling a temperature dependent component (value) of a voltage.
- V CGRV is a voltage to read (or read and program verify, used interchangeably herein) a memory cell state, applied to a gate of a non-volatile memory cell in excess of a threshold voltage.
- the adaptive aspects of the present invention are not limited to the structure/system described above with respect to FIGS. 1A and 1B .
- a NAND architecture of memory cell array 101 is described, other architectures, such as NOR, may be used to implement the adaptive aspects of the present invention.
- the present invention may be used for dual state or multi-state memory cells, where a dual state memory cell stores 1 bit of data and a multi-state memory cell stores more than 1 bit of data.
- first module 220 operates on voltage 222 to generate output 224 in response to signal 203 A independent of how second module 230 operates on voltage 232 in response to signal 205 A to generate output 229 .
- voltage and T CO levels are controlled independently.
Abstract
Description
- This patent application is related to U.S. patent application, Ser. No. 11/499,067, Docket No. SDK0814.000US, entitled “METHOD AND SYSTEM FOR INDEPENDENT CONTROL OF VOLTAGE AND ITS TEMPERATURE COEFFICIENT IN NON-VOLATILE MEMORY DEVICES”, filed on Aug. 4, 2006, the disclosure of which is incorporated herein by reference in its entirety.
- 1. Field of the Invention
- The present invention relates generally to non-volatile memory systems and particularly, to controlling voltage in non-volatile memory systems.
- 2. Background of the Invention
- Non-volatile semiconductor memory systems (or devices) have become popular for use in various electronic devices. For example, non-volatile semiconductor memory, such as Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory, is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices and other electronic devices.
- Typically, flash memory systems include an array of memory cells, which are selected by word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. One example of a flash memory system uses a NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates.
- In general, plural voltages are applied to memory cells for different operational modes; such as a read mode or program verify mode (jointly referred to herein as read and program verify mode), a select gate drain mode and others. It is desirable, to independently control a temperature dependent component and a temperature independent component of the applied voltages, using the same voltage generator system configured to operate in plural operational modes. Conventional systems may use plural voltage generator systems to control the temperate dependent and temperature independent components of applied voltages for plural operational modes.
- Therefore, there is a need for a system that can operate in plural operational modes and independently control the temperature dependent component and the temperature independent component of applied voltages.
- The present invention provides a system and associated method for independently controlling the temperature independent and temperature dependent components of voltages applied to a non-volatile memory system operating in plural operational modes.
- In one embodiment, a system for generating a voltage for a non-volatile memory system is provided. The system includes a voltage generator system including a temperature dependent voltage generator for generating a temperature-dependent component of a voltage, and a temperature independent voltage generator for generating a temperature independent component of the voltage, the voltage generator system configured to operate in one of a plurality of modes to generate a voltage applied to a memory cell; and a time multiplexing system for selecting a first input value and a second input value for one of the plurality of modes of operation of the voltage generator system; the first input value controlling a temperature dependent component of the voltage applied to the memory cell, and the second input value controlling a temperature independent component of the voltage applied to the memory cell.
- In another embodiment, a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to a memory cell; and a time multiplexing system for selecting a first input value and a second input value for one of the plurality of modes of operation of the voltage generator system; the first input value controlling a temperature dependent component of the voltage applied to the memory cell, and the second input value controlling a temperature independent component of the voltage applied to the memory cell.
- This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof in connection with the attached drawings.
- The foregoing and other features of several embodiments are now described with reference to the drawings. In the drawings, the same components have the same reference numerals. The illustrated embodiments are intended to illustrate, but not to limit the invention. The drawings include the following Figures:
-
FIG. 1A is block diagram of a flash memory system of an embodiment; -
FIG. 1B shows an embodiment of a NAND string, -
FIG. 1C is an illustration of a conventional architecture for a voltage generator system; -
FIG. 2A is a block diagram of an embodiment of a system for independently controlling temperature dependent and temperature independent voltage components for plural operational modes; -
FIG. 2B is a block diagram of an embodiment of a voltage generator system used in the system ofFIG. 2A ; -
FIG. 3 is a flow diagram of an embodiment for controlling temperature dependent and temperature independent components of VSGD; and -
FIG. 4 is a flow diagram of an embodiment for controlling temperature dependent and temperature independent components of VCGRV. - The following definitions are provided, as they are typically (but not exclusively) used in relation to non-volatile memory systems (for example, flash memory systems or flash memory devices, used hereinafter interchangeably) and referred to herein in descriptions of various embodiments of the present invention:
- “Temperature coefficient” or “TCO” is a multiplication factor operating on a temperature dependent variable for controlling a temperature dependent component (value) of a voltage.
- “VCGRV” is a voltage to read (or read and program verify, used interchangeably herein) a memory cell state, applied to a gate of a non-volatile memory cell in excess of a threshold voltage.
- “VSGD” is a voltage applied to a select gate drain node during a boosting phase of a programming cycle of a memory cell.
- In one aspect of the present invention a system is provided for independently controlling a temperature dependent component (via TCO) and a temperature independent component of an applied voltage, for plural operating modes of a non-volatile memory system. In one embodiment, the system may include a time multiplexing or an equivalent, which may be used to select input values in response to an operating mode of the non-volatile memory system, as described below.
- To facilitate an understanding of the adaptive aspects of the present invention, the general architecture and operation of a non-volatile memory system is described. The specific architecture and operation of the adaptive aspects of the present invention are then described with reference to the general architecture.
- Example of a Non-Volatile Memory System
-
FIGS. 1A and 1B illustrate anon-volatile memory system 100 in which the various aspects of the present invention may be implemented.FIG. 1A represents a block diagram ofnon-volatile memory system 100, including amemory cell array 101. In one embodiment,memory cell array 101 includes a plurality of memory cells M arranged in a matrix, which is controlled by acolumn control circuit 102, arow control circuit 103, a C-source control circuit 104 and a C-p-well control circuit 105. -
Column control circuit 102 is connected to bit lines BLs ofmemory cell array 101 for reading data stored in memory cells M, for determining a state of memory cells M during a program operation, and for controlling potential levels of bit lines BLs to promote the programming or to inhibit the programming of memory cells M. -
Row control circuit 103 is connected to word lines WLs to select one of word lines WLs, to apply read voltages, to apply program voltages combined with the bit line potential levels controlled bycolumn control circuit 102, and to apply an erase voltage coupled with a voltage of a p-type region on which the memory cells M are formed. The C-source control circuit 104 controls a common source line (labeled as “C-source” inFIG. 1B ) connected to the memory cells M. The C-p-well control circuit 105 controls the C-p-well voltage. - Data stored in memory cells M are read out by
column control circuit 102 and are output to external I/O lines via an I/O line and a data input/output circuit (or buffer) 106. The external I/O lines are connected to acontroller 110. - Program data to be stored in memory cells M are input to data input/
output circuit 106 via the external I/O lines and transferred tocolumn control circuit 102. Command data for controllingflash memory system 100 are input to a command interface (or circuit) 107 via external control lines connected withcontroller 110. Command data informsnon-volatile memory system 100 of the operation requested. An input command is transferred to astate machine 108 that controlscolumn control circuit 102,row control circuit 103, c-source control circuit 104, C-p-well control circuit 105 and data input/output circuit 106.State machine 108 can output a status ofnon-volatile memory system 100, such as READY/BUSY or PASS/FAIL signals (or commands). -
Controller 110 is connected or connectable with a host system such as a personal computer, a digital camera, or a personal digital assistant. The host system initiates commands, such as commands to store or read data to or frommemory cell array 101, and to provide or receive such data.Controller 110 converts such commands into command signals that can be interpreted and executed bycommand circuits 107.Controller 110 also typically includes buffer memory (not shown) for user data written to or read frommemory cell array 101. - A typical memory system includes one integrated
circuit chip 111 that includescontroller 110, and one or moreintegrated circuit chips 112 that each includes a memory array and associated control, input/output and state machine circuits. The memory array and controller circuits of a system may be integrated together on one or more integrated circuit chips. - The memory system may be embedded as part of a host system, or may be included in a memory card or other device that is removably insertable into a mating socket of host systems, or otherwise capable of connection with host systems. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
-
FIG. 1B illustrates an exemplary structure ofmemory cell array 101, which is a flash EEPROM of a NAND type device. In this example, memory cells M are partitioned into 1,024 blocks. The data stored in each block are simultaneously erased. The block is thus the minimum unit of a number of cells that are simultaneously erasable. In each block, in this example, there are 8,512 columns that are divided into even columns and odd columns. The bit lines are also divided into even bit lines BLe and odd bit lines BLo. - Four memory cells connected to the word lines WL0 to WL3 at each gate electrode are connected in series to form a NAND cell unit. One terminal of the NAND cell unit is connected to corresponding bit line BL via a first select transistor S whose gate electrode is coupled to a first select
gate line SGD 113. Another terminal of the NAND cell unit is connected to a C-source via a second select transistor S whose gate electrode is coupled to a second selectgate line SGS 114. Voltage VSGD is applied to first selectgate line SGD 113. Although only four floating gate transistors are shown to be included in each cell unit, for simplicity, a higher number of transistors, such as 8, 16 or even 32, are used. - In this example, during a user data read and programming operation, 4,256 memory cells M are simultaneously selected. The memory cells M selected have the same word line WL, for example WL2, and the same kind of bit line BL, for example, the even bit lines BLe0 to BLe4255. Therefore, 532 bytes of data can be read or programmed simultaneously.
- The adaptive aspects of the present invention are not limited to the structure/system described above with respect to
FIGS. 1A and 1B . For example, although, a NAND architecture ofmemory cell array 101 is described, other architectures, such as NOR, may be used to implement the adaptive aspects of the present invention. Further, the present invention may be used for dual state or multi-state memory cells, where a dual statememory cell stores 1 bit of data and a multi-state memory cell stores more than 1 bit of data. - Typical Solution for Controlling VSGD/VCGRV:
-
FIG. 1C shows aconventional system 115 for controlling VSGD/VCGRV, which includes two separatevoltage generator systems V SGD 121 andV CGRV 124, respectively.Voltage generator systems - VSGD voltage generator system 18 receives input 116 (provided by an on-board digital to analog (DAC) converter (not shown)) and generates
V SGD 121.V SGD 121 is transmitted viapass-gate 120 and then amplified bySGD driver 126.Pass-gate 120 is enabled bysignal 119, which is controlled by state machine 108 (FIG. 1A ).Output 128 fromSGD driver 126 is applied to first select gate line SGD 113 (FIG. 1B ). - VCGRV
voltage generator system 122 receives input signal 117 (from an on-board DAC) and generatesV CGRV 124.WL driver 127 amplifiesV CGRV 124 received viapass-gate 125.Signal 123 controlled bystate machine 108 enables VCGRV voltage generator 122 andpass-gate 125.Output 129 fromWL driver 127 is applied to an appropriate word line. - As shown in
FIG. 1C , the conventional solution typically uses two voltage generator systems for controlling temperature dependent and temperature independent components of VSGD and VCGRV. This increases cost and uses extra space on a flash memory device integrated circuit. - Integrated Solution for Controlling Voltage and TCO:
-
FIG. 2A showssystem 200 for independently controlling temperature dependent and temperature independent components of voltage levels applied during plural operating modes, according to one aspect of the present invention. In one embodiment, the operating modes include a read and program-verify cycle when VCGRV is applied (VCGRV mode), a boosting phase of a program cycle when VSGD is applied (VSGD mode), or any other mode.System 200 uses time multiplexing to select input values that are used to independently control the temperature dependent and temperature independent components of the applied voltages. - In one embodiment,
system 200 includes a multiplexer 203 (“MUX 203”) that receives input temperature coefficient values, TCO— VSGD 201 and TCO— VCGRV 202 for the VSGD mode and VCGRV mode, respectively. TCO values 201 and 202 are optimum values that may be stored in memory cells during testing and verification of flash memory system 100 (FIG. 1A ).MUX 203 selects one of the two input values (201 or 202) in response to signal 204 (or “command 204”, used interchangeably throughout this specification).Signal 204 is controlled bystate machine 108 and indicates whether a voltage is needed for the VCGRV or VSGD mode. Accordingly,MUX 203 generates anoutput 203A, the type of which depends on the operating mode indicated bysignal 204.Output 203A becomes an input to voltage generator system 211 (also referred to as “voltage generator 211” or “system 211”).Output 203A, as described below, controls the temperature dependent component of VCGRV or VSGD, depending on the operational mode. - Although
FIG. 2A shows only two input values to MUX 203, the adaptive aspects of the present invention are not limited to two input values. Thus,MUX 203 may receive more than two input values. -
System 200 also includesMUX 205, which receives input signals 206 and 207 from an onboard DAC (not shown).Signal 206 is an input for the VSGD mode and signal 207 is an input for the VCGRV mode.MUX 205 selects either signal 206 or 207 based onsignal 208, which is controlled by state machine 108 (similar to signal 204).Signal 208 indicates whethervoltage generator system 211 is to operate in the VSGD or VCGRV mode.MUX 205 generates anoutput signal 205A that is an input tovoltage generator system 211.Output 205A, as described below, controls the temperature independent component of VCGRV or VSGD, depending on the operational mode. - With respect to
FIG. 2A ,voltage generator system 211 independently controls TCO and voltage levels for both the VCGRV and VSGD mode (i.e. independently controls the temperature independent and temperature dependent components of VCGRV and VSGD).Voltage generator system 211 operates in the VCGRV or VSGD mode in response to signal 210 generated bystate machine 108. -
Voltage generator system 211 generatesoutput 211A for the VSGD or VCGRV mode.Output 211A is either sent to pass_gate 213 and SGD driver 216 (for the VSGD mode) orpass_gate 214 and WL driver 217 (for the VCGRV mode). -
Pass_gate 213 is enabled bysignal 212 for the VSGD mode, whilepass_gate 214 is enabled bysignal 215 for the VCGRV mode. Both signals 212 and 215 are controlled bystate machine 108.Output 218 is sent to first select gate line SGD 113 (FIG. 1B ), whileoutput 219 is applied to the respective word line. - To save overall power,
state machine 108 may turn off pass_gates 213 (in response to signal 212) and 214 (in response to signal 215), and voltage generator system 211 (in response to signal 210), when these components are not being used. -
FIG. 2B shows a block diagram showing components ofvoltage generator system 211 for independently controlling the temperature independent and temperature dependent components (i.e. voltage and TCO) of voltage applied during plural operating modes, according to one aspect of the present invention. In one embodiment,system 211 includes afirst module 220, asecond module 230 and a “difference” amplifier 227 (also referred to as “amplifier 227”). -
First module 220 includes avoltage generator 221 for generating a temperature dependentreference voltage V TD 222. The value ofreference voltage 222 depends on the operational mode of the flash memory system, such as whether the flash memory system is operating in the VCGRV, VSGD or any other mode.Multiplier 223 multipliesreference voltage 222 by a multiplication factor, K1.Signal 203A received fromMUX 203 varies K1 to controloutput 224. Output 224 (the temperature dependent component of the voltage) fromfirst module 220 is input (shown as 225) toamplifier 227. -
Second module 230 includes a band-gap voltage generator 231 that generates a temperature independent, band-gapreference voltage V BGAP 232.Multiplier 233 multiplies band-gap reference voltage 232 by a multiplication factor, K2.Signal 205A received fromMUX 205 varies K2 to controloutput 229. Output 229 (the temperature independent component) is input (shown as 228) toamplifier 227. - As illustrated in
FIG. 2B ,first module 220 operates onvoltage 222 to generateoutput 224 in response to signal 203A independent of howsecond module 230 operates onvoltage 232 in response to signal 205A to generateoutput 229. Specifically by varying K1 in response to signal 203A and K2 in response to signal 205A, voltage and TCO levels are controlled independently. -
Amplifier 227 combinesoutput 224, the temperature dependent component of the applied voltage andoutput 229, the temperature independent component of the applied voltage to generateoutput 226.Output 226 may be VCGRV, VSGD or any other voltage type, depending on the operational mode of the system. - The following provides an example for independently controlling VCGRV and TCO (i.e. independently controlling the temperature independent and temperature dependent components) using
system 211. VCGRV may be expressed by Equation (1) below: -
V CGRV =K 2 *V BGAP −K 1 *V CGRVTD Equation 1 - In
Equation 1 K1 is the voltage multiplier for the temperature dependent component, K2 is a multiplier for the temperature independent component,V BGAP 232 is temperature independent band-gap reference voltage, and VCGRVTD or (VTD) 222 is the temperature dependent voltage. - TCO of VCGRV may be determined by Equation (2):
-
- T is the absolute temperature
- Equation (1) and Equation (2) show that one embodiment of the present invention provides independent control of voltage level and TCO for
V CGRV 226. During flash memory device testing, optimum values for multipliers, K1 and K2 for plural operational modes may be stored in read only memory (not shown) or memory cells. - Process Flow:
-
FIG. 3 shows a top-level process flow diagram for independently controlling the temperature independent and temperature dependent components of VSGD, according to one aspect of the present invention. The process starts in step S300, when the VSGD mode is enabled. In one aspect, signals 204, 210 and 212 enable the VSGD mode. - In step S301, TCO
— VSGD 201 andDC_V SGD 206 are input tovoltage generator system 211 that independently controls voltage and TCO, as discussed above with respect toFIGS. 2A and 2B . In step S302,V SGD 226 is generated. -
FIG. 4 shows a top-level process flow diagram for independently controlling the temperature independent and temperature dependent components of VCGRV, according to one aspect of the present invention. The process starts in step S400, when the VCGRV mode is enabled. In one aspect, signals 208, 210 and 215 enable the VCGRV mode. - In step S401, TCO
— VCGRV 202 andDC_V CGRV 207 are input tovoltage generator system 211 that independently controls voltage and TCO, as discussed above with respect toFIGS. 2A and 2B . In step S402, VCGRV is generated. - While embodiments of the present invention are described above with respect to what is currently considered its preferred embodiments, it is to be understood that the invention is not limited to that described above. To the contrary, the invention is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100095847A1 (en) * | 2008-10-16 | 2010-04-22 | William Steven Lopes | System for conditioning fluids utilizing a magnetic fluid processor |
US7889575B2 (en) | 2008-09-22 | 2011-02-15 | Sandisk Corporation | On-chip bias voltage temperature coefficient self-calibration mechanism |
US8004917B2 (en) | 2008-09-22 | 2011-08-23 | Sandisk Technologies Inc. | Bandgap voltage and temperature coefficient trimming algorithm |
US8542000B1 (en) | 2012-03-19 | 2013-09-24 | Sandisk Technologies Inc. | Curvature compensated band-gap design |
US8941369B2 (en) | 2012-03-19 | 2015-01-27 | Sandisk Technologies Inc. | Curvature compensated band-gap design trimmable at a single temperature |
US9541456B2 (en) | 2014-02-07 | 2017-01-10 | Sandisk Technologies Llc | Reference voltage generator for temperature sensor with trimming capability at two temperatures |
US9715913B1 (en) | 2015-07-30 | 2017-07-25 | Sandisk Technologies Llc | Temperature code circuit with single ramp for calibration and determination |
Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864504A (en) * | 1995-11-17 | 1999-01-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory with temperature compensation for read/verify referencing scheme |
US6026023A (en) * | 1997-11-20 | 2000-02-15 | Nec Corporation | Non-volatile semiconductor memory |
US6205074B1 (en) * | 2000-02-29 | 2001-03-20 | Advanced Micro Devices, Inc. | Temperature-compensated bias generator |
US6314026B1 (en) * | 1999-02-08 | 2001-11-06 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor device using local self boost technique |
US6452437B1 (en) * | 1999-07-22 | 2002-09-17 | Kabushiki Kaisha Toshiba | Voltage generator for compensating for temperature dependency of memory cell current |
US6560152B1 (en) * | 2001-11-02 | 2003-05-06 | Sandisk Corporation | Non-volatile memory with temperature-compensated data read |
US6801454B2 (en) * | 2002-10-01 | 2004-10-05 | Sandisk Corporation | Voltage generation circuitry having temperature compensation |
US6807111B2 (en) * | 2000-12-28 | 2004-10-19 | Micron Technology, Inc. | Voltage and temperature compensated pulse generator |
US6859395B2 (en) * | 2002-11-29 | 2005-02-22 | Kabushiki Kaisha Toshiba | NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages |
US6870766B2 (en) * | 2002-04-04 | 2005-03-22 | Samsung Electronics Co., Ltd. | Multi-level flash memory with temperature compensation |
US7054195B2 (en) * | 2003-07-15 | 2006-05-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory |
US7057958B2 (en) * | 2003-09-30 | 2006-06-06 | Sandisk Corporation | Method and system for temperature compensation for memory cells with temperature-dependent behavior |
US20060133143A1 (en) * | 2004-12-08 | 2006-06-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and a method of word lines thereof |
US7180211B2 (en) * | 2003-09-22 | 2007-02-20 | Micro Technology, Inc. | Temperature sensor |
US7184313B2 (en) * | 2005-06-17 | 2007-02-27 | Saifun Semiconductors Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US7266031B2 (en) * | 2003-11-19 | 2007-09-04 | Infineon Technologies Ag | Internal voltage generator with temperature control |
US20070291566A1 (en) * | 2006-06-16 | 2007-12-20 | Nima Mokhlesi | Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
US20070291567A1 (en) * | 2006-06-16 | 2007-12-20 | Nima Mokhlesi | System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
US7313034B2 (en) * | 2004-09-01 | 2007-12-25 | Micron Technology, Inc. | Low supply voltage temperature compensated reference voltage generator and method |
US7313044B2 (en) * | 2004-02-05 | 2007-12-25 | Infineon Technologies, Ag | Integrated semiconductor memory with temperature-dependent voltage generation |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1253597B1 (en) | 2001-04-27 | 2008-11-05 | STMicroelectronics S.r.l. | Method and circuit for generating reference voltages for reading a multilevel memory cell |
-
2006
- 2006-12-29 US US11/618,544 patent/US7403434B1/en active Active
Patent Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864504A (en) * | 1995-11-17 | 1999-01-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory with temperature compensation for read/verify referencing scheme |
US6026023A (en) * | 1997-11-20 | 2000-02-15 | Nec Corporation | Non-volatile semiconductor memory |
US6314026B1 (en) * | 1999-02-08 | 2001-11-06 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor device using local self boost technique |
US6452437B1 (en) * | 1999-07-22 | 2002-09-17 | Kabushiki Kaisha Toshiba | Voltage generator for compensating for temperature dependency of memory cell current |
US6667904B2 (en) * | 1999-07-22 | 2003-12-23 | Kabushiki Kaisha Toshiba | Multi-level non-volatile semiconductor memory device with verify voltages having a smart temperature coefficient |
US6205074B1 (en) * | 2000-02-29 | 2001-03-20 | Advanced Micro Devices, Inc. | Temperature-compensated bias generator |
US6807111B2 (en) * | 2000-12-28 | 2004-10-19 | Micron Technology, Inc. | Voltage and temperature compensated pulse generator |
US6560152B1 (en) * | 2001-11-02 | 2003-05-06 | Sandisk Corporation | Non-volatile memory with temperature-compensated data read |
US6870766B2 (en) * | 2002-04-04 | 2005-03-22 | Samsung Electronics Co., Ltd. | Multi-level flash memory with temperature compensation |
US6801454B2 (en) * | 2002-10-01 | 2004-10-05 | Sandisk Corporation | Voltage generation circuitry having temperature compensation |
US6859395B2 (en) * | 2002-11-29 | 2005-02-22 | Kabushiki Kaisha Toshiba | NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages |
US7054195B2 (en) * | 2003-07-15 | 2006-05-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory |
US7180211B2 (en) * | 2003-09-22 | 2007-02-20 | Micro Technology, Inc. | Temperature sensor |
US7057958B2 (en) * | 2003-09-30 | 2006-06-06 | Sandisk Corporation | Method and system for temperature compensation for memory cells with temperature-dependent behavior |
US7266031B2 (en) * | 2003-11-19 | 2007-09-04 | Infineon Technologies Ag | Internal voltage generator with temperature control |
US7313044B2 (en) * | 2004-02-05 | 2007-12-25 | Infineon Technologies, Ag | Integrated semiconductor memory with temperature-dependent voltage generation |
US7313034B2 (en) * | 2004-09-01 | 2007-12-25 | Micron Technology, Inc. | Low supply voltage temperature compensated reference voltage generator and method |
US20060133143A1 (en) * | 2004-12-08 | 2006-06-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and a method of word lines thereof |
US7184313B2 (en) * | 2005-06-17 | 2007-02-27 | Saifun Semiconductors Ltd. | Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells |
US20070291566A1 (en) * | 2006-06-16 | 2007-12-20 | Nima Mokhlesi | Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
US20070291567A1 (en) * | 2006-06-16 | 2007-12-20 | Nima Mokhlesi | System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7889575B2 (en) | 2008-09-22 | 2011-02-15 | Sandisk Corporation | On-chip bias voltage temperature coefficient self-calibration mechanism |
US8004917B2 (en) | 2008-09-22 | 2011-08-23 | Sandisk Technologies Inc. | Bandgap voltage and temperature coefficient trimming algorithm |
US8228739B2 (en) | 2008-09-22 | 2012-07-24 | Sandisk Technologies Inc. | Bandgap voltage and temperature coefficient trimming algorithm |
US20100095847A1 (en) * | 2008-10-16 | 2010-04-22 | William Steven Lopes | System for conditioning fluids utilizing a magnetic fluid processor |
US8542000B1 (en) | 2012-03-19 | 2013-09-24 | Sandisk Technologies Inc. | Curvature compensated band-gap design |
US8941369B2 (en) | 2012-03-19 | 2015-01-27 | Sandisk Technologies Inc. | Curvature compensated band-gap design trimmable at a single temperature |
US9541456B2 (en) | 2014-02-07 | 2017-01-10 | Sandisk Technologies Llc | Reference voltage generator for temperature sensor with trimming capability at two temperatures |
US9683904B2 (en) | 2014-02-07 | 2017-06-20 | Sandisk Technologies Llc | Reference voltage generator for temperature sensor with trimming capability at two temperatures |
US9715913B1 (en) | 2015-07-30 | 2017-07-25 | Sandisk Technologies Llc | Temperature code circuit with single ramp for calibration and determination |
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