US20080135981A1 - Substrate Laser Marking - Google Patents
Substrate Laser Marking Download PDFInfo
- Publication number
- US20080135981A1 US20080135981A1 US12/034,750 US3475008A US2008135981A1 US 20080135981 A1 US20080135981 A1 US 20080135981A1 US 3475008 A US3475008 A US 3475008A US 2008135981 A1 US2008135981 A1 US 2008135981A1
- Authority
- US
- United States
- Prior art keywords
- feature
- canceled
- substrate
- sidewall portion
- upper sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/361—Removing material for deburring or mechanical trimming
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41C—PROCESSES FOR THE MANUFACTURE OR REPRODUCTION OF PRINTING SURFACES
- B41C1/00—Forme preparation
- B41C1/02—Engraving; Heads therefor
- B41C1/04—Engraving; Heads therefor using heads controlled by an electric information signal
- B41C1/05—Heat-generating engraving heads, e.g. laser beam, electron beam
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41M—PRINTING, DUPLICATING, MARKING, OR COPYING PROCESSES; COLOUR PRINTING
- B41M5/00—Duplicating or marking methods; Sheet materials for use therein
- B41M5/24—Ablative recording, e.g. by burning marks; Spark recording
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This invention relates to the fabrication of integrated circuits. More particularly, this invention relates to improving the yield of integrated circuits formed on substrates that are marked, such as with laser markings.
- the substrate such as a semiconductor wafer substrate
- identification purposes For example, in laser marking, laser radiation is used to partially melt and ablate a portion of the surface of the substrate to form a visible feature. These visible features, or indicia elements, are created in patterns to form identifying indicia.
- the features generally have the structure of a blind bore or hole as shown in FIG. 1 . Because of the shape of the feature, residue such as photoresist can remain in the feature, and the shape of the feature makes it difficult to completely remove the residue. The residue may, under subsequent processing conditions, eject from the feature and redeposit on nearby integrated circuits. Thus, the presence of the residue can adversely affect subsequent manufacturing steps and decrease the yield of integrated circuits on the substrate. As the geometries of integrated circuits continue to shrink, the detrimental effect of residue from laser marking tends to have an increasing impact on the yield.
- a method for forming a feature in a substrate where residue within the feature can be easily removed.
- An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate.
- the upper sidewall portion has an upper sidewall angle.
- a lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate.
- the lower sidewall portion has a lower sidewall angle.
- the upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion.
- any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.
- both the upper and the lower sidewalls are formed by laser ablation of the substrate.
- the upper sidewall angle of the upper sidewall is preferably between about thirty degrees and about sixty degrees, and the upper sidewall preferably has a depth of between about four microns and about eight microns.
- the lower sidewall angle of the lower sidewall is preferably between about sixty degrees and about ninety degrees, and the lower sidewall preferably has a depth of between about four microns and about eight microns. Most preferably the feature has a depth that is no more than about twelve microns.
- the invention provides identifying indicia on a substrate, where the identifying indicia are formed with a pattern of indicia elements.
- the indicia elements have a shape that aids in removal of foreign material from the indicia elements on the substrate.
- Each indicia element forms a blind bore in the substrate, and has a sidewall with a sidewall angle of between about thirty degrees and about sixty degrees.
- Each indicia element has a depth of no more than about twelve microns.
- FIG. 1 is a cross sectional view of a prior art feature where the geometry of the feature makes it difficult to remove residue from the feature
- FIG. 2 is a cross sectional view of a feature formed according to a first embodiment of the invention.
- FIG. 3 is a cross sectional view of a feature formed according to a second embodiment of the invention.
- the invention enables the formation of identifying indicia having improved geometry as compared to conventional marking features.
- a substrate 10 such as a silicon wafer, having a feature 12 formed as by laser radiation on the surface 14 of the substrate 10 .
- additional layers such as electrically conductive and electrically nonconductive layers typical to integrated circuit fabrication are applied over the substrate 10 , and have features formed therein.
- substrate refers not only to the base substrate 10 , such as the silicon wafer, but to the entirety of any succeeding layers deposited thereon.
- residue 16 easily collects in, and is difficult to remove from feature 12 due to the depth and relatively high aspect ratio of the feature 12 .
- the depth and shape of the feature 12 make it difficult to remove the residue 16 from the feature 12 .
- Conventional features 12 are typically formed in a single laser radiation step, and have wall angles ⁇ of at least about sixty degrees and a depth D of at least about twelve microns. With such a geometry, the residue 16 that remains in the bottom of the feature 12 becomes a potential source of contamination for the integrated circuits that are fabricated in close proximity to the feature 12 . For example, during subsequent baking processes, the photoresist debris 16 may explode from the bottom of the feature 12 and redeposit on nearby integrated circuits, thus damaging the integrated circuits and lowering the yield of integrated circuits on the substrate.
- Such features 12 are typically used to form identifying indicia on the surface of the substrate, and as such are formed on the substrate at or near the very beginning of substrate processing. Thus, there is ample opportunity for debris to collect within the feature 12 , and redeposit at later times on the nearby integrated circuits.
- the invention avoids undesirable marking geometries such as depicted in FIG. 1 , and provides feature shapes that aid in the removal of the residue that may deposit in the bottom of the features. Accordingly, and with reference to FIG. 2 , there is depicted a feature 12 formed in a substrate 10 in accordance with a first embodiment of the invention.
- the feature 12 having an upper sidewall portion 24 adjacent a lower sidewall portion 26 , is formed such as by laser radiation to provide a blind bore in the substrate 10 .
- the upper sidewall portion 24 has an upper sidewall angle that is more shallow than that of the lower sidewall portion 26 .
- the lower sidewall angle of the lower sidewall portion 26 is steeper than the upper sidewall angle of the upper sidewall portion 24 .
- the portion 24 preferably has an upper sidewall angle ⁇ of from about thirty degrees to about sixty degrees
- the portion 26 preferably has a lower sidewall angle ⁇ of from about sixty degrees to about ninety degrees.
- the depth d 1 of the upper sidewall portion 24 is preferably from about four microns to about eight microns, and the depth d 2 of the lower sidewall portion 26 is preferably from about four microns to about eight microns, with the combined depth of d 1 and d 2 preferably being less than about twelve microns.
- the feature 12 has sidewalls 30 with an angle ⁇ of from about thirty degrees to about sixty degrees.
- the depth d of the feature 12 is preferably no greater than about twelve microns.
- the feature 12 according to the present invention is preferably substantially circular in cross section so that the sidewalls are of substantially uniform slope.
- Indicia elements 12 having the structure and made in accordance with the method described herein are less susceptible to retaining residue. As described previously, the presence of residue in the features 12 can adversely affect the fabrication process and significantly reduce yields. In addition, it is desired to provide features having substantially circular cross sections to enhance the visibility of the marks. It has been observed that forming the holes in accordance with the invention facilitates the forming of holes of substantially circular cross section as compared to prior art methods.
- integrated circuits such as semiconductor devices
- processed in accordance with the methods as described above tend to have identifying indicia that are easier to remove residue from and which have superior visibility in the finished device. This results in improved integrated circuit quality and yield.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Plasma & Fusion (AREA)
- Mechanical Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Laser Beam Processing (AREA)
Abstract
Description
- This invention relates to the fabrication of integrated circuits. More particularly, this invention relates to improving the yield of integrated circuits formed on substrates that are marked, such as with laser markings.
- In the manufacture of integrated circuits, such as semiconductor devices, it is often desirable to form one or more features on the substrate, such as a semiconductor wafer substrate, for identification purposes. For example, in laser marking, laser radiation is used to partially melt and ablate a portion of the surface of the substrate to form a visible feature. These visible features, or indicia elements, are created in patterns to form identifying indicia.
- The features generally have the structure of a blind bore or hole as shown in
FIG. 1 . Because of the shape of the feature, residue such as photoresist can remain in the feature, and the shape of the feature makes it difficult to completely remove the residue. The residue may, under subsequent processing conditions, eject from the feature and redeposit on nearby integrated circuits. Thus, the presence of the residue can adversely affect subsequent manufacturing steps and decrease the yield of integrated circuits on the substrate. As the geometries of integrated circuits continue to shrink, the detrimental effect of residue from laser marking tends to have an increasing impact on the yield. - Another shortcoming of conventional processes is their ability to render features of desirable configuration. For example, to enhance the visibility of the features, it is desirable that the cross sections of the features be substantially circular. Conventional methods may not yield features having such characteristics.
- What is needed, therefore, is a method for forming features that have a shape that aids removal of residue from the features and which also renders features of more desirable configuration.
- The above and other needs are provided by a method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion.
- By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.
- In preferred embodiments of the invention, both the upper and the lower sidewalls are formed by laser ablation of the substrate. The upper sidewall angle of the upper sidewall is preferably between about thirty degrees and about sixty degrees, and the upper sidewall preferably has a depth of between about four microns and about eight microns. The lower sidewall angle of the lower sidewall is preferably between about sixty degrees and about ninety degrees, and the lower sidewall preferably has a depth of between about four microns and about eight microns. Most preferably the feature has a depth that is no more than about twelve microns.
- In an alternate embodiment the invention provides identifying indicia on a substrate, where the identifying indicia are formed with a pattern of indicia elements. The indicia elements have a shape that aids in removal of foreign material from the indicia elements on the substrate. Each indicia element forms a blind bore in the substrate, and has a sidewall with a sidewall angle of between about thirty degrees and about sixty degrees. Each indicia element has a depth of no more than about twelve microns.
- Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:
-
FIG. 1 is a cross sectional view of a prior art feature where the geometry of the feature makes it difficult to remove residue from the feature, -
FIG. 2 is a cross sectional view of a feature formed according to a first embodiment of the invention, and -
FIG. 3 is a cross sectional view of a feature formed according to a second embodiment of the invention. - The invention enables the formation of identifying indicia having improved geometry as compared to conventional marking features. With reference to
FIG. 1 , there is represented asubstrate 10, such as a silicon wafer, having afeature 12 formed as by laser radiation on thesurface 14 of thesubstrate 10. Various additional layers, such as electrically conductive and electrically nonconductive layers typical to integrated circuit fabrication are applied over thesubstrate 10, and have features formed therein. Accordingly, as used herein, the term “substrate” refers not only to thebase substrate 10, such as the silicon wafer, but to the entirety of any succeeding layers deposited thereon. - In the conventional structure depicted in
FIG. 1 ,residue 16 easily collects in, and is difficult to remove fromfeature 12 due to the depth and relatively high aspect ratio of thefeature 12. The depth and shape of thefeature 12 make it difficult to remove theresidue 16 from thefeature 12.Conventional features 12 are typically formed in a single laser radiation step, and have wall angles α of at least about sixty degrees and a depth D of at least about twelve microns. With such a geometry, theresidue 16 that remains in the bottom of thefeature 12 becomes a potential source of contamination for the integrated circuits that are fabricated in close proximity to thefeature 12. For example, during subsequent baking processes, thephotoresist debris 16 may explode from the bottom of thefeature 12 and redeposit on nearby integrated circuits, thus damaging the integrated circuits and lowering the yield of integrated circuits on the substrate. -
Such features 12 are typically used to form identifying indicia on the surface of the substrate, and as such are formed on the substrate at or near the very beginning of substrate processing. Thus, there is ample opportunity for debris to collect within thefeature 12, and redeposit at later times on the nearby integrated circuits. - The invention avoids undesirable marking geometries such as depicted in
FIG. 1 , and provides feature shapes that aid in the removal of the residue that may deposit in the bottom of the features. Accordingly, and with reference toFIG. 2 , there is depicted afeature 12 formed in asubstrate 10 in accordance with a first embodiment of the invention. - The
feature 12, having anupper sidewall portion 24 adjacent alower sidewall portion 26, is formed such as by laser radiation to provide a blind bore in thesubstrate 10. Theupper sidewall portion 24 has an upper sidewall angle that is more shallow than that of thelower sidewall portion 26. In other words, the lower sidewall angle of thelower sidewall portion 26 is steeper than the upper sidewall angle of theupper sidewall portion 24. For example, theportion 24 preferably has an upper sidewall angle β of from about thirty degrees to about sixty degrees, and theportion 26 preferably has a lower sidewall angle δ of from about sixty degrees to about ninety degrees. - The depth d1 of the
upper sidewall portion 24 is preferably from about four microns to about eight microns, and the depth d2 of thelower sidewall portion 26 is preferably from about four microns to about eight microns, with the combined depth of d1 and d2 preferably being less than about twelve microns. - In a second embodiment of the invention, the
feature 12 hassidewalls 30 with an angle θ of from about thirty degrees to about sixty degrees. The depth d of thefeature 12 is preferably no greater than about twelve microns. Thefeature 12 according to the present invention is preferably substantially circular in cross section so that the sidewalls are of substantially uniform slope. -
Indicia elements 12 having the structure and made in accordance with the method described herein are less susceptible to retaining residue. As described previously, the presence of residue in thefeatures 12 can adversely affect the fabrication process and significantly reduce yields. In addition, it is desired to provide features having substantially circular cross sections to enhance the visibility of the marks. It has been observed that forming the holes in accordance with the invention facilitates the forming of holes of substantially circular cross section as compared to prior art methods. - Thus, integrated circuits, such as semiconductor devices, processed in accordance with the methods as described above tend to have identifying indicia that are easier to remove residue from and which have superior visibility in the finished device. This results in improved integrated circuit quality and yield.
- It is appreciated that the materials as described above, while providing an especially preferred application of the invention, are by way of example only, and that other materials that are compatible with the materials, structures, and processes of integrated circuit processing are also generally applicable to the invention as disclosed herein.
- The foregoing embodiments of this invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as is suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/034,750 US20080135981A1 (en) | 2001-12-12 | 2008-02-21 | Substrate Laser Marking |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/020,764 US7371659B1 (en) | 2001-12-12 | 2001-12-12 | Substrate laser marking |
US12/034,750 US20080135981A1 (en) | 2001-12-12 | 2008-02-21 | Substrate Laser Marking |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/020,764 Division US7371659B1 (en) | 2001-12-12 | 2001-12-12 | Substrate laser marking |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080135981A1 true US20080135981A1 (en) | 2008-06-12 |
Family
ID=39361588
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/020,764 Active 2025-04-03 US7371659B1 (en) | 2001-12-12 | 2001-12-12 | Substrate laser marking |
US12/034,750 Abandoned US20080135981A1 (en) | 2001-12-12 | 2008-02-21 | Substrate Laser Marking |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/020,764 Active 2025-04-03 US7371659B1 (en) | 2001-12-12 | 2001-12-12 | Substrate laser marking |
Country Status (1)
Country | Link |
---|---|
US (2) | US7371659B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020084931A1 (en) * | 2018-10-22 | 2020-04-30 | 株式会社Sumco | Method for manufacturing silicon wafer with laser mark, and silicon wafer with laser mark |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102185659B1 (en) | 2014-02-11 | 2020-12-03 | 삼성전자주식회사 | Method of fabricating a wafer and the wafer |
US20220193828A1 (en) * | 2020-12-23 | 2022-06-23 | Amulaire Thermal Technology, Inc. | Lift-off structure for sprayed thin layer on substrate surface and method for the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020064947A1 (en) * | 2000-10-03 | 2002-05-30 | Takeyuki Itabashi | Wiring substrate and manufacturing method of the same along with electroless copper plating solution used therefor |
US6458710B1 (en) * | 2001-03-24 | 2002-10-01 | Esm Limited | Process for forming uniform multiple contact holes |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4237601A (en) * | 1978-10-13 | 1980-12-09 | Exxon Research & Engineering Co. | Method of cleaving semiconductor diode laser wafers |
JPH06196813A (en) * | 1992-10-14 | 1994-07-15 | Sony Corp | Semiconductor laser and manufacture thereof |
US6642477B1 (en) * | 2001-10-23 | 2003-11-04 | Imra America, Inc. | Method for laser drilling a counter-tapered through-hole in a material |
US6747216B2 (en) * | 2002-02-04 | 2004-06-08 | Intel Corporation | Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery |
-
2001
- 2001-12-12 US US10/020,764 patent/US7371659B1/en active Active
-
2008
- 2008-02-21 US US12/034,750 patent/US20080135981A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020064947A1 (en) * | 2000-10-03 | 2002-05-30 | Takeyuki Itabashi | Wiring substrate and manufacturing method of the same along with electroless copper plating solution used therefor |
US6458710B1 (en) * | 2001-03-24 | 2002-10-01 | Esm Limited | Process for forming uniform multiple contact holes |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020084931A1 (en) * | 2018-10-22 | 2020-04-30 | 株式会社Sumco | Method for manufacturing silicon wafer with laser mark, and silicon wafer with laser mark |
JP2020068231A (en) * | 2018-10-22 | 2020-04-30 | 株式会社Sumco | Manufacturing method for silicone wafer with laser mark |
TWI723532B (en) * | 2018-10-22 | 2021-04-01 | 日商Sumco股份有限公司 | Laser marking wafer manufacturing method and laser marking wafer |
KR20210055770A (en) * | 2018-10-22 | 2021-05-17 | 가부시키가이샤 사무코 | Method for manufacturing silicon wafer with laser mark and silicon wafer with laser mark |
CN113169034A (en) * | 2018-10-22 | 2021-07-23 | 胜高股份有限公司 | Method for manufacturing silicon wafer with laser mark and silicon wafer with laser mark |
US11515263B2 (en) | 2018-10-22 | 2022-11-29 | Sumco Corporation | Method of producing laser-marked silicon wafer and laser-marked silicon wafer |
KR102565926B1 (en) * | 2018-10-22 | 2023-08-09 | 가부시키가이샤 사무코 | Manufacturing method of silicon wafer with laser mark |
Also Published As
Publication number | Publication date |
---|---|
US7371659B1 (en) | 2008-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1293616C (en) | Integrated circuit inductor structure and non-destructive etch depth measurement | |
US4902377A (en) | Sloped contact etch process | |
US6548408B1 (en) | Method of minimizing repetitive chemical-mechanical polishing scratch marks, method of processing a semiconductor wafer outer surface, method of minimizing undesired node-to-node shorts of a length less than or equal to 0.3 micron, and semiconductor processing method | |
US4561932A (en) | Method of producing integrated silicon structures on isolated islets of the substrate | |
US20080135981A1 (en) | Substrate Laser Marking | |
US6054384A (en) | Use of hard masks during etching of openings in integrated circuits for high etch selectivity | |
US20060177630A1 (en) | Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method | |
TWI469205B (en) | Integrated circuit wafer and dicing method thereof | |
JP2001118870A (en) | Wafer integrated rigid support ring | |
JP4627448B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
US4654119A (en) | Method for making submicron mask openings using sidewall and lift-off techniques | |
US6291359B1 (en) | Methods of forming openings and methods of controlling the degree of taper of openings | |
US20090079095A1 (en) | Semiconductor wafer, semiconductor chip cut from the semiconductor wafer, and method of manufacturing semiconductor wafer | |
US20060134880A1 (en) | Methods of manufacturing a metal-insulator-metal capacitor | |
CN112885772B (en) | Method for manufacturing semiconductor structure | |
KR20060041497A (en) | Dry etching apparatus | |
US6348396B1 (en) | Semiconductor device and production thereof | |
US7411268B2 (en) | Fabricating deeper and shallower trenches in semiconductor structures | |
KR100771378B1 (en) | Semiconductor device and method for fabricating the same | |
US6486049B2 (en) | Method of fabricating semiconductor devices with contact studs formed without major polishing defects | |
US6383936B1 (en) | Method for removing black silicon in semiconductor fabrication | |
KR102297835B1 (en) | Method for manufacturing tapered sidewall via hole | |
KR100965216B1 (en) | laser marking method in wafer | |
KR100579852B1 (en) | Method for fabricating metal pattern to prevent form alignment mark shift phenomenon | |
US6174596B1 (en) | Process for fabricating dual damascene structure by applying an etch-differentiating technique on a light sensitive organic oxide layer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- AFTER EXAMINER'S ANSWER OR BOARD OF APPEALS DECISION |
|
AS | Assignment |
Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;BROADCOM CORPORATION;REEL/FRAME:044886/0608 Effective date: 20171208 |
|
AS | Assignment |
Owner name: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERA Free format text: SECURITY INTEREST;ASSIGNORS:HILCO PATENT ACQUISITION 56, LLC;BELL SEMICONDUCTOR, LLC;BELL NORTHERN RESEARCH, LLC;REEL/FRAME:045216/0020 Effective date: 20180124 |
|
AS | Assignment |
Owner name: BELL NORTHERN RESEARCH, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 Owner name: BELL SEMICONDUCTOR, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 Owner name: HILCO PATENT ACQUISITION 56, LLC, ILLINOIS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CORTLAND CAPITAL MARKET SERVICES LLC;REEL/FRAME:059720/0719 Effective date: 20220401 |