US20070287271A1 - Deposition of nano-crystal silicon using a single wafer chamber - Google Patents
Deposition of nano-crystal silicon using a single wafer chamber Download PDFInfo
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- US20070287271A1 US20070287271A1 US11/893,301 US89330107A US2007287271A1 US 20070287271 A1 US20070287271 A1 US 20070287271A1 US 89330107 A US89330107 A US 89330107A US 2007287271 A1 US2007287271 A1 US 2007287271A1
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 78
- 239000010703 silicon Substances 0.000 title claims abstract description 78
- 239000002159 nanocrystal Substances 0.000 title claims abstract description 53
- 230000008021 deposition Effects 0.000 title claims description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000007789 gas Substances 0.000 claims description 60
- 230000008569 process Effects 0.000 claims description 27
- 238000010438 heat treatment Methods 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000012159 carrier gas Substances 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 7
- 229910000077 silane Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 54
- 235000012431 wafers Nutrition 0.000 description 77
- 238000006243 chemical reaction Methods 0.000 description 40
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 17
- 239000010410 layer Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 11
- 239000002243 precursor Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000000203 mixture Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 7
- 239000000376 reactant Substances 0.000 description 7
- 238000012546 transfer Methods 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000012686 silicon precursor Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000004590 computer program Methods 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005086 pumping Methods 0.000 description 3
- 238000010926 purge Methods 0.000 description 3
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 239000005543 nano-size silicon particle Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- GVGCUCJTUSOZKP-UHFFFAOYSA-N nitrogen trifluoride Chemical compound FN(F)F GVGCUCJTUSOZKP-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/813—Of specified inorganic semiconductor composition, e.g. periodic table group IV-VI compositions
- Y10S977/814—Group IV based elements and compounds, e.g. CxSiyGez, porous silicon
Definitions
- Embodiments of the present invention relate to the field of semiconductor processing and more specifically, to a method and apparatus for controlling the crystal structure of a silicon film.
- Polysilicon films formed by Chemical Vapor Deposition (CVD) have wide use in the fabrication of integrated circuits such as microprocessors and memory devices.
- Polysilicon film deposition processes require adequate physical, chemical, and production-worthy properties.
- production-worthy properties include uniform thickness and composition for the polysilicon film (e.g., within wafer and wafer-to-wafer), low particulate and chemical contamination, and high throughput for manufacturing. When these properties are met, high electrical performance, reliable, and high yield device wafers can be manufactured at low cost.
- a given composition and flow rate of reactant gases and diluent inert gases are introduced into a reaction chamber containing multiple substrates (e.g., batch furnace).
- the gas species move to the substrate and the reactants are absorbed on the substrate.
- the atoms undergo migration and chemically react resulting in a film (e.g., polysilicon) being deposited on the substrate.
- the un-reacted gases and gaseous by-products of the reaction are desorbed and removed from the reaction chamber.
- Energy to drive the reactions can be supplied by several methods, (e.g. thermal, photons, catalysis, or plasma).
- a conventional CVD system typically includes gas sources, gas feed lines, mass-flow controllers, a reaction chamber, a method for heating substrates onto which the film is to be deposited, and temperature sensors.
- a conventional thermal CVD system utilizes temperature as the primary driver for the reaction of source gases.
- a batch of silicon wafers are vertically positioned in a wafer boat for deposition and inserted into a tube-shaped furnace.
- the wafers are radiantly heated (above 600° C.) by resistive heating coils in the tube.
- Reactant gases are metered into one end of the tube (e.g., gas inlet) using a mass flow controller.
- Reaction by-products are pumped out the other end of the tube (e.g., via an exhaust pump).
- nano-crystal silicon structures within a film depends on the controlling the size and density of the nano-crystal silicon.
- One problem with batch furnace systems is that they cannot accommodate nano-crystal film deposition at low temperatures (e.g., below 500° C.).
- Another problem with batch furnace systems is that they exhibit a disadvantage known as “depletion effects.” Depletion effects reduce gas phase concentrations as reactants are consumed by reactions on wafer surfaces. As such, wafers near the inlet are exposed to higher concentrations of reactant gases. Deposition rates are thus greater for wafers placed near the inlet and uniform thickness is difficult to obtain.
- Embodiments of a method for depositing a layer of nano-crystal silicon on a substrate are described.
- a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C.
- a silicon source is also fed into the single wafer chamber.
- a pressure between about 10 Torr to about 350 Torr is generated in the single wafer chamber.
- FIG. 1 illustrates a cross-sectional side view of one embodiment of a processing chamber having a resistive heater in a “wafer-process” position through a first cross-section and a second cross-section, each through one-half of the chamber.
- FIG. 2 illustrates of a similar cross-sectional side view as in FIG. 1 in a “wafer separate” position.
- FIG. 3 illustrates an illustration of a similar cross-sectional side view as in FIG. 1 in a “wafer load” position.
- FIG. 4 illustrates a block diagram of one embodiment of a method for depositing a discontinuous layer of nano-crystal silicon film on a substrate.
- FIG. 5 a illustrates one embodiment of a substrate having a dielectric formed on a silicon wafer.
- FIG. 5 b illustrates one embodiment of nano-crystal silicon formed on the substrate of FIG. 5 a.
- first element disposed on, above or below another element may be directly in contact with the first element or may have one or more intervening elements.
- one element disposed next to or adjacent another element may be directly in contact with the first element or may have one or more intervening elements.
- any reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the claimed subject matter.
- the appearances of the phrase, “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
- the process environment for forming the nano-crystal silicon film may be a single wafer deposition chamber, in which a CVD deposition method such as low pressure chemical vapor deposition (LPCVD) is used to form a nano-crystal silicon film on a substrate.
- LPCVD low pressure chemical vapor deposition
- the growth rate of the nano-crystal silicon film may be controlled to a desired level to form the silicon film with a particular density and dimension, wafer-to-wafer repeatability, and low thermal budget.
- the single wafer deposition chamber provides the advantage of precisely maintaining a desired deposition temperature as well as pressure control during nano-crystal silicon deposition.
- the nano-crystal silicon film may be discontinuous, and both doped and undoped nano-crystal silicon formation may be achieved with the single wafer chamber.
- the relative low deposition temperature results in an amorphous nano-crystal silicon layer.
- nano-crystal silicon formation may be achieved in a single step as carried out in a deposition chamber.
- the deposition of nano-crystal silicon on a substrate may be achieved by the reaction of vapor-phase chemicals (i.e., reactants) that contain the required constituents (e.g., silicon precursors).
- reactants vapor-phase chemicals
- the reactant gases are introduced into a reaction chamber and are decomposed and/or reacted at a heated surface of a substrate to form the nano-crystal silicon film.
- the reaction chamber may be one that accommodates only one substrate or wafer at a time.
- FIGS. 1-3 illustrate one embodiment of an apparatus that may be used to practice embodiments of the present invention.
- the apparatus may be a LPCVD chamber 100 .
- FIGS. 1-3 each show cross-sectional views through two different cross-sections, each cross-section representing a view through approximately one-half of LPCVD chamber 100 , of one type of reactor such as a resistive reactor.
- the LPCVD chamber 100 illustrated in FIGS. 1-3 is constructed of materials to maintain, in one embodiment, to provide a deposition chamber pressure between about 10 Torr to about 350 Torr.
- LPCVD chamber 100 may have a chamber volume of about 5-6 liters.
- FIG. 1 illustrates the inside of process chamber body 45 in a “wafer-process” position
- FIG. 2 illustrates the same view of the chamber in a “wafer-separate” position
- FIG. 3 illustrates the same cross-sectional side view of chamber body 45 in a “wafer-load” position.
- a wafer 500 is indicated in dashed lines to indicate its location in LPCVD chamber 100 .
- LPCVD chamber 100 is adapted to hold one wafer only (i.e., a single wafer chamber).
- Chamber body 45 may also be sized to accommodate a wafer having a diameter between about 200 mm to about 300 mm.
- FIGS. 1-3 illustrate chamber body 45 that defines reaction chamber 90 in which the thermal decomposition of a process gas or gases takes place to form a nano-crystal silicon film on wafer 500 .
- Chamber body 45 is constructed, in one embodiment, of aluminum and has a passage 55 for water to be pumped therethrough, for example, within the chamber walls, to isolate the reaction area around wafer 500 and prevent deposition on the inside walls of chamber 45 .
- LPCVD chamber 100 may be a “cold-wall” reaction chamber.
- Resident in reaction chamber 90 is resistive heater 80 including, in this view, susceptor 5 supported by shaft 65 .
- Susceptor 5 has a surface area sufficient to support a substrate such as a semiconductor wafer 500 (shown in dashed lines).
- Wafer 500 may be any surface, generated when making an integrated circuit, upon which a conductive layer may be formed.
- Wafer 500 thus may include, for example, active and passive devices that are formed on a silicon wafer such as transistors, capacitors, resistors, diffused junctions, gate electrodes, local interconnects, etc.
- FIG. 1 also illustrates a cross-sectional view of a portion of heater 80 , including a cross-section of the body of susceptor 5 and a cross-section of shaft 65 .
- FIG. 1 illustrates the body of susceptor 5 having two heating elements formed therein, first heating element 50 and second heating element 57 .
- Each heating element e.g., heating element 50 and heating element 57
- the material for susceptor 5 may be molybdenum (Mo), or other heating elements known in the art.
- first and second heating elements 50 , 57 include a thin layer of molybdenum material in a coiled configuration.
- LPCVD chamber 100 provides the advantage of allowing for precise control of the deposition temperature for nano-crystal silicon.
- LPCVD chamber 100 may include lamp heaters instead of the resistive type heaters described above with respect to heating elements 50 and 57 .
- the deposition temperature in LPCVD chamber 100 is relatively low (e.g., below 500° C.).
- the deposition temperature in LPCVD chamber 100 is between about 300° C. to about 490° C.
- the deposition temperature may be referred to as the measured or set temperature of susceptor 5 .
- the deposition temperature may be referred to as the measured or set temperature of first and second heating elements 50 , 57 or heater 80 .
- the deposition environment provided by LPCVD chamber 100 allows for the precise controlling of temperature and pressure, which are important factors for the formation of nano-crystal silicon on wafer 500 .
- reaction chamber 90 are compatible with the process gases and other chemicals, such as cleaning chemicals (e.g., nitrogen trifluoride, NF 3 ) that may be introduced into reaction chamber 90 .
- cleaning chemicals e.g., nitrogen trifluoride, NF 3
- the exposed surfaces of heater 80 may be comprised of a variety of materials provided that the materials are compatible with the process.
- susceptor 5 and shaft 65 of heater 80 may be comprised of similar aluminum nitride material.
- the surface of susceptor 5 may be comprised of high thermally conductive aluminum nitride materials (on the order of about 95% purity with a thermal conductivity from about 140 W/mK, in one embodiment) while shaft 65 is comprised of a lower thermally conductive aluminum nitride.
- susceptor 5 of heater 80 may be coupled to shaft 65 through diffusion bonding or brazing, because this type of coupling may withstand the environment of reaction chamber 90 .
- second heating element 57 is formed in a plane of the body of susceptor 5 that is disposed inferior (relative to the surface of susceptor in the figure) to first heating element 50 .
- First heating element 50 and second heating element 57 are separately coupled to power terminals.
- the power terminals extend in an inferior direction as conductive leads through a longitudinally extending opening through shaft 65 to a power source that supplies the requisite energy to heat the surface of susceptor 5 .
- Extending through openings in chamber lid are two pyrometers, first pyrometer 10 and second pyrometer 15 . Each pyrometer provides data about the temperature at the surface of susceptor 5 (or at the surface of a wafer on susceptor 5 ).
- thermocouple 70 extends through the longitudinally extending opening through shaft 65 to a point just below the superior or top surface of susceptor 5 .
- Process gas enters otherwise sealed reaction chamber 90 through gas distribution port 20 in a top surface of chamber lid 30 of chamber body 45 .
- the process gas then goes through blocker plate 24 to distribute the gas about an area consistent with the surface area of a wafer.
- the process gas is distributed through perforated face plate 25 located, in this view, above resistive heater 80 and coupled to chamber lid 30 inside reaction chamber 90 .
- the combination of blocker plate 24 with face plate 25 creates a uniform distribution of process gas near a top surface of wafer 500 .
- wafer 500 is placed in reaction chamber 90 on susceptor 5 of heater 80 through entry port 40 in a side portion of chamber body 45 .
- heater 80 is lowered so that the surface of susceptor 5 is below entry port 40 as illustrated in FIG. 3 .
- wafer 500 may be loaded by way of, for example, a transfer blade 41 into reaction chamber 90 onto the superior surface of susceptor 5 .
- entry 40 is sealed and heater 80 is advanced in a superior (e.g., upward) direction toward face plate 25 by lifter assembly 60 that is, for example, a step motor (as illustrated in FIG. 1 ).
- reaction chamber 90 is effectively divided into two zones, a first zone 2 above the superior surface of susceptor 5 and a second zone 4 below the inferior surface of susceptor 5 .
- first zone 2 includes an area 88 above wafer 500 such that nano-crystal silicon film/layer formation is confined to an upper surface (i.e., the surface below perforated face plate 25 ). That is, nano-crystal silicon film deposition is limited to one side of wafer 500 .
- area 88 defines a partial pressure area in reaction chamber 90 (i.e., (flow rate of precursor/total flow) ⁇ chamber pressure) for a gas source such as a silicon precursor.
- nano-crystal silicon formation may be accomplished in both the first and second zones for silicon film deposition on both sides of wafer 500 . Accordingly, area 88 and area 89 , corresponding to the top and bottom surfaces of wafer 500 , defines the partial pressure area for dual sided silicon film deposition.
- process gas controlled by a gas panel flows into reaction chamber 90 through gas distribution port 20 , through blocker plate 24 and perforated face plate 25 .
- Process gas thermally decomposes to form a film on the wafer.
- an inert bottom-purge gas e.g., nitrogen
- the pressure in reaction chamber 90 is established and maintained by a pressure regulator or regulators (not shown) coupled to reaction chamber 90 .
- the pressure is established and maintained by baratron pressure regulator(s) coupled to chamber body 45 as known in the art.
- the baratron pressure regulator(s) maintains pressure at a level between about 10 Torr to about 350 Torr for the deposition of nano-crystal silicon on wafer 500 .
- Residual process gas is pumped from reaction chamber 90 through pumping plate 85 to a collection vessel at a side of chamber body 45 (vacuum pumpout 31 ).
- Pumping plate 85 creates two flow regions resulting in a gas flow pattern that forms a nano-crystal silicon layer on wafer 500 .
- Pump 32 disposed exterior to apparatus provides vacuum pressure within pumping channel 4140 (below channel 414 in FIGS. 1-3 ) to draw both the process and purge gases out of the reaction chamber 90 through vacuum pump-out 31 .
- the gas is discharged from reaction chamber 90 along a discharge conduit 33 .
- the flow rate of the discharge gas through channel 4140 is preferably controlled by a throttle valve 34 disposed along conduit 33 .
- the pressure within processing reaction chamber 90 is monitored with sensors (not shown) and controlled by varying the cross-sectional area of conduit 33 with throttle valve 34 .
- a controller or processor receives signals from the sensors that indicate the chamber pressure and adjusts throttle valve 34 accordingly to maintain the desired pressure within reaction chamber 90 .
- reaction chamber 90 may be purged, for example, with an inert gas, such as nitrogen.
- heater 80 is advanced in an inferior direction (e.g., lowered) by lifter assembly 60 to the position shown in FIG. 2 .
- lift pins 95 having an end extending through openings or throughbores in a surface of susceptor 5 and a second end extending in a cantilevered fashion from an inferior (e.g., lower) surface of susceptor 5 , contact lift plate 75 positioned at the base of reaction chamber 90 .
- lift plate 75 remains at a wafer-process position (i.e., the same position as illustrated in FIG.
- lift pins 95 remain stationary and ultimately extend above the susceptor or top surface of susceptor 5 to separate a processed wafer 500 from the surface of susceptor 5 .
- the surface of susceptor 5 is moved to a position below entry port 40 .
- transfer blade 41 of a robotic mechanism is inserted through opening 40 beneath the heads of lift pins 95 and wafer 500 is supported by lift pins 95 .
- lifter assembly 60 inferiorly moves (e.g., lowers) heater 80 and lift plate 75 to a “wafer load” position.
- lift pins 95 are also moved in an inferior direction, until the surface of the processed wafer 500 contacts transfer blade 41 .
- the processed wafer 500 is then removed through entry port 40 by, for example, a robotic transfer mechanism that removes wafer 500 and transfers wafer 500 to the next processing step.
- a second wafer (not shown) may then be loaded into reaction chamber 90 .
- the steps described above are generally reversed to bring wafer 500 into a process position.
- Single wafer LPCVD chamber 100 includes a processor/controller 700 and a memory 702 , such as a hard disk drive.
- the processor/controller 700 may include a single board (SBC) analog and digital input/output boards, interface boards and stepper motor controller board and is coupled to power supply 704 .
- SBC single board
- Processor/controller 700 controls all activity of LPCVD chamber 100 .
- Controller 700 executes system control software, which is a computer program stored in a computer readable medium such as memory 702 .
- the computer readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a machine (i.e., a computer, network device, personal digital assistant, manufacturing tool such as a single wafer deposition chamber, any device with a set of one or more processors, etc.).
- a computer readable medium includes recordable/non-recordable media (e.g., read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices, etc.), as well as electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).
- the computer program includes sets of instructions that dictate the timing, mixture of gases, chamber pressure, heater temperature, power supply (e.g., 704 ), susceptor position, and other parameters of the nano-crystal silicon deposition process.
- the computer program code can be written in any conventional computer readable programming language such as 68000 assembly language, C, C++, Pascal, Fortran, or others.
- Subroutines for carrying out process gas mixing, pressure control, and heater control may be stored within memory 702 .
- Memory 702 also stores process parameters such as process gas flow rates and compositions, temperatures, and pressures necessary to form a nano-crystal silicon film, for example, having a discontinuous grain structure.
- LPCVD chamber 100 includes in memory 702 instructions and process parameters for providing a silicon source gas and a carrier gas mix into reaction chamber 90 , heating the susceptor 5 to a temperature between about 300° C. to about 490° C., and generating a pressure between about 10 Torr to about 350 Torr within reaction chamber 90 so that a nano-crystal silicon film may be deposited by thermal chemical vapor deposition onto wafer 500 .
- FIG. 4 illustrates a block diagram of one embodiment of a method for depositing a discontinuous layer of nano-crystal silicon film on a substrate, also with respect to the single wafer LPCVD chamber (e.g., 100 ) of FIGS. 1-3 .
- a wafer or substrate e.g., wafer 500
- deposition chamber e.g., single wafer deposition chamber 90 .
- the wafer may be a doped silicon wafer 502 having a gate dielectric layer 504 , such as silicon oxide or silicon oxynitride formed thereon as illustrated in FIG. 5 a .
- dopants include, but are not limited to, germane (GeH 4 ), phosphine (PH 3 ), and diborane (B 2 H 6 ).
- the silicon precursor gas may include a dopant in situ so that a separate doping procedure is not required (i.e., the dopant is delivered with the carrier gas).
- the nano-crystal silicon film may be formed over an interlayer dielectric 504 formed over a doped silicon wafer 502 .
- the wafer is transferred into the chamber by a transfer blade (e.g., 41 ) as shown in FIG. 3 .
- a heater e.g., heater 80
- FIG. 1 A heater is then raised from the wafer load position to the wafer process position as shown in FIG. 1 .
- the desired deposition temperature and pressure are obtained and stabilized in the chamber.
- the deposition temperature of the chamber may be between about 300° C. to about 490° C.
- the deposition pressure of the chamber may be set to a pressure between about 10 Torr to about 350 Torr.
- a preferred temperature may be between about 400° C. to about 475° C., and a preferred pressure may be between about 30 Torr to about 350 Torr.
- a flowing carrier gas or dilution gas may be introduced into the chamber.
- the carrier or dilution gas may be nitrogen or argon.
- a silicon source i.e., precursor
- a carrier gas e.g., nitrogen, helium, argon
- the silicon source and carrier gas are fed into the chamber to deposit a nano-crystal silicon film 506 on substrate 500 as shown in FIG. 5 b .
- the flow of the silicon source is limited to area 88 above the top surface of wafer 500 for deposition of nano-crystal silicon on one side of wafer 500 .
- the silicon source may be a gas such as silane (SiH 4 ), or alternatively other silicon source gases such as disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), and bis-tertiarybutylamino silane (BTBAS, (C 8 H 22 N 2 Si)).
- the carrier gas may be a mixture that includes H 2 and an inert gas (e.g., nitrogen, helium, argon).
- silane is fed into the chamber between about 50 standard cubic centimeters per minute (sccm) to about 150 sccm, while the deposition temperature (i.e., the temperature of heater 80 ) in chamber 90 is maintained at a steady temperature between about 440° C. to about 490° C. and a deposition pressure of about 150 Torr to about 350 Torr.
- Another important process parameter includes the partial pressure of the silane precursor. As discussed above, the partial pressure for a silicon precursor gas is measured for area 88 above wafer 500 . In one embodiment, the partial pressure for silane may be between about 0.5 to about 3.5 Torr.
- this silicon precursor gas is fed into chamber 90 between about 50 sccm to about 150 sccm, while the deposition temperature in chamber 90 is maintained at a steady temperature between about 425° C. to about 475° C., and a deposition pressure of about 30 Torr to about 225 Torr.
- the partial pressure of the disilane precursor may be between about 0.1 Torr to about 3.0 Torr.
- this precursor gas is fed into chamber 90 between about 200 sccm to about 350 sccm, while the deposition temperature in chamber 90 is maintained at a steady temperature that is between about 400° C. to about 450° C., and a deposition pressure of about 30 Torr to about 200 Torr.
- the partial pressure of the trisilane precursor may be between about 0.1 Torr to about 2.5 Torr.
- the silicon source gas is added to the first component (upper component) of the carrier gas mix and flows into reaction chamber 90 through inlet port 20 .
- a precursor gas may be fed into reaction chamber 90 on both sides of wafer 500 for nano-silicon crystal formation (i.e., simultaneous deposition of nano-crystal silicon through areas 88 and 89 of chamber 90 ).
- a silane precursor gas may be fed into chamber 90 between about 120 sccm to about 180 sccm, while the deposition temperature in chamber 90 is maintained between about 475° C. to about 525° C., and a partial pressure (with area defined by areas 88 , 89 ) between about 0.8 Torr to about 1.2 Torr.
- a disilane precursor gas may be fed into chamber 90 between about 10 sccm to about 25 sccm, with a deposition temperature in chamber 90 is between about 450° C. to about 500° C., and a partial pressure between about 0.08 Torr to about 1.6 Torr.
- the thermal energy from a susceptor (e.g., susceptor 5 ) and wafer (e.g., wafer 500 or wafer 502 ) disposed within the chamber causes the silicon source gas to thermally decompose and deposit a discontinuous and amorphous nano-crystal silicon film on gate dielectric or interlayer dielectric 504 disposed above silicon wafer 502 as shown in FIG. 5 b .
- the layer of nano-crystal silicon in one embodiment, may have a density of greater than about 1E10 crystal/cm2 and an average grain diameter of less than about 5 nanometers.
- a gate electrode formed from nano-crystal silicon is that the nano-scale particles have a larger bandgap than larger, bulk silicon due to confinement in the small particles.
- the deposition pressure, temperature, and process gas flow rates and concentration are chosen so that a nano-crystal silicon film is deposited at a deposition rate in the range of about 5 ⁇ /min (Angstroms per minute) to about 15 ⁇ /min.
- the deposition rate may depend on the process chemistry, temperature, or pressure.
- silane may be deposited at a rate of about 5 ⁇ /min based on a deposition temperature between about 440° C. to about 490° C., a deposition pressure of about 150 Torr to about 350 Torr, and a partial pressure of about 0.5 Torr to about 3.5 Torr.
- the process gas mix is continually fed into the chamber until a nano-crystal silicon film 506 of a desired thickness is formed.
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Abstract
Numerous embodiments of a method for depositing a layer of nano-crystal silicon on a substrate. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C. A silicon source is also fed into the single wafer chamber.
Description
- This is a Divisional Application of Ser. No. 10/898,094 filed Jul. 23, 2004, which is presently pending.
- Embodiments of the present invention relate to the field of semiconductor processing and more specifically, to a method and apparatus for controlling the crystal structure of a silicon film.
- Polysilicon films formed by Chemical Vapor Deposition (CVD) have wide use in the fabrication of integrated circuits such as microprocessors and memory devices. Polysilicon film deposition processes require adequate physical, chemical, and production-worthy properties. For example, production-worthy properties include uniform thickness and composition for the polysilicon film (e.g., within wafer and wafer-to-wafer), low particulate and chemical contamination, and high throughput for manufacturing. When these properties are met, high electrical performance, reliable, and high yield device wafers can be manufactured at low cost.
- In a CVD process, a given composition and flow rate of reactant gases and diluent inert gases are introduced into a reaction chamber containing multiple substrates (e.g., batch furnace). The gas species move to the substrate and the reactants are absorbed on the substrate. The atoms undergo migration and chemically react resulting in a film (e.g., polysilicon) being deposited on the substrate. The un-reacted gases and gaseous by-products of the reaction are desorbed and removed from the reaction chamber. Energy to drive the reactions can be supplied by several methods, (e.g. thermal, photons, catalysis, or plasma). A conventional CVD system typically includes gas sources, gas feed lines, mass-flow controllers, a reaction chamber, a method for heating substrates onto which the film is to be deposited, and temperature sensors. A conventional thermal CVD system utilizes temperature as the primary driver for the reaction of source gases.
- In one type of CVD system for polysilicon deposition, a batch of silicon wafers are vertically positioned in a wafer boat for deposition and inserted into a tube-shaped furnace. The wafers are radiantly heated (above 600° C.) by resistive heating coils in the tube. Reactant gases are metered into one end of the tube (e.g., gas inlet) using a mass flow controller. Reaction by-products are pumped out the other end of the tube (e.g., via an exhaust pump).
- As semiconductor technology advances, there is a requirement for film deposition to occur at lower and lower temperatures to enable, for example, ultra shallow junctions for sub-100 nanometer (nm) devices. The formation of nano-crystal silicon structures within a film depends on the controlling the size and density of the nano-crystal silicon. One problem with batch furnace systems is that they cannot accommodate nano-crystal film deposition at low temperatures (e.g., below 500° C.). Another problem with batch furnace systems is that they exhibit a disadvantage known as “depletion effects.” Depletion effects reduce gas phase concentrations as reactants are consumed by reactions on wafer surfaces. As such, wafers near the inlet are exposed to higher concentrations of reactant gases. Deposition rates are thus greater for wafers placed near the inlet and uniform thickness is difficult to obtain.
- Embodiments of a method for depositing a layer of nano-crystal silicon on a substrate are described. In one embodiment of the present invention, a substrate is placed in a single wafer chamber and heated to a temperature between about 300° C. to about 490° C. A silicon source is also fed into the single wafer chamber. In an alternative embodiment, a pressure between about 10 Torr to about 350 Torr is generated in the single wafer chamber.
- Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which:
-
FIG. 1 illustrates a cross-sectional side view of one embodiment of a processing chamber having a resistive heater in a “wafer-process” position through a first cross-section and a second cross-section, each through one-half of the chamber. -
FIG. 2 illustrates of a similar cross-sectional side view as inFIG. 1 in a “wafer separate” position. -
FIG. 3 illustrates an illustration of a similar cross-sectional side view as inFIG. 1 in a “wafer load” position. -
FIG. 4 illustrates a block diagram of one embodiment of a method for depositing a discontinuous layer of nano-crystal silicon film on a substrate. -
FIG. 5 a illustrates one embodiment of a substrate having a dielectric formed on a silicon wafer. -
FIG. 5 b illustrates one embodiment of nano-crystal silicon formed on the substrate ofFIG. 5 a. - In the following description, numerous specific details are set forth such as examples of specific materials or components in order to provide a thorough understanding of embodiments of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice embodiments of the present invention. In other instances, well known components or methods have not been described in detail in order to avoid unnecessarily obscuring embodiments of the present invention.
- The terms “on,” “above,” “below,” “between,” and “adjacent” as used herein refer to a relative position of one layer or element with respect to other layers or elements. As such, a first element disposed on, above or below another element may be directly in contact with the first element or may have one or more intervening elements. Moreover, one element disposed next to or adjacent another element may be directly in contact with the first element or may have one or more intervening elements.
- Any reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the claimed subject matter. The appearances of the phrase, “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
- Embodiments of depositing and/or forming nano-crystal silicon films on a substrate are described. In one embodiment of the present invention, the process environment for forming the nano-crystal silicon film may be a single wafer deposition chamber, in which a CVD deposition method such as low pressure chemical vapor deposition (LPCVD) is used to form a nano-crystal silicon film on a substrate. The growth rate of the nano-crystal silicon film may be controlled to a desired level to form the silicon film with a particular density and dimension, wafer-to-wafer repeatability, and low thermal budget. The single wafer deposition chamber provides the advantage of precisely maintaining a desired deposition temperature as well as pressure control during nano-crystal silicon deposition. In one embodiment, the nano-crystal silicon film may be discontinuous, and both doped and undoped nano-crystal silicon formation may be achieved with the single wafer chamber. In another embodiment, the relative low deposition temperature results in an amorphous nano-crystal silicon layer. Embodiments of the present invention are advantageous over prior art methods for forming nano-crystal silicon layers that involve multiple steps (e.g., amorphous silicon deposition followed by an annealing process to recrystallize the amorphous silicon into nano-crystals). In one embodiment of the present invention, nano-crystal silicon formation may be achieved in a single step as carried out in a deposition chamber.
- The deposition of nano-crystal silicon on a substrate may be achieved by the reaction of vapor-phase chemicals (i.e., reactants) that contain the required constituents (e.g., silicon precursors). The reactant gases are introduced into a reaction chamber and are decomposed and/or reacted at a heated surface of a substrate to form the nano-crystal silicon film. In one embodiment, the reaction chamber may be one that accommodates only one substrate or wafer at a time.
FIGS. 1-3 illustrate one embodiment of an apparatus that may be used to practice embodiments of the present invention. In one particular embodiment, the apparatus may be aLPCVD chamber 100.FIGS. 1-3 each show cross-sectional views through two different cross-sections, each cross-section representing a view through approximately one-half ofLPCVD chamber 100, of one type of reactor such as a resistive reactor. TheLPCVD chamber 100 illustrated inFIGS. 1-3 is constructed of materials to maintain, in one embodiment, to provide a deposition chamber pressure between about 10 Torr to about 350 Torr. For the purpose of illustration,LPCVD chamber 100 may have a chamber volume of about 5-6 liters. As described in greater detail below,FIG. 1 illustrates the inside ofprocess chamber body 45 in a “wafer-process” position,FIG. 2 illustrates the same view of the chamber in a “wafer-separate” position, andFIG. 3 illustrates the same cross-sectional side view ofchamber body 45 in a “wafer-load” position. In each illustration, awafer 500 is indicated in dashed lines to indicate its location inLPCVD chamber 100. In one embodiment,LPCVD chamber 100 is adapted to hold one wafer only (i.e., a single wafer chamber).Chamber body 45 may also be sized to accommodate a wafer having a diameter between about 200 mm to about 300 mm. -
FIGS. 1-3 illustratechamber body 45 that definesreaction chamber 90 in which the thermal decomposition of a process gas or gases takes place to form a nano-crystal silicon film onwafer 500.Chamber body 45 is constructed, in one embodiment, of aluminum and has apassage 55 for water to be pumped therethrough, for example, within the chamber walls, to isolate the reaction area aroundwafer 500 and prevent deposition on the inside walls ofchamber 45. In one embodiment,LPCVD chamber 100 may be a “cold-wall” reaction chamber. Resident inreaction chamber 90 isresistive heater 80 including, in this view,susceptor 5 supported byshaft 65.Susceptor 5 has a surface area sufficient to support a substrate such as a semiconductor wafer 500 (shown in dashed lines).Wafer 500 may be any surface, generated when making an integrated circuit, upon which a conductive layer may be formed.Wafer 500 thus may include, for example, active and passive devices that are formed on a silicon wafer such as transistors, capacitors, resistors, diffused junctions, gate electrodes, local interconnects, etc. -
FIG. 1 also illustrates a cross-sectional view of a portion ofheater 80, including a cross-section of the body ofsusceptor 5 and a cross-section ofshaft 65. In this illustration,FIG. 1 illustrates the body ofsusceptor 5 having two heating elements formed therein,first heating element 50 andsecond heating element 57. Each heating element (e.g.,heating element 50 and heating element 57) is made of a material with thermal expansion properties similar to the material ofsusceptor 5. In one embodiment, the material forsusceptor 5 may be molybdenum (Mo), or other heating elements known in the art. In one embodiment, first andsecond heating elements LPCVD chamber 100 provides the advantage of allowing for precise control of the deposition temperature for nano-crystal silicon. In an alternative embodiment,LPCVD chamber 100 may include lamp heaters instead of the resistive type heaters described above with respect toheating elements - One advantage of the nano-crystal silicon deposition methods described herein is that the deposition temperature is relatively low (e.g., below 500° C.). In one embodiment, the deposition temperature in
LPCVD chamber 100 is between about 300° C. to about 490° C. In one embodiment, the deposition temperature may be referred to as the measured or set temperature ofsusceptor 5. In an alternative embodiment, the deposition temperature may be referred to as the measured or set temperature of first andsecond heating elements heater 80. The deposition environment provided byLPCVD chamber 100 allows for the precise controlling of temperature and pressure, which are important factors for the formation of nano-crystal silicon onwafer 500. Because nano-crystal silicon formation occurs at relatively low temperature, maintaining a precise deposition temperature may be critical. In one embodiment,heater 80 withheating elements blocker plate 24 andperforated face plate 25 provides the advantage of uniform gas distribution towardswafer 500. In one embodiment, materials forreaction chamber 90 are compatible with the process gases and other chemicals, such as cleaning chemicals (e.g., nitrogen trifluoride, NF3) that may be introduced intoreaction chamber 90. - The exposed surfaces of
heater 80 may be comprised of a variety of materials provided that the materials are compatible with the process. For example,susceptor 5 andshaft 65 ofheater 80 may be comprised of similar aluminum nitride material. Alternatively, the surface ofsusceptor 5 may be comprised of high thermally conductive aluminum nitride materials (on the order of about 95% purity with a thermal conductivity from about 140 W/mK, in one embodiment) whileshaft 65 is comprised of a lower thermally conductive aluminum nitride. In one embodiment,susceptor 5 ofheater 80 may be coupled toshaft 65 through diffusion bonding or brazing, because this type of coupling may withstand the environment ofreaction chamber 90. - In
FIG. 1 ,second heating element 57 is formed in a plane of the body ofsusceptor 5 that is disposed inferior (relative to the surface of susceptor in the figure) tofirst heating element 50.First heating element 50 andsecond heating element 57 are separately coupled to power terminals. The power terminals extend in an inferior direction as conductive leads through a longitudinally extending opening throughshaft 65 to a power source that supplies the requisite energy to heat the surface ofsusceptor 5. Extending through openings in chamber lid are two pyrometers,first pyrometer 10 and second pyrometer 15. Each pyrometer provides data about the temperature at the surface of susceptor 5 (or at the surface of a wafer on susceptor 5). Also of note in the cross-section ofheater 80 as shown inFIG. 1 is the presence ofthermocouple 70.Thermocouple 70 extends through the longitudinally extending opening throughshaft 65 to a point just below the superior or top surface ofsusceptor 5. - Process gas enters otherwise sealed
reaction chamber 90 throughgas distribution port 20 in a top surface ofchamber lid 30 ofchamber body 45. The process gas then goes throughblocker plate 24 to distribute the gas about an area consistent with the surface area of a wafer. Thereafter, the process gas is distributed throughperforated face plate 25 located, in this view, aboveresistive heater 80 and coupled tochamber lid 30 insidereaction chamber 90. In one embodiment, the combination ofblocker plate 24 withface plate 25 creates a uniform distribution of process gas near a top surface ofwafer 500. - As illustrated,
wafer 500 is placed inreaction chamber 90 onsusceptor 5 ofheater 80 throughentry port 40 in a side portion ofchamber body 45. To accommodate a wafer for processing,heater 80 is lowered so that the surface ofsusceptor 5 is belowentry port 40 as illustrated inFIG. 3 . In one embodiment, with a robotic transfer mechanism,wafer 500 may be loaded by way of, for example, atransfer blade 41 intoreaction chamber 90 onto the superior surface ofsusceptor 5. Once loaded,entry 40 is sealed andheater 80 is advanced in a superior (e.g., upward) direction towardface plate 25 bylifter assembly 60 that is, for example, a step motor (as illustrated inFIG. 1 ). The advancement stops when thewafer 500 is a short distance (e.g., 400-700 mils) from face plate 25 (seeFIG. 1 ). In the wafer-process position ofFIG. 1 ,reaction chamber 90 is effectively divided into two zones, afirst zone 2 above the superior surface ofsusceptor 5 and asecond zone 4 below the inferior surface ofsusceptor 5. - With
wafer 500 disposed withinreaction chamber 90,first zone 2 includes anarea 88 abovewafer 500 such that nano-crystal silicon film/layer formation is confined to an upper surface (i.e., the surface below perforated face plate 25). That is, nano-crystal silicon film deposition is limited to one side ofwafer 500. In one embodiment,area 88 defines a partial pressure area in reaction chamber 90 (i.e., (flow rate of precursor/total flow)×chamber pressure) for a gas source such as a silicon precursor. In an alternative embodiment, nano-crystal silicon formation may be accomplished in both the first and second zones for silicon film deposition on both sides ofwafer 500. Accordingly,area 88 andarea 89, corresponding to the top and bottom surfaces ofwafer 500, defines the partial pressure area for dual sided silicon film deposition. - At this point, process gas controlled by a gas panel flows into
reaction chamber 90 throughgas distribution port 20, throughblocker plate 24 andperforated face plate 25. Process gas thermally decomposes to form a film on the wafer. At the same time, an inert bottom-purge gas, e.g., nitrogen, is introduced into the second chamber zone to inhibit film formation in that zone. In a pressure controlled system, the pressure inreaction chamber 90 is established and maintained by a pressure regulator or regulators (not shown) coupled toreaction chamber 90. In one embodiment, for example, the pressure is established and maintained by baratron pressure regulator(s) coupled tochamber body 45 as known in the art. In one embodiment, the baratron pressure regulator(s) maintains pressure at a level between about 10 Torr to about 350 Torr for the deposition of nano-crystal silicon onwafer 500. - Residual process gas is pumped from
reaction chamber 90 through pumpingplate 85 to a collection vessel at a side of chamber body 45 (vacuum pumpout 31). Pumpingplate 85 creates two flow regions resulting in a gas flow pattern that forms a nano-crystal silicon layer onwafer 500. -
Pump 32 disposed exterior to apparatus provides vacuum pressure within pumping channel 4140 (belowchannel 414 inFIGS. 1-3 ) to draw both the process and purge gases out of thereaction chamber 90 through vacuum pump-out 31. The gas is discharged fromreaction chamber 90 along adischarge conduit 33. The flow rate of the discharge gas throughchannel 4140 is preferably controlled by athrottle valve 34 disposed alongconduit 33. In one embodiment, the pressure within processingreaction chamber 90 is monitored with sensors (not shown) and controlled by varying the cross-sectional area ofconduit 33 withthrottle valve 34. Preferably, a controller or processor (also not shown) receives signals from the sensors that indicate the chamber pressure and adjuststhrottle valve 34 accordingly to maintain the desired pressure withinreaction chamber 90. - Once processing of
wafer 500 is complete,reaction chamber 90 may be purged, for example, with an inert gas, such as nitrogen. After processing and purging,heater 80 is advanced in an inferior direction (e.g., lowered) bylifter assembly 60 to the position shown inFIG. 2 . Asheater 80 is moved, lift pins 95, having an end extending through openings or throughbores in a surface ofsusceptor 5 and a second end extending in a cantilevered fashion from an inferior (e.g., lower) surface ofsusceptor 5, contactlift plate 75 positioned at the base ofreaction chamber 90. As illustrated inFIG. 2 , in one embodiment,lift plate 75 remains at a wafer-process position (i.e., the same position as illustrated inFIG. 1 ). Asheater 80 continues to move in an inferior direction through the action ofassembly 60, lift pins 95 remain stationary and ultimately extend above the susceptor or top surface ofsusceptor 5 to separate a processedwafer 500 from the surface ofsusceptor 5. The surface ofsusceptor 5 is moved to a position belowentry port 40. - Once a processed
wafer 500 is separated from the surface ofsusceptor 5,transfer blade 41 of a robotic mechanism is inserted through opening 40 beneath the heads of lift pins 95 andwafer 500 is supported by lift pins 95. Next,lifter assembly 60 inferiorly moves (e.g., lowers)heater 80 andlift plate 75 to a “wafer load” position. By movinglift plates 75 in an inferior direction, lift pins 95 are also moved in an inferior direction, until the surface of the processedwafer 500 contacts transferblade 41. The processedwafer 500 is then removed throughentry port 40 by, for example, a robotic transfer mechanism that removeswafer 500 andtransfers wafer 500 to the next processing step. A second wafer (not shown) may then be loaded intoreaction chamber 90. The steps described above are generally reversed to bringwafer 500 into a process position. - Single
wafer LPCVD chamber 100 includes a processor/controller 700 and amemory 702, such as a hard disk drive. The processor/controller 700 may include a single board (SBC) analog and digital input/output boards, interface boards and stepper motor controller board and is coupled topower supply 704. Processor/controller 700 controls all activity ofLPCVD chamber 100.Controller 700 executes system control software, which is a computer program stored in a computer readable medium such asmemory 702. The computer readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a machine (i.e., a computer, network device, personal digital assistant, manufacturing tool such as a single wafer deposition chamber, any device with a set of one or more processors, etc.). For example, a computer readable medium includes recordable/non-recordable media (e.g., read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices, etc.), as well as electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). - The computer program includes sets of instructions that dictate the timing, mixture of gases, chamber pressure, heater temperature, power supply (e.g., 704), susceptor position, and other parameters of the nano-crystal silicon deposition process. The computer program code can be written in any conventional computer readable programming language such as 68000 assembly language, C, C++, Pascal, Fortran, or others. Subroutines for carrying out process gas mixing, pressure control, and heater control may be stored within
memory 702.Memory 702 also stores process parameters such as process gas flow rates and compositions, temperatures, and pressures necessary to form a nano-crystal silicon film, for example, having a discontinuous grain structure. In one embodiment,LPCVD chamber 100 includes inmemory 702 instructions and process parameters for providing a silicon source gas and a carrier gas mix intoreaction chamber 90, heating thesusceptor 5 to a temperature between about 300° C. to about 490° C., and generating a pressure between about 10 Torr to about 350 Torr withinreaction chamber 90 so that a nano-crystal silicon film may be deposited by thermal chemical vapor deposition ontowafer 500. -
FIG. 4 illustrates a block diagram of one embodiment of a method for depositing a discontinuous layer of nano-crystal silicon film on a substrate, also with respect to the single wafer LPCVD chamber (e.g., 100) ofFIGS. 1-3 . As set forth inblock 402 of diagram 400, a wafer or substrate (e.g., wafer 500) is placed in deposition chamber (e.g., single wafer deposition chamber 90). In one embodiment of the present invention, where the deposited nano-crystal silicon film is to be used as a gate electrode for a transistor of a semiconductor integrated circuit, the wafer may be a dopedsilicon wafer 502 having agate dielectric layer 504, such as silicon oxide or silicon oxynitride formed thereon as illustrated inFIG. 5 a. Examples of dopants include, but are not limited to, germane (GeH4), phosphine (PH3), and diborane (B2H6). In one embodiment, the silicon precursor gas may include a dopant in situ so that a separate doping procedure is not required (i.e., the dopant is delivered with the carrier gas). If the nano-crystal silicon film is used as an interconnect or capacitor electrode, then the nano-crystal silicon film may be formed over aninterlayer dielectric 504 formed over a dopedsilicon wafer 502. The wafer is transferred into the chamber by a transfer blade (e.g., 41) as shown inFIG. 3 . A heater (e.g., heater 80) is then raised from the wafer load position to the wafer process position as shown inFIG. 1 . - Next, as set forth in
blocks - Next, once the temperature, pressure, and gas flows have been stabilized, a silicon source (i.e., precursor) is fed into the chamber with a carrier gas (e.g., nitrogen, helium, argon) with a partial pressure of about 0.1 Torr to about 3.5 Torr, block 408. The silicon source and carrier gas are fed into the chamber to deposit a nano-
crystal silicon film 506 onsubstrate 500 as shown inFIG. 5 b. The flow of the silicon source is limited toarea 88 above the top surface ofwafer 500 for deposition of nano-crystal silicon on one side ofwafer 500. In one embodiment of the present invention, the silicon source may be a gas such as silane (SiH4), or alternatively other silicon source gases such as disilane (Si2H6), trisilane (Si3H8), and bis-tertiarybutylamino silane (BTBAS, (C8H22N2Si)). In one embodiment, the carrier gas may be a mixture that includes H2 and an inert gas (e.g., nitrogen, helium, argon). In one example, silane is fed into the chamber between about 50 standard cubic centimeters per minute (sccm) to about 150 sccm, while the deposition temperature (i.e., the temperature of heater 80) inchamber 90 is maintained at a steady temperature between about 440° C. to about 490° C. and a deposition pressure of about 150 Torr to about 350 Torr. Another important process parameter includes the partial pressure of the silane precursor. As discussed above, the partial pressure for a silicon precursor gas is measured forarea 88 abovewafer 500. In one embodiment, the partial pressure for silane may be between about 0.5 to about 3.5 Torr. - For disilane, this silicon precursor gas is fed into
chamber 90 between about 50 sccm to about 150 sccm, while the deposition temperature inchamber 90 is maintained at a steady temperature between about 425° C. to about 475° C., and a deposition pressure of about 30 Torr to about 225 Torr. The partial pressure of the disilane precursor may be between about 0.1 Torr to about 3.0 Torr. For trisilane, this precursor gas is fed intochamber 90 between about 200 sccm to about 350 sccm, while the deposition temperature inchamber 90 is maintained at a steady temperature that is between about 400° C. to about 450° C., and a deposition pressure of about 30 Torr to about 200 Torr. The partial pressure of the trisilane precursor may be between about 0.1 Torr to about 2.5 Torr. In one embodiment of the present invention, the silicon source gas is added to the first component (upper component) of the carrier gas mix and flows intoreaction chamber 90 throughinlet port 20. - In an alternative embodiment, a precursor gas may be fed into
reaction chamber 90 on both sides ofwafer 500 for nano-silicon crystal formation (i.e., simultaneous deposition of nano-crystal silicon throughareas chamber 90 between about 120 sccm to about 180 sccm, while the deposition temperature inchamber 90 is maintained between about 475° C. to about 525° C., and a partial pressure (with area defined byareas 88, 89) between about 0.8 Torr to about 1.2 Torr. A disilane precursor gas may be fed intochamber 90 between about 10 sccm to about 25 sccm, with a deposition temperature inchamber 90 is between about 450° C. to about 500° C., and a partial pressure between about 0.08 Torr to about 1.6 Torr. - The thermal energy from a susceptor (e.g., susceptor 5) and wafer (e.g.,
wafer 500 or wafer 502) disposed within the chamber causes the silicon source gas to thermally decompose and deposit a discontinuous and amorphous nano-crystal silicon film on gate dielectric orinterlayer dielectric 504 disposed abovesilicon wafer 502 as shown inFIG. 5 b. Although theFIG. 5 b is illustrated in a simplified form for clarity of explanation, the layer of nano-crystal silicon, in one embodiment, may have a density of greater than about 1E10 crystal/cm2 and an average grain diameter of less than about 5 nanometers. In one embodiment of the present invention, only thermal energy is used to decompose the silicon source gas without the aid of additional energy sources such as plasma or photon enhancement. One advantage of a gate electrode formed from nano-crystal silicon is that the nano-scale particles have a larger bandgap than larger, bulk silicon due to confinement in the small particles. - In one embodiment of the present invention, the deposition pressure, temperature, and process gas flow rates and concentration are chosen so that a nano-crystal silicon film is deposited at a deposition rate in the range of about 5 Å/min (Angstroms per minute) to about 15 Å/min. The deposition rate may depend on the process chemistry, temperature, or pressure. For example, silane may be deposited at a rate of about 5 Å/min based on a deposition temperature between about 440° C. to about 490° C., a deposition pressure of about 150 Torr to about 350 Torr, and a partial pressure of about 0.5 Torr to about 3.5 Torr. The process gas mix is continually fed into the chamber until a nano-
crystal silicon film 506 of a desired thickness is formed. - In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of embodiments of the invention as set forth in the appended claims. The specification and figures are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (13)
1. A method, comprising:
positioning a substrate in a single wafer chamber;
heating the single wafer chamber to generate a deposition temperature between about 300° C. to about 490° C.; and
feeding a silicon gas source directed toward a surface of the substrate with a partial pressure between about 0.1 Torr to about 3.5 Torr to form a layer of nano-crystal silicon on the substrate.
2. The method of claim 1 , further comprising generating a deposition pressure between about 10 Torr to about 350 Torr.
3. The method of claim 2 , wherein feeding further comprises adding a nitrogen carrier gas to the silicon source.
4. The method of claim 1 , wherein said layer nano-crystal silicon comprises an amorphous and discontinuous layer.
5. The method of claim 1 , wherein the layer of nano-crystal silicon has a density of greater than about 1E10 crystal/cm2 and an average grain diameter of less than about 5 nanometers.
6. The method of claim 1 , wherein the silicon source comprises silane.
7. The method of claim 1 , wherein the silicon source comprises disilane.
8. The method of claim 1 , wherein heating maintaining the deposition temperature with dual resistive heaters disposed within the single wafer chamber.
9. An apparatus, comprising:
a machine accessible medium including data that, when accessed by a machine, causes the machine to perform operations comprising:
generating a deposition temperature between about 300° C. to about 490° C.;
generating a deposition pressure between about 10 Torr to about 350 Torr; and
feeding a silicon source with a partial pressure between about 0.1 Torr to about 3.5 Torr into the machine to deposit a layer of nano-crystal silicon on the substrate.
10. The apparatus of claim 9 , wherein the machine comprises a single wafer deposition chamber.
11. The apparatus of claim 10 , wherein the single wafer deposition chamber comprises:
a substrate holder to hold the substrate during nano-crystal silicon deposition;
a gas delivery system to introduce a process gas mix into the single wafer deposition chamber;
a pump coupled to a gas outlet to control the deposition pressure; and
a controller to control the gas delivery system and pump.
12. The apparatus of claim 10 , wherein the layer of nano-crystal silicon is amorphous and discontinuous.
13. The apparatus of claim 10 , wherein the layer of nano-crystal silicon has a density of greater than about 1E10 crystal/cm2 and an average grain diameter of less than about 5 nanometers.
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US11/893,301 US20070287271A1 (en) | 2004-07-23 | 2007-08-13 | Deposition of nano-crystal silicon using a single wafer chamber |
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US10/898,094 US7265036B2 (en) | 2004-07-23 | 2004-07-23 | Deposition of nano-crystal silicon using a single wafer chamber |
US11/893,301 US20070287271A1 (en) | 2004-07-23 | 2007-08-13 | Deposition of nano-crystal silicon using a single wafer chamber |
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US10/898,094 Division US7265036B2 (en) | 2004-07-23 | 2004-07-23 | Deposition of nano-crystal silicon using a single wafer chamber |
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US11/893,301 Abandoned US20070287271A1 (en) | 2004-07-23 | 2007-08-13 | Deposition of nano-crystal silicon using a single wafer chamber |
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US (2) | US7265036B2 (en) |
JP (1) | JP4979578B2 (en) |
KR (1) | KR20070039964A (en) |
CN (1) | CN1989270A (en) |
WO (1) | WO2006019861A1 (en) |
Cited By (1)
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US20100204951A1 (en) * | 2007-02-14 | 2010-08-12 | Zettl Alexander K | Method to determine thermal profiles of nanoscale circuitry |
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US20080246101A1 (en) * | 2007-04-05 | 2008-10-09 | Applied Materials Inc. | Method of poly-silicon grain structure formation |
US7846793B2 (en) * | 2007-10-03 | 2010-12-07 | Applied Materials, Inc. | Plasma surface treatment for SI and metal nanocrystal nucleation |
JP5283370B2 (en) * | 2007-11-29 | 2013-09-04 | 株式会社ニューフレアテクノロジー | Vapor growth apparatus and vapor growth method |
WO2009082840A1 (en) * | 2007-12-27 | 2009-07-09 | Applied Materials, Inc. | Method for forming a polysilicon film |
JP2013045789A (en) * | 2011-08-22 | 2013-03-04 | National Institute Of Advanced Industrial & Technology | Manufacturing method of silicon carbide semiconductor device |
US10546942B2 (en) * | 2017-07-25 | 2020-01-28 | International Business Machines Corporation | Nanosheet transistor with optimized junction and cladding defectivity control |
CN114086158A (en) * | 2021-11-29 | 2022-02-25 | 重庆忽米网络科技有限公司 | Wafer deposition processing method for CVD equipment |
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Also Published As
Publication number | Publication date |
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KR20070039964A (en) | 2007-04-13 |
US20060019469A1 (en) | 2006-01-26 |
WO2006019861A1 (en) | 2006-02-23 |
US7265036B2 (en) | 2007-09-04 |
CN1989270A (en) | 2007-06-27 |
JP2008507846A (en) | 2008-03-13 |
JP4979578B2 (en) | 2012-07-18 |
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