US20070187803A1 - Plasma Enhanced Deposited, Fully Oxidized PSG Film - Google Patents

Plasma Enhanced Deposited, Fully Oxidized PSG Film Download PDF

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US20070187803A1
US20070187803A1 US11/740,038 US74003807A US2007187803A1 US 20070187803 A1 US20070187803 A1 US 20070187803A1 US 74003807 A US74003807 A US 74003807A US 2007187803 A1 US2007187803 A1 US 2007187803A1
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oxide film
plasma enhanced
sccm
substrate
fully oxidized
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US11/740,038
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Katie Pentas
Mark Bordelon
Jack Linn
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Intersil Americas LLC
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Intersil Americas LLC
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40Oxides
    • C23C16/401Oxides containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31625Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

Definitions

  • the present disclosure relates generally to an integrated circuit having oxide films and, more specifically, to a plasma enhanced deposited oxide film.
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • TO thermal oxidation
  • oxide films have retained more charge than thermal oxidized films because the film includes dangling atoms, which are not fully bonded to each other (namely, incomplete reacted species).
  • the present disclosure has found that a modification of the PECVD process has substantially decreased the charge retention of the oxide and has improved the Si—O—Si bonding within the oxide so as to be more fully oxidized. This more fully oxidized bonding is reflected by an increase in the Si—O—Si bond peak wavelength in the IR spectrum. It is also capable of increased levels of doping, which have improved re-flow characteristics, as well as other characteristics.
  • the present method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine.
  • the chamber is pressurized and energy is applied to create a plasma.
  • the energy may be a dual frequency energy.
  • the gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O ⁇ Si bond peak absorbance in the IR spectrum of at least 1092 cm ⁇ 1 .
  • the oxide film uniformity has a standard deviation of 0.7% maximum.
  • FIG. 1 is a diagram of an apparatus for carrying out the present method and the resulting integrated circuit.
  • a device or chamber 10 has multiple gas inlets 12 and 14 .
  • the plasma enhancement elements or energy source are schematically shown at 16 .
  • the chamber and the process is conducted to produce an oxide film 22 on a substrate 20 .
  • An example of the system 10 may be a Novellus Concept 1 PECVD device. Since the device is well known, all other elements have been excluded, including the details of the plasma enhancing portion 16 .
  • the dual frequency percentages have been changed with an increase of the percentage of high frequency power compared to low frequency power.
  • the dual frequency also makes the film compressive.
  • the deposition may be performed without the dual frequency if the compressive characteristics are not desired.
  • the film of the present disclosure more closely resembles that of a thermal oxide film.
  • the silane flow is 180 sccm, 650 sccm for 3% phosphine, 9,500 sccm for N 2 O and 4,000 sccm for N 2 .
  • the pressure was 2.8 torrs.
  • the deposition occurs at temperatures of 400° C.
  • the increase of the Si—O—Si peak wavelength to 1096 cm ⁇ 1 is substantial since 1096 cm ⁇ 1 is the highest thermal oxide peak absorbance.
  • the increase in the Si—O—Si peak wavelength indicates nearly complete oxidation of the Si—O—Si bonding in the current PECVD film.
  • PECVD films have not even been able to reach this value, due to incomplete reaction of the reactant gases.
  • the standard deviation of film uniformity of the oxide in the experiments have been between 0.4% and 0.7%.
  • the stress of the film is compressive at ⁇ 1.44E8 dyne/cm 2 .
  • the deposition rate was not compromised in the present process and remains at about 3,800 angstroms per minute.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O—Si bond peak absorbance in the IR spectrum of at least 1092 cm−1.

Description

    CROSS-REFERENCE
  • This application claims the benefit of U.S. patent application Ser. No. 10/953,573 filed Sep. 30, 2004 and Provisional Patent Application Ser. No. 60/583,844 filed on Jun. 30, 2004, which are incorporated herein by reference.
  • BACKGROUND AND SUMMARY OF THE DISCLOSURE
  • The present disclosure relates generally to an integrated circuit having oxide films and, more specifically, to a plasma enhanced deposited oxide film.
  • One method of deposition is chemical vapor deposition (CVD), which includes plasma enhanced chemical vapor deposition (PECVD). The other method is thermal oxidation (TO). Various devices in an integrated circuit may be affected by the charge retention in the oxide film. Specifically, in metal oxide silicon transistors, once the biasing of the device is removed, the oxide may retain various levels of charge. This would affect the turn off and/or reactivation of the device. Historically, CVD oxide films have retained more charge than thermal oxidized films because the film includes dangling atoms, which are not fully bonded to each other (namely, incomplete reacted species).
  • This problem is addressed in the article “Development of a Fully Oxidized PECVD PSG Film,” Semiconductor International, p. 105 (August 2000). The suggested solution is to increase the N2O:SiH4 ratio and process pressure and using only high frequency RF power. The Si—O—Si bond peak wavelength in the infrared (IR) spectrum was 1091 cm−1 for the CVD oxide film compared to 1095 cm−1 for the TO oxide film.
  • The present disclosure has found that a modification of the PECVD process has substantially decreased the charge retention of the oxide and has improved the Si—O—Si bonding within the oxide so as to be more fully oxidized. This more fully oxidized bonding is reflected by an increase in the Si—O—Si bond peak wavelength in the IR spectrum. It is also capable of increased levels of doping, which have improved re-flow characteristics, as well as other characteristics.
  • The present method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O≦Si bond peak absorbance in the IR spectrum of at least 1092 cm−1. The oxide film uniformity has a standard deviation of 0.7% maximum.
  • These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram of an apparatus for carrying out the present method and the resulting integrated circuit.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • A device or chamber 10 has multiple gas inlets 12 and 14. The plasma enhancement elements or energy source are schematically shown at 16. The chamber and the process is conducted to produce an oxide film 22 on a substrate 20.
  • An example of the system 10 may be a Novellus Concept 1 PECVD device. Since the device is well known, all other elements have been excluded, including the details of the plasma enhancing portion 16.
  • The following Table 1 shows the parameters of the current recipe and three examples of the new recipe wherein the flow rate of 9,500 sccm for N2O and 4,000 sccm for N2 are the same for all recipes:
    TABLE 1
    PREVIOUS CURRENT NEW NEW NEW
    PARAMETER RECIPE RECIPE RECIPE A RECIPE B RECIPE C
    Silane Flow 200 sccm 180 sccm 200 sccm 180 sccm 180 sccm
    Phosphine Flow 540 sccm 540 sccm 670 sccm 650 sccm 680 sccm
    HF Power 40% 40% 60% 60% 60%
    LF Power 60% 60% 40% 40% 40%
    Pressure 2.6 T 2.6 T 3 T 2.8 T 2.8 T
    Peak Wavelength ˜1086 cm−1 ˜1089 cm−1 ˜1092 cm−1 1096.4 cm−1 1092.3 cm−1
  • A review of Table 1 will indicate that decreasing the silane flow or maintaining the same while substantially increasing the dopant or phosphine flow and increasing the pressure is provided by the present method. This causes an increase in the Si—O—Si bond peak wavelength in the IR spectrum, which is reflective of more complete and fully oxidized bonding within the silicon oxide film. The phosphorous content in the oxide may be in the range of 6% to 8%. This is an example for a silicon oxide formed on a silicon substrate. The more fully oxidized and completely reacted Si—O—Si bonding reduces the charge retention of the silicon oxide. This leads to improved performance of the integrated circuit devices. The resulting standard deviation of film uniformity of the oxide is generally in the range of 0.4% to 0.7%.
  • The dual frequency percentages have been changed with an increase of the percentage of high frequency power compared to low frequency power. The dual frequency also makes the film compressive. The deposition may be performed without the dual frequency if the compressive characteristics are not desired. The film of the present disclosure more closely resembles that of a thermal oxide film.
  • A detailed explanation of all of the gas flows for one example may be as follows: The silane flow is 180 sccm, 650 sccm for 3% phosphine, 9,500 sccm for N2O and 4,000 sccm for N2. The pressure was 2.8 torrs. The deposition occurs at temperatures of 400° C.
  • The increase of the Si—O—Si peak wavelength to 1096 cm−1 is substantial since 1096 cm−1 is the highest thermal oxide peak absorbance. The increase in the Si—O—Si peak wavelength indicates nearly complete oxidation of the Si—O—Si bonding in the current PECVD film. In general, PECVD films have not even been able to reach this value, due to incomplete reaction of the reactant gases. As previously discussed, the standard deviation of film uniformity of the oxide in the experiments have been between 0.4% and 0.7%. It should also be noted that the stress of the film is compressive at −1.44E8 dyne/cm2. The deposition rate was not compromised in the present process and remains at about 3,800 angstroms per minute.
  • Although the present disclosure has been described and illustrated in detail, it is to be clearly understood that this is done by way of illustration and example only and is not to be taken by way of limitation. The scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims (4)

1. An integrated circuit comprising:
a substrate;
a plasma enhanced deposited silicon oxide film on the substrate; and
the silicon oxide film having a peak absorbance in the IR spectrum of at least 1092 cm−1.
2. The integrated circuit of claim 1, wherein the silicon oxide film uniformity has a standard deviation of 0.7% maximum.
3. The integrated circuit of claim 2, wherein the silicon oxide film has a phosphorus content in the range of 6% to 8%.
4. The integrated circuit of claim 1, wherein the silicon oxide film has a phosphorus content in the range of 6% to 8%.
US11/740,038 2004-06-30 2007-04-25 Plasma Enhanced Deposited, Fully Oxidized PSG Film Abandoned US20070187803A1 (en)

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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4327965A (en) * 1979-10-29 1982-05-04 International Standard Electric Corporation Single mode fibre and method of manufacture
US4376672A (en) * 1981-10-26 1983-03-15 Applied Materials, Inc. Materials and methods for plasma etching of oxides and nitrides of silicon
US4394401A (en) * 1980-08-08 1983-07-19 Fujitsu Limited Method of plasma enhanced chemical vapor deposition of phosphosilicate glass film
US4474831A (en) * 1982-08-27 1984-10-02 Varian Associates, Inc. Method for reflow of phosphosilicate glass
US4985373A (en) * 1982-04-23 1991-01-15 At&T Bell Laboratories Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures
US5231057A (en) * 1990-08-20 1993-07-27 Fujitsu Limited Method of depositing insulating layer on underlying layer using plasma-assisted cvd process using pulse-modulated plasma
US5851842A (en) * 1996-05-16 1998-12-22 Kabushiki Kaisha Toshiba Measurement system and measurement method
US6013584A (en) * 1997-02-19 2000-01-11 Applied Materials, Inc. Methods and apparatus for forming HDP-CVD PSG film used for advanced pre-metal dielectric layer applications
US6246105B1 (en) * 1997-11-05 2001-06-12 Seiko Epson Corporation Semiconductor device and manufacturing process thereof
US6268297B1 (en) * 1997-11-26 2001-07-31 Texas Instruments Incorporated Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces
US20040092046A1 (en) * 2002-11-06 2004-05-13 Kim Tae-Kyoung Method of measuring a concentration of a material and method of measuring a concentration of a dopant of a semiconductor device
US20040119145A1 (en) * 2001-09-13 2004-06-24 Tech Semiconducor Singapore Pte. Ltd. Method for depositing a very high phosphorus doped silicon oxide film
US7001854B1 (en) * 2001-08-03 2006-02-21 Novellus Systems, Inc. Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6042901A (en) * 1996-02-20 2000-03-28 Lam Research Corporation Method for depositing fluorine doped silicon dioxide films
US6303518B1 (en) * 1999-09-30 2001-10-16 Novellus Systems, Inc. Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers
US7080528B2 (en) * 2002-10-23 2006-07-25 Applied Materials, Inc. Method of forming a phosphorus doped optical core using a PECVD process

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4327965A (en) * 1979-10-29 1982-05-04 International Standard Electric Corporation Single mode fibre and method of manufacture
US4394401A (en) * 1980-08-08 1983-07-19 Fujitsu Limited Method of plasma enhanced chemical vapor deposition of phosphosilicate glass film
US4376672A (en) * 1981-10-26 1983-03-15 Applied Materials, Inc. Materials and methods for plasma etching of oxides and nitrides of silicon
US4985373A (en) * 1982-04-23 1991-01-15 At&T Bell Laboratories Multiple insulating layer for two-level interconnected metallization in semiconductor integrated circuit structures
US4474831A (en) * 1982-08-27 1984-10-02 Varian Associates, Inc. Method for reflow of phosphosilicate glass
US5231057A (en) * 1990-08-20 1993-07-27 Fujitsu Limited Method of depositing insulating layer on underlying layer using plasma-assisted cvd process using pulse-modulated plasma
US5851842A (en) * 1996-05-16 1998-12-22 Kabushiki Kaisha Toshiba Measurement system and measurement method
US6013584A (en) * 1997-02-19 2000-01-11 Applied Materials, Inc. Methods and apparatus for forming HDP-CVD PSG film used for advanced pre-metal dielectric layer applications
US6246105B1 (en) * 1997-11-05 2001-06-12 Seiko Epson Corporation Semiconductor device and manufacturing process thereof
US6268297B1 (en) * 1997-11-26 2001-07-31 Texas Instruments Incorporated Self-planarizing low-temperature doped-silicate-glass process capable of gap-filling narrow spaces
US7001854B1 (en) * 2001-08-03 2006-02-21 Novellus Systems, Inc. Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures
US20040119145A1 (en) * 2001-09-13 2004-06-24 Tech Semiconducor Singapore Pte. Ltd. Method for depositing a very high phosphorus doped silicon oxide film
US20040092046A1 (en) * 2002-11-06 2004-05-13 Kim Tae-Kyoung Method of measuring a concentration of a material and method of measuring a concentration of a dopant of a semiconductor device

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US7223706B2 (en) 2007-05-29

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