US20070164354A1 - MOS transistor with elevated source and drain structures and method of fabrication thereof - Google Patents
MOS transistor with elevated source and drain structures and method of fabrication thereof Download PDFInfo
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- US20070164354A1 US20070164354A1 US11/726,161 US72616107A US2007164354A1 US 20070164354 A1 US20070164354 A1 US 20070164354A1 US 72616107 A US72616107 A US 72616107A US 2007164354 A1 US2007164354 A1 US 2007164354A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Definitions
- a conventional scaled-down MOS transistor 100 which is fabricated within a semiconductor substrate 102 , includes a source extension region 106 a and a drain extension region 106 b .
- the source extension region 106 a and the drain extension region 106 b have shallow junctions in order to minimize the short-channel effect that occurs in MOS transistors having sub-micron or nanometer dimensions.
- the MOS transistor 100 further includes a source region 108 a and a drain region 108 b that have deeper junctions, relative to the source extension region 106 a and the drain extension region 106 b, to provide lower resistance.
- the MOS transistor 100 also includes a gate structure 110 , which is comprised of a gate dielectric 112 and a gate electrode 114 .
- An insulative spacer 118 which is typically comprised of silicon nitride (SiN), is disposed on the sidewalls of the gate structure 110 .
- the MOS transistor 100 further includes silicide regions 120 a, 120 b, and 120 c to provide low-resistance electrical contact with the source/drain 106 a / 106 b and the gate electrode 114 .
- the MOS transistor is electrically isolated from other devices by shallow trench isolation structures 104 .
- the transistor 100 has effective resistances R that are connected in series to the source and the drain. This inhibits the flow of electric current, thus decreasing operation speed.
- a second problem concerns the rise of channel dopant concentration, which in turn causes a rise in threshold voltage in the field effect transistor.
- the impurity concentration of the channel impurity region is necessarily raised.
- contemporary semiconductor devices are designed to operate with a lower power supply voltage, such as ranging from 5V to 3.3V.
- the threshold voltage of the field effect transistor needs to be lower. For this reason, any rise in the threshold voltage of MOS transistor due to the rise in channel dopant concentration is undesirable.
- a channel doping level that is too high in scaled-down devices gives rise to superfluous leakage current and junction breakdown.
- a gate structure 210 comprised of a gate dielectric 212 and a gate electrode 214 is formed on the surface of the semiconductor substrate 202 .
- a source extension region 206 a and a drain extension region 206 b are then formed in the semiconductor substrate.
- a spacer 218 typically comprised of silicon nitride (SiN), is formed on the sidewalls of the gate structure 210 .
- An epitaxial layer 205 typically comprised of silicon, is grown on the exposed portions of the source/drain extension regions 206 a / 206 b, typically using selective epitaxial growth.
- the MOS transistor 200 further includes silicide regions 220 a, 220 b, and 220 c to provide electrical contacts to the elevated source/drain regions 208 a / 208 b and the gate electrode 214 .
- a MOS transistor having an elevated source/drain produced according to the structure of FIG. 2 is effective for reducing the resistance of the source and drain regions by increasing the thickness and the doping level by elevating the source/drain regions 208 a / 208 b .
- the dopants of the source/drain extension regions 206 a / 206 b diffuse into the region immediately under the gate 210 , which result in junction leakage current through the source/drain extension regions 206 a / 206 b.
- the present invention is directed to a MOS transistor having elevated source and drain structures, and a method of formation thereof, that overcomes the limitations of the conventional embodiments.
- the present invention provides for a transistor that includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region.
- the performance characteristics of the transistor of the present invention can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate.
- the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
- the present invention is directed to a method for forming a MOS transistor having elevated source and drain structures.
- a sacrificial gate pattern is provided on a substrate.
- An epitaxial layer is provided on the substrate adjacent the sacrificial gate pattern.
- a silicon nitride film and a silicon oxide film are provided on the epitaxial layer adjacent the sacrificial gate pattern.
- the sacrificial gate pattern is removed to expose a portion of the substrate and wall portions of the epitaxial layer.
- a gate dielectric layer is provided on the exposed portion of the substrate and along the wall portions of the epitaxial layer.
- a gate electrode is provided on the gate dielectric layer. The silicon oxide film and silicon nitride film are removed.
- the epitaxial layer is doped with impurities using the gate electrode as a mask to form source/drain extension regions in the epitaxial layer proximal to the gate dielectric layer. Insulating spacers are provided on sidewalls of an upper portion of the gate electrode.
- the epitaxial layer is doped with impurities using the gate electrode and insulating spacers as a mask to form deep source/drain regions adjacent the source/drain extension regions.
- the source/drain extension regions are formed by doping the epitaxial layer with impurities prior to providing the silicon nitride film and silicon oxide film on the epitaxial layer.
- Providing the sacrificial gate pattern may comprise sequentially forming a silicon oxide film and a silicon nitride film and patterning the sequentially formed films to form the sacrificial gate pattern.
- the substrate is, for example, of a type selected from the group consisting of: silicon; silicon-on-insulator (SOI); SiGe; SiGe-on-insulator(SGOI); strained silicon; strained silicon-on-insulator; and GaAs.
- the substrate is optionally formed of a material of a first conductivity type and the impurities used for doping the epitaxial layer are of a second conductivity type opposite that of the first conductivity type.
- a pad oxide layer may be formed on the epitaxial layer.
- the step of providing a silicon nitride film and a silicon oxide film on the epitaxial layer adjacent the sacrificial gate pattern may comprise: sequentially providing a silicon nitride film and a silicon oxide film on the epitaxial layer and the sacrificial gate pattern; and planarizing the silicon nitride film, silicon oxide film and sacrificial gate pattern to expose an upper surface of the sacrificial gate pattern.
- the silicon oxide film is provided, for example, by a chemical vapor deposition (CVD) process.
- the step of planarizing comprises, for example, planarizing by a chemical-mechanical polishing process (CMP) or an etch-back treatment.
- CMP chemical-mechanical polishing process
- Removal of the sacrificial gate pattern comprises etching the sacrificial gate pattern to expose an upper surface of the substrate, or, optionally, forming a recess in the substrate, in which case the gate dielectric layer is formed on bottom and side walls of the recess of the substrate.
- the recess is preferably of a depth that is less than 50 nm.
- the exposed portion of the substrate may be doped with impurities to form a channel region following removal of the sacrificial gate pattern, or, optionally, prior to providing the sacrificial gate pattern on the substrate, the channel region corresponding to an area of the substrate covered by the sacrificial gate pattern.
- the gate dielectric layer preferably comprises a material selected from the group of materials consisting of: silicon oxide film; silicon oxy-nitride (SiON); tantalum oxide; and a high-dielectric-constant material.
- the step of providing the gate electrode comprises, for example, forming a gate electrode material film on the gate dielectric layer and the silicon oxide film; and planarizing the gate electrode material film and silicon oxide film.
- Planarizing comprises, for example, planarizing by a chemical-mechanical polishing process (CMP) or an etch-back treatment.
- CMP chemical-mechanical polishing process
- the gate electrode comprises a material selected from the group of materials consisting of polysilicon film; silicon geranium film; silicide film; metal film; and a laminate film.
- the step of removing the silicon oxide film and silicon nitride film comprises removing using a wet etching process.
- the step of providing insulating spacers on sidewalls of an upper portion of the gate electrode comprises, for example, providing a silicon nitride film on the resultant structure; and anisotropically etching the silicon nitride film.
- a silicon oxide buffer layer may be provided on the resultant structure.
- Doping the epitaxial layer with impurities using the gate electrode and insulating spacers as a mask to form source/drain regions adjacent the source/drain extension regions comprises, for example, doping with impurities of a same conductivity type as that of the source/drain extension regions.
- a silicide film may optionally be formed on the source/drain regions and the gate electrode.
- the silicide film comprises, for example, a cobalt silicide film.
- the source/drain extension regions are formed, for example, to a first depth and the deep source/drain regions are formed to a second depth. In one example, the first depth is less than the second depth.
- the deep source/drain regions and/or the source/drain extension regions may optionally extend into the substrate.
- Trench isolation structures in the substrate may be formed on opposite sides of the deep source/drain regions, for example, according to a shallow trench isolation process.
- the present invention is directed to a MOS transistor having elevated source and drain structures.
- a gate dielectric layer is provided on a substrate.
- a gate electrode is provided on the gate dielectric layer.
- An epitaxial layer is provided adjacent the gate dielectric layer on the substrate.
- First source/drain regions are provided in the epitaxial layer adjacent the gate dielectric layer at lower side portions of the gate electrode.
- the gate dielectric layer extends across a bottom portion and the lower side portions of the gate electrode;
- the first source/drain regions are formed by doping the epitaxial layer with impurities.
- the substrate is formed of a material of a first conductivity type and. wherein the impurities used for doping the epitaxial layer are of a second conductivity type opposite that of the first conductivity type.
- Insulating spacers may be provided on the epitaxial layer at an upper side portion of the gate electrode; and second source/drain regions may be provided adjacent the first source/drain regions opposite the gate electrode .
- the second source/drain regions are formed, for example, by doping exposed surfaces with impurities using the gate electrode and insulating spacers as a mask.
- the first source/drain regions comprise source/drain extension regions and the second source/drain regions comprise deep source/drain regions.
- the first source/drain regions are formed to a first depth in the epitaxial layer and the second source/drain regions are formed to a second depth.
- the first depth is, in one example, less than the second depth.
- the first source/drain regions and/or the second source/drain regions may optionally extend into a portion of the substrate.
- the substrate may be formed of a type selected from the group consisting of: silicon; silicon-on-insulator (SOI); SiGe; SiGe-on-insulator(SGOI); strained silicon; strained silicon-on-insulator; and GaAs.
- the epitaxial layer may comprise silicon.
- the gate dielectric layer and gate electrode extend into a trench formed in an upper portion of the substrate.
- the trench is of a depth that is less than 50 nm.
- a channel region is formed in the substrate under the gate electrode and adjacent the lower side portions of the gate electrode.
- the gate dielectric layer comprises a material selected from the group of materials consisting of: silicon oxide film; silicon oxy-nitride (SiON); tantalum oxide; and a high-dielectric-constant material.
- the gate electrode comprises a material selected from the group of materials consisting of polysilicon film; silicon geranium film; silicide film; metal film; and a laminate film.
- a silicon oxide buffer layer may be provided between the gate electrode and the insulating spacers.
- a silicide film for example comprising a cobalt silicide film, may be formed on the source/drain regions and the gate electrode.
- FIG. 1 is a cross-sectional schematic view of a conventional MOS transistor.
- FIG. 2 is a cross-sectional schematic view of a conventional MOS transistor having elevated source and drain regions.
- FIG. 3 is a cross-sectional schematic view of a MOS transistor having elevated source and drain regions, in accordance with a first embodiment of the present invention.
- FIG. 4 is a cross-sectional schematic view of a MOS transistor having elevated source and drain regions, in accordance with a second embodiment of the present invention.
- FIGS. 5, 6 and 7 are cross-sectional schematic views of MOS transistors having elevated source and drain regions, wherein the source and drain regions and the source and drain extension regions are of various depths, in accordance with the present invention.
- FIGS. 8A and 8B are cross-sectional schematic views of MOS transistor having elevated source and drain regions, in accordance with the first and second embodiments of the present invention formed on an silicon-on-insulator (SOI) substrate.
- SOI silicon-on-insulator
- FIGS. 9A-9L are cross-sectional schematic views of a method for fabricating the MOS transistor of the first embodiment of the present invention.
- FIGS. 10A-10C are cross-sectional schematic views of a method for fabricating the MOS transistor of the second embodiment of the present invention.
- a MOS transistor structure 300 according to the present invention is illustrated in FIG. 3 .
- a gate electrode 314 is formed over a semiconductor substrate 302 to form a gate 310 .
- a gate dielectric 312 for example formed of silicon oxide (SiO 2 ), is formed under the gate electrode 314 and at the lower portions of the sidewalls of the gate electrode 314 .
- An epitaxial layer 305 for example comprising silicon or silicon germanium, is formed on the substrate 302 adjacent opposite sides of the gate 310 .
- An insulative spacer 318 is formed at the upper portions of the sidewalls of the gate 310 .
- a source extension region 306 a and a drain extension region 306 b are formed under the spacers 318 .
- a source 308 a and a drain 308 b are formed on the exposed portions of the source/drain extension regions 306 a / 306 b, i.e. portions of the epitaxial regions that do not lie under the spacers 318 .
- the MOS transistor 300 may further optionally include silicide regions 320 a, 320 b, and 320 c to provide low-resistance electrical contacts for the elevated source/drain 306 a / 306 b and the gate electrode 314 .
- the insulative spacer 318 is comprised, for example, of silicon nitride (SiN).
- an optional silicon oxide layer 316 may be formed as a buffer layer between the SiN spacer 318 and other silicon layers such as the gate electrode 314 and epitaxial layer 305 .
- the gate electrode 414 may optionally be formed in a trench 417 or a recessed portion, of the semiconductor substrate 402 , as shown.
- the gate dielectric 412 is partially formed under, and at the lower portions of, the sidewalls of the gate electrode, for example, on the bottom and side surfaces of the gate trench 417 of the semiconductor substrate 402 and at the sidewalls of the epitaxial layer 405 as shown.
- the trench embodiment of FIG. 4 provides for an effective lengthening of the channel region between the source and drain extension regions 406 a, 406 b.
- the effective channel length of the transistor structure of the present invention can be varied by controlling several factors, including the thickness of the epitaxial layer 305 ( 405 ), the depth of the source/drain extension regions 306 a / 306 b ( 406 a / 406 b ), the depth of the source/drain regions 308 a / 308 b ( 408 a / 408 b ), and the depth of the gate trench 417 .
- the depths of the source/drain regions 308 a / 308 b extend into the semiconductor substrate 302 ( 402 ) as shown.
- the depths of the source/drain extension regions 306 a / 306 b may also extend into the semiconductor substrate 302 ( 402 ) (not shown).
- FIG. 1 In the example of FIG. 1
- the source/drain regions 508 a / 508 b extend to the boundary between the epitaxial layer 505 and the semiconductor substrate 502 , while the source/drain extension regions 506 a / 506 b extend partially through the epitaxial layer 505 .
- the source/drain regions 608 a / 608 b extend to the boundary between the epitaxial layer 605 and the semiconductor substrate 602 , and the source/drain extension regions 606 a / 606 b also extend to the boundary between the epitaxial layer 605 and the semiconductor substrate 602 .
- FIG. 6 the source/drain regions 608 a / 608 b extend to the boundary between the epitaxial layer 605 and the semiconductor substrate 602 .
- the source/drain regions 708 a / 708 b partially extend through the epitaxial layer 705
- the source/drain extension regions 706 a / 706 b also partially extend through the epitaxial layer 705 to a depth that is different than that of the source/drain regions 708 a / 708 b.
- the channel length is controlled primarily by the gate length; however, in the transistor of the present invention, the channel length is not only controlled by the gate length but also controlled according to the thickness of the epitaxial layer, the depth of the source/drain regions, and the depth of the gate trench.
- the impurities in the source/drain extension regions 306 a / 306 b are located in the epitaxial layer 305 , the impurities will not diffuse into the region under the gate 310 , as in the conventional embodiments, even following a heat treatment of the silicon substrate 302 . In this manner, shortening of the channel length relative to the gate length, is prevented.
- the channel length can be variably lengthened to include the lower sidewall of the gate as well as the region located immediately under the gate electrode by controlling the thickness of epitaxial layer 305 , the depth of the source/drain extension regions 306 a / 306 b in the epitaxial layer, or the depth of the gate trench 417 in the semiconductor substrate. In this manner, a channel of sufficient length can be achieved in a transistor structure that includes a minimized gate length.
- the concentration distribution of impurities in the channel region between the source extension region and the drain extension region can be precisely controlled.
- the resulting threshold voltage of a MOS transistor can be accurately predicted, and, accordingly, a semiconductor device having optimal electrical characteristics can be obtained.
- rise in the threshold voltage of the MOS transistor can be restrained, for example, by forming source/drain regions 308 a / 308 d in the epitaxial layer 305 to have lower impurity concentrations, thereby affording compatibility with a decrease in the power supply voltage of the semiconductor device.
- the material of the semiconductor substrate is not limited to silicon, but may comprise any of a number of other semiconductor materials or configurations including silicon-on-insulator (SOI), SiGe, SiGe-on-insulator (SGOI), strained silicon (silicon-on-SiGe), strained silicon-on-insulator, and GaAs.
- SOI silicon-on-insulator
- SGOI SiGe-on-insulator
- strained silicon silicon-on-SiGe
- GaAs GaAs.
- the MOS transistor 800 formed on an SOI substrate 802 includes a gate 810 that is formed in a trench 817 formed in the SOI substrate 802 , as in the embodiment of FIG. 4 .
- the transistor 700 , 800 in accordance with the present invention is fully compatible with SOI fabrication processes. As such, the thickness of the channel impurity region in the transistor can be maintained or decreased dramatically, while increasing the junction depths of the resultant elevated source/drain regions.
- the depth of the source/drain regions becomes shallow, since the thickness of the surface silicon is relatively shallow. As a result, the resulting resistance of the source/drain region increases.
- the present invention alleviates this problem, since the source/drain regions have adequate depth by virtue of the epitaxial layer.
- the gate dielectric 312 , 412 may be formed of silicon oxide film, as stated above, or alternatively, silicon-oxy-nitride (SiON). Alternatively, a film comprising a high-dielectric-constant material such as tantalum oxide may be used.
- the gate dielectric layer may be formed, for example, in a deposition process, or, alternatively, in a thermal oxidation process.
- a silicon germanium film, a silicide film, or a metal film, for example, may be used instead of the polysilicon film.
- a laminate film of the above materials may be used.
- FIGS. 9A-9L A first embodiment of the present invention is shown and described above with reference to FIG. 3 .
- a method of fabricating a semiconductor device according to the first embodiment of the present invention will now be described with reference to FIGS. 9A-9L .
- an element isolation film 304 is formed in a silicon substrate 302 , for example, by a shallow trench isolation method.
- impurities are doped into the silicon substrate 302 , so as to form a well region and a channel impurity region (not shown).
- a silicon oxide film 332 and a silicon nitride film 334 are sequentially formed on the silicon substrate 302 and are subjected to anisotropic etching in order to form a dummy gate electrode 330 .
- an epitaxial layer 305 is selectively grown on the substrate 302 on sides of the dummy gate 330 .
- selective epitaxial growth SEG
- SEG selective epitaxial growth
- the epitaxial layer 305 may optionally be doped at this stage to form the source/drain extension regions, or alternatively, may remain un-doped at this stage.
- doping of the source/drain extension regions follows formation of the gate electrode, as described below with reference to FIG. 9I .
- an optional pad oxide layer (not shown) is provided on the epitaxial layer 305 as a buffer layer, in order to protect the epitaxial layer during implantation of dopants.
- the optional pad oxide layer may be grown by thermal oxidation.
- a silicon nitride film 337 is formed on the entire surface of the resulting structure of FIG. 9B .
- a silicon oxide film 338 is formed, for example, by a CVD method.
- the silicon oxide film 338 is subjected, for example, to a chemical mechanical polishing treatment, or an entire surface etching-back treatment, so as to planarize the surface of the silicon oxide film 338 and to expose the surface of the silicon nitride 334 as shown in FIG. 9D .
- the dummy gate 330 including the silicon nitride film 334 and the silicon oxide film 332 , is removed, exposing a portion of surface of the semiconductor substrate 302 . Since the surface of the semiconductor substrate above the channel region is exposed, the channel impurity region may be optionally formed at this time, rather than forming the channel impurity region during formation of the well region as described above with respect to FIG. 9A . In this manner, the channel impurity region can be formed in the semiconductor substrate in a region that is localized to the area under the region of the now removed dummy gate pattern. This is especially beneficial for the FIG. 4 embodiment, which includes a trench formed in the semiconductor substrate, and a channel region formed under the trench.
- a gate dielectric 312 layer for example of silicon oxide film, is formed on the exposed channel impurity region and the side walls of the epitaxial layer 305 .
- the gate dielectric 312 layer may be formed of silicon oxide using a thermal oxidation process, or, alternatively, a deposition of high-dielectric-constant material such as silicon oxy-nitride (SiON), aluminum oxide, HfO 2 , or tantalum oxide may be used.
- a gate electrode 314 for example of polysilicon film, is deposited on the gate dielectric 312 .
- the gate electrode 314 material may alternatively comprise, for example, a silicon germanium film, a silicide film, a tungsten film, a TiN film, or a metal film, or laminates thereof.
- the polysilicon film is next planarized, for example, by a chemical mechanical polishing treatment or a entire surface etch-back treatment to remove the upper portion of the gate dielectric layer 312 and to expose the silicon oxide film 338 .
- the silicon oxide 338 and silicon nitride 337 layers are removed, for example by a wet etching process, to form a gate structure 310 .
- a pad oxide film 316 for example of silicon oxide material, formed by thermal oxidation or deposition, may optionally be formed on the epitaxial layer 305 as a buffer layer, in order to protect the surface of the epitaxial layer 305 from damage during the implanting process.
- a silicon nitride (SiN) film is provided to cover the substrate, which is then subjected to anisotropic etching, or alternatively a dry etch process, so as to form spacers 318 on the upper sidewalls of the gate 310 .
- the silicon oxide buffer layer 316 between the SiN spacer 318 and the other silicon layers, such as the gate electrode 314 and the epitaxial layer 305 remains following the anisotropic etch.
- impurities having the same conductivity type as the source/drain extension regions 306 a / 306 b are implanted into the epitaxial layer 305 , so as to form a source region 308 a and a drain region 308 b .
- the source/drain extension regions 308 a / 308 b remain under the spacers 318 and the source/drain regions 308 a / 308 b are formed beside the spacers 318 in the epitaxial layer.
- the depth of the source and drain regions 308 a, 308 b is controlled according to the doping process for example, according to the concentration of impurities and the length of time of exposure.
- a cobalt film is formed, for example, by a sputtering method, and then subjected to a heat treatment at a temperature ranging between 500° C. and 1000° C. in a nitrogen atmosphere or an argon atmosphere, so as to allow the cobalt film to react with the silicon in the epitaxial layer 305 and the gate 310 , thereby to form cobalt silicide films 320 a, 320 b, and 320 c in a self-aligned manner on exposed surfaces of the source/drain regions 308 a / 308 b and the gate electrode 314 , respectively. Unreacted cobalt film is then removed using conventional means.
- the silicide films may comprise other suitable materials, including Co, Ni, W, Ti, and combinations thereof.
- the source/drain extension regions 306 a / 306 b may be formed at the step shown in FIG. 9B , using the dummy gate pattern 330 as a mask. However, this approach requires additional steps.
- FIG. 4 A second embodiment of the invention is shown and described above with reference to FIG. 4 .
- the gate electrode 414 is formed in a trench or a recessed portion 417 of the semiconductor substrate 402 .
- Other components of the transistor configuration of the second embodiment are similar to those of the first configuration above, and therefore their description will be omitted here.
- Components of FIG. 4 having a reference numeral beginning with the prefix “4” and a unique suffix “4xx” share the same purpose as those components of FIG. 3 , described above, having the same suffix “3xx”.
- FIGS. 10A-10C A method of fabricating a semiconductor device according to the second embodiment of the present invention will now be described with reference to FIGS. 10A-10C .
- the dummy gate including the silicon nitride film and the silicon oxide film, is removed, exposing a portion of surface of the semiconductor substrate 302 .
- the exposed surface of the semiconductor substrate is further subjected to etching in order to form a trench 417 or recessed region.
- the depth of the trench 417 is determined according to the desired channel length of the resulting device; the deeper the trench 417 , the longer the effective channel length. In general, the depth of the trench 417 is less than 50 nm.
- the channel impurity region may be optionally formed at this time, rather than forming the channel impurity region during formation of the well region as described above with respect to FIG. 9A .
- the channel impurity region can be formed in the semiconductor substrate in a region that is localized to the area under the region of the now removed dummy gate pattern. This is especially beneficial for the present embodiment, which includes a trench formed in the semiconductor substrate, and a channel region formed under the trench, since the channel region is not fully defined until the trench is formed.
- a gate dielectric 412 layer for example of silicon oxide film, is formed on the exposed channel impurity region, the side walls of the trench 417 , and the side walls of the epitaxial layer 405 .
- the gate dielectric 412 layer may be formed of silicon oxide using a thermal oxidation process, or, alternatively, a deposition of high-dielectric-constant material such as silicon oxy-nitride (SiON), aluminum oxide, HfO 2 , or tantalum oxide may be used.
- a gate electrode 414 for example of polysilicon film, is deposited on the gate dielectric layer 412 .
- the gate electrode 414 material may alternatively comprise, for example, a silicon germanium film, a silicide film, a tungsten film, a TiN film, or a metal film, or laminates thereof.
- the polysilicon film is next planarized, for example, by a chemical mechanical polishing treatment or a entire surface etch-back treatment to remove the upper portion of the gate dielectric layer 412 and to expose the silicon oxide film 438 .
- the performance characteristics of the resulting transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and the optional trench.
- the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
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Abstract
A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
Description
- This application is a divisional of U.S. application Ser. No. 10/697,826, filed on Oct. 30, 2003, which relies for priority upon Korean Patent Application No. 03-12793, filed on Feb. 28, 2003, the contents of which are herein incorporated by reference in their entirety.
- the semiconductor industry, minimization of the feature size of MOS transistors in integrated circuits is a common goal. This goal is essentially driven by the need to produce integrated circuits at ever-lower costs, while improving circuit functionality and speed. Such downscaling can be achieved by reducing the characteristic dimensions of the transistors, i.e. reducing the gate lengths, the gate oxide thickness, and the junction depths, and by increasing the channel doping levels. However, scaled-down MOS transistors generally suffer from a phenomenon referred to as the “short-channel effect”. The short-channel effect has an adverse impact on the switching performance of the transistors, because such switching is inefficiently controlled by the gate electrode, which leads to an undesired decrease in the threshold voltage. Mechanically, the depletion regions around the source and the drain occupy an increasingly large fraction of the channel region, so that a lower potential on the gate is needed to achieve inversion in the channel.
- Referring to the
FIG. 1 , a conventional scaled-down MOS transistor 100, which is fabricated within asemiconductor substrate 102, includes asource extension region 106 a and adrain extension region 106 b. Thesource extension region 106 a and thedrain extension region 106 b have shallow junctions in order to minimize the short-channel effect that occurs in MOS transistors having sub-micron or nanometer dimensions. TheMOS transistor 100 further includes asource region 108 a and adrain region 108 b that have deeper junctions, relative to thesource extension region 106 a and thedrain extension region 106 b, to provide lower resistance. TheMOS transistor 100 also includes agate structure 110, which is comprised of a gate dielectric 112 and agate electrode 114. Aninsulative spacer 118, which is typically comprised of silicon nitride (SiN), is disposed on the sidewalls of thegate structure 110. TheMOS transistor 100 further includessilicide regions drain 106 a/106 b and thegate electrode 114. The MOS transistor is electrically isolated from other devices by shallowtrench isolation structures 104. - A problem lies in that impurities in the source/
drain extension regions 106 a/106 b tend to diffuse to the region immediately under thegate 110. The portions of the source/drain extension regions 106 a/106 b formed immediately under thegate 110 have a higher electric resistance relative to the portions of theextension regions 106 a/106 b located immediately under thesidewall spacers 118. For this reason, thetransistor 100 has effective resistances R that are connected in series to the source and the drain. This inhibits the flow of electric current, thus decreasing operation speed. - A second problem concerns the rise of channel dopant concentration, which in turn causes a rise in threshold voltage in the field effect transistor. In order to meet miniaturization requirements in MOS transistors, the impurity concentration of the channel impurity region is necessarily raised. At the same time, contemporary semiconductor devices are designed to operate with a lower power supply voltage, such as ranging from 5V to 3.3V. For operation with such a low power supply voltage, the threshold voltage of the field effect transistor needs to be lower. For this reason, any rise in the threshold voltage of MOS transistor due to the rise in channel dopant concentration is undesirable. On the other hand, a channel doping level that is too high in scaled-down devices gives rise to superfluous leakage current and junction breakdown.
- In an attempt to overcome the stated disadvantages, elevated source and drain structures have been suggested. Referring to
FIG. 2 , agate structure 210 comprised of a gate dielectric 212 and agate electrode 214 is formed on the surface of thesemiconductor substrate 202. Asource extension region 206 a and adrain extension region 206 b are then formed in the semiconductor substrate. Aspacer 218, typically comprised of silicon nitride (SiN), is formed on the sidewalls of thegate structure 210. An epitaxial layer 205, typically comprised of silicon, is grown on the exposed portions of the source/drain extension regions 206 a/206 b, typically using selective epitaxial growth. Following the growth of the epitaxial layer 205, dopants are implanted and activated to form anelevated source 208 a and an elevateddrain 208 b. TheMOS transistor 200 further includessilicide regions drain regions 208 a/208 b and thegate electrode 214. - A MOS transistor having an elevated source/drain produced according to the structure of
FIG. 2 is effective for reducing the resistance of the source and drain regions by increasing the thickness and the doping level by elevating the source/drain regions 208 a/208 b. However, it is inevitable that the dopants of the source/drain extension regions 206 a/206 b diffuse into the region immediately under thegate 210, which result in junction leakage current through the source/drain extension regions 206 a/206 b. - The present invention is directed to a MOS transistor having elevated source and drain structures, and a method of formation thereof, that overcomes the limitations of the conventional embodiments. In particular, the present invention provides for a transistor that includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region.
- The performance characteristics of the transistor of the present invention can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
- In one aspect, the present invention is directed to a method for forming a MOS transistor having elevated source and drain structures. A sacrificial gate pattern is provided on a substrate. An epitaxial layer is provided on the substrate adjacent the sacrificial gate pattern. A silicon nitride film and a silicon oxide film are provided on the epitaxial layer adjacent the sacrificial gate pattern. The sacrificial gate pattern is removed to expose a portion of the substrate and wall portions of the epitaxial layer. A gate dielectric layer is provided on the exposed portion of the substrate and along the wall portions of the epitaxial layer. A gate electrode is provided on the gate dielectric layer. The silicon oxide film and silicon nitride film are removed. The epitaxial layer is doped with impurities using the gate electrode as a mask to form source/drain extension regions in the epitaxial layer proximal to the gate dielectric layer. Insulating spacers are provided on sidewalls of an upper portion of the gate electrode. The epitaxial layer is doped with impurities using the gate electrode and insulating spacers as a mask to form deep source/drain regions adjacent the source/drain extension regions.
- In one embodiment, the source/drain extension regions are formed by doping the epitaxial layer with impurities prior to providing the silicon nitride film and silicon oxide film on the epitaxial layer. Providing the sacrificial gate pattern may comprise sequentially forming a silicon oxide film and a silicon nitride film and patterning the sequentially formed films to form the sacrificial gate pattern.
- The substrate is, for example, of a type selected from the group consisting of: silicon; silicon-on-insulator (SOI); SiGe; SiGe-on-insulator(SGOI); strained silicon; strained silicon-on-insulator; and GaAs. The substrate is optionally formed of a material of a first conductivity type and the impurities used for doping the epitaxial layer are of a second conductivity type opposite that of the first conductivity type. A pad oxide layer may be formed on the epitaxial layer.
- The step of providing a silicon nitride film and a silicon oxide film on the epitaxial layer adjacent the sacrificial gate pattern may comprise: sequentially providing a silicon nitride film and a silicon oxide film on the epitaxial layer and the sacrificial gate pattern; and planarizing the silicon nitride film, silicon oxide film and sacrificial gate pattern to expose an upper surface of the sacrificial gate pattern. The silicon oxide film is provided, for example, by a chemical vapor deposition (CVD) process. The step of planarizing comprises, for example, planarizing by a chemical-mechanical polishing process (CMP) or an etch-back treatment.
- Removal of the sacrificial gate pattern comprises etching the sacrificial gate pattern to expose an upper surface of the substrate, or, optionally, forming a recess in the substrate, in which case the gate dielectric layer is formed on bottom and side walls of the recess of the substrate. The recess is preferably of a depth that is less than 50 nm.
- The exposed portion of the substrate may be doped with impurities to form a channel region following removal of the sacrificial gate pattern, or, optionally, prior to providing the sacrificial gate pattern on the substrate, the channel region corresponding to an area of the substrate covered by the sacrificial gate pattern.
- The gate dielectric layer preferably comprises a material selected from the group of materials consisting of: silicon oxide film; silicon oxy-nitride (SiON); tantalum oxide; and a high-dielectric-constant material.
- The step of providing the gate electrode comprises, for example, forming a gate electrode material film on the gate dielectric layer and the silicon oxide film; and planarizing the gate electrode material film and silicon oxide film. Planarizing comprises, for example, planarizing by a chemical-mechanical polishing process (CMP) or an etch-back treatment.
- The gate electrode comprises a material selected from the group of materials consisting of polysilicon film; silicon geranium film; silicide film; metal film; and a laminate film. The step of removing the silicon oxide film and silicon nitride film comprises removing using a wet etching process.
- The step of providing insulating spacers on sidewalls of an upper portion of the gate electrode comprises, for example, providing a silicon nitride film on the resultant structure; and anisotropically etching the silicon nitride film. Prior to providing the silicon nitride film, a silicon oxide buffer layer may be provided on the resultant structure.
- Doping the epitaxial layer with impurities using the gate electrode and insulating spacers as a mask to form source/drain regions adjacent the source/drain extension regions comprises, for example, doping with impurities of a same conductivity type as that of the source/drain extension regions.
- A silicide film may optionally be formed on the source/drain regions and the gate electrode. The silicide film comprises, for example, a cobalt silicide film.
- The source/drain extension regions are formed, for example, to a first depth and the deep source/drain regions are formed to a second depth. In one example, the first depth is less than the second depth. The deep source/drain regions and/or the source/drain extension regions may optionally extend into the substrate.
- Trench isolation structures in the substrate may be formed on opposite sides of the deep source/drain regions, for example, according to a shallow trench isolation process.
- In another aspect, the present invention is directed to a MOS transistor having elevated source and drain structures. A gate dielectric layer is provided on a substrate. A gate electrode is provided on the gate dielectric layer. An epitaxial layer is provided adjacent the gate dielectric layer on the substrate. First source/drain regions are provided in the epitaxial layer adjacent the gate dielectric layer at lower side portions of the gate electrode.
- In one example, the gate dielectric layer extends across a bottom portion and the lower side portions of the gate electrode; The first source/drain regions are formed by doping the epitaxial layer with impurities. The substrate is formed of a material of a first conductivity type and. wherein the impurities used for doping the epitaxial layer are of a second conductivity type opposite that of the first conductivity type.
- Insulating spacers may be provided on the epitaxial layer at an upper side portion of the gate electrode; and second source/drain regions may be provided adjacent the first source/drain regions opposite the gate electrode . In this case, the second source/drain regions are formed, for example, by doping exposed surfaces with impurities using the gate electrode and insulating spacers as a mask. The first source/drain regions comprise source/drain extension regions and the second source/drain regions comprise deep source/drain regions. The first source/drain regions are formed to a first depth in the epitaxial layer and the second source/drain regions are formed to a second depth. The first depth is, in one example, less than the second depth. The first source/drain regions and/or the second source/drain regions may optionally extend into a portion of the substrate.
- The substrate may be formed of a type selected from the group consisting of: silicon; silicon-on-insulator (SOI); SiGe; SiGe-on-insulator(SGOI); strained silicon; strained silicon-on-insulator; and GaAs. The epitaxial layer may comprise silicon.
- The gate dielectric layer and gate electrode extend into a trench formed in an upper portion of the substrate. In one example, the trench is of a depth that is less than 50 nm.
- A channel region is formed in the substrate under the gate electrode and adjacent the lower side portions of the gate electrode.
- The gate dielectric layer comprises a material selected from the group of materials consisting of: silicon oxide film; silicon oxy-nitride (SiON); tantalum oxide; and a high-dielectric-constant material. The gate electrode comprises a material selected from the group of materials consisting of polysilicon film; silicon geranium film; silicide film; metal film; and a laminate film. A silicon oxide buffer layer may be provided between the gate electrode and the insulating spacers. A silicide film, for example comprising a cobalt silicide film, may be formed on the source/drain regions and the gate electrode.
- The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
-
FIG. 1 is a cross-sectional schematic view of a conventional MOS transistor. -
FIG. 2 is a cross-sectional schematic view of a conventional MOS transistor having elevated source and drain regions. -
FIG. 3 is a cross-sectional schematic view of a MOS transistor having elevated source and drain regions, in accordance with a first embodiment of the present invention. -
FIG. 4 is a cross-sectional schematic view of a MOS transistor having elevated source and drain regions, in accordance with a second embodiment of the present invention. -
FIGS. 5, 6 and 7 are cross-sectional schematic views of MOS transistors having elevated source and drain regions, wherein the source and drain regions and the source and drain extension regions are of various depths, in accordance with the present invention. -
FIGS. 8A and 8B are cross-sectional schematic views of MOS transistor having elevated source and drain regions, in accordance with the first and second embodiments of the present invention formed on an silicon-on-insulator (SOI) substrate. -
FIGS. 9A-9L are cross-sectional schematic views of a method for fabricating the MOS transistor of the first embodiment of the present invention. -
FIGS. 10A-10C are cross-sectional schematic views of a method for fabricating the MOS transistor of the second embodiment of the present invention. - A
MOS transistor structure 300 according to the present invention is illustrated inFIG. 3 . Agate electrode 314 is formed over asemiconductor substrate 302 to form agate 310. Agate dielectric 312, for example formed of silicon oxide (SiO2), is formed under thegate electrode 314 and at the lower portions of the sidewalls of thegate electrode 314. Anepitaxial layer 305, for example comprising silicon or silicon germanium, is formed on thesubstrate 302 adjacent opposite sides of thegate 310. Aninsulative spacer 318, is formed at the upper portions of the sidewalls of thegate 310. In theepitaxial layer 305, asource extension region 306 a and adrain extension region 306 b are formed under thespacers 318. Asource 308 a and adrain 308 b are formed on the exposed portions of the source/drain extension regions 306 a/306 b, i.e. portions of the epitaxial regions that do not lie under thespacers 318. TheMOS transistor 300 may further optionally includesilicide regions drain 306 a/306 b and thegate electrode 314. - The
insulative spacer 318 is comprised, for example, of silicon nitride (SiN). In addition, an optionalsilicon oxide layer 316 may be formed as a buffer layer between theSiN spacer 318 and other silicon layers such as thegate electrode 314 andepitaxial layer 305. - With reference to
FIG. 4 , thegate electrode 414 may optionally be formed in atrench 417 or a recessed portion, of thesemiconductor substrate 402, as shown. In this case, thegate dielectric 412 is partially formed under, and at the lower portions of, the sidewalls of the gate electrode, for example, on the bottom and side surfaces of thegate trench 417 of thesemiconductor substrate 402 and at the sidewalls of theepitaxial layer 405 as shown. The trench embodiment ofFIG. 4 provides for an effective lengthening of the channel region between the source anddrain extension regions - The effective channel length of the transistor structure of the present invention can be varied by controlling several factors, including the thickness of the epitaxial layer 305 (405), the depth of the source/
drain extension regions 306 a/306 b (406 a/406 b), the depth of the source/drain regions 308 a/308 b (408 a/408 b), and the depth of thegate trench 417. - In the exemplary embodiments of
FIGS. 3 and 4 , the depths of the source/drain regions 308 a/308 b (408 a/408 b) extend into the semiconductor substrate 302 (402) as shown. Optionally, the depths of the source/drain extension regions 306 a/306 b (406 a/406 b) may also extend into the semiconductor substrate 302 (402) (not shown). In the example ofFIG. 5 , the source/drain regions 508 a/508 b extend to the boundary between theepitaxial layer 505 and thesemiconductor substrate 502, while the source/drain extension regions 506 a/506 b extend partially through theepitaxial layer 505. In the example ofFIG. 6 , the source/drain regions 608 a/608 b extend to the boundary between theepitaxial layer 605 and thesemiconductor substrate 602, and the source/drain extension regions 606 a/606 b also extend to the boundary between theepitaxial layer 605 and thesemiconductor substrate 602. In the example ofFIG. 7 , the source/drain regions 708 a/708 b partially extend through theepitaxial layer 705, and the source/drain extension regions 706 a/706 b also partially extend through theepitaxial layer 705 to a depth that is different than that of the source/drain regions 708 a/708 b. - By controlling the channel length, various device characteristics can be achieved , and the short-channel effect can be prevented, despite the need for down-scaling of device size. In a conventional transistor, the channel length is controlled primarily by the gate length; however, in the transistor of the present invention, the channel length is not only controlled by the gate length but also controlled according to the thickness of the epitaxial layer, the depth of the source/drain regions, and the depth of the gate trench.
- According to the present invention, with reference to
FIG. 3 , since the impurities in the source/drain extension regions 306 a/306 b are located in theepitaxial layer 305, the impurities will not diffuse into the region under thegate 310, as in the conventional embodiments, even following a heat treatment of thesilicon substrate 302. In this manner, shortening of the channel length relative to the gate length, is prevented. Furthermore, the channel length can be variably lengthened to include the lower sidewall of the gate as well as the region located immediately under the gate electrode by controlling the thickness ofepitaxial layer 305, the depth of the source/drain extension regions 306 a/306 b in the epitaxial layer, or the depth of thegate trench 417 in the semiconductor substrate. In this manner, a channel of sufficient length can be achieved in a transistor structure that includes a minimized gate length. - According to the present invention, the concentration distribution of impurities in the channel region between the source extension region and the drain extension region can be precisely controlled. As a result, the resulting threshold voltage of a MOS transistor can be accurately predicted, and, accordingly, a semiconductor device having optimal electrical characteristics can be obtained.
- Rise in the threshold voltage of the MOS transistor can be restrained, for example, by forming source/
drain regions 308 a/308 d in theepitaxial layer 305 to have lower impurity concentrations, thereby affording compatibility with a decrease in the power supply voltage of the semiconductor device. - The material of the semiconductor substrate is not limited to silicon, but may comprise any of a number of other semiconductor materials or configurations including silicon-on-insulator (SOI), SiGe, SiGe-on-insulator (SGOI), strained silicon (silicon-on-SiGe), strained silicon-on-insulator, and GaAs. A cross-sectional schematic view of an embodiment of the present invention, where a MOS transistor is formed on an
SOI substrate 702, is shown inFIGS. 8A and 8B . In theFIG. 8A embodiment, theMOS transistor 700 formed on anSOI substrate 702 includes a gate 710 that is formed on theSOI substrate 702, as in the embodiment ofFIG. 3 . In theFIG. 8B embodiment, theMOS transistor 800 formed on anSOI substrate 802 includes agate 810 that is formed in atrench 817 formed in theSOI substrate 802, as in the embodiment ofFIG. 4 . In this manner, thetransistor - In an SOI device, the depth of the source/drain regions becomes shallow, since the thickness of the surface silicon is relatively shallow. As a result, the resulting resistance of the source/drain region increases. The present invention alleviates this problem, since the source/drain regions have adequate depth by virtue of the epitaxial layer.
- The
gate dielectric - A first embodiment of the present invention is shown and described above with reference to
FIG. 3 . A method of fabricating a semiconductor device according to the first embodiment of the present invention will now be described with reference toFIGS. 9A-9L . - Initially, referring to
FIG. 9A , anelement isolation film 304 is formed in asilicon substrate 302, for example, by a shallow trench isolation method. Next, impurities are doped into thesilicon substrate 302, so as to form a well region and a channel impurity region (not shown). Next, asilicon oxide film 332 and asilicon nitride film 334 are sequentially formed on thesilicon substrate 302 and are subjected to anisotropic etching in order to form adummy gate electrode 330. - Next, referring to
FIG. 9B , anepitaxial layer 305 is selectively grown on thesubstrate 302 on sides of thedummy gate 330. For example selective epitaxial growth (SEG) may be used to form theepitaxial layer 305 such that it is formed on the surface of the silicon substrate and not on thesilicon nitride 334 layer or oxidetrench isolation elements 304. Theepitaxial layer 305 may optionally be doped at this stage to form the source/drain extension regions, or alternatively, may remain un-doped at this stage. In a preferred embodiment, doping of the source/drain extension regions follows formation of the gate electrode, as described below with reference toFIG. 9I . If the epitaxial layer is doped at this stage, an optional pad oxide layer (not shown) is provided on theepitaxial layer 305 as a buffer layer, in order to protect the epitaxial layer during implantation of dopants. The optional pad oxide layer may be grown by thermal oxidation. - As shown in
FIG. 9C , asilicon nitride film 337 is formed on the entire surface of the resulting structure ofFIG. 9B . Next, asilicon oxide film 338 is formed, for example, by a CVD method. Next, thesilicon oxide film 338 is subjected, for example, to a chemical mechanical polishing treatment, or an entire surface etching-back treatment, so as to planarize the surface of thesilicon oxide film 338 and to expose the surface of thesilicon nitride 334 as shown inFIG. 9D . - Referring to
FIG. 9E , thedummy gate 330, including thesilicon nitride film 334 and thesilicon oxide film 332, is removed, exposing a portion of surface of thesemiconductor substrate 302. Since the surface of the semiconductor substrate above the channel region is exposed, the channel impurity region may be optionally formed at this time, rather than forming the channel impurity region during formation of the well region as described above with respect toFIG. 9A . In this manner, the channel impurity region can be formed in the semiconductor substrate in a region that is localized to the area under the region of the now removed dummy gate pattern. This is especially beneficial for theFIG. 4 embodiment, which includes a trench formed in the semiconductor substrate, and a channel region formed under the trench. - Referring to
FIG. 9F , agate dielectric 312 layer, for example of silicon oxide film, is formed on the exposed channel impurity region and the side walls of theepitaxial layer 305. Thegate dielectric 312 layer may be formed of silicon oxide using a thermal oxidation process, or, alternatively, a deposition of high-dielectric-constant material such as silicon oxy-nitride (SiON), aluminum oxide, HfO2, or tantalum oxide may be used. Next, agate electrode 314, for example of polysilicon film, is deposited on thegate dielectric 312. Thegate electrode 314 material may alternatively comprise, for example, a silicon germanium film, a silicide film, a tungsten film, a TiN film, or a metal film, or laminates thereof. With reference toFIG. 9G , the polysilicon film is next planarized, for example, by a chemical mechanical polishing treatment or a entire surface etch-back treatment to remove the upper portion of thegate dielectric layer 312 and to expose thesilicon oxide film 338. Next, with reference toFIG. 9H , thesilicon oxide 338 andsilicon nitride 337 layers are removed, for example by a wet etching process, to form agate structure 310. - Next, as shown in
FIG. 9I , impurities having an opposite conductivity type to that of the silicon substrate are implanted into theepitaxial layer 305 so as to form respective source extension anddrain extension regions pad oxide film 316, for example of silicon oxide material, formed by thermal oxidation or deposition, may optionally be formed on theepitaxial layer 305 as a buffer layer, in order to protect the surface of theepitaxial layer 305 from damage during the implanting process. - Referring to
FIG. 9J , a silicon nitride (SiN) film is provided to cover the substrate, which is then subjected to anisotropic etching, or alternatively a dry etch process, so as to form spacers 318 on the upper sidewalls of thegate 310. The siliconoxide buffer layer 316 between theSiN spacer 318 and the other silicon layers, such as thegate electrode 314 and theepitaxial layer 305, remains following the anisotropic etch. - Referring to
FIG. 9K , using thegate 310 and thespacers 318 as a mask, impurities having the same conductivity type as the source/drain extension regions 306 a/306 b are implanted into theepitaxial layer 305, so as to form asource region 308 a and adrain region 308 b. At this time, the source/drain extension regions 308 a/308 b remain under thespacers 318 and the source/drain regions 308 a/308 b are formed beside thespacers 318 in the epitaxial layer. The depth of the source and drainregions - Referring to
FIG. 9L , a cobalt film is formed, for example, by a sputtering method, and then subjected to a heat treatment at a temperature ranging between 500° C. and 1000° C. in a nitrogen atmosphere or an argon atmosphere, so as to allow the cobalt film to react with the silicon in theepitaxial layer 305 and thegate 310, thereby to formcobalt silicide films drain regions 308 a/308 b and thegate electrode 314, respectively. Unreacted cobalt film is then removed using conventional means. Alternatively, the silicide films may comprise other suitable materials, including Co, Ni, W, Ti, and combinations thereof. - In this manner, by deferring formation of the source/
drain extension regions 306 a/306 b until after thegate electrode 314 is formed, fewer steps are required for fabrication of the transistor structure of the present invention. Alternatively, as stated above, the source/drain extension regions 306 a/306 b may be formed at the step shown inFIG. 9B , using thedummy gate pattern 330 as a mask. However, this approach requires additional steps. - A second embodiment of the invention is shown and described above with reference to
FIG. 4 . In the second embodiment, thegate electrode 414 is formed in a trench or a recessedportion 417 of thesemiconductor substrate 402. Other components of the transistor configuration of the second embodiment are similar to those of the first configuration above, and therefore their description will be omitted here. Components ofFIG. 4 having a reference numeral beginning with the prefix “4” and a unique suffix “4xx” share the same purpose as those components ofFIG. 3 , described above, having the same suffix “3xx”. - A method of fabricating a semiconductor device according to the second embodiment of the present invention will now be described with reference to
FIGS. 10A-10C . - The processes preceding the step shown at
FIG. 10A are identical to those shown inFIGS. 9A-9D above with reference to the first embodiment. - Referring to
FIG. 10A , the dummy gate, including the silicon nitride film and the silicon oxide film, is removed, exposing a portion of surface of thesemiconductor substrate 302. The exposed surface of the semiconductor substrate is further subjected to etching in order to form atrench 417 or recessed region. The depth of thetrench 417 is determined according to the desired channel length of the resulting device; the deeper thetrench 417, the longer the effective channel length. In general, the depth of thetrench 417 is less than 50 nm. - As explained above, since the surface of the semiconductor substrate above the channel region is exposed, the channel impurity region may be optionally formed at this time, rather than forming the channel impurity region during formation of the well region as described above with respect to
FIG. 9A . In this manner, the channel impurity region can be formed in the semiconductor substrate in a region that is localized to the area under the region of the now removed dummy gate pattern. This is especially beneficial for the present embodiment, which includes a trench formed in the semiconductor substrate, and a channel region formed under the trench, since the channel region is not fully defined until the trench is formed. - Referring to
FIG. 10B , agate dielectric 412 layer, for example of silicon oxide film, is formed on the exposed channel impurity region, the side walls of thetrench 417, and the side walls of theepitaxial layer 405. As described above, thegate dielectric 412 layer may be formed of silicon oxide using a thermal oxidation process, or, alternatively, a deposition of high-dielectric-constant material such as silicon oxy-nitride (SiON), aluminum oxide, HfO2, or tantalum oxide may be used. Next, agate electrode 414, for example of polysilicon film, is deposited on thegate dielectric layer 412. Thegate electrode 414 material may alternatively comprise, for example, a silicon germanium film, a silicide film, a tungsten film, a TiN film, or a metal film, or laminates thereof. With reference toFIG. 10C , the polysilicon film is next planarized, for example, by a chemical mechanical polishing treatment or a entire surface etch-back treatment to remove the upper portion of thegate dielectric layer 412 and to expose thesilicon oxide film 438. - Thereafter, the processes are identical to those shown in reference to
FIG. 9H toFIG. 9L explained in the first embodiment. - The performance characteristics of the resulting transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and the optional trench. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.
- While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (22)
1. A MOS transistor having elevated source and drain structures, comprising:
a gate dielectric layer on a substrate;
a gate electrode on the gate dielectric layer, wherein the gate dielectric layer includes a horizontal portion that extends across a bottom portion of the gate electrode and side portions that extend in a vertical direction along lower side portions of the gate electrode;
an epitaxial layer contacting the side portions of the gate dielectric layer on the substrate and extending from a point of contact with the side portions of the gate dielectric layer substantially parallel to the substrate in a horizontal direction; and
first source/drain regions in the epitaxial layer contacting the side portions of the gate dielectric layer at the lower side portions of the gate electrode.
2. The transistor of claim 1 , further comprising insulating sidewall spacers on the epitaxial layer at upper side portions of the gate electrode.
3. The transistor of claim 2 , further comprising second source/drain regions adjacent the first source/drain regions opposite the gate electrode.
4. The transistor of claim 3 , wherein the second source/drain regions are formed by doping exposed surfaces with impurities using the gate electrode and the insulating sidewall spacers as masks.
5. The transistor of claim 3 , wherein the first source/drain regions comprise source/drain extension regions and wherein the second source/drain regions comprise deep source/drain regions.
6. The transistor of claim 3 , wherein depths of the first source/drain regions are less than depths of the second source/drain regions.
7. The transistor of claim 3 , wherein the second source/drain regions extend into portions of the substrate.
8. The transistor of claim 3 , wherein the first source/drain regions extend into portions of the substrate.
9. The transistor of claim 2 , further comprising a silicon oxide buffer layer between the gate electrode and the insulating sidewall spacers.
10. The transistor of claim 1 , wherein the first source/drain regions are formed by doping the epitaxial layer with impurities.
11. The transistor of claim 1 , wherein the substrate is formed using one selected from the group consisting of: silicon, silicon-on-insulator (SOI), SiGe, SiGe-on-insulator (SGOI), strained silicon, strained silicon-on-insulator, and GaAs.
12. The transistor of claim 1 , wherein the epitaxial layer comprises silicon or silicon germanium.
13. The transistor of claim 1 , wherein the gate dielectric layer and the gate electrode extend into a trench formed in an upper portion of the substrate.
14. The transistor of claim 13 , wherein the trench is of a depth that is less than about 50 nm.
15. The transistor of claim 1 , further comprising a channel region in the substrate under the gate electrode and adjacent the lower side portions of the gate electrode.
16. The transistor of claim 1 , wherein the gate dielectric layer comprises a material selected from the group consisting of: silicon oxide, silicon oxy-nitride (SiON), tantalum oxide, and a high-dielectric-constant material.
17. The transistor of claim 1 , wherein the gate dielectric layer is formed using a deposition process or a thermal oxidation process.
18. The transistor of claim 1 wherein the gate electrode comprises a film selected from the group consisting of a polysilicon film, a silicon geranium film, a silicide film, a metal film, and a laminate film.
19. The transistor of claim 1 , further comprising a silicide film on the first source/drain regions and the gate electrode.
20. The transistor of claim 19 , wherein the silicide film comprises a material selected from the group consisting of Co, Ni, W, Ti and combinations thereof.
21. The transistor of claim 1 , wherein the gate dielectric layer and the gate electrode are formed following formation of the epitaxial layer.
22. The transistor of claim 1 , wherein the gate dielectric layer and the gate electrode are formed in an opening between neighboring portions of the epitaxial layer, the opening exposing the substrate.
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US11/726,161 US20070164354A1 (en) | 2003-02-28 | 2007-03-21 | MOS transistor with elevated source and drain structures and method of fabrication thereof |
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KR10-2003-0012793A KR100499159B1 (en) | 2003-02-28 | 2003-02-28 | Semiconductor device having a recessed channel and method of manufacturing the same |
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US10/697,826 US7227224B2 (en) | 2003-02-28 | 2003-10-30 | MOS transistor with elevated source and drain structures and method of fabrication thereof |
US11/726,161 US20070164354A1 (en) | 2003-02-28 | 2007-03-21 | MOS transistor with elevated source and drain structures and method of fabrication thereof |
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JP2004266278A (en) | 2004-09-24 |
KR20040077289A (en) | 2004-09-04 |
TW200416964A (en) | 2004-09-01 |
US20070166926A1 (en) | 2007-07-19 |
DE102004005502A1 (en) | 2004-09-16 |
US7227224B2 (en) | 2007-06-05 |
US20070164373A1 (en) | 2007-07-19 |
DE102004064122B4 (en) | 2010-08-05 |
US7569456B2 (en) | 2009-08-04 |
US20040169221A1 (en) | 2004-09-02 |
JP4744812B2 (en) | 2011-08-10 |
CN1525542A (en) | 2004-09-01 |
KR100499159B1 (en) | 2005-07-01 |
TWI272699B (en) | 2007-02-01 |
CN100474534C (en) | 2009-04-01 |
DE102004005502B4 (en) | 2008-04-17 |
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