US20070117384A1 - Chemical vapor deposition metallization processes and chemical vapor deposition apparatus used therein - Google Patents
Chemical vapor deposition metallization processes and chemical vapor deposition apparatus used therein Download PDFInfo
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- US20070117384A1 US20070117384A1 US11/624,645 US62464507A US2007117384A1 US 20070117384 A1 US20070117384 A1 US 20070117384A1 US 62464507 A US62464507 A US 62464507A US 2007117384 A1 US2007117384 A1 US 2007117384A1
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- 238000000034 method Methods 0.000 title claims abstract description 95
- 230000008569 process Effects 0.000 title claims abstract description 86
- 238000005229 chemical vapour deposition Methods 0.000 title claims description 72
- 238000001465 metallisation Methods 0.000 title abstract description 8
- 238000001816 cooling Methods 0.000 claims abstract description 37
- 238000012546 transfer Methods 0.000 claims abstract description 30
- 239000007789 gas Substances 0.000 claims description 35
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 13
- 239000000112 cooling gas Substances 0.000 claims description 12
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 9
- 239000002826 coolant Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 79
- 239000002184 metal Substances 0.000 abstract description 79
- 239000004065 semiconductor Substances 0.000 abstract description 51
- 239000000758 substrate Substances 0.000 abstract description 50
- 230000004888 barrier function Effects 0.000 abstract description 30
- 238000011065 in-situ storage Methods 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 115
- 239000012535 impurity Substances 0.000 description 24
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 239000012298 atmosphere Substances 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 239000006117 anti-reflective coating Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- 229910052734 helium Inorganic materials 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 125000001309 chloro group Chemical group Cl* 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Definitions
- the present invention relates to fabrication processes of semiconductor devices and fabrication equipment used therein and, more particularly, to metallization processes and chemical vapor deposition apparatus used therein, and more particularly, to in situ metallization processes and chemical vapor deposition apparatus used therein.
- Metal lines are necessarily used in fabrication of semiconductor devices.
- the formation of the metal lines includes forming a metal layer on a semiconductor substrate and patterning the metal layer using photolithography/etch processes. During the photolithography process, an irregular reflection may occur on the surface of the metal layer. The irregular reflection is due to the surface roughness of the metal layer. Accordingly, an anti-reflective coating layer is widely used in order to suppress the irregular reflection.
- a method of forming the metal layer and the anti-reflective coating layer is taught in U.S. Pat. No. 6,187,667 B1 to Shan et al., entitled “Method of Forming Metal Layer and/or Antireflective Coating Layer On An Integrated Circuit.” According to Shan et al., the metal layer is cooled prior to formation of the anti-reflective coating layer on the metal layer. Thus, it can prevent protrusions such as bumps from being produced on the surface of the metal layer during the formation of the anti-reflective coating layer.
- metal atoms in the metal layer may be diffused into the impurity region. In this case, junction leakage current of the impurity region can be increased to cause a malfunction of a semiconductor device.
- the barrier metal layer is formed using a chemical vapor deposition (CVD) technique at a high temperature of about 700° C. in order to obtain good step coverage, and the metal layer is formed at a low temperature less than 500° C. Therefore, when the barrier metal layer and the metal layer are sequentially formed using an in-situ process in a single deposition apparatus, the electrical characteristics of the contact resistance between the metal layer and the impurity region may be degraded due to the high temperature of the barrier metal layer.
- CVD chemical vapor deposition
- a metallization process employing a copper layer is taught in U.S. Pat. No. 5,989,623 to Chen, et al., entitled “Dual Damascene Metallization.”
- Chen, et al. there is a deposition system for forming copper lines.
- the deposition system has a configuration that a CVD titanium nitride chamber and a CVD copper chamber are attached to a single transfer chamber.
- a source gas used in formation of a CVD titanium nitride layer can be introduced into the CVD copper chamber through the transfer chamber or vice versa. Therefore, the titanium nitride layer or the copper layer may contain impurities.
- a chemical vapor deposition (CVD) metallization process using a CVD apparatus includes forming a barrier metal layer on a semiconductor substrate, cooling the semiconductor substrate having the barrier metal layer without breaking vacuum, and forming an additional metal layer on the cooled barrier metal layer.
- CVD chemical vapor deposition
- FIG. 1A is a schematic view illustrating CVD apparatus according to an embodiment of the present invention.
- FIG. 1B is an enlarged view illustrating one example of a cooling chamber shown in FIG. 1A ;
- FIG. 1C is an enlarged view illustrating another example of a cooling chamber shown in FIG. 1A ;
- FIG. 2 is a process flow chart to illustrate methods of forming metal layers using the CVD apparatus shown in FIG. 1 ;
- FIGS. 3 to 6 are sectional views to illustrate methods of forming metal layers using the CVD apparatus shown in FIG. 1 ;
- FIG. 7A is a graph to illustrate a contact resistance characteristic of N-type impurity regions of contact structures fabricated using a conventional method of forming a metal layer and a contact resistance characteristic of N-type impurity regions of contact structures fabricated using a method of forming a metal layer according to one embodiment of the present invention.
- FIG. 7B is a graph to illustrate a contact resistance characteristic of P-type impurity regions of contact structures fabricated using a conventional method of forming a metal layer and a contact resistance characteristic of P-type impurity regions of contact structures fabricated using a method of forming a metal layer according to one embodiment of the present invention.
- At least one cooling chamber is placed between first and second transfer chambers T 1 and T 2 , which are separated from each other.
- the at least one cooling chamber may include first and second cooling compartments C 1 and C 2 .
- the first transfer chamber T 1 has a first robot R 1 installed therein.
- the second transfer chamber T 2 has a second robot R 2 installed therein.
- First and second load lock chambers L 1 and L 2 are attached to the first transfer chamber T 1 .
- the first load lock chamber L 1 provides a space for temporarily storing a semiconductor substrate to be loaded into the first transfer chamber T 1
- the second load lock chamber L 2 provides a space for temporarily storing a semiconductor substrate to be unloaded from the first transfer chamber T 1 .
- the first load lock chamber L 1 corresponds to an input load lock chamber
- the second load lock chamber L 2 corresponds to an output load lock chamber.
- a first group of CVD process chambers P 11 , P 12 and P 13 , respectively, are attached to the first transfer chamber T 1 .
- the first robot R 1 transfers a semiconductor substrate stored in the first load lock chamber L 1 into any one of the first group of CVD process chambers P 11 , P 12 and P 13 and the cooling chambers C 1 and C 2 .
- the first robot R 1 may transfer a semiconductor substrate into any one of the first group of CVD process chambers P 11 , P 12 and P 13 and the cooling chambers C 1 and C 2 and into the second load lock chamber L 2 .
- any one of the first group of CVD process chambers P 11 , P 12 and P 13 may be a plasma CVD chamber.
- the first CVD process chamber P 11 may be a plasma CVD chamber including a cathode plate 51 and an anode plate 53 , which are installed inside the first CVD process chamber P 11 .
- the cathode plate 51 is used as a chuck on which a semiconductor substrate is placed, and the anode plate 53 is installed over the cathode plate 51 .
- the first CVD process chamber P 11 includes a plurality of source gas injection conduits 55 and 57 . Source gases are injected into the first CVD process chamber P 11 through the source gas injection conduits 55 and 57 .
- the first CVD process chamber P 11 includes an exhaust line 59 .
- the atmosphere inside the first CVD process chamber P 11 is exhausted through the exhaust line 59 .
- the first CVD process chamber P 11 can be used to form an ohmic layer, such as a titanium layer.
- another chamber of the first group of CVD process chambers P 11 , P 12 and P 13 may be a thermal CVD chamber.
- the second CVD process chamber P 12 may be a thermal CVD chamber having a chuck 61 and a heater block 63 installed therein. The heater block 63 is installed below the chuck 61 to heat up a semiconductor substrate placed on the chuck 61 .
- the second CVD process chamber P 12 may also include a plurality of source gas injection conduits 65 and 67 and an exhaust line 69 like the first CVD process chamber P 11 .
- the second CVD process chamber P 12 can be used to form a barrier metal layer, such as a titanium nitride layer.
- the third CVD process chamber P 13 may also have the same configuration as the first CVD process chamber P 11 or the second CVD process chamber P 12 as described above.
- a second group of CVD process chambers P 21 and P 22 are attached to the second transfer chamber T 2 .
- the second robot R 2 transfers a semiconductor substrate in the first or second cooling chamber C 1 or C 2 into one chamber of the second group of CVD process chambers P 21 and P 22 .
- the second robot R 2 may transfer a semiconductor substrate in one chamber of the second group of CVD process chambers P 21 and P 22 into the first or second cooling chamber C 1 or C 2 .
- One of the second group of CVD process chambers P 21 and P 22 may be a thermal CVD chamber having the same configuration as the second CVD process chamber P 12 .
- the fourth CVD process chamber P 21 can include a chuck 71 and a heater block 73 installed therein as well as a plurality of source gas injection conduits 75 , 77 and 79 and an exhaust line 81 .
- the fourth CVD process chamber can be used to form a metal layer, such as a tungsten layer.
- the fifth CVD process chamber P 22 may also have the same configuration as the aforementioned plasma CVD chamber or the thermal CVD chamber.
- a stage 103 is installed in a scaled space that is defined by a chamber wall 101 .
- a semiconductor substrate (not shown) is placed on the stage 103 .
- a circulation conduit 105 which functions as a circulation path of a cooling medium, is installed inside the stage 103 .
- De-ionized water (DIW), helium gas or the like may be used as the cooling medium.
- DIW De-ionized water
- helium gas or the like may be used as the cooling medium.
- An exhaust line 107 is installed to exit through a portion of the chamber wall 101 .
- the exhaust line 107 is connected to an exhaust pump 109 .
- the atmosphere inside the chamber wall 101 can be exhausted through the exhaust line 107 .
- a chuck 113 is installed inside a sealed space that is defined by a chamber wall 111 .
- At least one cooling gas injection line is installed at the chamber wall 111 .
- first to third cooling gas injection lines 115 , 117 and 119 may be installed in the chamber wall 111 .
- a cooling gas is injected into the chamber through at least one of the cooling gas injection lines 115 , 117 and 119 , respectively, and the cooling gas cools the semiconductor substrate loaded on the chuck 113 .
- the first to third cooling gas injection lines 115 , 117 and 119 can be used as lines for supplying argon gas, nitrogen gas, and helium gas, respectively.
- an exhaust line 121 is installed in a portion of the chamber wall 111 , and the exhaust line 121 is connected to an exhaust pump 123 .
- the atmosphere in the chamber can be exhausted out through the exhaust line 121 .
- a device isolation layer 13 is formed at a semiconductor substrate 11 to define first and second active regions 13 a and 13 b, which are spaced apart from each other.
- An N-type impurity region 15 and a P-type impurity region 17 are respectively formed at the first and second active regions 13 a and 13 b using an ion implantation process and an annealing process well known in the art.
- An interlayer insulating layer 19 is formed on the semiconductor substrate having the impurity regions 15 and 17 . The interlayer insulating layer 19 is patterned to form a first contact hole 21 a exposing the N-type impurity region 15 and a second contact hole 21 b exposing the P-type impurity region 17 .
- the semiconductor substrate having the interlayer insulating layer 19 is temporarily loaded into the first load lock chamber (L 1 of FIG. 1A ).
- the semiconductor substrate in the first load lock chamber L 1 is transferred onto the cathode plate 51 in the first CVD process chamber P 11 using the first robot R 1 .
- An ohmic layer 23 is formed on the semiconductor substrate located in the first CVD process chamber P 11 using a plasma CVD process (step 1 of FIG. 2 ).
- the ohmic layer 23 is formed by applying an RF power between the cathode plate 51 and the anode plate 53 , and injecting source gases into the first CVD process chamber P 11 through the source gas injection conduits 55 and 57 .
- the source gases are a titanium chloride (TiCl4) gas and a hydrogen gas
- a plasma CVD titanium layer is formed on the semiconductor substrate.
- the plasma CVD titanium layer is formed at a temperature of about 400° C. to about 650° C.
- the first and second contact holes 21 a and 21 b expose interconnection lines (not shown) formed of a conductive layer, instead of the impurity regions 15 and 17 , the process for forming the ohmic layer 23 can be omitted.
- the semiconductor substrate having the ohmic layer 23 is transferred onto the chuck 61 located in the second CVD process chamber P 12 using the first robot R 1 .
- a barrier metal layer 25 is formed on the semiconductor substrate using a thermal CVD process inside the second CVD process chamber P 12 (step 3 of FIG. 2 ).
- the barrier metal layer 25 is formed by heating the semiconductor substrate at a temperature of about 600° C. to about 800° C. using the heater block 63 , and injecting source gases into the second CVD process chamber P 12 through the source gas injection conduits 65 and 67 .
- the source gases are a titanium chloride (TiCl4) gas and an ammonia (NH3) gas
- a titanium nitride (TiN) layer is formed on the semiconductor substrate.
- both of the ohmic layer 23 and the barrier metal layer 25 can be formed using the plasma CVD process or the thermal CVD process.
- the semiconductor substrate having the barrier metal layer 25 is transferred into the first cooling chamber C 1 using the first robot R 1 .
- the semiconductor substrate having the barrier metal layer 25 is loaded on the stage 103 .
- the semiconductor substrate on the stage 103 is cooled down to a room temperature by a cooling medium that flows through the circulation conduit 105 (step 5 of FIG. 2 ).
- the cooling medium may be de-ionized water or helium gas.
- the semiconductor substrate having the barrier metal layer 25 is loaded onto the chuck 113 .
- the semiconductor substrate on the chuck 113 is cooled down to a room temperature by a cooling gas introduced into the first cooling chamber C 1 through at least one of the first to third cooling gas injection conduits 115 , 117 and 119 (step 5 of FIG. 2 ).
- the cooling gas may be at least one of an argon gas, a nitrogen gas and a helium gas.
- the cooling time can be reduced without any contamination due to the particles in the atmosphere, since the barrier metal layer 25 is intentionally cooled down using a cooling gas or a cooling medium without breaking vacuum.
- the semiconductor substrate having the cooled barrier metal layer is loaded onto the chuck 71 in the fourth CVD process chamber P 21 using the second robot R 2 in the second transfer chamber T 2 .
- the semiconductor substrate on the chuck 71 is heated up to a temperature of from about 300° C. to about 450° C. by the heater block 73 , and source gases are injected into the fourth CVD process chamber P 21 through the source gas injection conduits 75 , 77 and 79 .
- a metal layer 27 is formed on the cooled semiconductor substrate inside the fourth CVD process chamber P 21 (step 7 of FIG. 2 ).
- the metal layer 27 is a tungsten layer.
- the barrier metal layer 25 is formed inside the second CVD process chamber P 12 attached to the first transfer chamber T 1
- the metal layer 27 is formed inside the fourth CVD process chamber P 21 attached to the second transfer chamber T 2 , which is separated from the first transfer chamber T 1 . Therefore, even though the source gases used in formation of the barrier metal layer 25 remain in the first transfer chamber T 1 , the source gases in the first transfer chamber T 1 may not be introduced into the fourth CVD process chamber P 21 while the semiconductor substrate having the barrier metal layer 25 is loaded into the fourth CVD process chamber P 21 in order to form the metal layer 27 .
- the tungsten layer do not contain the impurities such as titanium atoms, chlorine atoms and nitrogen atoms decomposed from the TiCl4 gas and the NH3 gas, which are used in formation of the titanium nitride layer 25 .
- the semiconductor substrate having the metal layer 27 is transferred into the second cooling chamber C 2 .
- the semiconductor substrate in the second cooling chamber C 2 can be cooled down using the same manner as the cooling process performed inside the first cooling chamber Cl.
- the cooled semiconductor substrate in the second cooling chamber C 2 is transferred into the second load lock chamber L 2 using the first robot R 1 , and the semiconductor substrate in the second load lock chamber L 2 is unloaded.
- the semiconductor substrate in the second cooling chamber C 2 can be transferred into the second load lock chamber L 2 using the first robot R 1 without the application of the cooling process.
- the metal layer 27 , the barrier metal layer 25 and the ohmic layer 23 may be sequentially planarized until a top surface of the interlayer insulating layer 19 is exposed.
- a first ohmic layer pattern 23 a, a first barrier metal layer pattern 25 a, and a first metal contact plug 27 a are formed inside the first contact hole 21 a
- a second ohmic layer pattern 23 b, a second barrier metal layer pattern 25 b, and a second metal contact plug 27 b are formed inside the second contact hole 21 b.
- a metal interconnection layer such as an aluminum layer is formed on the semiconductor substrate having the metal contact plugs 27 a and 27 b.
- the metal interconnection layer is patterned to form a first metal line 29 a covering the first metal contact plug 27 a and a second metal line 29 b covering the second metal contact plug 27 b.
- the abscissas represent split groups, and the ordinates represent contact resistance.
- group “A” denotes the contact resistance of the conventional contact structures fabricated using breaking vacuum
- group “C” denotes the contact resistance of the conventional contact structures fabricated using an in-situ metallization process without application of the cooling process.
- group “B” denotes the contact resistance of the contact structures fabricated according to the embodiment of the present invention.
- All of the structures indicated by groups “A,” “B” and “C” were fabricated to have impurity regions formed at a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate having the impurity regions, contact holes penetrating predetermined regions of the interlayer insulating layer to expose the impurity regions, metal plugs filling the contact holes, and a titanium layer and a titanium nitride layer interposed between the metal plugs and the impurity regions.
- Both the N-type contact size and the P-type contact size were 0.29 mm ⁇ 0.29 mm on a photo mask.
- thermo CVD temperature TiN layer source gases TiCl 4 + NH 3 process 5 Torr pressure cooling process vacuum break in-situ skipped (cooling in the cooling atmosphere) (nitrogen, room temperature) metal plug deposition 400° C.
- thermal CVD temperature tungsten source gases WF 6 + H 2 + SiH 4 plug process 90 Torr pressure
- the contact resistance values of the samples formed according to the present invention were similar to those of the samples formed using the prior art (group “A”) employing the natural cooling process.
- the contact resistance values of the conventional samples (group “C”) formed without any cooling process were relatively non-uniform as compared to those of the samples according to the present invention.
- the samples of group “C” exhibited higher contact resistance values than the samples according to the present invention. It can be understood that this is because the temperature of the semiconductor substrate having the TiN layer is higher than the deposition temperature of the tungsten layer.
- the semiconductor substrate having the barrier metal layer is cooled using the in-situ cooling chamber, and the metal layer is formed on the cooled semiconductor substrate. Therefore, the effect that the temperature of the barrier metal layer which influences the contact resistance can be significantly reduced. As a result, the present invention allows the formation of the reliable contact structure without any degradation of the throughput.
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Abstract
CVD metallization processes and CVD apparatus used therein are provided. The processes include forming a barrier metal layer on a semiconductor substrate and cooling the semiconductor substrate having the barrier metal layer without breaking vacuum. An additional metal layer may be formed on the cooled barrier metal layer. The in-situ cooling process is preferably performed inside a cooling chamber installed between first and second transfer chambers, which are separated from each other. The barrier metal layer may be formed inside a CVD process chamber attached to the first transfer chamber, and the additional metal layer may be formed inside another CVD process chamber attached to the second transfer chamber.
Description
- This application is a Divisional of U.S. patent application Ser. No. 10/855,114, filed on May 26, 2004, which claims the benefit of Korean Patent Application No. 2003-34946, filed on May 30, 2003, the contents of which are incorporated herein by reference in their entirety.
- 1. Field of the Invention
- The present invention relates to fabrication processes of semiconductor devices and fabrication equipment used therein and, more particularly, to metallization processes and chemical vapor deposition apparatus used therein, and more particularly, to in situ metallization processes and chemical vapor deposition apparatus used therein.
- 2. Description of the Related Art
- Metal lines are necessarily used in fabrication of semiconductor devices. The formation of the metal lines includes forming a metal layer on a semiconductor substrate and patterning the metal layer using photolithography/etch processes. During the photolithography process, an irregular reflection may occur on the surface of the metal layer. The irregular reflection is due to the surface roughness of the metal layer. Accordingly, an anti-reflective coating layer is widely used in order to suppress the irregular reflection.
- A method of forming the metal layer and the anti-reflective coating layer is taught in U.S. Pat. No. 6,187,667 B1 to Shan et al., entitled “Method of Forming Metal Layer and/or Antireflective Coating Layer On An Integrated Circuit.” According to Shan et al., the metal layer is cooled prior to formation of the anti-reflective coating layer on the metal layer. Thus, it can prevent protrusions such as bumps from being produced on the surface of the metal layer during the formation of the anti-reflective coating layer.
- In the event that the metal layer directly contacts an impurity region formed at a predetermined area of a semiconductor substrate through a contact hole that penetrates an interlayer insulating layer, metal atoms in the metal layer may be diffused into the impurity region. In this case, junction leakage current of the impurity region can be increased to cause a malfunction of a semiconductor device.
- Accordingly, most of highly-integrated semiconductor devices widely employ a barrier metal layer interposed between the metal layer and the impurity region. In general, the barrier metal layer is formed using a chemical vapor deposition (CVD) technique at a high temperature of about 700° C. in order to obtain good step coverage, and the metal layer is formed at a low temperature less than 500° C. Therefore, when the barrier metal layer and the metal layer are sequentially formed using an in-situ process in a single deposition apparatus, the electrical characteristics of the contact resistance between the metal layer and the impurity region may be degraded due to the high temperature of the barrier metal layer.
- Further, a metallization process employing a copper layer is taught in U.S. Pat. No. 5,989,623 to Chen, et al., entitled “Dual Damascene Metallization.” According to Chen, et al., there is a deposition system for forming copper lines. However, the deposition system has a configuration that a CVD titanium nitride chamber and a CVD copper chamber are attached to a single transfer chamber. Thus, a source gas used in formation of a CVD titanium nitride layer can be introduced into the CVD copper chamber through the transfer chamber or vice versa. Therefore, the titanium nitride layer or the copper layer may contain impurities.
- Furthermore, a technology of filling contact holes is taught in U.S. Pat. No. 6,238,533 to Satipunwaycha, et al., entitled “Integrated PVD System For Aluminum Hole Filling Using Ionized Metal Adhesion Layer.” According to Satipunwaycha, et al., there is provided a deposition system for forming aluminum lines. The deposition system includes two transfer chambers separated from each other and physical vapor deposition (PVD) chambers attached to the transfer chambers. However, the PVD technique exhibits remarkably poor step coverage as compared to a typical CVD technique. Therefore, according to Satipunwaycha, et al., there are some limitations in forming a uniform barrier metal layer and metal contact plugs in contact holes having a high aspect ratio.
- In one embodiment, a chemical vapor deposition (CVD) metallization process using a CVD apparatus includes forming a barrier metal layer on a semiconductor substrate, cooling the semiconductor substrate having the barrier metal layer without breaking vacuum, and forming an additional metal layer on the cooled barrier metal layer. As a result, the present invention allows the formation of the reliable contact structure without any degradation of the throughput.
- The exemplary embodiments of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
-
FIG. 1A is a schematic view illustrating CVD apparatus according to an embodiment of the present invention; -
FIG. 1B is an enlarged view illustrating one example of a cooling chamber shown inFIG. 1A ; -
FIG. 1C is an enlarged view illustrating another example of a cooling chamber shown inFIG. 1A ; -
FIG. 2 is a process flow chart to illustrate methods of forming metal layers using the CVD apparatus shown inFIG. 1 ; - FIGS. 3 to 6 are sectional views to illustrate methods of forming metal layers using the CVD apparatus shown in
FIG. 1 ; -
FIG. 7A is a graph to illustrate a contact resistance characteristic of N-type impurity regions of contact structures fabricated using a conventional method of forming a metal layer and a contact resistance characteristic of N-type impurity regions of contact structures fabricated using a method of forming a metal layer according to one embodiment of the present invention; and -
FIG. 7B is a graph to illustrate a contact resistance characteristic of P-type impurity regions of contact structures fabricated using a conventional method of forming a metal layer and a contact resistance characteristic of P-type impurity regions of contact structures fabricated using a method of forming a metal layer according to one embodiment of the present invention. - The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. In addition, when it is described that one layer is positioned ‘on’ another layer or substrate, the layer can be directly formed on another layer or substrate, or the third layer can be positioned between one layer and another layer or substrate. Like numbers refer to like elements throughout the specification.
- Referring to
FIG. 1A , at least one cooling chamber is placed between first and second transfer chambers T1 and T2, which are separated from each other. The at least one cooling chamber may include first and second cooling compartments C1 and C2. The first transfer chamber T1 has a first robot R1 installed therein. Similarly, the second transfer chamber T2 has a second robot R2 installed therein. - First and second load lock chambers L1 and L2 are attached to the first transfer chamber T1. The first load lock chamber L1 provides a space for temporarily storing a semiconductor substrate to be loaded into the first transfer chamber T1, and the second load lock chamber L2 provides a space for temporarily storing a semiconductor substrate to be unloaded from the first transfer chamber T1. Thus, the first load lock chamber L1 corresponds to an input load lock chamber, and the second load lock chamber L2 corresponds to an output load lock chamber.
- A first group of CVD process chambers P11, P12 and P13, respectively, are attached to the first transfer chamber T1. The first robot R1 transfers a semiconductor substrate stored in the first load lock chamber L1 into any one of the first group of CVD process chambers P11, P12 and P13 and the cooling chambers C1 and C2. Alternatively, the first robot R1 may transfer a semiconductor substrate into any one of the first group of CVD process chambers P11, P12 and P13 and the cooling chambers C1 and C2 and into the second load lock chamber L2.
- Any one of the first group of CVD process chambers P11, P12 and P13 may be a plasma CVD chamber. For instance, the first CVD process chamber P11 may be a plasma CVD chamber including a
cathode plate 51 and ananode plate 53, which are installed inside the first CVD process chamber P11. Thecathode plate 51 is used as a chuck on which a semiconductor substrate is placed, and theanode plate 53 is installed over thecathode plate 51. In this case, the first CVD process chamber P11 includes a plurality of sourcegas injection conduits gas injection conduits exhaust line 59. The atmosphere inside the first CVD process chamber P11 is exhausted through theexhaust line 59. The first CVD process chamber P11, can be used to form an ohmic layer, such as a titanium layer. - In the meantime, another chamber of the first group of CVD process chambers P11, P12 and P13 may be a thermal CVD chamber. For example, the second CVD process chamber P12 may be a thermal CVD chamber having a
chuck 61 and aheater block 63 installed therein. Theheater block 63 is installed below thechuck 61 to heat up a semiconductor substrate placed on thechuck 61. In this case, the second CVD process chamber P12 may also include a plurality of sourcegas injection conduits exhaust line 69 like the first CVD process chamber P11. The second CVD process chamber P12, can be used to form a barrier metal layer, such as a titanium nitride layer. - The third CVD process chamber P13 may also have the same configuration as the first CVD process chamber P11 or the second CVD process chamber P12 as described above.
- A second group of CVD process chambers P21 and P22 are attached to the second transfer chamber T2. In this case, the second robot R2 transfers a semiconductor substrate in the first or second cooling chamber C1 or C2 into one chamber of the second group of CVD process chambers P21 and P22. On the contrary, the second robot R2 may transfer a semiconductor substrate in one chamber of the second group of CVD process chambers P21 and P22 into the first or second cooling chamber C1 or C2.
- One of the second group of CVD process chambers P21 and P22 may be a thermal CVD chamber having the same configuration as the second CVD process chamber P12. The fourth CVD process chamber P21 can include a chuck 71 and a
heater block 73 installed therein as well as a plurality of sourcegas injection conduits 75, 77 and 79 and anexhaust line 81. The fourth CVD process chamber, can be used to form a metal layer, such as a tungsten layer. The fifth CVD process chamber P22 may also have the same configuration as the aforementioned plasma CVD chamber or the thermal CVD chamber. - Referring to
FIG. 1B , astage 103 is installed in a scaled space that is defined by achamber wall 101. A semiconductor substrate (not shown) is placed on thestage 103. Acirculation conduit 105, which functions as a circulation path of a cooling medium, is installed inside thestage 103. De-ionized water (DIW), helium gas or the like may be used as the cooling medium. When the cooling medium flows through thecirculation conduit 105, the semiconductor substrate on thestage 103 is cooled. Anexhaust line 107 is installed to exit through a portion of thechamber wall 101. Theexhaust line 107 is connected to anexhaust pump 109. Thus, the atmosphere inside thechamber wall 101 can be exhausted through theexhaust line 107. - Referring to
FIG. 1C , achuck 113 is installed inside a sealed space that is defined by achamber wall 111. At least one cooling gas injection line is installed at thechamber wall 111. For example, first to third coolinggas injection lines chamber wall 111. A cooling gas is injected into the chamber through at least one of the coolinggas injection lines chuck 113. In detail, the first to third coolinggas injection lines exhaust line 121 is installed in a portion of thechamber wall 111, and theexhaust line 121 is connected to anexhaust pump 123. Thus, the atmosphere in the chamber can be exhausted out through theexhaust line 121. - Referring to
FIG. 3 , adevice isolation layer 13 is formed at asemiconductor substrate 11 to define first and secondactive regions type impurity region 15 and a P-type impurity region 17 are respectively formed at the first and secondactive regions layer 19 is formed on the semiconductor substrate having theimpurity regions layer 19 is patterned to form afirst contact hole 21 a exposing the N-type impurity region 15 and asecond contact hole 21 b exposing the P-type impurity region 17. - Referring to
FIGS. 1A, 2 and 4, the semiconductor substrate having the interlayer insulatinglayer 19 is temporarily loaded into the first load lock chamber (L1 ofFIG. 1A ). The semiconductor substrate in the first load lock chamber L1 is transferred onto thecathode plate 51 in the first CVD process chamber P11 using the first robot R1. Anohmic layer 23 is formed on the semiconductor substrate located in the first CVD process chamber P11 using a plasma CVD process (step 1 ofFIG. 2 ). In detail, theohmic layer 23 is formed by applying an RF power between thecathode plate 51 and theanode plate 53, and injecting source gases into the first CVD process chamber P11 through the sourcegas injection conduits impurity regions ohmic layer 23 can be omitted. - Subsequently, the semiconductor substrate having the
ohmic layer 23 is transferred onto thechuck 61 located in the second CVD process chamber P12 using the first robot R1. Abarrier metal layer 25 is formed on the semiconductor substrate using a thermal CVD process inside the second CVD process chamber P12 (step 3 ofFIG. 2 ). In detail, thebarrier metal layer 25 is formed by heating the semiconductor substrate at a temperature of about 600° C. to about 800° C. using theheater block 63, and injecting source gases into the second CVD process chamber P12 through the sourcegas injection conduits - Alternatively, both of the
ohmic layer 23 and thebarrier metal layer 25 can be formed using the plasma CVD process or the thermal CVD process. - The semiconductor substrate having the
barrier metal layer 25 is transferred into the first cooling chamber C1 using the first robot R1. In the event that the first cooling chamber C1 has the configuration as shown inFIG. 1B , the semiconductor substrate having thebarrier metal layer 25 is loaded on thestage 103. The semiconductor substrate on thestage 103 is cooled down to a room temperature by a cooling medium that flows through the circulation conduit 105 (step 5 ofFIG. 2 ). The cooling medium may be de-ionized water or helium gas. - Alternatively, when the second cooling chamber C1 has the configuration as shown in
FIG. 1C , the semiconductor substrate having thebarrier metal layer 25 is loaded onto thechuck 113. The semiconductor substrate on thechuck 113 is cooled down to a room temperature by a cooling gas introduced into the first cooling chamber C1 through at least one of the first to third coolinggas injection conduits step 5 ofFIG. 2 ). The cooling gas may be at least one of an argon gas, a nitrogen gas and a helium gas. - As a result, the cooling time can be reduced without any contamination due to the particles in the atmosphere, since the
barrier metal layer 25 is intentionally cooled down using a cooling gas or a cooling medium without breaking vacuum. - Referring to
FIGS. 1A, 2 and 5, the semiconductor substrate having the cooled barrier metal layer is loaded onto the chuck 71 in the fourth CVD process chamber P21 using the second robot R2 in the second transfer chamber T2. The semiconductor substrate on the chuck 71 is heated up to a temperature of from about 300° C. to about 450° C. by theheater block 73, and source gases are injected into the fourth CVD process chamber P21 through the sourcegas injection conduits 75, 77 and 79. Thus, ametal layer 27 is formed on the cooled semiconductor substrate inside the fourth CVD process chamber P21 (step 7 ofFIG. 2 ). In the event that a tungsten fluoride (WF6) gas, a silane (SiH4) gas and a hydrogen gas are injected through the first to third sourcegas injection conduits 75, 77 and 79, respectively, themetal layer 27 is a tungsten layer. - As described above, the
barrier metal layer 25 is formed inside the second CVD process chamber P12 attached to the first transfer chamber T1, and themetal layer 27 is formed inside the fourth CVD process chamber P21 attached to the second transfer chamber T2, which is separated from the first transfer chamber T1. Therefore, even though the source gases used in formation of thebarrier metal layer 25 remain in the first transfer chamber T1, the source gases in the first transfer chamber T1 may not be introduced into the fourth CVD process chamber P21 while the semiconductor substrate having thebarrier metal layer 25 is loaded into the fourth CVD process chamber P21 in order to form themetal layer 27. In other words, the tungsten layer do not contain the impurities such as titanium atoms, chlorine atoms and nitrogen atoms decomposed from the TiCl4 gas and the NH3 gas, which are used in formation of thetitanium nitride layer 25. - The semiconductor substrate having the
metal layer 27 is transferred into the second cooling chamber C2. The semiconductor substrate in the second cooling chamber C2 can be cooled down using the same manner as the cooling process performed inside the first cooling chamber Cl. The cooled semiconductor substrate in the second cooling chamber C2 is transferred into the second load lock chamber L2 using the first robot R1, and the semiconductor substrate in the second load lock chamber L2 is unloaded. - Alternatively, the semiconductor substrate in the second cooling chamber C2 can be transferred into the second load lock chamber L2 using the first robot R1 without the application of the cooling process. p Referring to
FIG. 6 , themetal layer 27, thebarrier metal layer 25 and theohmic layer 23 may be sequentially planarized until a top surface of the interlayer insulatinglayer 19 is exposed. As a result, a firstohmic layer pattern 23 a, a first barriermetal layer pattern 25 a, and a first metal contact plug 27 a, are formed inside thefirst contact hole 21 a, and a secondohmic layer pattern 23 b, a second barriermetal layer pattern 25 b, and a second metal contact plug 27 b, are formed inside thesecond contact hole 21 b. A metal interconnection layer such as an aluminum layer is formed on the semiconductor substrate having the metal contact plugs 27 a and 27 b. The metal interconnection layer is patterned to form afirst metal line 29 a covering the first metal contact plug 27 a and asecond metal line 29 b covering the second metal contact plug 27 b. - In
FIGS. 7A and 7B , the abscissas represent split groups, and the ordinates represent contact resistance. In detail, group “A” denotes the contact resistance of the conventional contact structures fabricated using breaking vacuum, and group “C” denotes the contact resistance of the conventional contact structures fabricated using an in-situ metallization process without application of the cooling process. Also, group “B” denotes the contact resistance of the contact structures fabricated according to the embodiment of the present invention. All of the structures indicated by groups “A,” “B” and “C” were fabricated to have impurity regions formed at a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate having the impurity regions, contact holes penetrating predetermined regions of the interlayer insulating layer to expose the impurity regions, metal plugs filling the contact holes, and a titanium layer and a titanium nitride layer interposed between the metal plugs and the impurity regions. Both the N-type contact size and the P-type contact size were 0.29 mm×0.29 mm on a photo mask. - The contact structures showing the measurement results of
FIGS. 7A and 7B were fabricated using the main process conditions described in the following Table 1.TABLE 1 process condition Process parameter group “A” group “B” group “C” N-type impurity ion As, 5 × 1015 atoms/cm2 implantation P-type impurity ion BF2, 1 × 1015 atoms/cm2 implantation annealing 700° C., nitrogen atmosphere, RTP ohmic layer thickness 100 angstroms (plasma CVD deposition 650° C. Ti layer) temperature source gases TiCl4 + H2 process 5 Torr pressure barrier metal thickness 200 angstroms layer deposition 700° C. (thermal CVD temperature TiN layer) source gases TiCl4 + NH3 process 5 Torr pressure cooling process vacuum break in-situ skipped (cooling in the cooling atmosphere) (nitrogen, room temperature) metal plug deposition 400° C. (thermal CVD temperature tungsten source gases WF6 + H2 + SiH4 plug) process 90 Torr pressure - In Table 1, samples of group “A” were naturally cooled down in the atmosphere after formation of the thermal CVD TiN layer, and samples of group “B” were cooled down using a nitrogen gas inside an in-situ cooling chamber after formation of the thermal CVD TiN layer. That is, the samples of group “B” were fabricated using the CVD apparatus shown in
FIG. 1A . In contrast, no cooling process was applied to samples of group “C.” That is, a tungsten layer was directly formed on the thermal CVD TiN layer using an in-situ process. - As can be seen from
FIGS. 7A and 7B , the contact resistance values of the samples formed according to the present invention (group “B”) were similar to those of the samples formed using the prior art (group “A”) employing the natural cooling process. In contrast, the contact resistance values of the conventional samples (group “C”) formed without any cooling process were relatively non-uniform as compared to those of the samples according to the present invention. Particularly, in the contact resistance values of the N-type impurity regions shown inFIG. 7A , the samples of group “C” exhibited higher contact resistance values than the samples according to the present invention. It can be understood that this is because the temperature of the semiconductor substrate having the TiN layer is higher than the deposition temperature of the tungsten layer. - As described above, according to an aspect of the present invention, the semiconductor substrate having the barrier metal layer is cooled using the in-situ cooling chamber, and the metal layer is formed on the cooled semiconductor substrate. Therefore, the effect that the temperature of the barrier metal layer which influences the contact resistance can be significantly reduced. As a result, the present invention allows the formation of the reliable contact structure without any degradation of the throughput.
- Although the preferred embodiments of the present invention have been described in detail hereinabove, it should be understood that many variations and/or modifications of the basic inventive concepts apparent to those skilled in the art will still fall within the spirit and scope of the present invention as defined in the appended claims.
Claims (7)
1. A chemical vapor deposition (CVD) apparatus comprising:
first and second transfer chambers separated from each other;
at least one cooling chamber installed between the first and second transfer chambers;
a first CVD process chamber attached to the first transfer chamber; and
a second CVD process chamber attached to the second transfer chamber.
2. The CVD apparatus according to claim 1 , further comprising:
first and second load lock chambers attached to the first transfer chamber.
3. The CVD apparatus according to claim 1 , wherein the at least one cooling chamber includes a stage, and the stage includes a circulation conduit through which a cooling medium flows.
4. The CVD apparatus according to claim 1 , wherein the at least one cooling chamber having a chuck installed therein, and at least one cooling gas injection line for supplying a cooling gas thereto.
5. The CVD apparatus according to claim 1 , wherein the first CVD process chamber comprises a plasma CVD process chamber and/or a thermal CVD process chamber.
6. The CVD apparatus according to claim 1 , wherein the second CVD process chamber comprises a thermal CVD process chamber.
7. The CVD apparatus according to claim 1 , wherein a source gas injected into the first CVD process chamber is different from a source gas injected into the second CVD process chamber.
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KR1020030034946A KR100576363B1 (en) | 2003-05-30 | 2003-05-30 | In-situ chemical vapor deposition metallization process and chemical vapor deposition apparatus used therein |
US10/855,114 US7183207B2 (en) | 2003-05-30 | 2004-05-26 | Chemical vapor deposition metallization processes and chemical vapor deposition apparatus used therein |
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KR100652317B1 (en) * | 2005-08-11 | 2006-11-29 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal pad of the semiconductor device |
KR100855325B1 (en) * | 2006-12-27 | 2008-09-04 | 세메스 주식회사 | Loadlock chamber, apparatus of treating substrate and method of treating the same |
US7968952B2 (en) | 2006-12-29 | 2011-06-28 | Intel Corporation | Stressed barrier plug slot contact structure for transistor performance enhancement |
US7719062B2 (en) * | 2006-12-29 | 2010-05-18 | Intel Corporation | Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement |
JP2008186926A (en) * | 2007-01-29 | 2008-08-14 | Fujitsu Ltd | Semiconductor device and manufacturing method therefor |
CN101399185B (en) * | 2007-09-30 | 2011-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for protecting metallic layer and forming solder pad, metallic routing layer and micro-mirror surface |
JP5655308B2 (en) * | 2010-01-07 | 2015-01-21 | ヤマハ株式会社 | Manufacturing method of semiconductor device |
KR101463961B1 (en) * | 2013-02-15 | 2014-11-26 | 최대규 | Plasma process system |
US8956939B2 (en) * | 2013-04-29 | 2015-02-17 | Asm Ip Holding B.V. | Method of making a resistive random access memory device |
JP2014216647A (en) | 2013-04-29 | 2014-11-17 | エーエスエムアイピー ホールディング ビー.ブイ. | Method for manufacturing resistive random access memory having metal-doped resistive switching layer |
US9520562B2 (en) | 2013-07-19 | 2016-12-13 | Asm Ip Holding B.V. | Method of making a resistive random access memory |
US9472757B2 (en) | 2013-07-19 | 2016-10-18 | Asm Ip Holding B.V. | Method of making a resistive random access memory device |
JP6788393B2 (en) * | 2016-06-29 | 2020-11-25 | 東京エレクトロン株式会社 | How to form a copper film |
US11476267B2 (en) * | 2019-05-24 | 2022-10-18 | Applied Materials, Inc. | Liner for V-NAND word line stack |
TWI750749B (en) * | 2020-07-28 | 2021-12-21 | 華邦電子股份有限公司 | Chemical vapor deposition process and methof of forming film |
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US20040241988A1 (en) | 2004-12-02 |
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US7183207B2 (en) | 2007-02-27 |
JP2004363596A (en) | 2004-12-24 |
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