US20070099339A1 - Fabrication method for a chip packaging structure - Google Patents

Fabrication method for a chip packaging structure Download PDF

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US20070099339A1
US20070099339A1 US11/261,462 US26146205A US2007099339A1 US 20070099339 A1 US20070099339 A1 US 20070099339A1 US 26146205 A US26146205 A US 26146205A US 2007099339 A1 US2007099339 A1 US 2007099339A1
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chip packaging
layer
packaging structure
fabrication method
structure according
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US7320901B2 (en
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Wen-Yin Chang
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GIOTEK OPTOELECTRONICS Co Ltd
Light Ocean Tech Corp
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Taiwan Solutions Systems Corp
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Assigned to LIGHT OCEAN TECHNOLOGY CORP. reassignment LIGHT OCEAN TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAIWAN SOLUTIONS SYSTEMS CORP.
Assigned to LIGHT OCEAN TECHNOLOGY CORP., GIOTEK OPTOELECTRONICS CO., LTD. reassignment LIGHT OCEAN TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIGHT OCEAN TECHNOLOGY CORP.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01046—Palladium [Pd]
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    • H01L2924/01—Chemical elements
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention generally relates to chip package technology, and more particularly relates to a fabrication method of a chip packaging structure with good heat dissipation.
  • the semiconductor technology is rapidly enhanced with the development the multi-function of the computer and the Internet communication product.
  • the electronics packaging not only provides the transmission of the electronics signal and the electric power, but the most important thing is the heating sinking and the protection of the package structure.
  • Owing to the heat source of the electronics packaging elements is mainly from the chip that provides with the characteristics of the high power, high density, small volume, so the heat capacity of the heat sinking is much higher than conventional packaging technology. Hence, the chip package with good heat dissipation becomes more important than before.
  • One of objects of the present invention is to provide a fabrication method for a chip packaging structure that utilizes the method of plating metal to electrically connect different layers so as to replace the traditional method that drills hole first and then plates metal in the hole.
  • Another of objects of the present invention is to provide a fabrication method for a chip packaging structure that utilizes the method of plating metal to electrically connect different layers.
  • the metal in the conductive through hole is solid metal so as can provide the good ability of heat sinking.
  • one of objects of the present invention is to provide a fabrication method for a chip packaging structure that utilizes the present manufacturing processes of the package industry without extra process or equipment so as to decrease the PCB processes and lower the package cost.
  • one embodiment of the present invention provides a fabrication method for a chip packaging structure including: providing a carrier plate, wherein a conductive layer is formed on the upper surface of the carrier plate; forming a plurality of trenches penetrating through the conductive layer by utilizing the photolithography process; forming a first patterned photoresist layer on those trenches and a first photoresist layer on the downward surface of the carrier plate, wherein those trenches are filled by the first patterned photoresist layer; filling at least a metal layer on the conductive layer between the first patterned photoresist layer; performing a metal surface treatment on the surface of the metal layer, wherein the metal layer includes a plurality of conductive joints; removing the first patterned layer and the first photoresist layer; and proceeding a chip packaging process.
  • FIG. 1 to FIG. 11 are schematic representations of the cross-section view of the formulation steps of the fabrication method for a chip packaging structure in accordance with one embodiment of the present invention.
  • FIG. 12 and FIG. 13 are schematic representations of the cross-section view of the fabrication method for a chip packaging structure in accordance with another embodiment of the present invention.
  • FIG. 1 to FIG. 11 are schematic representations of the cross-section view of the formulation steps of the fabrication method for a chip packaging structure illustrates one embodiment of the present invention.
  • a carrier plate 10 is made of metal, glass, ceramic, or polymer material.
  • the carrier plate 10 , the adhesive layer 20 and the conductive layer 30 may be the commercial product.
  • the adhesive layer 20 may be formed on the carrier plate 10 by the method of laminating, printing, spin coating, sputtering, electroless plating, or plating.
  • the conductive layer 30 may be formed on the adhesive layer 20 by the method of laminating, printing, spray coating, spin coating, evaporation, sputtering, electroless plating, or plating.
  • the adhesive layer 20 is made of metal, glass, ceramic or polymer material.
  • a surface roughing treatment process may be performed on the conductive layer 30 , wherein the surface roughing treatment process includes the method of micro etching, sand blasting, polishing, blackening, or browning.
  • a plurality of trenches penetrating through the conductive layer 30 are formed by utilizing the photolithography process, referring to FIG. 2 , FIG. 3 and FIG. 4 .
  • the suitable method such as coating or adhering
  • the patterned film 42 and the film 40 are used as the mask to etch to form trenches penetrating through the conductive layer 30 .
  • the patterned film 42 and the film 40 are removed. Trenches may be also penetrating the adhesive layer 20 and the conductive layer 30 .
  • a first patterned photoresist layer 46 and a first photoresist layer are respectively formed on the conductive layer 30 and on the downward surface of the carrier plate 10 by utilizing the photolithography process.
  • the first patterned photoresist layer 46 is filled upto the trenches penetrating the conductive layer 30 or penetrating the conductive layer 30 and the adhesive layer 20 .
  • a metal layer 50 is filled on the conductive layer 30 between the first patterned photoresist layer 46 .
  • the metal layer 50 is made of Cu, Pd, Ni or Ni/Pd/Au and formed by the method of sputtering, evaporation, electroless plating, or plating.
  • the metal layer 50 is used for electrically connecting the upper layer and the downward layer. After, a surface roughing treatment processing may be performed on the surface of the metal layer 50 , wherein the surface roughing treatment process includes the method of micro etching, sand blasting, polishing, blackening, or browning.
  • a second patterned photoresist layer 49 and a second photoresist layer 48 are respectively formed on the first patterned photoresist layer 46 and the downward surface of the first photoresist layer 44 .
  • a metal surface treatment is performed on the surface of the metal layer 50 .
  • the metal surface treatment is performed by the method of printing, evaporation, sputtering, electroless plating, or plating.
  • a metal treatment layer 60 formed by the metal surface treatment is made of Ni, Au, Ag, or Cu.
  • the second patterned photoresist layer 49 , the second photoresist layer 48 , the first patterned photoresist layer 46 and the first photoresist layer 44 are removed.
  • the metal layer 50 is dividing into a chip carrier area and conductive joints. In another embodiment, the metal layer 50 is only used for the conductive joints.
  • the first patterned photoresist layer 46 and the first photoresist layer 44 may be removed firstly.
  • the second patterned photoresist layer 49 and the second photoresist layer 48 are respectively formed on the trenches and the downward surface of the carrier plate 10 .
  • the second patterned photoresist layer 49 and the second photoresist layer 48 are removed.
  • a chip packaging process is performed.
  • a chip 70 is arranged on the chip carrier area and pluralities of leads 80 are used for electrically connecting the chip 70 and the conductive joints.
  • an encapsulant 90 is formed to cover the chip 70 and leads 80 .
  • the carrier plate 10 and the adhesive layer 20 are removed and then a pad 62 is formed on the downward surface of the conductive layer 30 by utilizing the surface mount technology (SMT) method.
  • the pad 62 is used for connecting with other electronics equipments. In one embodiment, it may only remove the carrier plate 10 and then form a pad on the downward surface of the adhesive layer 20 by utilizing the surface mount technology (SMT) method.
  • the chip packaging process can utilize the wire bonding method or the flip chip bonding method.
  • FIG. 12 and FIG. 13 are schematic representations of the cross-section view illustrate another embodiment of the present invention.
  • the metal layer 50 is merely used for electrically connecting.
  • An isolation layer 55 is formed on the adhesive layer 20 at the designated chip carrier area by utilizing the appropriate method, such as coating, for carrying the chip 70 .
  • FIG. 13 it could be understood that the chip 70 is arranged on the isolation layer 55 and the bonding height of the chip 70 and leads 80 could be different so as to resolve the disadvantage of the common lead frame that could not heighten the chip 70 .
  • the short problem is prevented so as can enhance the flexibility of the PCB layout.
  • the present invention is to provide a fabrication method for a chip packaging structure that utilizes the plating metal way to connect different layers so as to replace the traditional way to drill hole and then plate metal in the hole.
  • the metal in the conductive through hole is solid metal so as can provide good ability of heat sinking.
  • the present invention utilizes the existing manufacturing processes of the package industry without extra process or equipment so as can decrease the PCB processes and lower the package cost.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A fabrication method for a chip packaging structure disclosed herein is utilizing the method of plating metal to connect different layers so as to replace the traditional method that drill hole firstly and then plate metal in the hole. In the present invention, the metal in the conductive through hole is solid metal so as can provide good ability of heat sinking. Besides, the present fabrication method utilizes the existing manufacturing processes without extra process or equipment so as can decrease the PCB processes and lower the package cost.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to chip package technology, and more particularly relates to a fabrication method of a chip packaging structure with good heat dissipation.
  • 2. Description of the Prior Art
  • Accordingly, the semiconductor technology is rapidly enhanced with the development the multi-function of the computer and the Internet communication product. Owing to the requirement of the diversification, portable, thin film and compact, the processes of the chip package industry is gradually developed to the trend of high power, high density, thin, film and compact. The electronics packaging not only provides the transmission of the electronics signal and the electric power, but the most important thing is the heating sinking and the protection of the package structure.
  • Owing to the heat source of the electronics packaging elements is mainly from the chip that provides with the characteristics of the high power, high density, small volume, so the heat capacity of the heat sinking is much higher than conventional packaging technology. Hence, the chip package with good heat dissipation becomes more important than before.
    • SUMMARY OF THE INVENTION
  • One of objects of the present invention is to provide a fabrication method for a chip packaging structure that utilizes the method of plating metal to electrically connect different layers so as to replace the traditional method that drills hole first and then plates metal in the hole.
  • Another of objects of the present invention is to provide a fabrication method for a chip packaging structure that utilizes the method of plating metal to electrically connect different layers. The metal in the conductive through hole is solid metal so as can provide the good ability of heat sinking.
  • Further one of objects of the present invention is to provide a fabrication method for a chip packaging structure that utilizes the present manufacturing processes of the package industry without extra process or equipment so as to decrease the PCB processes and lower the package cost.
  • Accordingly, one embodiment of the present invention provides a fabrication method for a chip packaging structure including: providing a carrier plate, wherein a conductive layer is formed on the upper surface of the carrier plate; forming a plurality of trenches penetrating through the conductive layer by utilizing the photolithography process; forming a first patterned photoresist layer on those trenches and a first photoresist layer on the downward surface of the carrier plate, wherein those trenches are filled by the first patterned photoresist layer; filling at least a metal layer on the conductive layer between the first patterned photoresist layer; performing a metal surface treatment on the surface of the metal layer, wherein the metal layer includes a plurality of conductive joints; removing the first patterned layer and the first photoresist layer; and proceeding a chip packaging process.
  • Other advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
  • FIG. 1 to FIG. 11 are schematic representations of the cross-section view of the formulation steps of the fabrication method for a chip packaging structure in accordance with one embodiment of the present invention; and
  • FIG. 12 and FIG. 13 are schematic representations of the cross-section view of the fabrication method for a chip packaging structure in accordance with another embodiment of the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIG. 1 to FIG. 11 are schematic representations of the cross-section view of the formulation steps of the fabrication method for a chip packaging structure illustrates one embodiment of the present invention.
  • Referring to FIG. 1, first, a carrier plate 10 is made of metal, glass, ceramic, or polymer material. There are sequentially arranged an adhesive layer 20 and a conductive layer 30 on the upper surface of the carrier plate 10. The carrier plate 10, the adhesive layer 20 and the conductive layer 30 may be the commercial product. Besides, the adhesive layer 20 may be formed on the carrier plate 10 by the method of laminating, printing, spin coating, sputtering, electroless plating, or plating. Then, the conductive layer 30 may be formed on the adhesive layer 20 by the method of laminating, printing, spray coating, spin coating, evaporation, sputtering, electroless plating, or plating. The adhesive layer 20 is made of metal, glass, ceramic or polymer material. A surface roughing treatment process may be performed on the conductive layer 30, wherein the surface roughing treatment process includes the method of micro etching, sand blasting, polishing, blackening, or browning.
  • Following, a plurality of trenches penetrating through the conductive layer 30 are formed by utilizing the photolithography process, referring to FIG. 2, FIG. 3 and FIG. 4. By using the suitable method, such as coating or adhering, there are sequentially formed a patterned film 42 and a film 40 on the conductive layer 30 and on the downward surface of the carrier plate 10 by utilizing the image transferring. The patterned film 42 and the film 40 are used as the mask to etch to form trenches penetrating through the conductive layer 30. Then, the patterned film 42 and the film 40 are removed. Trenches may be also penetrating the adhesive layer 20 and the conductive layer 30.
  • Next, referring to FIG. 5, a first patterned photoresist layer 46 and a first photoresist layer are respectively formed on the conductive layer 30 and on the downward surface of the carrier plate 10 by utilizing the photolithography process. The first patterned photoresist layer 46 is filled upto the trenches penetrating the conductive layer 30 or penetrating the conductive layer 30 and the adhesive layer 20. As shown in FIG. 6, a metal layer 50 is filled on the conductive layer 30 between the first patterned photoresist layer 46. The metal layer 50 is made of Cu, Pd, Ni or Ni/Pd/Au and formed by the method of sputtering, evaporation, electroless plating, or plating. The metal layer 50 is used for electrically connecting the upper layer and the downward layer. After, a surface roughing treatment processing may be performed on the surface of the metal layer 50, wherein the surface roughing treatment process includes the method of micro etching, sand blasting, polishing, blackening, or browning.
  • Following, referring to FIG. 7, a second patterned photoresist layer 49 and a second photoresist layer 48 are respectively formed on the first patterned photoresist layer 46 and the downward surface of the first photoresist layer 44. Next, a metal surface treatment is performed on the surface of the metal layer 50. The metal surface treatment is performed by the method of printing, evaporation, sputtering, electroless plating, or plating. A metal treatment layer 60 formed by the metal surface treatment is made of Ni, Au, Ag, or Cu. Next, such as shown in FIG. 8, the second patterned photoresist layer 49, the second photoresist layer 48, the first patterned photoresist layer 46 and the first photoresist layer 44 are removed. In one embodiment, the metal layer 50 is dividing into a chip carrier area and conductive joints. In another embodiment, the metal layer 50 is only used for the conductive joints. Such as not shown in the figure, before the metal surface treatment and after filling the metal layer 50, the first patterned photoresist layer 46 and the first photoresist layer 44 may be removed firstly. Then, the second patterned photoresist layer 49 and the second photoresist layer 48 are respectively formed on the trenches and the downward surface of the carrier plate 10. After the metal surface treatment, the second patterned photoresist layer 49 and the second photoresist layer 48 are removed.
  • After, referring to FIG. 9, a chip packaging process is performed. A chip 70 is arranged on the chip carrier area and pluralities of leads 80 are used for electrically connecting the chip 70 and the conductive joints. Following, an encapsulant 90 is formed to cover the chip 70 and leads 80. Next, referring to FIG. 10 and FIG. 11, in the present embodiment, the carrier plate 10 and the adhesive layer 20 are removed and then a pad 62 is formed on the downward surface of the conductive layer 30 by utilizing the surface mount technology (SMT) method. The pad 62 is used for connecting with other electronics equipments. In one embodiment, it may only remove the carrier plate 10 and then form a pad on the downward surface of the adhesive layer 20 by utilizing the surface mount technology (SMT) method. In the present invention, the chip packaging process can utilize the wire bonding method or the flip chip bonding method.
  • FIG. 12 and FIG. 13 are schematic representations of the cross-section view illustrate another embodiment of the present invention. Referring to FIG. 12, comparing the difference of the embodiment above mentioned, in the present embodiment, the metal layer 50 is merely used for electrically connecting. An isolation layer 55 is formed on the adhesive layer 20 at the designated chip carrier area by utilizing the appropriate method, such as coating, for carrying the chip 70. As shown in FIG. 13, it could be understood that the chip 70 is arranged on the isolation layer 55 and the bonding height of the chip 70 and leads 80 could be different so as to resolve the disadvantage of the common lead frame that could not heighten the chip 70. Besides, owing to the chip 70 is arranged on the isolation layer 55, the short problem is prevented so as can enhance the flexibility of the PCB layout.
  • To sum up the forgoing, the present invention is to provide a fabrication method for a chip packaging structure that utilizes the plating metal way to connect different layers so as to replace the traditional way to drill hole and then plate metal in the hole. The metal in the conductive through hole is solid metal so as can provide good ability of heat sinking. The present invention utilizes the existing manufacturing processes of the package industry without extra process or equipment so as can decrease the PCB processes and lower the package cost.
  • While the present invention is susceptible to various modifications and alternative forms, a specific example thereof has been shown in the drawings and is herein described in detail. It should be understood, however, that the invention is not to be limited to the particular form disclosed, but to the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims.

Claims (21)

1. A fabrication method for a chip packaging structure comprising:
providing a carrier plate, wherein a conductive layer is formed on an upper surface of said carrier plate;
forming a plurality of trenches penetrating through said conductive layer by utilizing the photolithography process;
forming a first patterned photoresist layer on said upper surface and a first photoresist layer on a downward surface of said carrier plate, wherein said trenches are filled by said first patterned photoresist layer;
filling at least a metal layer on said conductive layer between said first patterned photoresist layer, wherein said metal layer includes a plurality of conductive joints;
performing a metal surface treatment on the surface of said metal layer;
removing said first patterned layer and said first photoresist layer; and
proceeding a chip packaging process.
2. The fabrication method for a chip packaging structure according to claim 1, further comprising providing an adhesive layer between said carrier plate and said conductive layer.
3. The fabrication method for a chip packaging structure according to claim 1, wherein said carrier plate is made of metal, glass, ceramic, or polymer material.
4. The fabrication method for a chip packaging structure according to claim 2, wherein said adhesive player is made of metal, conductive material, or polymer material.
5. The fabrication method for a chip packaging structure according to claim 1, wherein said metal layer is made of Cu, Pd, Ni or Ni/Pd/Au.
6. The fabrication method for a chip packaging structure according to claim 1, wherein said metal layer is formed by the method of sputtering, evaporation, electroless plating, or plating.
7. The fabrication method for a chip packaging structure according to claim 2, wherein said adhesive layer is formed by the method of adhering, laminating, printing, spray coating, spin coating, evaporation, sputtering, electroless plating, or plating.
8. The fabrication method for a chip packaging structure according to claim 1, wherein said conductive layer is formed by the method of adhering, laminating, printing, spray coating, spin coating, evaporation, sputtering, electroless plating, or plating.
9. The fabrication method for a chip packaging structure according to claim 1, further comprising a step of forming a second patterned photoresist layer on said first patterned photoresist layer and a second photoresist layer on the downward surface of said first photoresist layer.
10. The fabrication method for a chip packaging structure according to claim 1, wherein said first patterned photoresist layer and said first photoresist layer are formed by utilizing the photolithography process.
11. The fabrication method for a chip packaging structure according to claim 9, wherein said second patterned photoresist layer and said second photoresist layer are formed by utilizing the photolithography process.
12. The fabrication method for a chip packaging structure according to claim 1, wherein said metal surface treatment is utilizing the method of printing, evaporation, sputtering, electroless plating, or plating.
13. The fabrication method for a chip packaging structure according to claim 12, wherein a metal treatment layer formed by said metal surface treatment is made of Ni/Au, Ag, or Cu.
14. The fabrication method for a chip packaging structure according to claim 1, further comprising a surface roughing treatment process on said metal layer and said conductive layer.
15. The fabrication method for a chip packaging structure according to claim 14, wherein said surface roughing treatment process comprises the method of micro etching, sand blasting, polishing, blackening, or browning.
16. The fabrication method for a chip packaging structure according to claim 1, before performing metal surface treatment and after removing said patterned photoresist layer and said first photoresist layer, further comprising a step of forming a second patterned photoresist layer on said trench and a second photoresist layer on said downward surface of said carrier plate.
17. The fabrication method for a chip packaging structure according to claim 16, further comprising a step of removing said second patterned photoresist layer and said second photoresist layer before said chip packaging process.
18. The fabrication method for a chip packaging structure according to claim 1, wherein said chip packaging process comprising the following steps:
arranging at least one chip on a chip carrier area of said metal layer;
electrically connecting said conductive joints to said chip with a plurality of leads; and
forming a package encapsulant to cover said chip and said leads.
19. The fabrication method for a chip packaging structure according to claim 1, further comprising a step of forming an isolation layer between said conductive joints after said metal surface treatment.
20. The fabrication method for a chip packaging structure according to claim 19, wherein said chip packaging process comprising the following steps:
arranging at least one chip on a chip carrier area of said isolation layer;
electrically connecting said conductive joints to said chip with a plurality of leads; and
forming a package encapsulant to cover said chip and said leads.
21. The fabrication method for a chip packaging structure according to claim 1, wherein said chip packaging process is utilizing the wire bonding method or the flip chip bonding method.
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US20080157309A1 (en) * 2006-12-27 2008-07-03 Shinko Electric Industries Co., Ltd. Lead frame and method of manufacturing the same, and semiconductor device
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CN106783794A (en) * 2017-03-16 2017-05-31 江阴芯智联电子科技有限公司 It is pre-packaged without wire electrodepositable lead-frame packages structure and its manufacture method
CN109509734A (en) * 2018-12-21 2019-03-22 江阴芯智联电子科技有限公司 Subtractive process pre-packaged lead frame structure and its manufacturing method

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157309A1 (en) * 2006-12-27 2008-07-03 Shinko Electric Industries Co., Ltd. Lead frame and method of manufacturing the same, and semiconductor device
US7838972B2 (en) * 2006-12-27 2010-11-23 Shinko Electric Industries Co., Ltd. Lead frame and method of manufacturing the same, and semiconductor device
US20100210071A1 (en) * 2009-02-13 2010-08-19 Infineon Technologies Ag Method of manufacturing semiconductor devices
US8288207B2 (en) * 2009-02-13 2012-10-16 Infineon Technologies Ag Method of manufacturing semiconductor devices
US20150090688A1 (en) * 2013-09-27 2015-04-02 Avago Technologies General Ip (Singapore) Pte. Ltd Method of fabricating printed circuit board (pcb) substrate having a cavity
US9085826B2 (en) * 2013-09-27 2015-07-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Method of fabricating printed circuit board (PCB) substrate having a cavity
CN106783794A (en) * 2017-03-16 2017-05-31 江阴芯智联电子科技有限公司 It is pre-packaged without wire electrodepositable lead-frame packages structure and its manufacture method
CN109509734A (en) * 2018-12-21 2019-03-22 江阴芯智联电子科技有限公司 Subtractive process pre-packaged lead frame structure and its manufacturing method

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