US20070085172A1 - System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference - Google Patents
System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference Download PDFInfo
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- US20070085172A1 US20070085172A1 US11/608,249 US60824906A US2007085172A1 US 20070085172 A1 US20070085172 A1 US 20070085172A1 US 60824906 A US60824906 A US 60824906A US 2007085172 A1 US2007085172 A1 US 2007085172A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates generally to the field of system-on-chip (SoC) technology and, more particularly, to a system-on-chip with shield rings surrounding the specific functional blocks such as analogy/mixed-signal, RF signal, and/or memory blocks for the purposes of eliminating electromagnetic or static electricity interference.
- SoC system-on-chip
- SoC system-on-chip
- SoC SoC applications, it is desirable to integrate many functional blocks into a single integrated circuit.
- the most commonly used blocks include a microprocessor or micro-controller, static random access memory (SRAM) blocks, non-volatile memory blocks, and various special function logic blocks.
- SRAM static random access memory
- Electromagnetic interference (EMI) and signal coupling caused by EMI are becoming exceptionally crucial issues in the design of modern SoC systems.
- a system-on-chip (SoC) with EMI shield rings therein at least includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference.
- the EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart.
- a shield structure in a chip includes a first rampart consisting of a plurality of metal layers and a plurality of via layers.
- the first rampart has a first connection window, wherein the shield structure shields a pre-selected region of the chip, and wherein at least one serpentine signal line passes through the first connection window.
- FIG. 1 is a schematic functional block diagram illustrating an exemplary system-on-chip (SoC) in accordance with one preferred embodiment of the present invention
- FIG. 2 is a schematic cross-section taken along line I-I′ of FIG. 1 ;
- FIG. 3 is a schematic top view showing a portion of the shield ring at the analog/digital interface of the SoC;
- FIG. 4 is a cross-sectional view of FIG. 3 along line II-II;
- FIGS. 5-7 are schematic diagrams illustrating variations of the shield ring structure in accordance with preferred embodiments of this invention.
- FIG. 9 are schematic top views illustrating the preferred analog/digital connection windows, channels or paths and corresponding signal lines passing therethrough according to this invention.
- FIG. 1 is a schematic functional block diagram illustrating an exemplary system-on-chip (SoC) 10 in accordance with one preferred embodiment of the present invention.
- the exemplary dual-core SoC 10 which may be suited to portable communications or multimedia applications, generally comprises an embedded processor core 12 , a digital signal processor (DSP) 14 , an on-chip memory block 16 , an on-chip bus interface 18 , an MPEG decoder 20 , and an analog/mixed-signal block 22 .
- the aforesaid functional blocks are integrated and fabricated on one single chip.
- the configuration of the SoC 10 as set forth in FIG. 1 is presented only for illustration purposes, and should not be limiting. In another SoC configuration, an RF signal integrated circuit may be provided for other application purposes.
- the embedded processor core 12 may be a 16/32-bit RISC (abbr. of “reduced instruction set computer”) microprocessor available from ARM limited.
- the on-chip memory block 16 may consist of a dynamic random access memory (DRAM), non-volatile memory (NVM) or the like.
- DRAM dynamic random access memory
- NVM non-volatile memory
- the salient feature of the present invention is that, as specifically indicated in FIG. 1 , the on-chip memory block 16 is deliberately surrounded by a shield ring 160 , and the analog/mixed-signal block 22 is deliberately surrounded by a shield ring 220 .
- the shield ring 160 and shield ring 220 are both grounded to create a screen to avoid signal coupling caused by electromagnetic interference resulting from the digital clock circuits that are driven at high speeds.
- a schematic cross-section taken along line I-I′ of FIG. 1 is demonstrated in FIG. 2 .
- the demonstrated shield ring 220 comprises a metal rampart 240 encircling the schematic analog/mixed-signal integrated circuit 250 .
- the metal rampart 240 is a stacked wall fabricated layer by layer including, from bottom to top, the contact layer (denoted as “CONT”), the first layer metal (M 1 ), the first via layer (V 1 ), the second layer metal (M 2 ), the second via layer (V 2 ), the third layer metal (M 3 ), the third via layer (V 3 ), and the fourth metal layer (M 4 ).
- a pick up diffusion 260 is provided in the silicon-on insulator (SOI) substrate 280 to connect the metal rampart 240 .
- the pick up diffusion 260 is implanted into the substrate 280 at positions adjacent to the shallow trench isolation (STI).
- a pad layer 290 is provided to connect the shield ring 220 with a ground line.
- FIG. 3 is a schematic top view showing a portion of the shield ring at the analog/digital interface of the SoC.
- FIG. 4 is a cross-sectional view of FIG. 3 along line II-II′.
- the metal rampart 240 consisting of multi-layer metals and vias has a digital/analogy (A/D) connection window 300 , which allows DSP 14 to communicate with the shielded analog/mixed-signal block 22 through a signal line 320 passing therethrough.
- the position of the A/D connection window 300 is remote from the main working signal line of the analog/mixed-signal integrated circuit.
- the signal line 320 may be accompanied with two adjacent grounded lines 340 , which are formed at the same metal layer, for example, the fourth metal layer (M 4 ), as the signal line 320 , and are disposed at opposite sides of the signal line 320 with a minimum rule.
- the signal coupling effect on the signal line 320 which results from the high-speed digital clock, can be alleviated.
- FIG. 5 is a schematic diagram illustrating a variation of the shield ring structure in accordance with one embodiment of this invention.
- the shield ring structure 420 is disposed at the center of the chip 400 , which surrounds a shielded region 410 such as an on-chip memory block or an analog/mixed-signal block.
- a seal ring 440 is disposed along perimeter of the chip 400 .
- the seal ring 440 provides the chip 400 with protection from stress during wafer dicing.
- the grounded shield ring structure 420 is grounded to create a screen to avoid signal coupling caused by electromagnetic interference resulting from the digital clock circuits of the chip 400 driven at high speeds.
- the shield ring structure 420 may be a double-ring structure comprising two layers of ramparts.
- the signal lines passing through the shield ring structure 420 are not explicitly shown.
- the signal lines passing through the metal rampart of the shield ring structure 420 may be at the same level or different levels.
- the signal lines may pass through corresponding analog/digital connection windows.
- two signal lines may pass through one analog/digital connection windows, wherein one signal line may be situated directed above the other.
- FIG. 6 is a schematic diagram illustrating another variation of the shield ring structure in accordance with one embodiment of this invention.
- the shielded region 410 such as on-chip memory blocks or analog/mixed-signal blocks is situated at one corner of the chip 400 .
- the shielded region 410 has four sides. Two consecutive sides of the shielded region 410 are shielded by the seal ring 440 . The other two sides of the shielded region 410 are shielded by the two-side rampart 420 a .
- a complementary shield ring 460 is disposed along the remanent seal ring 440 and along the two-side shield ring 420 .
- the shield ring structure 420 may be a double-ring structure comprising an inner layer and an outer layer of ramparts.
- FIG. 7 is a schematic diagram illustrating still another variation of the shield ring structure in accordance with one embodiment of this invention.
- the shielded region 410 such as on-chip memory blocks or analog/mixed-signal blocks is situated at one corner of the chip 400 .
- the shielded region 410 is surrounded by a four-side shield ring 420 .
- the four-side shield ring 420 is further surrounded by a two-side complementary shield ring 460 and the seal ring 440 .
- the two-side complementary shield ring 460 is connected with the seal ring 440 .
- FIG. 8 and FIG. 9 are schematic top views illustrating the preferred analog/digital connection windows, channels or paths and corresponding signal lines passing therethrough according to this invention.
- FIG. 8 an enlarged portion of metal rampart of shield ring 520 is demonstrated.
- a serpentine analog/digital connection channel 500 extends from one side of the metal rampart of shield ring 520 to the other.
- a signal line 540 penetrates the metal rampart of shield ring 520 through the serpentine analog/digital connection channel 500 .
- At least one dielectric layer 560 is interposed between the signal line 540 and the metal rampart of shield ring 520 .
- the serpentine analog/digital connection channel 500 can reduce noise leakage.
- an inner metal rampart of shield ring 520 a is surrounded by an outer metal rampart of shield ring 520 b .
- the inner metal rampart of shield ring 520 a has an analog/digital connection window 530 a .
- the outer metal rampart of shield ring 520 b has an analog/digital connection window 530 b that is not aligned with the analog/digital connection window 530 a .
- a signal line 540 passes through the analog/digital connection windows 530 a and 520 b .
- the analog/digital connection windows 530 a and 520 b may be formed at different levels. It is understood that the serpentine analog/digital connection channel 500 depicted in FIG. 8 may be formed in at least one of the metal rampart of shield ring 520 a and 520 b.
Abstract
Description
- This is a continuation-in-part of U.S. application Ser. No. 10/906,583 filed Feb. 25, 2005.
- 1. Field of the Invention
- The present invention relates generally to the field of system-on-chip (SoC) technology and, more particularly, to a system-on-chip with shield rings surrounding the specific functional blocks such as analogy/mixed-signal, RF signal, and/or memory blocks for the purposes of eliminating electromagnetic or static electricity interference.
- 2. Description of the Prior Art
- Today the functionality and economics of many consumer products are being transformed by “system-on-chip” (SoC) technology. The continuing increase in the transistor densities means that it is now possible to integrate the processor, peripherals and some or all of the system memory on a single chip.
- For SoC applications, it is desirable to integrate many functional blocks into a single integrated circuit. The most commonly used blocks include a microprocessor or micro-controller, static random access memory (SRAM) blocks, non-volatile memory blocks, and various special function logic blocks.
- Frequencies are continuously increasing, while integration trends are squeezing entire systems into extraordinary high circuit densities. Electromagnetic interference (EMI) and signal coupling caused by EMI are becoming exceptionally crucial issues in the design of modern SoC systems.
- In light of the above, there is a need in this industry to provide a solution that the EMI problems can be addressed or eliminated as early as possible during the design phase both on the aspect of the cost and on aspect of the time-to-market of the products.
- It is therefore a primary object of the present invention to provide an improved system-on-chip design to solve the above-mentioned problems.
- It is another object of the present invention to provide a system-on-chip that is immune to electromagnetic interference and static electricity interference.
- According to the claimed invention, a system-on-chip (SoC) with EMI shield rings therein is provided. The SoC at least includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart.
- From one aspect of this invention, a shield structure in a chip is provided. The shield structure includes a first rampart consisting of a plurality of metal layers and a plurality of via layers. The first rampart has a first connection window, wherein the shield structure shields a pre-selected region of the chip, and wherein at least one serpentine signal line passes through the first connection window.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
-
FIG. 1 is a schematic functional block diagram illustrating an exemplary system-on-chip (SoC) in accordance with one preferred embodiment of the present invention; -
FIG. 2 is a schematic cross-section taken along line I-I′ ofFIG. 1 ; -
FIG. 3 is a schematic top view showing a portion of the shield ring at the analog/digital interface of the SoC; -
FIG. 4 is a cross-sectional view ofFIG. 3 along line II-II; -
FIGS. 5-7 are schematic diagrams illustrating variations of the shield ring structure in accordance with preferred embodiments of this invention; and -
FIG. 9 are schematic top views illustrating the preferred analog/digital connection windows, channels or paths and corresponding signal lines passing therethrough according to this invention. -
FIG. 1 is a schematic functional block diagram illustrating an exemplary system-on-chip (SoC) 10 in accordance with one preferred embodiment of the present invention. As shown inFIG. 1 , the exemplary dual-core SoC 10, which may be suited to portable communications or multimedia applications, generally comprises an embeddedprocessor core 12, a digital signal processor (DSP) 14, an on-chip memory block 16, an on-chip bus interface 18, anMPEG decoder 20, and an analog/mixed-signal block 22. The aforesaid functional blocks are integrated and fabricated on one single chip. It is to be understood that the configuration of theSoC 10 as set forth inFIG. 1 is presented only for illustration purposes, and should not be limiting. In another SoC configuration, an RF signal integrated circuit may be provided for other application purposes. - By way of example, the embedded
processor core 12 may be a 16/32-bit RISC (abbr. of “reduced instruction set computer”) microprocessor available from ARM limited. The on-chip memory block 16 may consist of a dynamic random access memory (DRAM), non-volatile memory (NVM) or the like. The salient feature of the present invention is that, as specifically indicated inFIG. 1 , the on-chip memory block 16 is deliberately surrounded by ashield ring 160, and the analog/mixed-signal block 22 is deliberately surrounded by ashield ring 220. - In operation, the
shield ring 160 andshield ring 220 are both grounded to create a screen to avoid signal coupling caused by electromagnetic interference resulting from the digital clock circuits that are driven at high speeds. To explain theaforesaid shield rings FIG. 1 is demonstrated inFIG. 2 . - As shown in
FIG. 2 , the demonstratedshield ring 220 comprises ametal rampart 240 encircling the schematic analog/mixed-signal integratedcircuit 250. Themetal rampart 240 is a stacked wall fabricated layer by layer including, from bottom to top, the contact layer (denoted as “CONT”), the first layer metal (M1), the first via layer (V1), the second layer metal (M2), the second via layer (V2), the third layer metal (M3), the third via layer (V3), and the fourth metal layer (M4). At the bottom of theshield ring 220, apick up diffusion 260 is provided in the silicon-on insulator (SOI)substrate 280 to connect themetal rampart 240. Thepick up diffusion 260 is implanted into thesubstrate 280 at positions adjacent to the shallow trench isolation (STI). At the top of theshield ring 220, apad layer 290 is provided to connect theshield ring 220 with a ground line. - Please refer to
FIG. 3 andFIG. 4 .FIG. 3 is a schematic top view showing a portion of the shield ring at the analog/digital interface of the SoC.FIG. 4 is a cross-sectional view ofFIG. 3 along line II-II′. As shown inFIG. 3 andFIG. 4 , themetal rampart 240 consisting of multi-layer metals and vias has a digital/analogy (A/D)connection window 300, which allows DSP 14 to communicate with the shielded analog/mixed-signal block 22 through asignal line 320 passing therethrough. Preferably, the position of the A/D connection window 300 is remote from the main working signal line of the analog/mixed-signal integrated circuit. - Alternatively, as specifically indicated in
FIG. 3 , thesignal line 320 may be accompanied with two adjacentgrounded lines 340, which are formed at the same metal layer, for example, the fourth metal layer (M4), as thesignal line 320, and are disposed at opposite sides of thesignal line 320 with a minimum rule. By doing this, the signal coupling effect on thesignal line 320, which results from the high-speed digital clock, can be alleviated. -
FIG. 5 is a schematic diagram illustrating a variation of the shield ring structure in accordance with one embodiment of this invention. As shown inFIG. 5 , theshield ring structure 420 is disposed at the center of thechip 400, which surrounds a shieldedregion 410 such as an on-chip memory block or an analog/mixed-signal block. Aseal ring 440 is disposed along perimeter of thechip 400. Theseal ring 440 provides thechip 400 with protection from stress during wafer dicing. The groundedshield ring structure 420 is grounded to create a screen to avoid signal coupling caused by electromagnetic interference resulting from the digital clock circuits of thechip 400 driven at high speeds. Theshield ring structure 420 may be a double-ring structure comprising two layers of ramparts. - The signal lines passing through the
shield ring structure 420 are not explicitly shown. The signal lines passing through the metal rampart of theshield ring structure 420 may be at the same level or different levels. The signal lines may pass through corresponding analog/digital connection windows. Alternatively, two signal lines may pass through one analog/digital connection windows, wherein one signal line may be situated directed above the other. -
FIG. 6 is a schematic diagram illustrating another variation of the shield ring structure in accordance with one embodiment of this invention. As shown inFIG. 6 , the shieldedregion 410 such as on-chip memory blocks or analog/mixed-signal blocks is situated at one corner of thechip 400. The shieldedregion 410 has four sides. Two consecutive sides of the shieldedregion 410 are shielded by theseal ring 440. The other two sides of the shieldedregion 410 are shielded by the two-side rampart 420 a. Acomplementary shield ring 460 is disposed along theremanent seal ring 440 and along the two-side shield ring 420. Likewise, theshield ring structure 420 may be a double-ring structure comprising an inner layer and an outer layer of ramparts. -
FIG. 7 is a schematic diagram illustrating still another variation of the shield ring structure in accordance with one embodiment of this invention. As shown inFIG. 7 , the shieldedregion 410 such as on-chip memory blocks or analog/mixed-signal blocks is situated at one corner of thechip 400. The shieldedregion 410 is surrounded by a four-side shield ring 420. The four-side shield ring 420 is further surrounded by a two-sidecomplementary shield ring 460 and theseal ring 440. The two-sidecomplementary shield ring 460 is connected with theseal ring 440. -
FIG. 8 andFIG. 9 are schematic top views illustrating the preferred analog/digital connection windows, channels or paths and corresponding signal lines passing therethrough according to this invention. As shown inFIG. 8 , an enlarged portion of metal rampart ofshield ring 520 is demonstrated. A serpentine analog/digital connection channel 500 extends from one side of the metal rampart ofshield ring 520 to the other. Asignal line 540 penetrates the metal rampart ofshield ring 520 through the serpentine analog/digital connection channel 500. At least onedielectric layer 560 is interposed between thesignal line 540 and the metal rampart ofshield ring 520. The serpentine analog/digital connection channel 500 can reduce noise leakage. - As shown in
FIG. 9 , an inner metal rampart ofshield ring 520 a is surrounded by an outer metal rampart ofshield ring 520 b. The inner metal rampart ofshield ring 520 a has an analog/digital connection window 530 a. The outer metal rampart ofshield ring 520 b has an analog/digital connection window 530 b that is not aligned with the analog/digital connection window 530 a. Asignal line 540 passes through the analog/digital connection windows digital connection windows digital connection channel 500 depicted inFIG. 8 may be formed in at least one of the metal rampart ofshield ring - Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (12)
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US11/608,249 US7786546B2 (en) | 2005-02-25 | 2006-12-08 | System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference |
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US10/906,583 US7170144B2 (en) | 2005-02-25 | 2005-02-25 | System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference |
US11/608,249 US7786546B2 (en) | 2005-02-25 | 2006-12-08 | System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference |
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US10/906,583 Continuation-In-Part US7170144B2 (en) | 2005-02-25 | 2005-02-25 | System-on-chip with shield rings for shielding functional blocks therein from electromagnetic interference |
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US20080048228A1 (en) * | 2006-08-22 | 2008-02-28 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
US20150014828A1 (en) * | 2013-07-11 | 2015-01-15 | United Microelectronics Corp. | Semiconductor Device Having Shielding Structure |
CN105609486A (en) * | 2015-12-25 | 2016-05-25 | 电子科技大学 | Ground shielding structure for millimeter wave/terahertz multi-metal layer semiconductor device |
EP2311087B1 (en) * | 2008-07-01 | 2018-08-22 | Xmos Ltd | Integrated circuit structure |
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US8803290B2 (en) * | 2008-10-03 | 2014-08-12 | Qualcomm Incorporated | Double broken seal ring |
US9888562B2 (en) | 2012-12-24 | 2018-02-06 | Apple Inc. | Electromagnetic interference shielding and strain relief structures for coupled printed circuits |
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US20150014828A1 (en) * | 2013-07-11 | 2015-01-15 | United Microelectronics Corp. | Semiconductor Device Having Shielding Structure |
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CN105609486A (en) * | 2015-12-25 | 2016-05-25 | 电子科技大学 | Ground shielding structure for millimeter wave/terahertz multi-metal layer semiconductor device |
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