US20060281311A1 - Integrated circuitry - Google Patents

Integrated circuitry Download PDF

Info

Publication number
US20060281311A1
US20060281311A1 US11/254,680 US25468005A US2006281311A1 US 20060281311 A1 US20060281311 A1 US 20060281311A1 US 25468005 A US25468005 A US 25468005A US 2006281311 A1 US2006281311 A1 US 2006281311A1
Authority
US
United States
Prior art keywords
layer
silicon nitride
silicon dioxide
forming
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/254,680
Inventor
Shane Trapp
Brian Lawlor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/254,680 priority Critical patent/US20060281311A1/en
Publication of US20060281311A1 publication Critical patent/US20060281311A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Definitions

  • This invention relates to methods of forming integrated circuitry, to methods of forming contact openings, and to integrated circuitry.
  • Semiconductor processing often involves the deposition of films or layers over or on a semiconductor substrate surface which may or may not have other layers already formed thereon.
  • portions of an outer layer are masked, typically using photoresist, to provide a desired pattern over the outer layer.
  • An underlying layer is then removed by chemical etching through the mask opening, with the mask covering and protecting other areas from the etching.
  • some layers are removed by mechanical polishing action or by chemical mechanical polishing action. In many such instances, it is also desirable to remove one or more layers while stopping on some immediately underlying layer.
  • the invention includes methods of forming integrated circuitry, methods of forming contact openings, and integrated circuitry.
  • a silicon nitride comprising layer is formed over a semiconductor substrate.
  • the silicon nitride comprising layer includes Al, Ga or a mixture thereof.
  • a silicon dioxide comprising layer is formed proximate the silicon nitride comprising layer.
  • the silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal.
  • a substantially undoped silicon dioxide comprising layer is formed over a semiconductor substrate.
  • the substantially undoped silicon dioxide comprising layer includes B, Al, Ga or mixtures thereof.
  • a doped silicon dioxide comprising layer is formed proximate the substantially undoped silicon dioxide comprising layer.
  • the doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal.
  • integrated circuitry includes a pair of spaced conductive device components received over a substrate, with such at least partially defining a node location there between.
  • Each device component has at least one sidewall which faces the other device component of the pair.
  • An insulative material mass is received over each of the sidewalls.
  • the masses are laterally spaced from one another in a non-contacting relationship.
  • the masses comprise a first insulative material comprising B, Al, Ga or mixtures thereof.
  • a conductive contact is received between the insulative material masses in electrical connection with the node location.
  • FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.
  • FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1 .
  • FIG. 3 is a view of the FIG. 1 wafer fragment at an alternate processing step to that shown by FIG. 2 .
  • FIG. 4 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2 .
  • FIG. 5 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 4 .
  • FIG. 6 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 5 .
  • FIG. 7 is a diagrammatic sectional view of an alternate embodiment semiconductor wafer fragment in process in accordance with an aspect of the invention.
  • FIG. 8 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 7 .
  • FIG. 9 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 8 .
  • FIG. 10 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 9 .
  • FIG. 11 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 10 .
  • FIG. 12 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 11 .
  • FIG. 1 depicts a wafer fragment 10 comprising a bulk monocrystalline silicon substrate region 12 .
  • semiconductor substrate or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • the term “layer” encompasses both the singular and the plural unless otherwise indicated.
  • a pad oxide layer 14 is formed over semiconductor substrate 12 .
  • a silicon nitride comprising layer 16 is formed over pad oxide layer 14 and semiconductor substrate 12 .
  • An exemplary thickness range for layer 14 is from 50 Angstroms to 150 Angstroms, while an exemplary thickness range for layer 16 is from 400 Angstroms to 1200 Angstroms.
  • Silicon nitride comprising layer 16 has an outer surface 18 .
  • At least one enriched region 20 is formed within silicon nitride comprising layer 16 .
  • Enriched region 20 is characterized at least by the presence of Al, Ga or mixture thereof.
  • One preferred method of forming enriched region 20 is by ion implanting at least one of Al and Ga into silicon nitride comprising layer 16 .
  • Another preferred method is by plasma enhanced or gas phase thermal diffusion.
  • An exemplary diffusion species for aluminum is trimethyl aluminum, while an exemplary diffusion species for gallium is trimethyl gallium.
  • enriched region 20 extends to at least a portion of outer surface 18 , with FIG. 2 depicting region 20 extending to all of outer surface 20 .
  • An example preferred implant is to place a peak concentration depth from about 10 Angstroms to about 400 Angstroms beneath outer surface 18 .
  • trimethyl aluminum and trimethyl gallim would be exemplary implant species.
  • Exemplary doses are from 5 ⁇ 10 12 ions/cm 2 to 15 ⁇ 10 12 ions/cm 2 , with a narrower preferred range being from 10 ⁇ 10 12 ions/cm 2 to 12 ⁇ 10 12 ions/cm 2 .
  • Exemplary implant energies are from 2 KeV to 25 Kev.
  • FIG. 3 depicts an alternate preferred embodiment wafer fragment 10 a whereby enriched region 20 a is spaced from outer surface 18 .
  • regions 20 and 20 a might also be formed by methods other than ion implanting or gas phase diffusion, for example and by way of example only such as during the deposition of layer 16 (i.e., during chemical vapor deposition) or by deposition of a separate layer thereover.
  • the forming of said silicon nitride comprising layer might comprise chemical vapor deposition over a previously deposited layer consisting essentially of silicon nitride.
  • layers 16 and 14 have been patterned to form an opening 22 therethrough and into semiconductor substrate 12 .
  • a silicon dioxide comprising layer 24 is formed proximate silicon nitride comprising layer 16 and, in the preferred embodiment as shown, is formed on (in contact with) silicon nitride comprising layer 16 .
  • Silicon dioxide comprising layer 24 might be doped or substantially undoped.
  • doped means doping with one or both of phosphorous and boron, and to a total dopant concentration of one or more of such materials to at least 1% by weight average.
  • “Substantially undoped” means a total combined doping of boron and/or phosphorous, if any, at less than 1% by weight.
  • silicon dioxide comprising layer 24 is removed substantially selectively relative to silicon nitride comprising layer 16 , with the at least one enriched region 20 preferably enhancing selectivity to silicon nitride comprising layer 16 during the removing.
  • Such removing is preferably by chemical etching, or by other techniques for example by polishing.
  • substantially selectively means a removal rate of one material relative to another of at least 1.5:1.
  • an exemplary process for etching silicon dioxide selectively relative to silicon nitride where region 20 facilitates selectivity in the etch includes a TEL DRM reactive ion etcher, operated at 1500 W, 45 mTorr, Ar flow at 500 sccm, C 4 F 8 flow at 12 sccm, and CH 2 F 2 flow at 6 sccm.
  • Regions 20 / 20 a might, of course, in the depicted first exemplary embodiment, be formed prior to or subsequent to fabrication of the exemplary opening 22 . Further, in one preferred embodiment, silicon nitride comprising layer 16 with enriched region 20 / 20 a can be annealed prior to the removing action. Such might be desirable to facilitate migration of the gallium or aluminum to bond sites within silicon nitride comprising layer 16 . Any alternate or additional fabrication is also contemplated in the context of the accompanying claims.
  • the invention also contemplates forming integrated circuitry comprising forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate.
  • At least one enriched region analogous to regions 20 and 20 a in the above-described first preferred silicon nitride comprising layer embodiment is formed within the substantially undoped silicon dioxide comprising layer.
  • the enriched region comprises B, Al, Ga or mixtures thereof.
  • An exemplary diffusion species for Boron is diborane, while an exemplary implant species for boron is B 11 .
  • a doped silicon dioxide comprising layer is formed proximate, and more preferably on, the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer.
  • the at least one enriched region preferably enhances selectivity to the substantially undoped silicon dioxide comprising layer during the removing.
  • removing is preferably by chemical etching, with removal by polishing or other techniques also of course being contemplated.
  • an exemplary process for etching doped silicon dioxide selectively relative to substantially undoped silicon dioxide where region 20 facilitates selectivity in the etch includes a 12 Liter Applied Materials 5000 Etch Chamber, operated at 1000 W, 50 mTorr, Ar flow at 120 sccm, CF 4 flow at 30 sccm, CHF 3 flow at 50 sccm, and CH 2 F 2 flow at 15 sccm.
  • the invention also more generically contemplates forming a silicon nitride comprising layer also comprising Al, Ga or a mixture thereof.
  • a silicon nitride comprising layer also comprising Al, Ga or a mixture thereof.
  • Such Al, Ga or a mixture thereof might be present in the silicon nitride comprising layer as an enriched region, as described in the above preferred embodiments, or such might be substantially homogeneously distributed within the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the subject removing.
  • the invention also more generically contemplates B, Al, Ga or mixtures thereof being present within the substantially undoped silicon dioxide comprising layer, with such enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing.
  • the B, Al, Ga or mixtures thereof might be present as an enriched region or portion thereof, or might be substantially homogeneously distributed within the substantially undoped silicon dioxide comprising layer.
  • FIG. 7 depicts a semiconductor wafer fragment 40 comprising a bulk monocrystalline silicon substrate 42 .
  • a pair of field effect transistor gate stacks 44 and 46 are shown formed over substrate 42 .
  • Such respectively comprise a gate dielectric layer 48 , a conductive polysilicon portion 50 , an overlying higher conductive silicide layer 52 , and an overlying insulative cap 54 .
  • Regions 50 and 52 constitute the conductive portion of stacks 44 and 46 , and depict an exemplary pair of spaced conductive device components formed over semiconductor substrate 42 .
  • any alternate pair of spaced conductive device components are contemplated.
  • spaced conductive device components 50 / 52 have at least one sidewall 56 which faces the other device component of the pair.
  • This particular preferred embodiment is described in conjunction with a method of forming a contact opening within insulative material to a node location, for example location 60 , located between conductive device components 50 / 52 of each stack 44 and 46 .
  • an insulative layer 62 is formed over device components 50 / 52 and on substrate material 42 between the device components.
  • layer 62 comprises silicon nitride.
  • insulative layer 62 comprises substantially undoped silicon dioxide.
  • a continuous enriched outer region 64 comprising B, Al, Ga or mixtures thereof is formed. Exemplary techniques for forming the same include those as described above.
  • outer region 64 is formed to be continuous, and also to extend to at least a portion of, and to the entirety of as shown, the outer surfaces of insulative layer 62 .
  • layer 62 has been anisotropically etched, preferably without any photomasking, effective to form insulative material masses 66 , 68 , 70 and 72 in the form of insulative spacers, with insulative masses 68 and 70 being formed over facing sidewalls 56 of conductive device components 50 / 52 .
  • Such insulative material masses have lateral outer surfaces 74 extending from bases thereof proximate substrate 42 to the tops of the illustrated constructions.
  • Spacers 66 , 68 , 70 and 72 also comprise respective enriched lateral outer regions 76 comprising B, Al, Ga or mixtures thereof.
  • insulative material masses over each of sidewalls 56 , with the preferred masses being laterally spaced from one another in a non-contacting relationship. Any alternate existing or yet-to-be-developed method of forming insulative masses is also contemplated.
  • enriched lateral outer regions 76 extend to at least a portion of the respective outer lateral surfaces 74 , and are elevationally spaced from substrate material 42 between the device components.
  • a second insulative material 80 is formed between insulative material masses 68 and 70 , and otherwise preferably over the substrate as shown.
  • insulative masses 68 and 70 comprise substantially undoped silicon dioxide
  • one preferred material for layer 80 is doped silicon dioxide.
  • insulative masses 68 and 70 comprise silicon nitride
  • two exemplary materials for layer 80 include doped silicon dioxide and substantially undoped silicon dioxide.
  • a contact opening 82 is etched into insulative material 80 to node location 60 between insulative material masses 68 , 70 substantially selectively relative thereto.
  • Lateral outer enriched regions 76 preferably enhance selectivity to the insulative masses during such etching.
  • the invention contemplates inclusion of B, Al, Ga or mixtures thereof within insulative material masses 68 , 70 whether in enriched regions 76 as shown, substantially homogeneously distributed within the insulative material masses, or otherwise.
  • conductive material 86 is shown having been formed within contact opening 82 between insulative material masses 68 and 70 in electrical connection with node location 60 .
  • Such might be provided by the provision of one or more conductive layers which, in the preferred embodiment, shows the formation of a conductive contact to a node location 60 .
  • Node location 60 might be a diffusion region, or any node location constituting a portion of integrated circuitry being formed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

Description

    RELATED PATENT DATA
  • This patent resulted from a continuation application of U.S. patent application Ser. No. 10/391,952, filed Mar. 18, 2003, entitled “Integrated Circuitry”, naming Shane J. Trapp and Brian F. Lawlor as inventors, the disclosure of which is incorporated by reference; which patent resulted from a divisional application of U.S. patent application Ser. No. 09/924,816, filed Aug. 7, 2001, entitled “Integrated Circuitry”, naming Shane J. Trapp and Brian F. Lawlor as inventors, now U.S. Pat. No. 6,806,197, the disclosure of which is incorporated by reference.
    • TECHNICAL FIELD
  • This invention relates to methods of forming integrated circuitry, to methods of forming contact openings, and to integrated circuitry.
    • BACKGROUND OF THE INVENTION
  • Semiconductor processing often involves the deposition of films or layers over or on a semiconductor substrate surface which may or may not have other layers already formed thereon. In typical circuitry fabrication, portions of an outer layer are masked, typically using photoresist, to provide a desired pattern over the outer layer. An underlying layer is then removed by chemical etching through the mask opening, with the mask covering and protecting other areas from the etching. Often it is desirable to etch an outer layer or layers selectively relative to an underlying layer. Accordingly, materials on the substrate, etch chemistry and conditions are continually being developed and improved to achieve a manner by which the desired layer(s) can be etched while stopping and substantially not etching an underlying layer.
  • Also, some layers are removed by mechanical polishing action or by chemical mechanical polishing action. In many such instances, it is also desirable to remove one or more layers while stopping on some immediately underlying layer.
    • SUMMARY
  • The invention includes methods of forming integrated circuitry, methods of forming contact openings, and integrated circuitry. In one implementation, a silicon nitride comprising layer is formed over a semiconductor substrate. The silicon nitride comprising layer includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate the silicon nitride comprising layer. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal.
  • In one implementation, a substantially undoped silicon dioxide comprising layer is formed over a semiconductor substrate. The substantially undoped silicon dioxide comprising layer includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal.
  • In one implementation, integrated circuitry includes a pair of spaced conductive device components received over a substrate, with such at least partially defining a node location there between. Each device component has at least one sidewall which faces the other device component of the pair. An insulative material mass is received over each of the sidewalls. The masses are laterally spaced from one another in a non-contacting relationship. The masses comprise a first insulative material comprising B, Al, Ga or mixtures thereof. A conductive contact is received between the insulative material masses in electrical connection with the node location.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment in process in accordance with an aspect of the invention.
  • FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.
  • FIG. 3 is a view of the FIG. 1 wafer fragment at an alternate processing step to that shown by FIG. 2.
  • FIG. 4 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2.
  • FIG. 5 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 4.
  • FIG. 6 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 5.
  • FIG. 7 is a diagrammatic sectional view of an alternate embodiment semiconductor wafer fragment in process in accordance with an aspect of the invention.
  • FIG. 8 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 7.
  • FIG. 9 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 8.
  • FIG. 10 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 9.
  • FIG. 11 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 10.
  • FIG. 12 is a view of the FIG. 7 wafer fragment at an alternate processing step to that shown by FIG. 11.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
  • Exemplary preferred embodiments of forming integrated circuitry are initially described with reference to FIGS. 1-6. FIG. 1 depicts a wafer fragment 10 comprising a bulk monocrystalline silicon substrate region 12. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated.
  • A pad oxide layer 14 is formed over semiconductor substrate 12. A silicon nitride comprising layer 16 is formed over pad oxide layer 14 and semiconductor substrate 12. An exemplary thickness range for layer 14 is from 50 Angstroms to 150 Angstroms, while an exemplary thickness range for layer 16 is from 400 Angstroms to 1200 Angstroms. Silicon nitride comprising layer 16 has an outer surface 18.
  • Referring to FIG. 2, at least one enriched region 20 is formed within silicon nitride comprising layer 16. Enriched region 20 is characterized at least by the presence of Al, Ga or mixture thereof. One preferred method of forming enriched region 20 is by ion implanting at least one of Al and Ga into silicon nitride comprising layer 16. Another preferred method is by plasma enhanced or gas phase thermal diffusion. An exemplary diffusion species for aluminum is trimethyl aluminum, while an exemplary diffusion species for gallium is trimethyl gallium. Preferably, enriched region 20 extends to at least a portion of outer surface 18, with FIG. 2 depicting region 20 extending to all of outer surface 20. An example preferred implant is to place a peak concentration depth from about 10 Angstroms to about 400 Angstroms beneath outer surface 18. Again, trimethyl aluminum and trimethyl gallim would be exemplary implant species. Exemplary doses are from 5×1012 ions/cm2 to 15×1012 ions/cm2, with a narrower preferred range being from 10×1012 ions/cm2 to 12×1012 ions/cm2. Exemplary implant energies are from 2 KeV to 25 Kev. FIG. 3 depicts an alternate preferred embodiment wafer fragment 10 a whereby enriched region 20 a is spaced from outer surface 18. Of course, regions 20 and 20 a might also be formed by methods other than ion implanting or gas phase diffusion, for example and by way of example only such as during the deposition of layer 16 (i.e., during chemical vapor deposition) or by deposition of a separate layer thereover. For example, and by way of example only, the forming of said silicon nitride comprising layer might comprise chemical vapor deposition over a previously deposited layer consisting essentially of silicon nitride.
  • Referring to FIG. 4, layers 16 and 14 have been patterned to form an opening 22 therethrough and into semiconductor substrate 12.
  • Referring to FIG. 5, a silicon dioxide comprising layer 24 is formed proximate silicon nitride comprising layer 16 and, in the preferred embodiment as shown, is formed on (in contact with) silicon nitride comprising layer 16. Silicon dioxide comprising layer 24 might be doped or substantially undoped. In the context of this document, “doped” means doping with one or both of phosphorous and boron, and to a total dopant concentration of one or more of such materials to at least 1% by weight average. “Substantially undoped” means a total combined doping of boron and/or phosphorous, if any, at less than 1% by weight.
  • Referring to FIG. 6, silicon dioxide comprising layer 24 is removed substantially selectively relative to silicon nitride comprising layer 16, with the at least one enriched region 20 preferably enhancing selectivity to silicon nitride comprising layer 16 during the removing. Such removing is preferably by chemical etching, or by other techniques for example by polishing. In the context of this document, “substantially selectively” means a removal rate of one material relative to another of at least 1.5:1. By way of example only, an exemplary process for etching silicon dioxide selectively relative to silicon nitride where region 20 facilitates selectivity in the etch includes a TEL DRM reactive ion etcher, operated at 1500 W, 45 mTorr, Ar flow at 500 sccm, C4F8 flow at 12 sccm, and CH2F2 flow at 6 sccm.
  • Regions 20/20 a might, of course, in the depicted first exemplary embodiment, be formed prior to or subsequent to fabrication of the exemplary opening 22. Further, in one preferred embodiment, silicon nitride comprising layer 16 with enriched region 20/20 a can be annealed prior to the removing action. Such might be desirable to facilitate migration of the gallium or aluminum to bond sites within silicon nitride comprising layer 16. Any alternate or additional fabrication is also contemplated in the context of the accompanying claims.
  • In one implementation, the invention also contemplates forming integrated circuitry comprising forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate. At least one enriched region analogous to regions 20 and 20 a in the above-described first preferred silicon nitride comprising layer embodiment is formed within the substantially undoped silicon dioxide comprising layer. The enriched region comprises B, Al, Ga or mixtures thereof. An exemplary diffusion species for Boron is diborane, while an exemplary implant species for boron is B11. A doped silicon dioxide comprising layer is formed proximate, and more preferably on, the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer. The at least one enriched region preferably enhances selectivity to the substantially undoped silicon dioxide comprising layer during the removing. Again, removing is preferably by chemical etching, with removal by polishing or other techniques also of course being contemplated. By way of example only, an exemplary process for etching doped silicon dioxide selectively relative to substantially undoped silicon dioxide where region 20 facilitates selectivity in the etch includes a 12 Liter Applied Materials 5000 Etch Chamber, operated at 1000 W, 50 mTorr, Ar flow at 120 sccm, CF4 flow at 30 sccm, CHF3 flow at 50 sccm, and CH2F2 flow at 15 sccm.
  • The above-described preferred embodiments are associated with forming respective enriched regions within the subject layers. However, in one aspect, the invention also more generically contemplates forming a silicon nitride comprising layer also comprising Al, Ga or a mixture thereof. Such Al, Ga or a mixture thereof might be present in the silicon nitride comprising layer as an enriched region, as described in the above preferred embodiments, or such might be substantially homogeneously distributed within the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the subject removing.
  • With respect to a substantially undoped silicon dioxide comprising layer, the invention also more generically contemplates B, Al, Ga or mixtures thereof being present within the substantially undoped silicon dioxide comprising layer, with such enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing. Again by way of example only, the B, Al, Ga or mixtures thereof might be present as an enriched region or portion thereof, or might be substantially homogeneously distributed within the substantially undoped silicon dioxide comprising layer.
  • By way of example only, alternate preferred embodiments of the invention are described with reference to FIGS. 7-12. FIG. 7 depicts a semiconductor wafer fragment 40 comprising a bulk monocrystalline silicon substrate 42. A pair of field effect transistor gate stacks 44 and 46 are shown formed over substrate 42. Such respectively comprise a gate dielectric layer 48, a conductive polysilicon portion 50, an overlying higher conductive silicide layer 52, and an overlying insulative cap 54. Regions 50 and 52 constitute the conductive portion of stacks 44 and 46, and depict an exemplary pair of spaced conductive device components formed over semiconductor substrate 42. Of course, any alternate pair of spaced conductive device components are contemplated. For purposes of the continuing discussion, spaced conductive device components 50/52 have at least one sidewall 56 which faces the other device component of the pair. This particular preferred embodiment is described in conjunction with a method of forming a contact opening within insulative material to a node location, for example location 60, located between conductive device components 50/52 of each stack 44 and 46.
  • Referring to FIG. 8, an insulative layer 62 is formed over device components 50/52 and on substrate material 42 between the device components. In one preferred embodiment, layer 62 comprises silicon nitride. In another preferred exemplary embodiment, insulative layer 62 comprises substantially undoped silicon dioxide. In the depicted preferred embodiment, a continuous enriched outer region 64 comprising B, Al, Ga or mixtures thereof is formed. Exemplary techniques for forming the same include those as described above. Preferably as shown, outer region 64 is formed to be continuous, and also to extend to at least a portion of, and to the entirety of as shown, the outer surfaces of insulative layer 62.
  • Referring to FIG. 9, layer 62 has been anisotropically etched, preferably without any photomasking, effective to form insulative material masses 66, 68, 70 and 72 in the form of insulative spacers, with insulative masses 68 and 70 being formed over facing sidewalls 56 of conductive device components 50/52. Such insulative material masses have lateral outer surfaces 74 extending from bases thereof proximate substrate 42 to the tops of the illustrated constructions. Spacers 66, 68, 70 and 72 also comprise respective enriched lateral outer regions 76 comprising B, Al, Ga or mixtures thereof. Such provides but one example of forming insulative material masses over each of sidewalls 56, with the preferred masses being laterally spaced from one another in a non-contacting relationship. Any alternate existing or yet-to-be-developed method of forming insulative masses is also contemplated. In the depicted preferred embodiment, enriched lateral outer regions 76 extend to at least a portion of the respective outer lateral surfaces 74, and are elevationally spaced from substrate material 42 between the device components.
  • Referring to FIG. 10, a second insulative material 80, different from the first insulative material, is formed between insulative material masses 68 and 70, and otherwise preferably over the substrate as shown. Where insulative masses 68 and 70 comprise substantially undoped silicon dioxide, one preferred material for layer 80 is doped silicon dioxide. Where insulative masses 68 and 70 comprise silicon nitride, two exemplary materials for layer 80 include doped silicon dioxide and substantially undoped silicon dioxide.
  • Referring to FIG. 11, a contact opening 82 is etched into insulative material 80 to node location 60 between insulative material masses 68, 70 substantially selectively relative thereto. Lateral outer enriched regions 76 preferably enhance selectivity to the insulative masses during such etching. In a more generic sense, the invention contemplates inclusion of B, Al, Ga or mixtures thereof within insulative material masses 68, 70 whether in enriched regions 76 as shown, substantially homogeneously distributed within the insulative material masses, or otherwise.
  • Referring to FIG. 12, conductive material 86 is shown having been formed within contact opening 82 between insulative material masses 68 and 70 in electrical connection with node location 60. Such might be provided by the provision of one or more conductive layers which, in the preferred embodiment, shows the formation of a conductive contact to a node location 60. Node location 60 might be a diffusion region, or any node location constituting a portion of integrated circuitry being formed.
  • The above-described preferred embodiments are only exemplary in connection with methodical aspects of the invention, which are only limited by the accompanying claims as literally worded and as interpreted in accordance with the doctrine of equivalents. The invention also contemplates integrated circuitry independent of the method of fabrication as literally claimed without limitation to the preferred depicted embodiments, and as interpreted in accordance with the doctrine of equivalents.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (28)

1-88. (canceled)
89. A method of forming integrated circuitry comprising:
forming a silicon nitride-comprising layer over a semiconductor substrate;
forming an opening through the silicon nitride-comprising layer;
forming at least one enriched region within the silicon nitride-comprising layer, the enriched region comprising Al, Ga or a mixture thereof;
forming a silicon dioxide-comprising layer over the silicon nitride-comprising layer to within the opening;
removing the silicon dioxide-comprising layer substantially selectively relative to the silicon nitride-comprising layer and leaving at least some of the silicon dioxide-comprising layer within the opening.
90. The method of claim 89 wherein the enriched region is formed before forming the opening.
91. The method of claim 89 wherein the enriched region is formed after forming the opening.
92. The method of claim 89 comprising forming said opening into semiconductive material of the semiconductor substrate below the silicon nitride-comprising layer.
93. The method of claim 89 wherein the silicon nitride-comprising layer has an outer surface, the enriched region extending to at least a portion of the outer surface.
94. The method of claim 89 wherein the silicon nitride-comprising layer has an outer surface, the enriched region being spaced from the outer surface.
95. The method of claim 89 wherein the enriched region comprises Al.
96. The method of claim 89 wherein the enriched region comprises Ga.
97. The method of claim 89 wherein the enriched region comprises Al and Ga.
98. The method of claim 89 further comprising annealing the silicon nitride-comprising layer prior to the removing.
99. The method of claim 89 wherein the silicon dioxide-comprising layer is formed on the silicon nitride-comprising layer.
100. The method of claim 89 wherein the silicon dioxide-comprising layer is substantially undoped.
101. The method of claim 89 wherein the silicon dioxide-comprising layer is doped.
102. The method of claim 89 wherein the removing comprises etching.
103. A method of forming integrated circuitry comprising:
forming a silicon nitride-comprising layer over a semiconductor substrate;
forming an opening through the silicon nitride-comprising layer;
implanting at least one of Al and Ga into the silicon nitride-comprising layer;
forming a silicon dioxide-comprising layer over the silicon nitride-comprising layer to within the opening;
removing the silicon dioxide-comprising layer substantially selectively relative to the silicon nitride-comprising layer and leaving at least some of the silicon dioxide-comprising layer within the opening.
104. The method of claim 103 wherein the implanting occurs before forming the opening.
105. The method of claim 103 wherein the implanting occurs after forming-the opening.
106. The method of claim 103 comprising forming said opening into semiconductive material of the semiconductor substrate below the silicon nitride-comprising layer.
107. The method of claim 103 comprising implanting Al.
108. The method of claim 103 comprising implanting Ga.
109. The method of claim 103 wherein the silicon nitride-comprising layer has an outer surface, the implanting forming an implanted region which extends to at least a portion of the outer surface.
110. The method of claim 103 wherein the silicon nitride-comprising layer has an outer surface, the implanting forming an implanted region which is spaced from the outer surface.
111. The method of claim 103 comprising implanting Al and Ga.
112. The method of claim 89 further comprising annealing the silicon nitride-comprising layer prior to the removing.
113. The method of claim 89 wherein the silicon dioxide-comprising layer is formed on the silicon nitride-comprising layer.
114. The method of claim 89 wherein the silicon dioxide-comprising layer is substantially undoped.
115. The method of claim 89 wherein the silicon dioxide-comprising layer is doped.
US11/254,680 2001-08-07 2005-10-19 Integrated circuitry Abandoned US20060281311A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/254,680 US20060281311A1 (en) 2001-08-07 2005-10-19 Integrated circuitry

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/924,816 US6806197B2 (en) 2001-08-07 2001-08-07 Method of forming integrated circuitry, and method of forming a contact opening
US10/391,952 US7291895B2 (en) 2001-08-07 2003-03-18 Integrated circuitry
US11/254,680 US20060281311A1 (en) 2001-08-07 2005-10-19 Integrated circuitry

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/391,952 Continuation US7291895B2 (en) 2001-08-07 2003-03-18 Integrated circuitry

Publications (1)

Publication Number Publication Date
US20060281311A1 true US20060281311A1 (en) 2006-12-14

Family

ID=25450778

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/924,816 Expired - Fee Related US6806197B2 (en) 2001-08-07 2001-08-07 Method of forming integrated circuitry, and method of forming a contact opening
US10/391,952 Expired - Fee Related US7291895B2 (en) 2001-08-07 2003-03-18 Integrated circuitry
US11/254,680 Abandoned US20060281311A1 (en) 2001-08-07 2005-10-19 Integrated circuitry

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/924,816 Expired - Fee Related US6806197B2 (en) 2001-08-07 2001-08-07 Method of forming integrated circuitry, and method of forming a contact opening
US10/391,952 Expired - Fee Related US7291895B2 (en) 2001-08-07 2003-03-18 Integrated circuitry

Country Status (1)

Country Link
US (3) US6806197B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060141766A1 (en) * 2004-12-29 2006-06-29 Hynix Semiconductor Inc. Method of manufacturing semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806197B2 (en) * 2001-08-07 2004-10-19 Micron Technology, Inc. Method of forming integrated circuitry, and method of forming a contact opening
US9859402B2 (en) 2015-03-16 2018-01-02 United Microelectronics Corp. Method of using an ion implantation process to prevent a shorting issue of a semiconductor device
CN110265290B (en) * 2019-06-27 2020-06-30 英特尔半导体(大连)有限公司 Method for enhancing semiconductor etching capability

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514251A (en) * 1983-04-11 1985-04-30 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which patterns are formed in a layer of silicon nitride by means of ion implantation
US4780426A (en) * 1986-10-07 1988-10-25 Kabushiki Kaisha Toshiba Method for manufacturing high-breakdown voltage semiconductor device
US4843034A (en) * 1987-06-12 1989-06-27 Massachusetts Institute Of Technology Fabrication of interlayer conductive paths in integrated circuits
US5436186A (en) * 1994-04-22 1995-07-25 United Microelectronics Corporation Process for fabricating a stacked capacitor
US5780338A (en) * 1997-04-11 1998-07-14 Vanguard International Semiconductor Corporation Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits
US5792689A (en) * 1997-04-11 1998-08-11 Vanguard International Semiconducter Corporation Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory
US5989950A (en) * 1998-01-26 1999-11-23 Texas Instruments - Acer Incorporated Reduced mask CMOS salicided process
US6063548A (en) * 1998-09-04 2000-05-16 Taiwan Semiconductor Manufacturing Company Method for making DRAM using a single photoresist masking step for making capacitors with node contacts
US6066550A (en) * 1998-06-05 2000-05-23 United Integrated Circuits Corp. Method of improving selectivity between silicon nitride and silicon oxide
US6107130A (en) * 1996-12-06 2000-08-22 Advanced Micro Devices, Inc. CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
US6188114B1 (en) * 1998-12-01 2001-02-13 Advanced Micro Devices, Inc. Method of forming an insulated-gate field-effect transistor with metal spacers
US6194265B1 (en) * 1999-07-22 2001-02-27 Vanguard International Semiconductor Corporation Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure
US20010010373A1 (en) * 2000-01-24 2001-08-02 Sony Corporation Semiconductor light emitting device
US6281064B1 (en) * 1999-06-04 2001-08-28 International Business Machines Corporation Method for providing dual work function doping and protective insulating cap
US20020001889A1 (en) * 2000-06-28 2002-01-03 Kim Ji-Soo Methods for forming conductive contact body for integrated circuits using dummy dielectric layer
US20020004248A1 (en) * 1997-09-29 2002-01-10 Mi-Hyang Lee Ferroelectric memory devices including patterned conductive layers
US20020125522A1 (en) * 1997-09-22 2002-09-12 Shigeo Chishiki Semiconductor device and manufacturing method thereof
US6806197B2 (en) * 2001-08-07 2004-10-19 Micron Technology, Inc. Method of forming integrated circuitry, and method of forming a contact opening

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384287A (en) * 1991-12-13 1995-01-24 Nec Corporation Method of forming a semiconductor device having self-aligned contact holes
US5821147A (en) * 1995-12-11 1998-10-13 Lucent Technologies, Inc. Integrated circuit fabrication
US6162688A (en) * 1999-01-14 2000-12-19 Advanced Micro Devices, Inc. Method of fabricating a transistor with a dielectric underlayer and device incorporating same

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514251A (en) * 1983-04-11 1985-04-30 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which patterns are formed in a layer of silicon nitride by means of ion implantation
US4780426A (en) * 1986-10-07 1988-10-25 Kabushiki Kaisha Toshiba Method for manufacturing high-breakdown voltage semiconductor device
US4843034A (en) * 1987-06-12 1989-06-27 Massachusetts Institute Of Technology Fabrication of interlayer conductive paths in integrated circuits
US5087589A (en) * 1987-06-12 1992-02-11 Massachusetts Institute Of Technology Selectively programmable interconnections in multilayer integrated circuits
US5436186A (en) * 1994-04-22 1995-07-25 United Microelectronics Corporation Process for fabricating a stacked capacitor
US6107130A (en) * 1996-12-06 2000-08-22 Advanced Micro Devices, Inc. CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
US5780338A (en) * 1997-04-11 1998-07-14 Vanguard International Semiconductor Corporation Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits
US5792689A (en) * 1997-04-11 1998-08-11 Vanguard International Semiconducter Corporation Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory
US20020125522A1 (en) * 1997-09-22 2002-09-12 Shigeo Chishiki Semiconductor device and manufacturing method thereof
US20020004248A1 (en) * 1997-09-29 2002-01-10 Mi-Hyang Lee Ferroelectric memory devices including patterned conductive layers
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
US5989950A (en) * 1998-01-26 1999-11-23 Texas Instruments - Acer Incorporated Reduced mask CMOS salicided process
US6066550A (en) * 1998-06-05 2000-05-23 United Integrated Circuits Corp. Method of improving selectivity between silicon nitride and silicon oxide
US6063548A (en) * 1998-09-04 2000-05-16 Taiwan Semiconductor Manufacturing Company Method for making DRAM using a single photoresist masking step for making capacitors with node contacts
US6188114B1 (en) * 1998-12-01 2001-02-13 Advanced Micro Devices, Inc. Method of forming an insulated-gate field-effect transistor with metal spacers
US6281064B1 (en) * 1999-06-04 2001-08-28 International Business Machines Corporation Method for providing dual work function doping and protective insulating cap
US6194265B1 (en) * 1999-07-22 2001-02-27 Vanguard International Semiconductor Corporation Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure
US20010010373A1 (en) * 2000-01-24 2001-08-02 Sony Corporation Semiconductor light emitting device
US20020001889A1 (en) * 2000-06-28 2002-01-03 Kim Ji-Soo Methods for forming conductive contact body for integrated circuits using dummy dielectric layer
US6806197B2 (en) * 2001-08-07 2004-10-19 Micron Technology, Inc. Method of forming integrated circuitry, and method of forming a contact opening

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060141766A1 (en) * 2004-12-29 2006-06-29 Hynix Semiconductor Inc. Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
US20030203628A1 (en) 2003-10-30
US6806197B2 (en) 2004-10-19
US7291895B2 (en) 2007-11-06
US20030032296A1 (en) 2003-02-13

Similar Documents

Publication Publication Date Title
US7105431B2 (en) Masking methods
US8058130B2 (en) Method of forming a nitrogen-enriched region within silicon-oxide-containing masses
US5633522A (en) CMOS transistor with two-layer inverse-T tungsten gate
US6294476B1 (en) Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
US7153731B2 (en) Method of forming a field effect transistor with halo implant regions
US7790558B2 (en) Method and apparatus for increase strain effect in a transistor channel
US6274419B1 (en) Trench isolation of field effect transistors
US7183198B2 (en) Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes
US5298463A (en) Method of processing a semiconductor wafer using a contact etch stop
US6004852A (en) Manufacture of MOSFET having LDD source/drain region
US6617212B2 (en) Semiconductor device and method for fabricating the same using damascene process
US6057207A (en) Shallow trench isolation process using chemical-mechanical polish with self-aligned nitride mask on HDP-oxide
US20050009278A1 (en) Methods of fabricating multiple sets of field effect transistors
US20060281311A1 (en) Integrated circuitry
US7259105B2 (en) Methods of fabricating gate spacers for semiconductor devices
US6509221B1 (en) Method for forming high performance CMOS devices with elevated sidewall spacers
US6524938B1 (en) Method for gate formation with improved spacer profile control
US6004873A (en) Method for reducing the pattern sensitivity of ozone assisted chemical vapor deposited (CVD) silicon oxide insulator layers
KR100493483B1 (en) Methods for protecting device components from chemical mechanical polish induced defects
US6221745B1 (en) High selectivity mask oxide etching to suppress silicon pits
CN113921387A (en) Preparation method of semiconductor structure and semiconductor structure

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION