US20060258096A1 - Ultra high density flash memory - Google Patents
Ultra high density flash memory Download PDFInfo
- Publication number
- US20060258096A1 US20060258096A1 US11/491,328 US49132806A US2006258096A1 US 20060258096 A1 US20060258096 A1 US 20060258096A1 US 49132806 A US49132806 A US 49132806A US 2006258096 A1 US2006258096 A1 US 2006258096A1
- Authority
- US
- United States
- Prior art keywords
- forming
- regions
- troughs
- layer
- gate regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000015654 memory Effects 0.000 title claims abstract description 42
- 238000007667 floating Methods 0.000 claims abstract description 174
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000012212 insulator Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 70
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 68
- 238000000034 method Methods 0.000 claims description 49
- 238000005530 etching Methods 0.000 claims description 38
- 239000000377 silicon dioxide Substances 0.000 claims description 34
- 235000012239 silicon dioxide Nutrition 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 2
- 238000003860 storage Methods 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 description 18
- 230000000873 masking effect Effects 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 238000013500 data storage Methods 0.000 description 3
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 239000000872 buffer Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- -1 third spacers 1800 Chemical compound 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- This invention relates generally to integrated circuits, and particularly to floating gate transistor structures for use in nonvolatile semiconductor memories such as in flash EEPROM memory cells.
- EEPROMs Electrically erasable and programmable read only memories
- FET field-effect transistor
- floating electrically isolated
- EEPROM memories require a reduction in the size of the floating gate transistors and other EEPROM components in order to increase the EEPROM's density.
- memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication.
- F lithographic feature size
- DRAMS high density dynamic random access memories
- FIG. 1 is a schematic/block diagram illustrating generally an architecture of one embodiment of a nonvolatile memory, according to the teachings of the invention, including an array having a plurality of memory cells.
- FIG. 2 is a schematic diagram illustrating generally one embodiment of an array of memory cells according to the teachings of the invention.
- FIG. 3 is a perspective view illustrating generally one embodiment of a portion of an array of memory cells according to the teachings of the invention.
- FIG. 4 is a plan view from above of a working surface of a substrate, which illustrates one embodiment of one of a memory cell according to the teachings of the invention.
- FIGS. 5-20 illustrate generally various stages of one embodiment of a method of forming an array of memory cells according to the teachings of the invention.
- FIG. 21 is a perspective view of a structure dating from another embodiment of a method of forming the array of memory cells according to the invention, using semiconductor-on-insulator (SOI) techniques.
- SOI semiconductor-on-insulator
- FIG. 1 is a schematic/block diagram illustrating generally an architecture of one embodiment of a memory 100 according to the present invention.
- memory 100 is a nonvolatile ultra high density electrically erasable and programmable read only memory (EEPROM) allowing simultaneous erasure of multiple data bits, referred to as flash EEPROM.
- EEPROM electrically erasable and programmable read only memory
- the invention can be applied to other semiconductor memory devices, such as static or dynamic random access memories (SRAMs and DRAMS, respectively), synchronous random access memories or other types of memories that include a matrix of selectively addressable memory cells.
- Memory 100 includes a memory cell array 105 , having memory cells therein that include floating gate transistors, as described below.
- Y gate decoder 110 provides a plurality of first gate lines, YG 1 , YG 2 , . . . , YGN for addressing floating gate transistors in array 105 , as described below.
- X gate decoder 115 provides a plurality of second gate lines, XG 1 , XG 2 , . . . , XGN for addressing floating gate transistors in array 105 , as described below.
- Y source/drain decoder 120 provides a plurality of first source/drain interconnection lines YS 1 , YS 2 , . . .
- YSN for accessing first source/drain regions of the floating gate transistors in array 105 , as described below.
- Y source/drain decoder 120 may be omitted.
- X source/drain decoder 125 provides a plurality of data lines, XD 1 , XD 2 , . . . , XDN for accessing second source/drain regions of the floating gate transistors in array 105 , as described below.
- X source/drain decoder 125 also typically includes sense amplifiers and input/output (I/O) circuitry for reading, writing, and erasing data to and from array 105 .
- address buffers 135 control the operation of Y gate decoder 110 , X gate decoder 115 , Y source/drain decoder 120 , and X source/drain decoder 125 .
- the address signals A 0 -AN are provided by a controller such as a microprocessor that is fabricated separately or together with memory 100 , or otherwise provided by any other suitable circuits.
- the address signals A 0 -AN are decoded by Y gate decoder 110 , X gate decoder 115 , Y source/drain decoder 120 , and X source/drain decoder 125 to perform reading, writing, and erasing operations on memory cells that include a number of vertical floating gate field-effect transistors (FETs) formed on the sides of a semiconductor pillar on a substrate.
- FETs vertical floating gate field-effect transistors
- FIG. 2 is a schematic diagram illustrating generally one embodiment of array 105 in more detail.
- each memory cell 205 comprises four floating gate transistors 200 , e.g. four field-effect transistors (FETS), each having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions.
- the floating gate transistors 200 are arranged in cells 205 , such as cells 205 AA, 205 BA, . . . , 205 NA, in a first direction, e.g. in the Y-direction of the first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN, and in cells such as 205 AA, 205 AB . . .
- each cell 205 includes four floating gate transistors 200 that share a common first source/drain region, such as a source region coupled to one of the first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN.
- the floating gate transistors 200 of each cell 205 also share a common second source/drain region, such as a drain region coupled to one of the data lines, XD 1 , XD 2 , . . . , XDN.
- Each cell 205 has first and second source/drain regions that are fabricated using a common semiconductor pillar on a substrate, as explained below.
- FIG. 3 is a perspective view illustrating generally one embodiment of a portion of array 105 , including portions of two cells 205 of floating gate transistors 200 , such as illustrated in FIG. 2 .
- the substantially identical cells 205 are illustrated by way of example through cells 205 AA and 205 BA.
- Cells 205 AA and 205 BA each include a semiconductor pillar 300 , initially of a first conductivity type such as P-silicon, fabricated upon a monolithic substrate 305 .
- substrate 305 is a bulk semiconductor, such as P-silicon.
- a semiconductor-on-insulator (SOI) substrate 305 includes an insulating layer, such as silicon dioxide (SiO 2 ), as described below.
- Each pillar 300 includes a first source/drain region of a second conductivity type, such as N+ silicon source region 310 , formed proximally to a sub-micron dimensioned interface between pillar 300 and substrate 305 .
- Each pillar 300 also includes a second source/drain region of the second conductivity type, such as N+ silicon drain region 315 , that is distal to substrate 305 , and separated from source region 310 by a first conductivity type region, such as P-body region 320 .
- Each pillar 300 provides a source region 310 , a drain region 315 , and a body region 320 for the four floating gate transistors 200 of a particular memory cell 205 .
- the physical dimensions of each pillar 300 and the doping of P-body region 320 are both sufficiently small to allow operation of the floating gate transistors 200 that is characteristic of fully depleted body transistors.
- First source/drain region interconnection line YS 1 electrically interconnects the source region 310 of each pillar 300 . of cells 205 AA, 205 BA, . . . , 205 BN.
- YSN comprise a conductively doped semiconductor of the second conductivity type, such as N+ silicon, disposed at least partially within substrate 305 .
- dopants can be ion-implanted or diffused into substrate 305 to form the first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN.
- the first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN are formed above substrate 305 .
- a doped epitaxial semiconductor layer can be grown on substrate 305 , from which first source/drain interconnection lines YS 1 , YS 2 , . . .
- YSN are formed.
- an undoped epitaxial semiconductor layer can be grown on substrate 305 , and dopants then introduced by ion-implantation or diffusion to obtain the first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN of the desired conductivity.
- Each pillar 300 is outwardly formed from substrate 305 , and is illustrated in FIG. 3 as extending vertically upward from substrate 305 .
- Each pillar 300 has a top region that is separated from substrate 305 by four surrounding side regions.
- a floating gate 325 is formed substantially adjacent to each side surface of pillar 300 , and separated therefrom by a gate dielectric 330 , such that there are four floating gates 325 per pillar 300 , though FIG. 3 omits some of the floating gates 325 for clarity of illustration.
- Each floating gate 325 has a corresponding substantially adjacent control gate 335 , from which it is separated by an intergate dielectric 340 . Except at the periphery of array 105 , each control gate 335 is interposed between two approximately adjacent pillars 300 and shared by two floating gate transistors 200 , each of these floating gate transistors 200 having portions in one of the two approximately adjacent pillars 300 .
- first gate line YG 1 , YG 2 , . . . , YGN that are substantially parallel to each other in the first direction, e.g. the Y-direction.
- Each of the first gate lines YG 1 , YG 2 , . . . , YGN interconnects ones of the control gates 335 .
- first gate line YG 1 electrically interconnects control gates 335 of floating gate transistors 200 in cells 205 AA, 205 BA, . . . , 205 BN.
- the first gate lines YG 1 , YG 2 , . . . , YGN are disposed at least partially within substrate 305 , as described below.
- second gate lines XG 1 , XG 2 , . . . , XGN are interposed between approximately adjacent pillars 300 , except at the periphery of array 105 .
- Each of the second gate lines XG 1 , XG 2 , . . . , XGN interconnects ones of the control gates 335 .
- second gate line XG 2 electrically interconnects control gates 335 of floating gate transistors 200 , in which the control gates are shared between pairs of cells 205 , e.g. 205 AA and 205 BA, 205 AB and 205 BB . . . , 205 AN and 205 BN.
- the second gate lines XG 1 , XG 2 , . . . , XGN are disposed above substrate 305 , as described below.
- Drain regions 315 of the pillars 300 are interconnected by data lines XD 1 , XD 2 , . . . , XDN that are substantially parallel to each other in the second direction, e.g. the X-direction.
- FIG. 3 illustrates, by way of example, data lines XD 1 and XD 2 , which are shown schematically for clarity. However, it is understood that data lines XD 1 , XD 2 , . . . , XDN comprise metal or other interconnection lines that are isolated from the underlying topology, e.g. pillars 300 , floating gates 325 , control gates 335 , first gate lines YG 1 , YG 2 , . . . , YGN, and second gate lines XG 1 , XG 2 , . . . , XGN, by an insulating layer through which contact holes are etched to access the drain regions 315 of the pillars 300 .
- FIG. 4 is a plan view, looking toward the working surface of substrate 305 , illustrating generally by way of example one embodiment of one of cells 205 of four floating gate transistors 200 , such as cell 205 BB.
- each of the four floating gates 325 is adjacent to one side of pillar 300 , and separated therefrom by gate dielectric 330 .
- Each control gate 335 is separated from a corresponding floating gate 325 by an intergate dielectric 340 , and is integrally formed together with one of the first gate lines YG 1 , YG 2 , . . . , YGN or second gate lines XG 1 , XG 2 , . . . , XGN.
- control gates 335 that are integrally formed together with ones of the first gate lines YG 1 , YG 2 , . . . , YGN protrude upwardly therefrom such that an overlap capacitance is created with floating gates 325 that are disposed on either side thereof.
- the center-to-center spacing (“pitch”) between adjacent first gate lines YG 1 , YG 2 , . . . , YGN, such as between YG 2 and YG 3 , or between adjacent second gate lines XG 1 , XG 2 , . . . , XGN, such as between XG 2 and XG 3 , is twice the minimum lithographic feature size F. Since four floating gate transistors 200 are contained within a cell 205 having an area of 4F 2 , an area of only F 2 is needed per bit of data.
- multiple charge states are used to obtain correspondingly higher data storage densities, such that an area of less than F 2 is needed per bit of data, since more than one bit of data can be stored on a single floating gate transistor 200 .
- four charge states are used to store two bits of data per floating gate transistor 200 , corresponding to eight bits of data per memory cell 205 .
- One example of using more than two charge states to store more than one bit of data per transistor is set forth an article by T.-S. Jung et al., entitled “A 117-mm 2 3.3-V Only 128-Mb Multilevel NAND Flash Memory For Mass Storage Applications,” IEEE J. Solid - State Circuits , Vol. 31, No. 11, November 1996.
- a continuum of charge states is used to store analog data in array 105 .
- programming of one of the floating gate transistors 200 is by hot electron injection.
- a voltage of approximately 10 volts is provided, such as by one of Y gate decoder 110 or X gate decoder 115 , through a particular one of the first gate lines YG 1 , YG 2 , . . . , YGN or second gate lines XG 1 , XG 2 , . . . , XGN to a particular control gate 335 .
- a resulting inversion region (channel) is formed in the body region 320 at the surface that is approximately adjacent to the particular one of the first gate lines YG 1 , YG 2 , . . .
- a voltage of approximately 5 Volts is provided, such as by X source/drain decoder 125 , through a particular one of data lines XD 1 , XD 2 , . . . , XDN to a particular drain region 315 .
- a voltage of approximately 0 Volts is provided, such as by Y source/drain decoder 120 , through a particular one of first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN, to the particular source region 310 of the floating gate transistor 200 .
- Electrons are injected onto the floating gate 325 interposed between the control gate 335 and the pillar 300 in which the particular drain region 315 is disposed.
- the exact value of the voltages provided to the particular control gate 335 and drain region 315 will depend on the physical dimension of the floating gate transistor 200 , including the thickness of the gate dielectric 330 , the thickness of the intergate dielectric 340 , and the separation between source region 310 and drain region 315 .
- the floating gate transistor 200 may be programmed instead by Fowler-Nordheim tunneling of electrons h m the body region 320 , source region 310 , or drain region 315 .
- Addressing a particular memory cell 205 for reading data includes selecting a particular one of data lines XD 1 , XD 2 , . . . , XDN and also selecting a particular one of first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN. Addressing a particular floating gate transistor 200 within the particular memory cell 205 for reading data further includes selecting a particular one of first gate lines YG 1 , YG 2 , . . . , YGN or second gate lines XG 1 , XG 2 , . . . , XGN.
- reading data stored on a particular floating gate transistor 200 includes providing a voltage of approximately 5 volts, such as by one of Y gate decoder 110 or X gate decoder 115 , through a particular one of the first gate lines YG 1 , YG 2 , . . . , YGN or second gate lines XG 1 , XG 2 , . . . , XGN to the particular control gate 335 of the floating gate transistor 200 .
- a voltage of approximately 0 Volts is provided, such as by Y source/drain decoder 120 , through a particular one of first source/drain interconnection lines YS 1 , YS 2 , . . .
- a particular one of data lines XD 1 , D 2 . . . , XDN that is switchably coupled to the drab region 315 of the floating gate transistor 200 is precharged to a positive voltage by a sense amplifier in X source/drain decoder 125 , then coupled to the drain region 315 to determine the conductivity state of the floating gate transistor 200 between its source region 310 and drain region 315 .
- the floating gate transistor 200 will conduct between its source region 310 and drain region 315 , decreasing the voltage of the particular one of data lines XD 1 , XD 2 , . . . , XDN toward that voltage of its source region 310 , e.g. toward a “low” binary logic level of approximately 0 Volts. If there are electrons stored on the floating gate 325 , the floating gate transistor 200 will not conduct between its source region 310 and drain region 315 . As a result, the sense amplifier will tend to increase the voltage of the particular one of data lines XD 1 , XD 2 , . . . , XDN toward a positive voltage, e.g. toward a “high” binary logic voltage level.
- erasure of floating gate transistors 200 includes providing an erasure voltage difference of approximately between ⁇ 10 and ⁇ 12 Volts from a source region 310 to a corresponding control gate 335 .
- a voltage of approximately 0 Volts is provided, such as by Y source/drain decoder 120 , to source regions 310 of floating gate transistors 200 that are interconnected by one or several first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN.
- a voltage of approximately between ⁇ 10 and ⁇ 12 Volts is provided, such as by one of Y gate decoder 110 or X gate decoder 115 , through a corresponding one or several of the first gate lines YG 1 , YG 2 , . . . , YGN or second gate lines XG 1 , XG 2 , . . . , XGN to the control gates 335 of the floating gate transistors 200 to be erased.
- the negative voltage applied to the control gates 335 electrons are removed from the corresponding floating gates 325 by Fowler-Nordheim tunneling, thereby erasing the data from ones of the floating gate transistors 200 .
- a voltage of approximately between ⁇ 5 and ⁇ 6 Volts is applied to the control gates 335 and a voltage of approximately between +5 and +6 Volts is applied to the source regions 310 in order to obtain the erasure voltage difference of approximately between ⁇ 10 and ⁇ 12 Volts from a source region 310 to a corresponding control gate 335 .
- the exact value of the erasure voltage difference will vary depending upon the physical dimensions of the floating gate transistor 200 and the thicknesses of gate dielectric 330 and intergate dielectric 340 .
- the entire array 105 of floating gate transistors 200 is simultaneously erased by applying approximately between ⁇ 10 and ⁇ 12 Volts to each of first gate lines YG 1 , YG 2 , . . . , YGN and second gate lines XG 1 , XG 2 , . . . , XGN, and also applying 0 Volts to each of first source/drain interconnection lines YS 1 , YS 2 , . . . , YSN.
- one or more sectors of array 105 are simultaneously erased by selectively applying approximately between ⁇ 10 and ⁇ 12 Volts to one or more of first gate lines YG 1 , YG 2 , . . .
- FIGS. 5-20 illustrate generally one embodiment of a method of forming memory array 105 .
- the array 105 is formed using bulk silicon processing techniques and is described, by way of example, with respect to a particular technology having a minimum feature size F, which is also sometimes referred to as a critical dimension (CD), of 0.4 microns.
- CD critical dimension
- the process steps described below can be scaled accordingly for other minimum feature sizes without departing from the scope of the invention.
- a P-silicon starting material is used for substrate 305 .
- a first source/drain layer 500 is formed at a working surface of substrate 305 .
- first source/drain layer 500 is N+ silicon formed by ion-implantation of donor dopants into substrate 305 .
- first source/drain layer 500 is N+ silicon formed by epitaxial growth of silicon upon substrate 305 .
- a semiconductor epitaxial layer 505 is formed, such as by epitaxial growth.
- a second source/drain layer 510 such as N+ silicon of 150 nanometer approximate thickness, is formed at a surface of the epitaxial layer 505 , such as by ion-implantation of donor dopants into P-epitaxial layer 505 or by epitaxial growth of N+ silicon on P-epitaxial layer 505 .
- a thin layer of silicon dioxide (SiO 2 ), referred to as pad oxide 515 is deposited on the second source/drain layer 510 .
- Pad oxide 515 has a thickness of approximately 10 nanometers.
- a layer of silicon nitride (Si 3 N 4 ), referred to as pad nitride 520 is deposited on the pad oxide 515 .
- Pad nitride 520 has a thickness of approximately 200 nanometers.
- photoresist masking and selective etching techniques are used to form, in the first direction (e.g., the Y direction, which is perpendicular to the plane of the drawing of FIG. 6 ), a plurality of substantially parallel first troughs 600 that extend through the pad nitride 520 , pad oxide 515 , second source/drain layer 510 , the underlying portion of epitaxial layer 505 , and at least partially into first source/drain layer 500 .
- the photoresist is then removed.
- a thin silicon nitride oxidation barrier layer 700 is deposited by chemical vapor deposition (CVD) to protect against oxidation of sidewalls of first troughs 600 .
- Barrier layer 700 is anisotropically etched to expose bottom portions of first troughs 600 .
- a bottom insulation layer 705 of silicon dioxide is formed on the bottoms of first troughs 600 by thermal oxidation of the exposed bottom portions of first troughs 600 .
- barrier layer 700 is stripped from the sidewalls of the first troughs 600 , such as by a brief phosphoric acid etch, which is timed to expose the sidewalls of the first troughs 600 but which avoids significant removal of the pad nitride 520 .
- a first gate dielectric layer 800 such as, for example, silicon dioxide of thickness approximately between 5 nanometers and 10 nanometers (sometimes referred to as “tunnel oxide”), is formed substantially adjacent to the exposed sidewalls of the first troughs 600 .
- a first conductive layer 805 such as N+ doped polysilicon, is formed in the first troughs 600 , such as by CVD, to fill the first troughs 600 .
- the first conductive layer 805 is planarized, such as by chemical mechanical polishing (CMP) or other suitable planarization technique.
- CMP chemical mechanical polishing
- the first conductive layer 805 is etched back in the first troughs 600 to approximately 100 nanometers below the silicon surface, which is defined by the interface between the second source/drain layer 510 and the pad oxide 515 layer.
- a first spacer layer such as silicon nitride of an approximate thickness of 7 nanometers, is deposited by CVD and anisotropically etched by reactive ion etching (RIE) to leave nitride first spacers 900 along the sidewalls of the first troughs 600 .
- RIE reactive ion etching
- a second spacer layer such as silicon dioxide of an approximate thickness of 90 nanometers, is deposited by CVD and anisotropically etched by RIE to leave second spacers 905 along the sidewalls of the first troughs 600 .
- first conductive layer 805 in first troughs 600 between second spacers 905 is removed, such as by using spacers 905 as a mask while etching down to bottom insulation layer 705 , thereby forming from the first conductive layer 805 floating gate regions 1000 along the sidewalls of the first troughs 600 .
- a thin oxidation barrier layer 1005 such as silicon nitride of approximate thickness of 5 nanometers, is deposited by CVD. Barrier layer 1005 is removed from the bottom insulation layer 705 in first troughs 600 by anisotropic etching. The remaining portions of barrier layer 1005 protect the floating gate regions 1000 during subsequent processing described below.
- a portion of the bottom insulation layer 705 is removed, exposing a portion of the underlying substrate 305 , by an anisotropic etch that is timed to leave enough of second spacers 905 to protect floating gate regions 1000 during a subsequent etch of substrate 305 .
- a portion of substrate 305 that underlies a portion of first troughs 600 between the floating gate regions 1000 is removed by selectively anisotropically etching the substrate 305 to a depth sufficient to carry the first gate lines YG 1 , YG 2 , . . . , YGN.
- a first trough insulation layer 1100 is formed on sidewall and bottom regions of the etched portions of substrate 305 underlying the first troughs 600 .
- Barrier layer 1005 is removed to expose the floating gate regions 1000 in first troughs 600 , such as by wet etching.
- the first intergate dielectric 340 having an approximate thickness between 7 nanometers and 15 nanometers, is formed on the exposed portions of floating gate regions 1000 .
- a silicon dioxide intergate dielectric 340 is formed by thermal oxidation of the floating gate regions 1000 .
- an oxynitride intergate dielectric 340 is formed on the floating gate regions 1000 by CVD.
- First gate lines YG 1 , YG 2 , . . . , YGN are formed in the etched portions of substrate 305 underlying the first troughs 600 between opposing floating gate regions 1000 in the first troughs 600 .
- First gate lines YG 1 , YG 2 , . . . , YGN are insulated from substrate 305 by first trough insulation layer 1100 .
- Control gates 335 are formed in the first troughs 600 between opposing floating gate regions 1000 , and separated therefrom by the first intergate dielectric 340 .
- first gate lines YG 1 , YG 2 , . . . , YGN and control gates 335 are formed together by depositing N+ polysilicon to fill first troughs 600 , and etching back the deposited N+ polysilicon approximately to the top portion of the floating gate regions 1000 .
- a cap layer 1200 is formed, such as by CVD of silicon dioxide, and then planarized, such as by CMP, such that the top surface of cap layer 1200 is substantially even with the top surface of pad nitride 520 .
- a masking layer 1205 is formed, such as silicon nitride deposited by CVD to an approximate thickness of 100 nanometers.
- Another masking layer 1210 is also formed, such as polysilicon deposited by CVD to an approximate thickness of 100 nanometers.
- a photoresist layer 1215 is formed on masking layer 1210 .
- FIG. 13 is a perspective view, illustrating the selective etching, in a second direction (X-direction) that is substantially orthogonal to the first direction (Y-direction), of a plurality of substantially parallel second troughs 1300 , as described below.
- Forming second troughs 1300 includes selectively etching masking layer 1210 and underlying masking layer 1205 , such that portions of cap layer 1200 in the second troughs 1300 are exposed.
- a nonselective dry etch is used to simultaneously remove exposed silicon dioxide and polysilicon in intersecting portions of first troughs 600 and second troughs 1300 , including the removing of: portions of cap layer 1200 , gate dielectric 800 , floating gate regions 1000 , intergate dielectric 340 , and the control gate 335 portions of first gate lines YG 1 , YG 2 , . . . , YGN.
- the nonselective dry etch removal proceeds at least to the depth of the interface between floating gate regions 1000 and underlying bottom insulation layer 705 , thereby separating floating gate regions 1000 into the isolated floating gates 325 .
- the regions between first troughs 600 are protected by the pad nitride 520 and the regions between second troughs 1300 are protected by selectively patterned photoresist layer 1215 .
- the photoresist layer 1215 has been removed by conventional photoresist stripping techniques, thereby exposing the underlying. selectively patterned polysilicon masking layer 1210 .
- An insulating layer 1400 such as silicon dioxide deposited by CVD, is formed everywhere on the topography of the working surface of substrate 305 , thereby filling the nonselectively dry-etched intersections of the first troughs 600 and second troughs 1300 .
- the insulating layer 1400 is then planarized, such as by CMP, and recess etched to a depth that is slightly above the interface between second source-drain layer 510 and pad oxide 515 , thereby leaving behind recessed portions of insulating layer 1400 in the nonselectively dry-etched intersections of the first troughs 600 and second troughs 1300 , as illustrated in FIG. 14 .
- the exposed portions of pad nitride 520 are removed by a selective etch of silicon nitride, thereby exposing underlying portions of pad oxide 515 .
- the exposed portions of pad oxide 515 are removed by dipping into a wet etchant, which is timed to remove the exposed portions of pad oxide 515 , but to leave most of the remaining portions of the thicker silicon dioxide insulating layer 1400 intact.
- the removing of portions of pad oxide 515 exposes the second source/drain layer 510 portion of the underlying silicon epitaxial layer 505 .
- the exposed portions of silicon epitaxial layer 505 (e.g., between first troughs 600 and within second troughs 1300 ) are removed by a selective etching that is preferential to silicon over silicon dioxide, thereby forming recesses 1500 in second troughs 1300 between first troughs 600 .
- Recesses 1500 which are considered to be part of second troughs 1300 , are etched through epitaxial layer 505 and at least partially into first source/drain layer 500 . Etching recesses 1500 also removes the remaining portions of polysilicon masking layer 1210 , thereby exposing underlying silicon nitride masking layer 1205 , as illustrated in FIG. 15 .
- FIG. 16 is a cross-sectional view in the direction of second troughs 1300 (e.g. such that the X-direction is orthogonal to the plane of the illustration of FIG. 16 ). as indicated by the cut line 16 - 16 in FIG. 15 .
- a thin silicon nitride oxidation barrier layer 1600 is deposited by CVD to protect against oxidation of sidewalls of second troughs 1300 .
- Barrier layer 1600 is anisotropically etched to expose bottom portions of second troughs 1300 .
- a bottom insulation layer 1605 of silicon dioxide is formed on the bottoms of second troughs 1300 , such as silicon dioxide of approximate thickness of 50 nanometers formed by thermal oxidation of the exposed bottom portions of second troughs 1300 .
- barrier layer 1600 is stripped from the sidewalls of the second troughs 1300 , such as by a brief phosphoric acid etch, which is timed to expose the sidewalls of the second troughs 1300 but which avoids significant removal of the silicon nitride masking layer 1205 .
- a second gate dielectric layer 1700 such as silicon dioxide of thickness approximately between 5 nanometers and 10 nanometers (sometimes referred to as “tunnel oxide”), is formed substantially adjacent to the exposed sidewalls of the second troughs 1300 .
- a second conductive layer 1705 such as N+ doped polysilicon, is formed in the second troughs 1300 , such by CVP, to fill the second troughs 1300 .
- the second conductive layer 1705 is planarized such as by chemical mechanical polishing (CMP) or other suitable planarization technique.
- the second conductive layer 1705 is etched back in the second troughs 1300 to approximately at or slightly above the level of the silicon surface, which is defined by the interface between the second source/drain layer 510 and the pad oxide 515 layer.
- the top surface of the second conductive layer 1705 is approximately even with the top surface of the recessed portions of insulating layer 1400 .
- a spacer layer such as silicon nitride of an approximate thickness of 100 nanometers, is deposited by CVD and anisotropically etched by reactive ion etching (RTE) to leave nitride third spacers 1800 , along the sidewalls of the second troughs 1300 , e.g. on the etched back portions of the second conductive layer 1705 and on the recessed portions of insulating layer 1400 , and against the second gate dielectric 1700 .
- RTE reactive ion etching
- third spacers 1800 are used as a mask for the anisotropic etching of the etched back portions of polysilicon second conductive layer 1705 together with the recessed portions of silicon dioxide insulating layer 1400 .
- the second troughs 1300 are etched in insulating layer 1400 to a depth sufficient to carry a second gate line X 1 , X 2 , . . . , XN, but not so great as to expose the first gate lines Y 1 , Y 2 , . . . , YN underlying the recessed portions of silicon dioxide insulating layer 1400 in second troughs 1300 .
- the anisotropic etch is continued using a selective etchant to remove polysilicon but not silicon dioxide until the bottom insulation layer 1605 is exposed, thereby forming from the second conductive layer 1705 separate floating gates 325 along the sidewalls of the second troughs 1300 .
- a second intergate dielectric 2000 is formed in the second troughs 1300 , such that the second intergate dielectric 2000 has an approximate thickness between 7 nanometers and 15 nanometers and being formed by thermal growth of silicon dioxide or deposition of oxynitride by CVD.
- Control gates 335 are formed between opposing floating gates 325 in the second troughs 1300 and separated therefrom by the second intergate dielectric 2000 .
- the control gates 335 in second troughs 1300 are formed together with the second gate lines X 1 , X 2 , . . .
- XN in second troughs 1300 by a single deposition of N+ doped polysilicon that fills second troughs 1300 and is planarized, such as by CMP.
- Phosphoric acid is used to remove the remaining silicon nitride, such as third spacers 1800 , masking layer 1205 , and pad nitride 520 , leaving the structure illustrated in FIG. 20 .
- An insulator such as silicon dioxide is then deposited, and subsequent processing follows conventional techniques for forming contact holes, terminal metal, and inter level insulator steps to complete wiring of the cells 205 and other circuits of memory 100 .
- FIGS. 5-20 illustrate generally one embodiment of forming the memory array 105 using bulk silicon processing techniques
- a semiconductor-on-insulator (SOI) substrate is formed from substrate 305 .
- a P-silicon starting material is used for substrate 305 , and processing proceeds similarly to the bulk semiconductor embodiment described in FIG. 5-7 .
- an isotropic chemical etch is used to fully undercut the semiconductor regions separating the first troughs 600 , and a subsequent oxidation step is used to fill in the evacuated regions formed by the undercutting.
- an insulator is formed on the bottoms of first troughs 600 , bars of SOI are formed between first troughs 600 , and the topography on the working surface of substrate 305 is separated from substrate 305 by an insulating layer 2100 illustrated in the perspective view of FIG. 21 .
- substrate 305 is understood to include bulk semiconductor as well as SOI embodiments in which the semiconductor integrated circuits formed on the surface of substrate 305 are isolated from each other and an underlying semiconductor portion of substrate 305 by an insulating layer.
- processing of first troughs 600 to carry the first gate lines YG 1 , YG 2 , . . . , YGN varies slightly from the bulk semiconductor embodiment described with respect to FIGS. 10 and 11 .
- a barrier layer 1005 need not be formed to protect the floating gate regions 1000 .
- a portion of the substrate 305 that underlies a portion of the first troughs 600 between the floating gate regions 1000 is removed by selectively anisotropically etching the silicon dioxide insulator portion of substrate 305 to a depth sufficient to carry the first gate lines YG 1 , YG 2 , . . . , YGN.
- a portion of the resulting structure of array 105 is illustrated in the perspective view of FIG. 21 , which includes an insulating layer 2100 portion of substrate 305 , as described above.
- the present invention provides an ultra high density flash EEPROM having increased nonvolatile storage capacity. If a floating gate transistor 200 is used to store a single bit of data, an area of only F 2 is needed per bit of data. If multiple charge states (more than two) are used, an area of less than F 2 is needed per bit of data.
- the increased storage capacity of the ultra high density flash EEPROM is particularly advantageous in replacing hard disk drive data storage in computer systems. In such an application, the delicate mechanical components included in the hard disk drive are replaced by rugged, small, and durable solid-state ultra high density flash EEPROM packages.
- the ultra high density flash EEPROMs provide improved performance, extended rewrite cycles, increased reliability, lower power consumption, and improved portability.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar. Mutually orthogonal first gate lines and second gate lines provide addressing of the control gates. First source/drain terminals are row addressable by interconnection lines disposed substantially parallel to the first gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the second gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F2 is needed per bit of data.
Description
- This application is a Divisional of U.S. application Ser. No. 09/866,938, filed May 29, 2001, which is a Divisional of U.S. application Ser. No. 09/035,304, filed Feb. 27, 1998, which is a Divisional of U.S. application Ser. No. 08/889,554, filed Jul. 8, 1997, now issued as U.S. Pat. No. 5,973,356, all of which are incorporated herein by reference.
- This application is related to U.S. Pat. No. 5,936,274, which disclosure is herein incorporated by reference.
- This invention relates generally to integrated circuits, and particularly to floating gate transistor structures for use in nonvolatile semiconductor memories such as in flash EEPROM memory cells.
- Electrically erasable and programmable read only memories (EEPROMs) are reprogrammable nonvolatile memories that are widely used in computer systems for storing data both when power is supplied or removed. The typical data storage element of an EEPROM is a floating gate transistor, which is a field-effect transistor (FET) having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Data is represented by charge stored on the floating gate and the resulting conductivity obtained between source and drain regions.
- Increasing the storage capacity of EEPROM memories requires a reduction in the size of the floating gate transistors and other EEPROM components in order to increase the EEPROM's density. However, memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, the present generation of high density dynamic random access memories (DRAMS), which are capable of storing 256 Megabits of data, require an area of 8F2 per bit of data. There is a need in the art to provide even higher density memories in order to further increase storage capacity.
- In the drawings, like numerals describe substantially similar components throughout the several views.
-
FIG. 1 is a schematic/block diagram illustrating generally an architecture of one embodiment of a nonvolatile memory, according to the teachings of the invention, including an array having a plurality of memory cells. -
FIG. 2 is a schematic diagram illustrating generally one embodiment of an array of memory cells according to the teachings of the invention. -
FIG. 3 is a perspective view illustrating generally one embodiment of a portion of an array of memory cells according to the teachings of the invention. -
FIG. 4 is a plan view from above of a working surface of a substrate, which illustrates one embodiment of one of a memory cell according to the teachings of the invention. -
FIGS. 5-20 illustrate generally various stages of one embodiment of a method of forming an array of memory cells according to the teachings of the invention. -
FIG. 21 is a perspective view of a structure dating from another embodiment of a method of forming the array of memory cells according to the invention, using semiconductor-on-insulator (SOI) techniques. - In the following detailed description, reference is made to the accompanying drawings which form a part hereof. and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that the embodiments may be combined, or that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art, including bulk semiconductor and semiconductor-on-insulator (SOI) substrates. In the drawings, like numerals describe substantially similar components throughout the several views. The following detailed description is not to be taken in a limiting sense.
-
FIG. 1 is a schematic/block diagram illustrating generally an architecture of one embodiment of amemory 100 according to the present invention. In the embodiment ofFIG. 1 ,memory 100 is a nonvolatile ultra high density electrically erasable and programmable read only memory (EEPROM) allowing simultaneous erasure of multiple data bits, referred to as flash EEPROM. However, the invention can be applied to other semiconductor memory devices, such as static or dynamic random access memories (SRAMs and DRAMS, respectively), synchronous random access memories or other types of memories that include a matrix of selectively addressable memory cells. -
Memory 100 includes amemory cell array 105, having memory cells therein that include floating gate transistors, as described below.Y gate decoder 110 provides a plurality of first gate lines, YG1, YG2, . . . , YGN for addressing floating gate transistors inarray 105, as described below.X gate decoder 115 provides a plurality of second gate lines, XG1, XG2, . . . , XGN for addressing floating gate transistors inarray 105, as described below. Y source/drain decoder 120 provides a plurality of first source/drain interconnection lines YS1, YS2, . . . , YSN, for accessing first source/drain regions of the floating gate transistors inarray 105, as described below. In an embodiment in which commonly connected first source/drain interconnection lines YS1, YS2, . . . , YSN are used, Y source/drain decoder 120 may be omitted. X source/drain decoder 125 provides a plurality of data lines, XD1, XD2, . . . , XDN for accessing second source/drain regions of the floating gate transistors inarray 105, as described below. X source/drain decoder 125 also typically includes sense amplifiers and input/output (I/O) circuitry for reading, writing, and erasing data to and fromarray 105. In response to address signals A0-AN that are provided onaddress lines 130 during read, write, and erase operations,address buffers 135 control the operation ofY gate decoder 110,X gate decoder 115, Y source/drain decoder 120, and X source/drain decoder 125. The address signals A0-AN are provided by a controller such as a microprocessor that is fabricated separately or together withmemory 100, or otherwise provided by any other suitable circuits. As described in detail below, the address signals A0-AN are decoded byY gate decoder 110,X gate decoder 115, Y source/drain decoder 120, and X source/drain decoder 125 to perform reading, writing, and erasing operations on memory cells that include a number of vertical floating gate field-effect transistors (FETs) formed on the sides of a semiconductor pillar on a substrate. -
FIG. 2 is a schematic diagram illustrating generally one embodiment ofarray 105 in more detail. InFIG. 2 , each memory cell 205 comprises fourfloating gate transistors 200, e.g. four field-effect transistors (FETS), each having an electrically isolated (floating) gate that controls electrical conduction between source and drain regions. Thefloating gate transistors 200 are arranged in cells 205, such as cells 205AA, 205BA, . . . , 205NA, in a first direction, e.g. in the Y-direction of the first source/drain interconnection lines YS1, YS2, . . . , YSN, and in cells such as 205AA, 205AB . . . , 205AN in a second direction, e.g. in the X-direction of the data lines, XD1, XD2, . . . , XDN. In the embodiment ofFIG. 2 , each cell 205 includes fourfloating gate transistors 200 that share a common first source/drain region, such as a source region coupled to one of the first source/drain interconnection lines YS1, YS2, . . . , YSN. Thefloating gate transistors 200 of each cell 205 also share a common second source/drain region, such as a drain region coupled to one of the data lines, XD1, XD2, . . . , XDN. Each cell 205 has first and second source/drain regions that are fabricated using a common semiconductor pillar on a substrate, as explained below. -
FIG. 3 is a perspective view illustrating generally one embodiment of a portion ofarray 105, including portions of two cells 205 offloating gate transistors 200, such as illustrated inFIG. 2 . InFIG. 3 , the substantially identical cells 205 are illustrated by way of example through cells 205AA and 205BA. Cells 205AA and 205BA each include asemiconductor pillar 300, initially of a first conductivity type such as P-silicon, fabricated upon amonolithic substrate 305. In one embodiment,substrate 305 is a bulk semiconductor, such as P-silicon. In another embodiment, a semiconductor-on-insulator (SOI)substrate 305 includes an insulating layer, such as silicon dioxide (SiO2), as described below. - Each
pillar 300 includes a first source/drain region of a second conductivity type, such as N+silicon source region 310, formed proximally to a sub-micron dimensioned interface betweenpillar 300 andsubstrate 305. Eachpillar 300 also includes a second source/drain region of the second conductivity type, such as N+silicon drain region 315, that is distal tosubstrate 305, and separated fromsource region 310 by a first conductivity type region, such as P-body region 320. - Each
pillar 300 provides asource region 310, adrain region 315, and abody region 320 for the four floatinggate transistors 200 of a particular memory cell 205. In one embodiment, the physical dimensions of eachpillar 300 and the doping of P-body region 320 are both sufficiently small to allow operation of the floatinggate transistors 200 that is characteristic of fully depleted body transistors. First source/drain region interconnection line YS1 electrically interconnects thesource region 310 of eachpillar 300. of cells 205AA, 205BA, . . . , 205BN. In one embodiment, the first source/drain interconnection lines YS1, YS2, . . . , YSN, comprise a conductively doped semiconductor of the second conductivity type, such as N+ silicon, disposed at least partially withinsubstrate 305. For example, dopants can be ion-implanted or diffused intosubstrate 305 to form the first source/drain interconnection lines YS1, YS2, . . . , YSN. In another embodiment, the first source/drain interconnection lines YS1, YS2, . . . , YSN are formed abovesubstrate 305. For example, a doped epitaxial semiconductor layer can be grown onsubstrate 305, from which first source/drain interconnection lines YS1, YS2, . . . , YSN are formed. Alternatively, an undoped epitaxial semiconductor layer can be grown onsubstrate 305, and dopants then introduced by ion-implantation or diffusion to obtain the first source/drain interconnection lines YS1, YS2, . . . , YSN of the desired conductivity. - Each
pillar 300 is outwardly formed fromsubstrate 305, and is illustrated inFIG. 3 as extending vertically upward fromsubstrate 305. Eachpillar 300 has a top region that is separated fromsubstrate 305 by four surrounding side regions. A floatinggate 325 is formed substantially adjacent to each side surface ofpillar 300, and separated therefrom by agate dielectric 330, such that there are four floatinggates 325 perpillar 300, thoughFIG. 3 omits some of the floatinggates 325 for clarity of illustration. Each floatinggate 325 has a corresponding substantiallyadjacent control gate 335, from which it is separated by anintergate dielectric 340. Except at the periphery ofarray 105, eachcontrol gate 335 is interposed between two approximatelyadjacent pillars 300 and shared by two floatinggate transistors 200, each of these floatinggate transistors 200 having portions in one of the two approximatelyadjacent pillars 300. - Also interposed between approximately
adjacent pillars 300, except at the periphery ofarray 105, are first gate line YG1, YG2, . . . , YGN that are substantially parallel to each other in the first direction, e.g. the Y-direction. Each of the first gate lines YG1, YG2, . . . , YGN interconnects ones of thecontrol gates 335. For example, first gate line YG1 electrically interconnectscontrol gates 335 of floatinggate transistors 200 in cells 205AA, 205BA, . . . , 205BN. In the embodiment ofFIG. 3 , the first gate lines YG1, YG2, . . . , YGN are disposed at least partially withinsubstrate 305, as described below. - Also interposed between approximately
adjacent pillars 300, except at the periphery ofarray 105, are second gate lines XG1, XG2, . . . , XGN that are substantially parallel to each other in the second direction, e.g. the X-direction. Each of the second gate lines XG1, XG2, . . . , XGN interconnects ones of thecontrol gates 335. For example, second gate line XG2 electrically interconnectscontrol gates 335 of floatinggate transistors 200, in which the control gates are shared between pairs of cells 205, e.g. 205AA and 205BA, 205AB and 205BB . . . , 205AN and 205BN. In the embodiment ofFIG. 3 , the second gate lines XG1, XG2, . . . , XGN are disposed abovesubstrate 305, as described below. - Drain
regions 315 of thepillars 300 are interconnected by data lines XD1, XD2, . . . , XDN that are substantially parallel to each other in the second direction, e.g. the X-direction.FIG. 3 illustrates, by way of example, data lines XD1 and XD2, which are shown schematically for clarity. However, it is understood that data lines XD1, XD2, . . . , XDN comprise metal or other interconnection lines that are isolated from the underlying topology,e.g. pillars 300, floatinggates 325,control gates 335, first gate lines YG1, YG2, . . . , YGN, and second gate lines XG1, XG2, . . . , XGN, by an insulating layer through which contact holes are etched to access thedrain regions 315 of thepillars 300. -
FIG. 4 is a plan view, looking toward the working surface ofsubstrate 305, illustrating generally by way of example one embodiment of one of cells 205 of four floatinggate transistors 200, such as cell 205BB. InFIG. 4 , each of the four floatinggates 325 is adjacent to one side ofpillar 300, and separated therefrom bygate dielectric 330. Eachcontrol gate 335 is separated from a corresponding floatinggate 325 by anintergate dielectric 340, and is integrally formed together with one of the first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN. Thecontrol gates 335 that are integrally formed together with ones of the first gate lines YG1, YG2, . . . , YGN protrude upwardly therefrom such that an overlap capacitance is created with floatinggates 325 that are disposed on either side thereof. - The center-to-center spacing (“pitch”) between adjacent first gate lines YG1, YG2, . . . , YGN, such as between YG2 and YG3, or between adjacent second gate lines XG1, XG2, . . . , XGN, such as between XG2 and XG3, is twice the minimum lithographic feature size F. Since four floating
gate transistors 200 are contained within a cell 205 having an area of 4F2, an area of only F2 is needed per bit of data. In another embodiment, multiple charge states (more than two) are used to obtain correspondingly higher data storage densities, such that an area of less than F2 is needed per bit of data, since more than one bit of data can be stored on a single floatinggate transistor 200. In one embodiment, four charge states are used to store two bits of data per floatinggate transistor 200, corresponding to eight bits of data per memory cell 205. One example of using more than two charge states to store more than one bit of data per transistor is set forth an article by T.-S. Jung et al., entitled “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory For Mass Storage Applications,” IEEE J. Solid-State Circuits, Vol. 31, No. 11, November 1996. In a further embodiment, a continuum of charge states is used to store analog data inarray 105. - In one embodiment, programming of one of the floating
gate transistors 200 is by hot electron injection. For example, a voltage of approximately 10 volts is provided, such as by one ofY gate decoder 110 orX gate decoder 115, through a particular one of the first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN to aparticular control gate 335. A resulting inversion region (channel) is formed in thebody region 320 at the surface that is approximately adjacent to the particular one of the first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN. A voltage of approximately 5 Volts is provided, such as by X source/drain decoder 125, through a particular one of data lines XD1, XD2, . . . , XDN to aparticular drain region 315. A voltage of approximately 0 Volts is provided, such as by Y source/drain decoder 120, through a particular one of first source/drain interconnection lines YS1, YS2, . . . , YSN, to theparticular source region 310 of the floatinggate transistor 200. Electrons are injected onto the floatinggate 325 interposed between thecontrol gate 335 and thepillar 300 in which theparticular drain region 315 is disposed. The exact value of the voltages provided to theparticular control gate 335 and drainregion 315 will depend on the physical dimension of the floatinggate transistor 200, including the thickness of thegate dielectric 330, the thickness of theintergate dielectric 340, and the separation betweensource region 310 and drainregion 315. Alternatively, if higher voltages are provided to controlgate 335, and thegate dielectric 330 andintergate dielectric 340 are made thinner, the floatinggate transistor 200 may be programmed instead by Fowler-Nordheim tunneling of electrons h m thebody region 320,source region 310, or drainregion 315. - Addressing a particular memory cell 205 for reading data includes selecting a particular one of data lines XD1, XD2, . . . , XDN and also selecting a particular one of first source/drain interconnection lines YS1, YS2, . . . , YSN. Addressing a particular floating
gate transistor 200 within the particular memory cell 205 for reading data further includes selecting a particular one of first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN. - In one embodiment, reading data stored on a particular floating
gate transistor 200 includes providing a voltage of approximately 5 volts, such as by one ofY gate decoder 110 orX gate decoder 115, through a particular one of the first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN to theparticular control gate 335 of the floatinggate transistor 200. A voltage of approximately 0 Volts is provided, such as by Y source/drain decoder 120, through a particular one of first source/drain interconnection lines YS1, YS2, . . . , YSN, to theparticular source region 310 of the particular floatinggate transistor 200. A particular one of data lines XD1, D2 . . . , XDN that is switchably coupled to thedrab region 315 of the floatinggate transistor 200 is precharged to a positive voltage by a sense amplifier in X source/drain decoder 125, then coupled to thedrain region 315 to determine the conductivity state of the floatinggate transistor 200 between itssource region 310 and drainregion 315. - If there are no electrons stored on the floating
gate 325, the floatinggate transistor 200 will conduct between itssource region 310 and drainregion 315, decreasing the voltage of the particular one of data lines XD1, XD2, . . . , XDN toward that voltage of itssource region 310, e.g. toward a “low” binary logic level of approximately 0 Volts. If there are electrons stored on the floatinggate 325, the floatinggate transistor 200 will not conduct between itssource region 310 and drainregion 315. As a result, the sense amplifier will tend to increase the voltage of the particular one of data lines XD1, XD2, . . . , XDN toward a positive voltage, e.g. toward a “high” binary logic voltage level. - In one embodiment, erasure of floating
gate transistors 200 includes providing an erasure voltage difference of approximately between −10 and −12 Volts from asource region 310 to acorresponding control gate 335. For example, a voltage of approximately 0 Volts is provided, such as by Y source/drain decoder 120, to sourceregions 310 of floatinggate transistors 200 that are interconnected by one or several first source/drain interconnection lines YS1, YS2, . . . , YSN. A voltage of approximately between −10 and −12 Volts is provided, such as by one ofY gate decoder 110 orX gate decoder 115, through a corresponding one or several of the first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN to thecontrol gates 335 of the floatinggate transistors 200 to be erased. As a result of the negative voltage applied to thecontrol gates 335, electrons are removed from the corresponding floatinggates 325 by Fowler-Nordheim tunneling, thereby erasing the data from ones of the floatinggate transistors 200. In another example, a voltage of approximately between −5 and −6 Volts is applied to thecontrol gates 335 and a voltage of approximately between +5 and +6 Volts is applied to thesource regions 310 in order to obtain the erasure voltage difference of approximately between −10 and −12 Volts from asource region 310 to acorresponding control gate 335. The exact value of the erasure voltage difference will vary depending upon the physical dimensions of the floatinggate transistor 200 and the thicknesses ofgate dielectric 330 andintergate dielectric 340. - In one embodiment, the
entire array 105 of floatinggate transistors 200 is simultaneously erased by applying approximately between −10 and −12 Volts to each of first gate lines YG1, YG2, . . . , YGN and second gate lines XG1, XG2, . . . , XGN, and also applying 0 Volts to each of first source/drain interconnection lines YS1, YS2, . . . , YSN. In another embodiment, one or more sectors ofarray 105 are simultaneously erased by selectively applying approximately between −10 and −12 Volts to one or more of first gate lines YG1, YG2, . . . , YGN or second gate lines XG1, XG2, . . . , XGN, and also applying 0 Volts to one or more of first source/drain interconnection lines YS1, YS2, . . . , YSN. -
FIGS. 5-20 illustrate generally one embodiment of a method of formingmemory array 105. In this embodiment, thearray 105 is formed using bulk silicon processing techniques and is described, by way of example, with respect to a particular technology having a minimum feature size F, which is also sometimes referred to as a critical dimension (CD), of 0.4 microns. However, the process steps described below can be scaled accordingly for other minimum feature sizes without departing from the scope of the invention. - In
FIG. 5 , a P-silicon starting material is used forsubstrate 305. A first source/drain layer 500, of approximate thickness between 0.2 microns and 0.5 microns, is formed at a working surface ofsubstrate 305. In one embodiment, first source/drain layer 500 is N+ silicon formed by ion-implantation of donor dopants intosubstrate 305. In another embodiment, first source/drain layer 500 is N+ silicon formed by epitaxial growth of silicon uponsubstrate 305. On the first source/drain layer 500, asemiconductor epitaxial layer 505, such as P-silicon of 0.6 micron approximate thickness, is formed, such as by epitaxial growth. A second source/drain layer 510, such as N+ silicon of 150 nanometer approximate thickness, is formed at a surface of theepitaxial layer 505, such as by ion-implantation of donor dopants into P-epitaxial layer 505 or by epitaxial growth of N+ silicon on P-epitaxial layer 505. A thin layer of silicon dioxide (SiO2), referred to aspad oxide 515, is deposited on the second source/drain layer 510.Pad oxide 515 has a thickness of approximately 10 nanometers. A layer of silicon nitride (Si3N4), referred to aspad nitride 520, is deposited on thepad oxide 515.Pad nitride 520 has a thickness of approximately 200 nanometers. - In
FIG. 6 , photoresist masking and selective etching techniques are used to form, in the first direction (e.g., the Y direction, which is perpendicular to the plane of the drawing ofFIG. 6 ), a plurality of substantially parallelfirst troughs 600 that extend through thepad nitride 520,pad oxide 515, second source/drain layer 510, the underlying portion ofepitaxial layer 505, and at least partially into first source/drain layer 500. The photoresist is then removed. - In
FIG. 7 , a thin silicon nitrideoxidation barrier layer 700 is deposited by chemical vapor deposition (CVD) to protect against oxidation of sidewalls offirst troughs 600.Barrier layer 700 is anisotropically etched to expose bottom portions offirst troughs 600. Abottom insulation layer 705 of silicon dioxide is formed on the bottoms offirst troughs 600 by thermal oxidation of the exposed bottom portions offirst troughs 600. - In
FIG. 8 ,barrier layer 700 is stripped from the sidewalls of thefirst troughs 600, such as by a brief phosphoric acid etch, which is timed to expose the sidewalls of thefirst troughs 600 but which avoids significant removal of thepad nitride 520. A firstgate dielectric layer 800 such as, for example, silicon dioxide of thickness approximately between 5 nanometers and 10 nanometers (sometimes referred to as “tunnel oxide”), is formed substantially adjacent to the exposed sidewalls of thefirst troughs 600. A firstconductive layer 805, such as N+ doped polysilicon, is formed in thefirst troughs 600, such as by CVD, to fill thefirst troughs 600. The firstconductive layer 805 is planarized, such as by chemical mechanical polishing (CMP) or other suitable planarization technique. - In
FIG. 9 , the firstconductive layer 805 is etched back in thefirst troughs 600 to approximately 100 nanometers below the silicon surface, which is defined by the interface between the second source/drain layer 510 and thepad oxide 515 layer. A first spacer layer, such as silicon nitride of an approximate thickness of 7 nanometers, is deposited by CVD and anisotropically etched by reactive ion etching (RIE) to leave nitridefirst spacers 900 along the sidewalls of thefirst troughs 600. A second spacer layer, such as silicon dioxide of an approximate thickness of 90 nanometers, is deposited by CVD and anisotropically etched by RIE to leavesecond spacers 905 along the sidewalls of thefirst troughs 600. - In
FIG. 10 , a portion of the firstconductive layer 805 infirst troughs 600 betweensecond spacers 905 is removed, such as by usingspacers 905 as a mask while etching down tobottom insulation layer 705, thereby forming from the firstconductive layer 805 floatinggate regions 1000 along the sidewalls of thefirst troughs 600. A thinoxidation barrier layer 1005, such as silicon nitride of approximate thickness of 5 nanometers, is deposited by CVD.Barrier layer 1005 is removed from thebottom insulation layer 705 infirst troughs 600 by anisotropic etching. The remaining portions ofbarrier layer 1005 protect the floatinggate regions 1000 during subsequent processing described below. - In
FIG. 11 , a portion of thebottom insulation layer 705 is removed, exposing a portion of theunderlying substrate 305, by an anisotropic etch that is timed to leave enough ofsecond spacers 905 to protect floatinggate regions 1000 during a subsequent etch ofsubstrate 305. A portion ofsubstrate 305 that underlies a portion offirst troughs 600 between the floatinggate regions 1000 is removed by selectively anisotropically etching thesubstrate 305 to a depth sufficient to carry the first gate lines YG1, YG2, . . . , YGN. A firsttrough insulation layer 1100 is formed on sidewall and bottom regions of the etched portions ofsubstrate 305 underlying thefirst troughs 600.Barrier layer 1005 is removed to expose the floatinggate regions 1000 infirst troughs 600, such as by wet etching. - The
first intergate dielectric 340, having an approximate thickness between 7 nanometers and 15 nanometers, is formed on the exposed portions of floatinggate regions 1000. In one embodiment, a silicondioxide intergate dielectric 340 is formed by thermal oxidation of the floatinggate regions 1000. In another embodiment, anoxynitride intergate dielectric 340 is formed on the floatinggate regions 1000 by CVD. - First gate lines YG1, YG2, . . . , YGN are formed in the etched portions of
substrate 305 underlying thefirst troughs 600 between opposing floatinggate regions 1000 in thefirst troughs 600. First gate lines YG1, YG2, . . . , YGN are insulated fromsubstrate 305 by firsttrough insulation layer 1100.Control gates 335 are formed in thefirst troughs 600 between opposing floatinggate regions 1000, and separated therefrom by thefirst intergate dielectric 340. In one embodiment, first gate lines YG1, YG2, . . . , YGN and controlgates 335 are formed together by depositing N+ polysilicon to fillfirst troughs 600, and etching back the deposited N+ polysilicon approximately to the top portion of the floatinggate regions 1000. - In
FIG. 12 , acap layer 1200 is formed, such as by CVD of silicon dioxide, and then planarized, such as by CMP, such that the top surface ofcap layer 1200 is substantially even with the top surface ofpad nitride 520. Amasking layer 1205 is formed, such as silicon nitride deposited by CVD to an approximate thickness of 100 nanometers. Anothermasking layer 1210 is also formed, such as polysilicon deposited by CVD to an approximate thickness of 100 nanometers. Aphotoresist layer 1215 is formed onmasking layer 1210. -
FIG. 13 is a perspective view, illustrating the selective etching, in a second direction (X-direction) that is substantially orthogonal to the first direction (Y-direction), of a plurality of substantially parallelsecond troughs 1300, as described below. Formingsecond troughs 1300 includes selectively etchingmasking layer 1210 andunderlying masking layer 1205, such that portions ofcap layer 1200 in thesecond troughs 1300 are exposed. Withphotoresist layer 1215 still in place, a nonselective dry etch is used to simultaneously remove exposed silicon dioxide and polysilicon in intersecting portions offirst troughs 600 andsecond troughs 1300, including the removing of: portions ofcap layer 1200,gate dielectric 800, floatinggate regions 1000,intergate dielectric 340, and thecontrol gate 335 portions of first gate lines YG1, YG2, . . . , YGN. The nonselective dry etch removal proceeds at least to the depth of the interface between floatinggate regions 1000 and underlyingbottom insulation layer 705, thereby separating floatinggate regions 1000 into the isolated floatinggates 325. During the nonselective dry etch, the regions betweenfirst troughs 600 are protected by thepad nitride 520 and the regions betweensecond troughs 1300 are protected by selectively patternedphotoresist layer 1215. - In the plan view of
FIG. 14 , thephotoresist layer 1215 has been removed by conventional photoresist stripping techniques, thereby exposing the underlying. selectively patternedpolysilicon masking layer 1210. An insulatinglayer 1400, such as silicon dioxide deposited by CVD, is formed everywhere on the topography of the working surface ofsubstrate 305, thereby filling the nonselectively dry-etched intersections of thefirst troughs 600 andsecond troughs 1300. The insulatinglayer 1400 is then planarized, such as by CMP, and recess etched to a depth that is slightly above the interface between second source-drain layer 510 andpad oxide 515, thereby leaving behind recessed portions of insulatinglayer 1400 in the nonselectively dry-etched intersections of thefirst troughs 600 andsecond troughs 1300, as illustrated inFIG. 14 . - In the plan view of
FIG. 15 , the exposed portions of pad nitride 520 (e.g., betweenfirst troughs 600 and within second troughs 1300) are removed by a selective etch of silicon nitride, thereby exposing underlying portions ofpad oxide 515. The exposed portions of pad oxide 515 (e.g., betweenfirst troughs 600 and within second troughs 1300) are removed by dipping into a wet etchant, which is timed to remove the exposed portions ofpad oxide 515, but to leave most of the remaining portions of the thicker silicondioxide insulating layer 1400 intact. The removing of portions ofpad oxide 515 exposes the second source/drain layer 510 portion of the underlyingsilicon epitaxial layer 505. The exposed portions of silicon epitaxial layer 505 (e.g., betweenfirst troughs 600 and within second troughs 1300) are removed by a selective etching that is preferential to silicon over silicon dioxide, thereby formingrecesses 1500 insecond troughs 1300 betweenfirst troughs 600.Recesses 1500, which are considered to be part ofsecond troughs 1300, are etched throughepitaxial layer 505 and at least partially into first source/drain layer 500.Etching recesses 1500 also removes the remaining portions ofpolysilicon masking layer 1210, thereby exposing underlying siliconnitride masking layer 1205, as illustrated inFIG. 15 . -
FIG. 16 is a cross-sectional view in the direction of second troughs 1300 (e.g. such that the X-direction is orthogonal to the plane of the illustration ofFIG. 16 ). as indicated by the cut line 16-16 inFIG. 15 . InFIG. 16 , a thin silicon nitrideoxidation barrier layer 1600 is deposited by CVD to protect against oxidation of sidewalls ofsecond troughs 1300.Barrier layer 1600 is anisotropically etched to expose bottom portions ofsecond troughs 1300. Abottom insulation layer 1605 of silicon dioxide is formed on the bottoms ofsecond troughs 1300, such as silicon dioxide of approximate thickness of 50 nanometers formed by thermal oxidation of the exposed bottom portions ofsecond troughs 1300. - In
FIG. 17 ,barrier layer 1600 is stripped from the sidewalls of thesecond troughs 1300, such as by a brief phosphoric acid etch, which is timed to expose the sidewalls of thesecond troughs 1300 but which avoids significant removal of the siliconnitride masking layer 1205. A secondgate dielectric layer 1700, such as silicon dioxide of thickness approximately between 5 nanometers and 10 nanometers (sometimes referred to as “tunnel oxide”), is formed substantially adjacent to the exposed sidewalls of thesecond troughs 1300. A secondconductive layer 1705, such as N+ doped polysilicon, is formed in thesecond troughs 1300, such by CVP, to fill thesecond troughs 1300. The secondconductive layer 1705 is planarized such as by chemical mechanical polishing (CMP) or other suitable planarization technique. - In
FIG. 18 , the secondconductive layer 1705 is etched back in thesecond troughs 1300 to approximately at or slightly above the level of the silicon surface, which is defined by the interface between the second source/drain layer 510 and thepad oxide 515 layer. Thus, in thesecond troughs 1300, the top surface of the secondconductive layer 1705 is approximately even with the top surface of the recessed portions of insulatinglayer 1400. A spacer layer, such as silicon nitride of an approximate thickness of 100 nanometers, is deposited by CVD and anisotropically etched by reactive ion etching (RTE) to leave nitridethird spacers 1800, along the sidewalls of thesecond troughs 1300, e.g. on the etched back portions of the secondconductive layer 1705 and on the recessed portions of insulatinglayer 1400, and against thesecond gate dielectric 1700. - In the perspective view of
FIG. 19 ;third spacers 1800 are used as a mask for the anisotropic etching of the etched back portions of polysilicon secondconductive layer 1705 together with the recessed portions of silicondioxide insulating layer 1400. By first utilizing an etchant to remove silicon dioxide, thesecond troughs 1300 are etched in insulatinglayer 1400 to a depth sufficient to carry a second gate line X1, X2, . . . , XN, but not so great as to expose the first gate lines Y1, Y2, . . . , YN underlying the recessed portions of silicondioxide insulating layer 1400 insecond troughs 1300. Then, the anisotropic etch is continued using a selective etchant to remove polysilicon but not silicon dioxide until thebottom insulation layer 1605 is exposed, thereby forming from the secondconductive layer 1705 separate floatinggates 325 along the sidewalls of thesecond troughs 1300. - In the perspective view of
FIG. 20 , asecond intergate dielectric 2000 is formed in thesecond troughs 1300, such that thesecond intergate dielectric 2000 has an approximate thickness between 7 nanometers and 15 nanometers and being formed by thermal growth of silicon dioxide or deposition of oxynitride by CVD.Control gates 335 are formed between opposing floatinggates 325 in thesecond troughs 1300 and separated therefrom by thesecond intergate dielectric 2000. Thecontrol gates 335 insecond troughs 1300 are formed together with the second gate lines X1, X2, . . . , XN insecond troughs 1300 by a single deposition of N+ doped polysilicon that fillssecond troughs 1300 and is planarized, such as by CMP. Phosphoric acid is used to remove the remaining silicon nitride, such asthird spacers 1800,masking layer 1205, andpad nitride 520, leaving the structure illustrated inFIG. 20 . An insulator such as silicon dioxide is then deposited, and subsequent processing follows conventional techniques for forming contact holes, terminal metal, and inter level insulator steps to complete wiring of the cells 205 and other circuits ofmemory 100. - Though
FIGS. 5-20 illustrate generally one embodiment of forming thememory array 105 using bulk silicon processing techniques, in another embodiment a semiconductor-on-insulator (SOI) substrate is formed fromsubstrate 305. In one such embodiment, a P-silicon starting material is used forsubstrate 305, and processing proceeds similarly to the bulk semiconductor embodiment described inFIG. 5-7 . However, after thebarrier layer 700 is formed inFIG. 7 , an isotropic chemical etch is used to fully undercut the semiconductor regions separating thefirst troughs 600, and a subsequent oxidation step is used to fill in the evacuated regions formed by the undercutting. As a result, an insulator is formed on the bottoms offirst troughs 600, bars of SOI are formed betweenfirst troughs 600, and the topography on the working surface ofsubstrate 305 is separated fromsubstrate 305 by an insulatinglayer 2100 illustrated in the perspective view ofFIG. 21 . - Thus, in the above described Figures,
substrate 305 is understood to include bulk semiconductor as well as SOI embodiments in which the semiconductor integrated circuits formed on the surface ofsubstrate 305 are isolated from each other and an underlying semiconductor portion ofsubstrate 305 by an insulating layer. - One such method of forming bars of SOI is described in the Noble U.S. patent application Ser. No. 08/745,708 which is assigned to the assignee of the present application and which is herein incorporated by reference. Another such method of forming regions of SOI is described in the Forbes U.S. patent application Ser. No. 08/706,230, which is assigned to the assignee of the present application and which is herein incorporated by reference.
- In an SOI embodiment of the present invention, processing of
first troughs 600 to carry the first gate lines YG1, YG2, . . . , YGN varies slightly from the bulk semiconductor embodiment described with respect toFIGS. 10 and 11 . Abarrier layer 1005 need not be formed to protect the floatinggate regions 1000. A portion of thesubstrate 305 that underlies a portion of thefirst troughs 600 between the floatinggate regions 1000 is removed by selectively anisotropically etching the silicon dioxide insulator portion ofsubstrate 305 to a depth sufficient to carry the first gate lines YG1, YG2, . . . , YGN. A portion of the resulting structure ofarray 105 is illustrated in the perspective view ofFIG. 21 , which includes an insulatinglayer 2100 portion ofsubstrate 305, as described above. - Thus, the present invention provides an ultra high density flash EEPROM having increased nonvolatile storage capacity. If a floating
gate transistor 200 is used to store a single bit of data, an area of only F2 is needed per bit of data. If multiple charge states (more than two) are used, an area of less than F2 is needed per bit of data. The increased storage capacity of the ultra high density flash EEPROM is particularly advantageous in replacing hard disk drive data storage in computer systems. In such an application, the delicate mechanical components included in the hard disk drive are replaced by rugged, small, and durable solid-state ultra high density flash EEPROM packages. The ultra high density flash EEPROMs provide improved performance, extended rewrite cycles, increased reliability, lower power consumption, and improved portability. - It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. For example, though the memory cells 205 have been described with respect to a particular embodiment having four floating
gate transistors 200 perpillar 300, a different number of floating gate transistors per pillar could also be used. It is also understood that the above structures and methods, which have been described with respect to EEPROM memory devices having floatinggate transistors 200, are also applicable to dynamic random access memories (DRAMS) or other integrated circuits using vertically oriented field-effect transistors (s) that do not have floating gates. Thus, the scope of the invention is not limited to the particular embodiments shown and described herein.
Claims (34)
1. A method of forming a memory array on a substrate, comprising:
forming a first source/drain layer at a surface of the substrate;
forming a semiconductor epitaxial layer on the first source/drain layer;
forming a second source/drain layer at a surface of the epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming a first gate dielectric layer substantially adjacent to sidewall regions of the first troughs;
forming a first conductive layer in the first troughs;
removing a portion of the first conductive layer in the first troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the first gate dielectric layer;
etching a portion of the substrate underlying a portion of the first troughs between the floating gate regions;
forming a first intergate dielectric layer on exposed portions of the floating gate regions in the first troughs;
forming first gate lines in the underlying etched portion of the substrate between opposing floating gate regions in the first troughs; and
forming control gate regions in the first troughs between opposing floating gate regions and separated therefrom by the first intergate dielectric layer.
2. The method of claim 1 , further comprising:
etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming a second gate dielectric layer substantially adjacent to sidewall regions of the second troughs;
forming a second conductive layer in the second troughs;
removing a portion of the second conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the second gate dielectric layer;
forming a second intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; and
forming control gate regions and second gate lines between opposing floating gate regions in the second troughs by the second intergate dielectric layer.
3. The method of claim 1 , wherein the substrate further comprises a bulk semiconductor.
4. The method of claim 1 , wherein the substrate further comprises a semiconductor on insulator portion.
5. The method of claim 1 , further comprising:
forming an insulating layer undercutting semiconductor regions between the first troughs.
6. The method of claim 2 , further comprising:
forming a thin silicon nitride oxidation barrier layer by chemical vapor deposition on the sidewall regions of the second troughs;
anisotropically etching the thin silicon nitride oxidation barrier layer to expose bottom portions of the second troughs;
forming a bottom insulation layer on the bottom portions of the second troughs by thermal oxidation; and
stripping the thin silicon nitride oxidation barrier layer from the sidewall regions of the second troughs by a brief phosphoric acid etch.
7. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer and comprising P-silicon;
forming a thin layer of silicon dioxide on the second source/drain layer;
forming a layer of silicon nitride on the thin layer of silicon dioxide;
etching a plurality of substantially parallel troughs in the epitaxial layer;
forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;
forming gate lines between opposing floating gate regions in the troughs; and
forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.
8. The method of claim 7 , wherein forming the first source/drain layer further comprises forming the first source/drain layer with an approximate thickness ranging between 0.2 microns and 0.5 microns.
9. The method of claim 7 , wherein forming the thin layer of silicon dioxide further comprises forming the thin layer of silicon dioxide with an approximate thickness of 10 nanometers.
10. A method, comprising:
forming a first source/drain layer at a surface of a substrate, the first source/drain comprising N+ silicon formed by epitaxial growth of silicon upon the substrate;
forming a semiconductor epitaxial layer on the first source/drain layer;
forming a second source/drain layer at a surface of the epitaxial layer by ion implantation, the second source/drain layer comprising N+ silicon and having an approximate thickness of 150 nanometers;
forming a thin layer of silicon dioxide on the second source/drain layer, the thin layer of silicon dioxide having an approximate thickness of 10 nanometers;
forming a layer of silicon nitride on the thin layer of silicon dioxide, the layer of silicon nitride having an approximate thickness of 200 nanometers;
etching a plurality of substantially parallel troughs in the epitaxial layer;
forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;
forming gate lines between opposing floating gate regions in the troughs; and
forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.
11. The method of claim 10 , wherein forming the first source/drain layer further comprises forming the first source/drain layer with an approximate thickness ranging between 0.2 microns and 0.5 microns.
12. The method of claim 10 , wherein forming at least two floating gate regions further comprises forming the at least two floating gate regions along the sidewall regions of the troughs and separated from the sidewall regions by the gate dielectric layer, the gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.
13. A method, comprising:
forming a first source/drain layer at a surface of a substrate, the substrate comprised of a semiconductor-on-insulator portion, and the a first source/drain layer comprising N+ silicon formed by ion implantation of donor dopants into the substrate;
forming a semiconductor epitaxial layer on the first source/drain layer, the semiconductor epitaxial layer comprising P-silicon and having an approximate thickness of 0.6 microns;
forming a second source/drain layer at a surface of the epitaxial layer by ion implantation, the second source/drain layer comprising N+silicon and having an approximate thickness of 150 nanometers;
forming a thin layer of silicon dioxide on the second source/drain layer;
forming a layer of silicon nitride on the thin layer of silicon dioxide;
etching a plurality of substantially parallel troughs in the epitaxial layer;
forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;
forming gate lines between opposing floating gate regions in the troughs; and
forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.
14. The method of claim 13 , further comprising:
forming a conductive layer in the troughs.
15. The method of claim 14 , further comprising:
removing a portion of the conductive layer in the troughs; and
etching a portion of the substrate underlying a portion of the troughs between floating gate regions.
16. The method, comprising:
forming a first source/drain layer at a surface of a substrate, the first source/drain comprising N+silicon formed by ion implantation of donor dopants into the substrate;
forming a second source/drain layer at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer and comprising P-silicon;
forming a thin layer of silicon dioxide on the second source/drain layer;
forming a layer of silicon nitride on the thin layer of silicon dioxide;
etching a plurality of substantially parallel troughs in the epitaxial layer;
forming an insulating layer undercutting semiconductor regions between the troughs;
forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;
forming gate lines between opposing floating gate regions in the troughs; and
forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.
17. The method of claim 16 , wherein forming at least two floating gate regions further comprises forming at least two floating gate regions along the sidewall regions of the troughs and separated from the sidewall regions by the gate dielectric layer, the gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.
18. The method of claim 16 , wherein forming control gate regions further comprises forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer, the intergate dielectric layer having an approximate thickness that ranges between 7 nanometers and 15 nanometers.
19. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer;
etching a plurality of substantially parallel troughs in the epitaxial layer;
forming a thin silicon nitride oxidation barrier layer by chemical vapor deposition on sidewall regions of the troughs;
anisotropically etching the thin silicon nitride oxidation barrier layer to expose bottom portions of the troughs;
forming a bottom insulation layer on the bottom portions of the troughs by thermal oxidation;
forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer; and
forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.
20. The method of claim 19 , further comprising:
planarizing the first conductive layer using a chemical mechanical polish.
21. The method of claim 19 , further comprising:
stripping the thin silicon nitride oxidation barrier layer from the sidewall regions by a phosphoric acid etch.
22. The method of claim 19 , wherein forming a first source/drain layer further comprises:
forming the first source/drain layer at the surface of the substrate, wherein the substrate is a bulk semiconductor.
23. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming a first bottom insulation layer on bottom portions of the first troughs by thermal oxidation;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and
forming second control gate regions in the troughs between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.
24. The method of claim 23 , further comprising:
forming a second bottom insulation layer on bottom portions of the second troughs by thermal oxidation.
25. The method of claim 23 , further comprising:
forming the second dielectric layer by deposition of oxynitride using chemical vapor deposition.
26. The method of claim 23 , wherein forming first floating gate regions further comprises:
forming the first floating gate regions along the sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.
27. The method of claim 23 , wherein forming second control gate regions further comprises:
forming the second control gate regions along the sidewall regions of the second troughs and separated from the sidewall regions by the second gate dielectric layer, the second gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.
28. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming a first dielectric layer along sidewall regions of the first troughs;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first floating gate regions including a first conductive layer of N+ doped polysilicon;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions including N+ doped polysilicon;
forming first gate lines in the first troughs between opposing first floating gate regions;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
removing material at intersecting portions of first troughs and second troughs to separate the first floating gate regions into first isolated floating gates;
forming a second gate dielectric layer along sidewall regions of the second troughs;
forming second floating gate regions along the sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer, the second floating gate regions including a second conductive layer of N+ doped polysilicon;
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions including N+ doped polysilicon; and
forming second gate lines in the second troughs between opposing second floating gate regions.
29. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first floating gate regions including a first conductive layer of N+ doped polysilicon;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer, the second floating gate regions including a second conductive layer of N+ doped polysilicon; and
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.
30. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions including N+ doped polysilicon;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions including N+ doped polysilicon.
31. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;
forming first gate lines in the first troughs between opposing first floating gate regions;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer;
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer; and
forming second gate lines in the second troughs between opposing second floating gate regions.
32. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions are formed together with first gate lines by depositing N+ polysilicon in the first troughs;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions are formed together with second gate lines by depositing N+ polysilicon in the second troughs.
33. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
removing material at intersecting portions of first troughs and second troughs to separate the first floating gate regions into first isolated floating gates;
forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.
34. A method, comprising:
forming a first source/drain layer at a surface of a substrate;
forming a second source/drain layer at a surface of an epitaxial layer;
etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;
forming a first gate dielectric layer along sidewall regions of the first troughs;
forming first floating gate regions along the sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;
forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;
etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;
forming a second gate dielectric layer along sidewall regions of the second troughs;
forming second floating gate regions along the sidewall regions of the second troughs and separated from the sidewall regions by the second gate dielectric layer; and
forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/491,328 US20060258096A1 (en) | 1997-07-08 | 2006-07-21 | Ultra high density flash memory |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/889,554 US5973356A (en) | 1997-07-08 | 1997-07-08 | Ultra high density flash memory |
US09/035,304 US6238976B1 (en) | 1997-07-08 | 1998-02-27 | Method for forming high density flash memory |
US09/866,938 US20010029077A1 (en) | 1997-07-08 | 2001-05-29 | Ultra high density flash memory |
US11/491,328 US20060258096A1 (en) | 1997-07-08 | 2006-07-21 | Ultra high density flash memory |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/866,938 Division US20010029077A1 (en) | 1997-07-08 | 2001-05-29 | Ultra high density flash memory |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060258096A1 true US20060258096A1 (en) | 2006-11-16 |
Family
ID=25395348
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/889,554 Expired - Lifetime US5973356A (en) | 1997-07-08 | 1997-07-08 | Ultra high density flash memory |
US09/035,304 Expired - Lifetime US6238976B1 (en) | 1997-07-08 | 1998-02-27 | Method for forming high density flash memory |
US09/866,938 Abandoned US20010029077A1 (en) | 1997-07-08 | 2001-05-29 | Ultra high density flash memory |
US11/490,674 Abandoned US20060255397A1 (en) | 1997-07-08 | 2006-07-21 | Ultra high density flash memory |
US11/491,328 Abandoned US20060258096A1 (en) | 1997-07-08 | 2006-07-21 | Ultra high density flash memory |
US11/605,751 Abandoned US20070069281A1 (en) | 1997-07-08 | 2006-11-29 | Ultra high density flash memory |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/889,554 Expired - Lifetime US5973356A (en) | 1997-07-08 | 1997-07-08 | Ultra high density flash memory |
US09/035,304 Expired - Lifetime US6238976B1 (en) | 1997-07-08 | 1998-02-27 | Method for forming high density flash memory |
US09/866,938 Abandoned US20010029077A1 (en) | 1997-07-08 | 2001-05-29 | Ultra high density flash memory |
US11/490,674 Abandoned US20060255397A1 (en) | 1997-07-08 | 2006-07-21 | Ultra high density flash memory |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/605,751 Abandoned US20070069281A1 (en) | 1997-07-08 | 2006-11-29 | Ultra high density flash memory |
Country Status (1)
Country | Link |
---|---|
US (6) | US5973356A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010029077A1 (en) * | 1997-07-08 | 2001-10-11 | Micron Technology, Inc. | Ultra high density flash memory |
US20080080249A1 (en) * | 2006-10-03 | 2008-04-03 | Powerchip Semiconductor Corp. | Non-volatile memory, fabricating method and operating method thereof |
US20080305593A1 (en) * | 2007-06-11 | 2008-12-11 | Ching-Nan Hsiao | Memory structure and method of making the same |
US20080308858A1 (en) * | 2007-06-14 | 2008-12-18 | Micron Technology, Inc. | Semiconductor devices and electronic systems comprising floating gate transistors and methods of forming the same |
US20090321808A1 (en) * | 2008-06-26 | 2009-12-31 | International Business Machines Corporation | Structures, fabrication methods, and design structures for multiple bit flash memory cells |
WO2010083486A1 (en) * | 2009-01-19 | 2010-07-22 | Wms Gaming, Inc. | Transporting and using wagering game data |
US20110163371A1 (en) * | 2005-09-15 | 2011-07-07 | Song Ki-Whan | Methods of fabricating nonvolatile semiconductor memory devices |
US20140061781A1 (en) * | 2012-08-31 | 2014-03-06 | SK Hynix Inc. | Semiconductor device and method of fabricating the same |
Families Citing this family (168)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3583579B2 (en) * | 1997-06-06 | 2004-11-04 | 株式会社東芝 | Nonvolatile semiconductor memory device and method of manufacturing the same |
US5936274A (en) * | 1997-07-08 | 1999-08-10 | Micron Technology, Inc. | High density flash memory |
US6150687A (en) | 1997-07-08 | 2000-11-21 | Micron Technology, Inc. | Memory cell having a vertical transistor with buried source/drain and dual gates |
FR2767219B1 (en) * | 1997-08-08 | 1999-09-17 | Commissariat Energie Atomique | ELECTRICALLY COMPATIBLE PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY DEVICE WITH A CMOS / SELF-MANUFACTURING PROCESS |
US5914511A (en) | 1997-10-06 | 1999-06-22 | Micron Technology, Inc. | Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts |
US6066869A (en) * | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US6528837B2 (en) | 1997-10-06 | 2003-03-04 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US5907170A (en) * | 1997-10-06 | 1999-05-25 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US6025225A (en) * | 1998-01-22 | 2000-02-15 | Micron Technology, Inc. | Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same |
US5963469A (en) | 1998-02-24 | 1999-10-05 | Micron Technology, Inc. | Vertical bipolar read access for low voltage memory cell |
US6246083B1 (en) | 1998-02-24 | 2001-06-12 | Micron Technology, Inc. | Vertical gain cell and array for a dynamic random access memory |
US6242775B1 (en) | 1998-02-24 | 2001-06-05 | Micron Technology, Inc. | Circuits and methods using vertical complementary transistors |
US6274292B1 (en) * | 1998-02-25 | 2001-08-14 | Micron Technology, Inc. | Semiconductor processing methods |
US7804115B2 (en) * | 1998-02-25 | 2010-09-28 | Micron Technology, Inc. | Semiconductor constructions having antireflective portions |
US6448615B1 (en) | 1998-02-26 | 2002-09-10 | Micron Technology, Inc. | Methods, structures, and circuits for transistors with gate-to-body capacitive coupling |
US5991225A (en) | 1998-02-27 | 1999-11-23 | Micron Technology, Inc. | Programmable memory address decode array with vertical transistors |
US6124729A (en) | 1998-02-27 | 2000-09-26 | Micron Technology, Inc. | Field programmable logic arrays with vertical transistors |
US6307235B1 (en) | 1998-03-30 | 2001-10-23 | Micron Technology, Inc. | Another technique for gated lateral bipolar transistors |
US6104066A (en) | 1998-03-30 | 2000-08-15 | Micron Technology, Inc. | Circuit and method for low voltage, voltage sense amplifier |
US6229342B1 (en) | 1998-03-30 | 2001-05-08 | Micron Technology, Inc. | Circuits and method for body contacted and backgated transistors |
US6075272A (en) | 1998-03-30 | 2000-06-13 | Micron Technology, Inc. | Structure for gated lateral bipolar transistors |
US6225165B1 (en) * | 1998-05-13 | 2001-05-01 | Micron Technology, Inc. | High density SRAM cell with latched vertical transistors |
US6134175A (en) | 1998-08-04 | 2000-10-17 | Micron Technology, Inc. | Memory address decode array with vertical transistors |
US6208164B1 (en) | 1998-08-04 | 2001-03-27 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
US6268282B1 (en) | 1998-09-03 | 2001-07-31 | Micron Technology, Inc. | Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks |
US6281100B1 (en) | 1998-09-03 | 2001-08-28 | Micron Technology, Inc. | Semiconductor processing methods |
US6033955A (en) * | 1998-09-23 | 2000-03-07 | Advanced Micro Devices, Inc. | Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture |
US6204123B1 (en) * | 1998-10-30 | 2001-03-20 | Sony Corporation | Vertical floating gate transistor with epitaxial channel |
US6828683B2 (en) * | 1998-12-23 | 2004-12-07 | Micron Technology, Inc. | Semiconductor devices, and semiconductor processing methods |
US7235499B1 (en) * | 1999-01-20 | 2007-06-26 | Micron Technology, Inc. | Semiconductor processing methods |
JP3743189B2 (en) * | 1999-01-27 | 2006-02-08 | 富士通株式会社 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US6713346B2 (en) * | 1999-03-01 | 2004-03-30 | Micron Technology, Inc. | Methods of forming a line of flash memory cells |
US6440860B1 (en) * | 2000-01-18 | 2002-08-27 | Micron Technology, Inc. | Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride |
US6639835B2 (en) | 2000-02-29 | 2003-10-28 | Micron Technology, Inc. | Static NVRAM with ultra thin tunnel oxides |
US6605961B1 (en) | 2000-02-29 | 2003-08-12 | Micron Technology, Inc. | Low voltage PLA's with ultrathin tunnel oxides |
US6351428B2 (en) | 2000-02-29 | 2002-02-26 | Micron Technology, Inc. | Programmable low voltage decode circuits with ultra-thin tunnel oxides |
EP1312120A1 (en) | 2000-08-14 | 2003-05-21 | Matrix Semiconductor, Inc. | Dense arrays and charge storage devices, and methods for making same |
US6580124B1 (en) | 2000-08-14 | 2003-06-17 | Matrix Semiconductor Inc. | Multigate semiconductor device with vertical channel current and method of fabrication |
US6437389B1 (en) * | 2000-08-22 | 2002-08-20 | Micron Technology, Inc. | Vertical gate transistors in pass transistor programmable logic arrays |
DE10041749A1 (en) * | 2000-08-27 | 2002-03-14 | Infineon Technologies Ag | Vertical non-volatile semiconductor memory cell and method for its production |
US6624022B1 (en) | 2000-08-29 | 2003-09-23 | Micron Technology, Inc. | Method of forming FLASH memory |
KR100364803B1 (en) * | 2000-11-15 | 2002-12-16 | 주식회사 하이닉스반도체 | Method for manufacturing Nonvolatile Memory |
US6496034B2 (en) * | 2001-02-09 | 2002-12-17 | Micron Technology, Inc. | Programmable logic arrays with ultra thin body transistors |
US6566682B2 (en) * | 2001-02-09 | 2003-05-20 | Micron Technology, Inc. | Programmable memory address and decode circuits with ultra thin vertical body transistors |
US6424001B1 (en) | 2001-02-09 | 2002-07-23 | Micron Technology, Inc. | Flash memory with ultra thin vertical body transistors |
US6377070B1 (en) | 2001-02-09 | 2002-04-23 | Micron Technology, Inc. | In-service programmable logic arrays with ultra thin vertical body transistors |
US6559491B2 (en) * | 2001-02-09 | 2003-05-06 | Micron Technology, Inc. | Folded bit line DRAM with ultra thin body transistors |
US6531727B2 (en) * | 2001-02-09 | 2003-03-11 | Micron Technology, Inc. | Open bit line DRAM with ultra thin body transistors |
US6369422B1 (en) | 2001-05-01 | 2002-04-09 | Atmel Corporation | Eeprom cell with asymmetric thin window |
US6462387B1 (en) * | 2001-06-29 | 2002-10-08 | Chinatech Corporation | High density read only memory |
US6744094B2 (en) * | 2001-08-24 | 2004-06-01 | Micron Technology Inc. | Floating gate transistor with horizontal gate layers stacked next to vertical body |
US6754108B2 (en) * | 2001-08-30 | 2004-06-22 | Micron Technology, Inc. | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7476925B2 (en) * | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US7132711B2 (en) * | 2001-08-30 | 2006-11-07 | Micron Technology, Inc. | Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers |
US7012297B2 (en) | 2001-08-30 | 2006-03-14 | Micron Technology, Inc. | Scalable flash/NV structures and devices with extended endurance |
US7068544B2 (en) | 2001-08-30 | 2006-06-27 | Micron Technology, Inc. | Flash memory with low tunnel barrier interpoly insulators |
US7087954B2 (en) | 2001-08-30 | 2006-08-08 | Micron Technology, Inc. | In service programmable logic arrays with low tunnel barrier interpoly insulators |
US6778441B2 (en) * | 2001-08-30 | 2004-08-17 | Micron Technology, Inc. | Integrated circuit memory device and method |
US7075829B2 (en) | 2001-08-30 | 2006-07-11 | Micron Technology, Inc. | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators |
US6963103B2 (en) * | 2001-08-30 | 2005-11-08 | Micron Technology, Inc. | SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators |
US7042043B2 (en) | 2001-08-30 | 2006-05-09 | Micron Technology, Inc. | Programmable array logic or memory devices with asymmetrical tunnel barriers |
US7135734B2 (en) * | 2001-08-30 | 2006-11-14 | Micron Technology, Inc. | Graded composition metal oxide tunnel barrier interpoly insulators |
DE10146215A1 (en) * | 2001-09-19 | 2003-04-10 | Infineon Technologies Ag | Method for producing a semiconductor memory element arrangement, method for operating a semiconductor memory element arrangement and semiconductor memory element arrangement |
KR20030025315A (en) | 2001-09-20 | 2003-03-29 | 주식회사 하이닉스반도체 | Flash memory device and method for fabricating the same |
JP2004072060A (en) * | 2001-11-22 | 2004-03-04 | Innotech Corp | Transistor and semiconductor memory using the same, and method of driving the transistor |
US6953730B2 (en) | 2001-12-20 | 2005-10-11 | Micron Technology, Inc. | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
US6587396B1 (en) * | 2001-12-21 | 2003-07-01 | Winbond Electronics Corporation | Structure of horizontal surrounding gate flash memory cell |
US6784480B2 (en) * | 2002-02-12 | 2004-08-31 | Micron Technology, Inc. | Asymmetric band-gap engineered nonvolatile memory device |
US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
DE10220922B4 (en) * | 2002-05-10 | 2006-09-28 | Infineon Technologies Ag | Flash memory cell, arrangement of flash memory cells and method for producing flash memory cells |
AU2003263748A1 (en) * | 2002-06-21 | 2004-01-06 | Micron Technology, Inc. | Nrom memory cell, memory array, related devices and methods |
US6804136B2 (en) | 2002-06-21 | 2004-10-12 | Micron Technology, Inc. | Write once read only memory employing charge trapping in insulators |
US6970370B2 (en) * | 2002-06-21 | 2005-11-29 | Micron Technology, Inc. | Ferroelectric write once read only memory for archival storage |
US7154140B2 (en) * | 2002-06-21 | 2006-12-26 | Micron Technology, Inc. | Write once read only memory with large work function floating gates |
US20040041214A1 (en) * | 2002-08-29 | 2004-03-04 | Prall Kirk D. | One F2 memory cell, memory array, related devices and methods |
US7193893B2 (en) | 2002-06-21 | 2007-03-20 | Micron Technology, Inc. | Write once read only memory employing floating gates |
US6996009B2 (en) | 2002-06-21 | 2006-02-07 | Micron Technology, Inc. | NOR flash memory cell with high storage density |
US7847344B2 (en) | 2002-07-08 | 2010-12-07 | Micron Technology, Inc. | Memory utilizing oxide-nitride nanolaminates |
US7221017B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide-conductor nanolaminates |
US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
US6680508B1 (en) * | 2002-08-28 | 2004-01-20 | Micron Technology, Inc. | Vertical floating gate transistor |
US6838723B2 (en) * | 2002-08-29 | 2005-01-04 | Micron Technology, Inc. | Merged MOS-bipolar capacitor memory cell |
US7224024B2 (en) * | 2002-08-29 | 2007-05-29 | Micron Technology, Inc. | Single transistor vertical memory gain cell |
US6649453B1 (en) | 2002-08-29 | 2003-11-18 | Micron Technology, Inc. | Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation |
US6804142B2 (en) | 2002-11-12 | 2004-10-12 | Micron Technology, Inc. | 6F2 3-transistor DRAM gain cell |
US7030436B2 (en) * | 2002-12-04 | 2006-04-18 | Micron Technology, Inc. | Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means |
US7221010B2 (en) * | 2002-12-20 | 2007-05-22 | Cree, Inc. | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors |
US6956256B2 (en) * | 2003-03-04 | 2005-10-18 | Micron Technology Inc. | Vertical gain cell |
US6770934B1 (en) * | 2003-04-03 | 2004-08-03 | Powerchip Semiconductor Corp. | Flash memory device structure and manufacturing method thereof |
US7087943B2 (en) * | 2003-05-08 | 2006-08-08 | Intel Corporation | Direct alignment scheme between multiple lithography layers |
US7759719B2 (en) * | 2004-07-01 | 2010-07-20 | Chih-Hsin Wang | Electrically alterable memory cell |
US7550800B2 (en) * | 2003-06-06 | 2009-06-23 | Chih-Hsin Wang | Method and apparatus transporting charges in semiconductor device and semiconductor memory device |
US7297634B2 (en) * | 2003-06-06 | 2007-11-20 | Marvell World Trade Ltd. | Method and apparatus for semiconductor device and semiconductor memory device |
US7613041B2 (en) * | 2003-06-06 | 2009-11-03 | Chih-Hsin Wang | Methods for operating semiconductor device and semiconductor memory device |
US7115942B2 (en) * | 2004-07-01 | 2006-10-03 | Chih-Hsin Wang | Method and apparatus for nonvolatile memory |
US6963104B2 (en) * | 2003-06-12 | 2005-11-08 | Advanced Micro Devices, Inc. | Non-volatile memory device |
US6979857B2 (en) | 2003-07-01 | 2005-12-27 | Micron Technology, Inc. | Apparatus and method for split gate NROM memory |
US7095075B2 (en) | 2003-07-01 | 2006-08-22 | Micron Technology, Inc. | Apparatus and method for split transistor memory having improved endurance |
KR100549586B1 (en) | 2003-07-21 | 2006-02-08 | 매그나칩 반도체 유한회사 | Method for manufacturing nonvolatile memory transistor |
KR100518588B1 (en) * | 2003-08-07 | 2005-10-04 | 삼성전자주식회사 | Split gate type non-volatile semiconductor memory device having double-floating gate structure and process for manufacturing the same |
US6815758B1 (en) * | 2003-08-22 | 2004-11-09 | Powerchip Semiconductor Corp. | Flash memory cell |
US6933558B2 (en) * | 2003-12-04 | 2005-08-23 | Advanced Micro Devices, Inc. | Flash memory device |
US7269072B2 (en) * | 2003-12-16 | 2007-09-11 | Micron Technology, Inc. | NROM memory cell, memory array, related devices and methods |
US7050330B2 (en) * | 2003-12-16 | 2006-05-23 | Micron Technology, Inc. | Multi-state NROM device |
US7241654B2 (en) | 2003-12-17 | 2007-07-10 | Micron Technology, Inc. | Vertical NROM NAND flash memory array |
US7148538B2 (en) * | 2003-12-17 | 2006-12-12 | Micron Technology, Inc. | Vertical NAND flash memory array |
EP1711966B1 (en) * | 2004-01-22 | 2012-02-22 | International Business Machines Corporation | Vertical fin-fet mos devices |
US6878991B1 (en) | 2004-01-30 | 2005-04-12 | Micron Technology, Inc. | Vertical device 4F2 EEPROM memory |
US7075146B2 (en) | 2004-02-24 | 2006-07-11 | Micron Technology, Inc. | 4F2 EEPROM NROM memory arrays with vertical devices |
US7098105B2 (en) * | 2004-05-26 | 2006-08-29 | Micron Technology, Inc. | Methods for forming semiconductor structures |
US7151294B2 (en) * | 2004-08-03 | 2006-12-19 | Micron Technology, Inc. | High density stepped, non-planar flash memory |
US7442976B2 (en) | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7271052B1 (en) | 2004-09-02 | 2007-09-18 | Micron Technology, Inc. | Long retention time single transistor vertical memory gain cell |
US7457156B2 (en) * | 2004-09-02 | 2008-11-25 | Micron Technology, Inc. | NAND flash depletion cell structure |
US7271433B1 (en) | 2004-09-02 | 2007-09-18 | Micron Technology, Inc. | High-density single transistor vertical memory gain cell |
US7259415B1 (en) | 2004-09-02 | 2007-08-21 | Micron Technology, Inc. | Long retention time single transistor vertical memory gain cell |
JP2006177230A (en) * | 2004-12-22 | 2006-07-06 | Kayaba Ind Co Ltd | Pump device |
US7344942B2 (en) * | 2005-01-26 | 2008-03-18 | Micron Technology, Inc. | Isolation regions for semiconductor devices and their formation |
US7662729B2 (en) | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US20060273370A1 (en) * | 2005-06-07 | 2006-12-07 | Micron Technology, Inc. | NROM flash memory with vertical transistors and surrounding gates |
US7538389B2 (en) | 2005-06-08 | 2009-05-26 | Micron Technology, Inc. | Capacitorless DRAM on bulk silicon |
US7411244B2 (en) * | 2005-06-28 | 2008-08-12 | Chih-Hsin Wang | Low power electrically alterable nonvolatile memory cells and arrays |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US7608886B2 (en) * | 2006-01-06 | 2009-10-27 | Macronix International Co., Ltd. | Systems and methods for a high density, compact memory array |
US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
US20070253233A1 (en) * | 2006-03-30 | 2007-11-01 | Torsten Mueller | Semiconductor memory device and method of production |
US8734583B2 (en) | 2006-04-04 | 2014-05-27 | Micron Technology, Inc. | Grown nanofin transistors |
US8354311B2 (en) * | 2006-04-04 | 2013-01-15 | Micron Technology, Inc. | Method for forming nanofin transistors |
US7425491B2 (en) * | 2006-04-04 | 2008-09-16 | Micron Technology, Inc. | Nanowire transistor with surrounding gate |
US7491995B2 (en) | 2006-04-04 | 2009-02-17 | Micron Technology, Inc. | DRAM with nanofin transistors |
US7646054B2 (en) * | 2006-09-19 | 2010-01-12 | Sandisk Corporation | Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
US7696044B2 (en) * | 2006-09-19 | 2010-04-13 | Sandisk Corporation | Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
EP2064733A2 (en) * | 2006-09-19 | 2009-06-03 | Sandisk Corporation | Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
US7642160B2 (en) * | 2006-12-21 | 2010-01-05 | Sandisk Corporation | Method of forming a flash NAND memory cell array with charge storage elements positioned in trenches |
US7800161B2 (en) * | 2006-12-21 | 2010-09-21 | Sandisk Corporation | Flash NAND memory cell array with charge storage elements positioned in trenches |
JP5016928B2 (en) * | 2007-01-10 | 2012-09-05 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
TW200908229A (en) * | 2007-08-13 | 2009-02-16 | Nanya Technology Corp | Method of manufacturing non-volatile memory |
TWI349340B (en) * | 2007-09-03 | 2011-09-21 | Nanya Technology Corp | Method for manufacturing non-volatile memory |
TW200913166A (en) * | 2007-09-07 | 2009-03-16 | Nanya Technology Corp | Non-volatile memory and manufacturing method thereof |
US8072023B1 (en) | 2007-11-12 | 2011-12-06 | Marvell International Ltd. | Isolation for non-volatile memory cell array |
US8120088B1 (en) | 2007-12-07 | 2012-02-21 | Marvell International Ltd. | Non-volatile memory cell and array |
US7713814B2 (en) * | 2008-01-04 | 2010-05-11 | International Business Machines Corporation | Hybrid orientation substrate compatible deep trench capacitor embedded DRAM |
US7961506B2 (en) | 2008-02-05 | 2011-06-14 | Micron Technology, Inc. | Multiple memory cells with rectifying device |
US20090254705A1 (en) * | 2008-04-07 | 2009-10-08 | International Business Machines Corporation | Bus attached compressed random access memory |
US7804124B2 (en) * | 2008-05-09 | 2010-09-28 | International Business Machines Corporation | Device structures for a memory cell of a non-volatile random access memory and design structures for a non-volatile random access memory |
KR101498676B1 (en) | 2008-09-30 | 2015-03-09 | 삼성전자주식회사 | 3-Dimensional Semiconductor Device |
US8299519B2 (en) * | 2010-01-11 | 2012-10-30 | International Business Machines Corporation | Read transistor for single poly non-volatile memory using body contacted SOI device |
KR101663566B1 (en) * | 2010-03-03 | 2016-10-07 | 삼성전자주식회사 | Three dimensional semiconductor memory devices and methods of forming the same |
US8952429B2 (en) * | 2010-09-15 | 2015-02-10 | Institute of Microelectronics, Chinese Academy of Sciences | Transistor and method for forming the same |
TWI415247B (en) * | 2010-12-15 | 2013-11-11 | Powerchip Technology Corp | Dynamic random access memory cell and array having vertical channel transistor |
US8786014B2 (en) * | 2011-01-18 | 2014-07-22 | Powerchip Technology Corporation | Vertical channel transistor array and manufacturing method thereof |
US8609492B2 (en) * | 2011-07-27 | 2013-12-17 | Micron Technology, Inc. | Vertical memory cell |
KR101430415B1 (en) * | 2012-06-09 | 2014-08-14 | 서울대학교산학협력단 | Memory cell string based on gated-diode cell and memory array using the same |
US8772101B2 (en) * | 2012-11-08 | 2014-07-08 | Globalfoundries Inc. | Methods of forming replacement gate structures on semiconductor devices and the resulting device |
KR20150050877A (en) * | 2013-11-01 | 2015-05-11 | 에스케이하이닉스 주식회사 | Transistor and semiconductor device including the same |
US9318447B2 (en) | 2014-07-18 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of forming vertical structure |
US9847233B2 (en) * | 2014-07-29 | 2017-12-19 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and formation thereof |
US9627395B2 (en) | 2015-02-11 | 2017-04-18 | Sandisk Technologies Llc | Enhanced channel mobility three-dimensional memory structure and method of making thereof |
US9478495B1 (en) | 2015-10-26 | 2016-10-25 | Sandisk Technologies Llc | Three dimensional memory device containing aluminum source contact via structure and method of making thereof |
US9768231B2 (en) | 2016-02-12 | 2017-09-19 | Globalfoundries Singapore Pte. Ltd. | High density multi-time programmable resistive memory devices and method of forming thereof |
US10777450B2 (en) * | 2018-12-27 | 2020-09-15 | Nanya Technology Corporation | Semiconductor substrate and method of processing the same |
Citations (88)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3657575A (en) * | 1970-03-13 | 1972-04-18 | Hitachi Ltd | Threshold voltage compensating circuits for fets |
US3806741A (en) * | 1972-05-17 | 1974-04-23 | Standard Microsyst Smc | Self-biasing technique for mos substrate voltage |
US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4252579A (en) * | 1979-05-07 | 1981-02-24 | International Business Machines Corporation | Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition |
US4604162A (en) * | 1983-06-13 | 1986-08-05 | Ncr Corporation | Formation and planarization of silicon-on-insulator structures |
US4673962A (en) * | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4761385A (en) * | 1987-02-10 | 1988-08-02 | Motorola, Inc. | Forming a trench capacitor |
US4906590A (en) * | 1988-05-09 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a trench capacitor on a semiconductor substrate |
US4920515A (en) * | 1987-10-23 | 1990-04-24 | Ricoh Company, Ltd. | Programmable logic array having an improved testing arrangement |
US4920389A (en) * | 1988-03-08 | 1990-04-24 | Oki Electric Industry Co., Ltd. | Memory call array structure and process for producing the same |
US4929988A (en) * | 1987-08-25 | 1990-05-29 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of the manufacture thereof |
US4958318A (en) * | 1988-07-08 | 1990-09-18 | Eliyahou Harari | Sidewall capacitor DRAM cell |
US4987089A (en) * | 1990-07-23 | 1991-01-22 | Micron Technology, Inc. | BiCMOS process and process for forming bipolar transistors on wafers also containing FETs |
US5006909A (en) * | 1989-10-30 | 1991-04-09 | Motorola, Inc. | Dram with a vertical capacitor and transistor |
US5017504A (en) * | 1986-12-01 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Vertical type MOS transistor and method of formation thereof |
US5021355A (en) * | 1989-05-22 | 1991-06-04 | International Business Machines Corporation | Method of fabricating cross-point lightly-doped drain-source trench transistor |
US5028977A (en) * | 1989-06-16 | 1991-07-02 | Massachusetts Institute Of Technology | Merged bipolar and insulated gate transistors |
US5057896A (en) * | 1988-05-28 | 1991-10-15 | Fujitsu Limited | Semiconductor device and method of producing same |
US5072269A (en) * | 1988-03-15 | 1991-12-10 | Kabushiki Kaisha Toshiba | Dynamic ram and method of manufacturing the same |
US5110752A (en) * | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
US5128831A (en) * | 1991-10-31 | 1992-07-07 | Micron Technology, Inc. | High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias |
US5156987A (en) * | 1991-12-18 | 1992-10-20 | Micron Technology, Inc. | High performance thin film transistor (TFT) by solid phase epitaxial regrowth |
US5177576A (en) * | 1990-05-09 | 1993-01-05 | Hitachi, Ltd. | Dynamic random access memory having trench capacitors and vertical transistors |
US5181089A (en) * | 1989-08-15 | 1993-01-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and a method for producing the same |
US5191509A (en) * | 1991-12-11 | 1993-03-02 | International Business Machines Corporation | Textured polysilicon stacked trench capacitor |
US5202278A (en) * | 1991-09-10 | 1993-04-13 | Micron Technology, Inc. | Method of forming a capacitor in semiconductor wafer processing |
US5216266A (en) * | 1990-04-11 | 1993-06-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having memory cells formed in trench and manufacturing method therefor |
US5223081A (en) * | 1991-07-03 | 1993-06-29 | Doan Trung T | Method for roughening a silicon or polysilicon surface for a semiconductor substrate |
US5266514A (en) * | 1992-12-21 | 1993-11-30 | Industrial Technology Research Institute | Method for producing a roughened surface capacitor |
US5292676A (en) * | 1992-07-29 | 1994-03-08 | Micron Semiconductor, Inc. | Self-aligned low resistance buried contact process |
US5316962A (en) * | 1989-08-15 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Method of producing a semiconductor device having trench capacitors and vertical switching transistors |
US5320880A (en) * | 1992-10-20 | 1994-06-14 | Micron Technology, Inc. | Method of providing a silicon film having a roughened outer surface |
US5363325A (en) * | 1991-07-01 | 1994-11-08 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device having high integration density |
US5365477A (en) * | 1992-06-16 | 1994-11-15 | The United States Of America As Represented By The Secretary Of The Navy | Dynamic random access memory device |
US5385854A (en) * | 1993-07-15 | 1995-01-31 | Micron Semiconductor, Inc. | Method of forming a self-aligned low density drain inverted thin film transistor |
US5392245A (en) * | 1993-08-13 | 1995-02-21 | Micron Technology, Inc. | Redundancy elements using thin film transistors (TFTs) |
US5396093A (en) * | 1994-02-14 | 1995-03-07 | Industrial Technology Research Institute | Vertical DRAM cross point memory cell and fabrication method |
US5396452A (en) * | 1993-07-02 | 1995-03-07 | Wahlstrom; Sven E. | Dynamic random access memory |
US5409563A (en) * | 1993-02-26 | 1995-04-25 | Micron Technology, Inc. | Method for etching high aspect ratio features |
US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
US5427972A (en) * | 1987-02-13 | 1995-06-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a sidewall contact |
US5429955A (en) * | 1992-10-26 | 1995-07-04 | Texas Instruments Incorporated | Method for constructing semiconductor-on-insulator |
US5432739A (en) * | 1994-06-17 | 1995-07-11 | Philips Electronics North America Corporation | Non-volatile sidewall memory cell method of fabricating same |
US5445986A (en) * | 1993-09-03 | 1995-08-29 | Nec Corporation | Method of forming a roughened surface capacitor with two etching steps |
US5451538A (en) * | 1992-03-02 | 1995-09-19 | Motorola, Inc. | Method for forming a vertically integrated dynamic memory cell |
US5451889A (en) * | 1994-03-14 | 1995-09-19 | Motorola, Inc. | CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage current |
US5460988A (en) * | 1994-04-25 | 1995-10-24 | United Microelectronics Corporation | Process for high density flash EPROM cell |
US5483094A (en) * | 1993-09-20 | 1996-01-09 | Motorola, Inc. | Electrically programmable read-only memory cell |
US5495441A (en) * | 1994-05-18 | 1996-02-27 | United Microelectronics Corporation | Split-gate flash memory cell |
US5502629A (en) * | 1994-03-31 | 1996-03-26 | Fujitsu Limited | DC-DC converter |
US5508542A (en) * | 1994-10-28 | 1996-04-16 | International Business Machines Corporation | Porous silicon trench and capacitor structures |
US5519236A (en) * | 1993-06-28 | 1996-05-21 | Kabushiki Kaisha Toshiba | Semiconductor memory device having surrounding gate transistor |
US5528173A (en) * | 1995-05-10 | 1996-06-18 | Micron Technology, Inc. | Low power, high speed level shifter |
US5574299A (en) * | 1994-03-28 | 1996-11-12 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical conduction transistors and cylindrical cell gates |
US5616934A (en) * | 1993-05-12 | 1997-04-01 | Micron Technology, Inc. | Fully planarized thin film transistor (TFT) and process to fabricate same |
US5640350A (en) * | 1996-05-01 | 1997-06-17 | Iga; Adam Sempa | Multi-bit dynamic random access memory cell storage |
US5640342A (en) * | 1995-11-20 | 1997-06-17 | Micron Technology, Inc. | Structure for cross coupled thin film transistors and static random access memory cell |
US5641545A (en) * | 1995-06-07 | 1997-06-24 | Micron Technology, Inc. | Method to deposit highly conformal CVD films |
US5646900A (en) * | 1995-01-12 | 1997-07-08 | Mitsubishi Denki Kabushiki Kaisha | Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device |
US5691230A (en) * | 1996-09-04 | 1997-11-25 | Micron Technology, Inc. | Technique for producing small islands of silicon on insulator |
US5705415A (en) * | 1994-10-04 | 1998-01-06 | Motorola, Inc. | Process for forming an electrically programmable read-only memory cell |
US5714793A (en) * | 1995-04-03 | 1998-02-03 | The United States Of America As Represented By The Secretary Of The Navy | Complementary vertical bipolar junction transistors formed in silicon-on-saphire |
US5731609A (en) * | 1992-03-19 | 1998-03-24 | Kabushiki Kaisha Toshiba | MOS random access memory having array of trench type one-capacitor/one-transistor memory cells |
US5760434A (en) * | 1996-05-07 | 1998-06-02 | Micron Technology, Inc. | Increased interior volume for integrated memory cell |
US5789967A (en) * | 1995-03-31 | 1998-08-04 | Nec Corporation | Semiconductor device with boost voltage supply means |
US5821796A (en) * | 1996-09-23 | 1998-10-13 | Texas Instruments Incorporated | Circuitry for providing a high impedance state when powering down a single port node |
US5852375A (en) * | 1997-02-07 | 1998-12-22 | Silicon Systems Research Limited | 5v tolerant I/O circuit |
US5874760A (en) * | 1997-01-22 | 1999-02-23 | International Business Machines Corporation | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
US5877061A (en) * | 1997-02-25 | 1999-03-02 | International Business Machines Corporation | Methods for roughening and volume expansion of trench sidewalls to form high capacitance trench cell for high density dram applications |
US5879971A (en) * | 1995-09-28 | 1999-03-09 | Motorola Inc. | Trench random access memory cell and method of formation |
US5909618A (en) * | 1997-07-08 | 1999-06-01 | Micron Technology, Inc. | Method of making memory cell with vertical transistor and buried word and body lines |
US5914511A (en) * | 1997-10-06 | 1999-06-22 | Micron Technology, Inc. | Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts |
US5933717A (en) * | 1997-03-04 | 1999-08-03 | Advanced Micro Devices, Inc. | Vertical transistor interconnect structure and fabrication method thereof |
US5936274A (en) * | 1997-07-08 | 1999-08-10 | Micron Technology, Inc. | High density flash memory |
US5943267A (en) * | 1996-05-16 | 1999-08-24 | Altera Corporation | High-density nonvolatile memory cell |
US5973356A (en) * | 1997-07-08 | 1999-10-26 | Micron Technology, Inc. | Ultra high density flash memory |
US5990820A (en) * | 1996-05-07 | 1999-11-23 | Telefonaktiebolaget Lm Ericsson | Current-mode pipelined ADC with time-interleaved sampling and mixed reference and residue scaling |
US5996011A (en) * | 1997-03-25 | 1999-11-30 | Unified Research Laboratories, Inc. | System and method for filtering data received by a computer system |
US6072209A (en) * | 1997-07-08 | 2000-06-06 | Micro Technology, Inc. | Four F2 folded bit line DRAM cell structure having buried bit and word lines |
US6121084A (en) * | 2000-01-27 | 2000-09-19 | Micron Technology, Inc. | Semiconductor processing methods of forming hemispherical grain polysilicon layers, methods of forming capacitors, and capacitors |
US6172535B1 (en) * | 1999-11-04 | 2001-01-09 | Analog Devices, Inc. | High-speed analog comparator structures and methods |
US6172391B1 (en) * | 1997-08-27 | 2001-01-09 | Siemens Aktiengesellschaft | DRAM cell arrangement and method for the manufacture thereof |
US6181196B1 (en) * | 1997-12-18 | 2001-01-30 | Texas Instruments Incorporated | Accurate bandgap circuit for a CMOS process without NPN devices |
US6181121B1 (en) * | 1999-03-04 | 2001-01-30 | Cypress Semiconductor Corp. | Low supply voltage BICMOS self-biased bandgap reference using a current summing architecture |
US6208164B1 (en) * | 1998-08-04 | 2001-03-27 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
US6221788B1 (en) * | 1995-08-01 | 2001-04-24 | Matsushita Electronics Corporation | Semiconductor and a method for manufacturing an oxide film on the surface of a semiconductor substrate |
US6255708B1 (en) * | 1997-10-10 | 2001-07-03 | Rengarajan Sudharsanan | Semiconductor P-I-N detector |
US6528837B2 (en) * | 1997-10-06 | 2003-03-04 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
US4766569A (en) * | 1985-03-04 | 1988-08-23 | Lattice Semiconductor Corporation | Programmable logic array |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
US5102817A (en) * | 1985-03-21 | 1992-04-07 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US4663831A (en) * | 1985-10-08 | 1987-05-12 | Motorola, Inc. | Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
JPH01125858A (en) * | 1987-11-10 | 1989-05-18 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
US5327380B1 (en) * | 1988-10-31 | 1999-09-07 | Texas Instruments Inc | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
US4920065A (en) * | 1988-10-31 | 1990-04-24 | International Business Machines Corporation | Method of making ultra dense dram cells |
JPH0821689B2 (en) * | 1990-02-26 | 1996-03-04 | 株式会社東芝 | Semiconductor memory device and manufacturing method thereof |
US5222081A (en) * | 1991-06-28 | 1993-06-22 | Universal Data Systems, Inc. | Method of performing an autobaud function using a state flow machine |
KR940006679B1 (en) * | 1991-09-26 | 1994-07-25 | 현대전자산업 주식회사 | Dram cell having a vertical transistor and fabricating method thereof |
US5177028A (en) * | 1991-10-22 | 1993-01-05 | Micron Technology, Inc. | Trench isolation method having a double polysilicon gate formed on mesas |
JP3173854B2 (en) * | 1992-03-25 | 2001-06-04 | 株式会社半導体エネルギー研究所 | Method for manufacturing thin-film insulated gate semiconductor device and semiconductor device manufactured |
US5528062A (en) * | 1992-06-17 | 1996-06-18 | International Business Machines Corporation | High-density DRAM structure on soi |
US5422499A (en) * | 1993-02-22 | 1995-06-06 | Micron Semiconductor, Inc. | Sixteen megabit static random access memory (SRAM) cell |
US5306659A (en) * | 1993-03-29 | 1994-04-26 | International Business Machines Corporation | Reach-through isolation etching method for silicon-on-insulator devices |
US5438009A (en) * | 1993-04-02 | 1995-08-01 | United Microelectronics Corporation | Method of fabrication of MOSFET device with buried bit line |
GB9319070D0 (en) * | 1993-09-15 | 1993-11-03 | Ncr Int Inc | Stencil having improved wear-resistance and quality consistency and method of manufacturing the same |
US5393704A (en) * | 1993-12-13 | 1995-02-28 | United Microelectronics Corporation | Self-aligned trenched contact (satc) process |
US5492853A (en) * | 1994-03-11 | 1996-02-20 | Micron Semiconductor, Inc. | Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device |
US5440158A (en) * | 1994-07-05 | 1995-08-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Electrically programmable memory device with improved dual floating gates |
US5593912A (en) * | 1994-10-06 | 1997-01-14 | International Business Machines Corporation | SOI trench DRAM cell for 256 MB DRAM and beyond |
US5497017A (en) * | 1995-01-26 | 1996-03-05 | Micron Technology, Inc. | Dynamic random access memory array having a cross-point layout, tungsten digit lines buried in the substrate, and vertical access transistors |
US5508219A (en) * | 1995-06-05 | 1996-04-16 | International Business Machines Corporation | SOI DRAM with field-shield isolation and body contact |
US5990509A (en) * | 1997-01-22 | 1999-11-23 | International Business Machines Corporation | 2F-square memory cell for gigabit memory applications |
US5784760A (en) * | 1997-03-10 | 1998-07-28 | Pivot Point, Inc. | Retaining mechanism for securing connecting members |
US6066869A (en) * | 1997-10-06 | 2000-05-23 | Micron Technology, Inc. | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor |
US5872032A (en) * | 1997-11-03 | 1999-02-16 | Vanguard International Semiconductor Corporation | Fabrication method for a DRAM cell with bipolar charge amplification |
US6246083B1 (en) * | 1998-02-24 | 2001-06-12 | Micron Technology, Inc. | Vertical gain cell and array for a dynamic random access memory |
US6323719B1 (en) * | 2000-05-08 | 2001-11-27 | National Science Council | Pseudo bipolar junction transistor |
-
1997
- 1997-07-08 US US08/889,554 patent/US5973356A/en not_active Expired - Lifetime
-
1998
- 1998-02-27 US US09/035,304 patent/US6238976B1/en not_active Expired - Lifetime
-
2001
- 2001-05-29 US US09/866,938 patent/US20010029077A1/en not_active Abandoned
-
2006
- 2006-07-21 US US11/490,674 patent/US20060255397A1/en not_active Abandoned
- 2006-07-21 US US11/491,328 patent/US20060258096A1/en not_active Abandoned
- 2006-11-29 US US11/605,751 patent/US20070069281A1/en not_active Abandoned
Patent Citations (91)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3657575A (en) * | 1970-03-13 | 1972-04-18 | Hitachi Ltd | Threshold voltage compensating circuits for fets |
US3806741A (en) * | 1972-05-17 | 1974-04-23 | Standard Microsyst Smc | Self-biasing technique for mos substrate voltage |
US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4252579A (en) * | 1979-05-07 | 1981-02-24 | International Business Machines Corporation | Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition |
US4604162A (en) * | 1983-06-13 | 1986-08-05 | Ncr Corporation | Formation and planarization of silicon-on-insulator structures |
US4673962A (en) * | 1985-03-21 | 1987-06-16 | Texas Instruments Incorporated | Vertical DRAM cell and method |
US5017504A (en) * | 1986-12-01 | 1991-05-21 | Mitsubishi Denki Kabushiki Kaisha | Vertical type MOS transistor and method of formation thereof |
US4761385A (en) * | 1987-02-10 | 1988-08-02 | Motorola, Inc. | Forming a trench capacitor |
US5427972A (en) * | 1987-02-13 | 1995-06-27 | Mitsubishi Denki Kabushiki Kaisha | Method of making a sidewall contact |
US4929988A (en) * | 1987-08-25 | 1990-05-29 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device and method of the manufacture thereof |
US4920515A (en) * | 1987-10-23 | 1990-04-24 | Ricoh Company, Ltd. | Programmable logic array having an improved testing arrangement |
US4920389A (en) * | 1988-03-08 | 1990-04-24 | Oki Electric Industry Co., Ltd. | Memory call array structure and process for producing the same |
US5072269A (en) * | 1988-03-15 | 1991-12-10 | Kabushiki Kaisha Toshiba | Dynamic ram and method of manufacturing the same |
US4906590A (en) * | 1988-05-09 | 1990-03-06 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a trench capacitor on a semiconductor substrate |
US5057896A (en) * | 1988-05-28 | 1991-10-15 | Fujitsu Limited | Semiconductor device and method of producing same |
US4958318A (en) * | 1988-07-08 | 1990-09-18 | Eliyahou Harari | Sidewall capacitor DRAM cell |
US5021355A (en) * | 1989-05-22 | 1991-06-04 | International Business Machines Corporation | Method of fabricating cross-point lightly-doped drain-source trench transistor |
US5028977A (en) * | 1989-06-16 | 1991-07-02 | Massachusetts Institute Of Technology | Merged bipolar and insulated gate transistors |
US5181089A (en) * | 1989-08-15 | 1993-01-19 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and a method for producing the same |
US5316962A (en) * | 1989-08-15 | 1994-05-31 | Matsushita Electric Industrial Co., Ltd. | Method of producing a semiconductor device having trench capacitors and vertical switching transistors |
US5006909A (en) * | 1989-10-30 | 1991-04-09 | Motorola, Inc. | Dram with a vertical capacitor and transistor |
US5216266A (en) * | 1990-04-11 | 1993-06-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having memory cells formed in trench and manufacturing method therefor |
US5177576A (en) * | 1990-05-09 | 1993-01-05 | Hitachi, Ltd. | Dynamic random access memory having trench capacitors and vertical transistors |
US4987089A (en) * | 1990-07-23 | 1991-01-22 | Micron Technology, Inc. | BiCMOS process and process for forming bipolar transistors on wafers also containing FETs |
US5363325A (en) * | 1991-07-01 | 1994-11-08 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device having high integration density |
US5223081A (en) * | 1991-07-03 | 1993-06-29 | Doan Trung T | Method for roughening a silicon or polysilicon surface for a semiconductor substrate |
US5110752A (en) * | 1991-07-10 | 1992-05-05 | Industrial Technology Research Institute | Roughened polysilicon surface capacitor electrode plate for high denity dram |
US5202278A (en) * | 1991-09-10 | 1993-04-13 | Micron Technology, Inc. | Method of forming a capacitor in semiconductor wafer processing |
US5128831A (en) * | 1991-10-31 | 1992-07-07 | Micron Technology, Inc. | High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias |
US5191509A (en) * | 1991-12-11 | 1993-03-02 | International Business Machines Corporation | Textured polysilicon stacked trench capacitor |
US5156987A (en) * | 1991-12-18 | 1992-10-20 | Micron Technology, Inc. | High performance thin film transistor (TFT) by solid phase epitaxial regrowth |
US5451538A (en) * | 1992-03-02 | 1995-09-19 | Motorola, Inc. | Method for forming a vertically integrated dynamic memory cell |
US5731609A (en) * | 1992-03-19 | 1998-03-24 | Kabushiki Kaisha Toshiba | MOS random access memory having array of trench type one-capacitor/one-transistor memory cells |
US5365477A (en) * | 1992-06-16 | 1994-11-15 | The United States Of America As Represented By The Secretary Of The Navy | Dynamic random access memory device |
US5292676A (en) * | 1992-07-29 | 1994-03-08 | Micron Semiconductor, Inc. | Self-aligned low resistance buried contact process |
US5320880A (en) * | 1992-10-20 | 1994-06-14 | Micron Technology, Inc. | Method of providing a silicon film having a roughened outer surface |
US5429955A (en) * | 1992-10-26 | 1995-07-04 | Texas Instruments Incorporated | Method for constructing semiconductor-on-insulator |
US5266514A (en) * | 1992-12-21 | 1993-11-30 | Industrial Technology Research Institute | Method for producing a roughened surface capacitor |
US5409563A (en) * | 1993-02-26 | 1995-04-25 | Micron Technology, Inc. | Method for etching high aspect ratio features |
US5616934A (en) * | 1993-05-12 | 1997-04-01 | Micron Technology, Inc. | Fully planarized thin film transistor (TFT) and process to fabricate same |
US5519236A (en) * | 1993-06-28 | 1996-05-21 | Kabushiki Kaisha Toshiba | Semiconductor memory device having surrounding gate transistor |
US5396452A (en) * | 1993-07-02 | 1995-03-07 | Wahlstrom; Sven E. | Dynamic random access memory |
US5385854A (en) * | 1993-07-15 | 1995-01-31 | Micron Semiconductor, Inc. | Method of forming a self-aligned low density drain inverted thin film transistor |
US5644540A (en) * | 1993-08-13 | 1997-07-01 | Micron Technology, Inc. | Redundancy elements using thin film transistors (TFTs) |
US5392245A (en) * | 1993-08-13 | 1995-02-21 | Micron Technology, Inc. | Redundancy elements using thin film transistors (TFTs) |
US5445986A (en) * | 1993-09-03 | 1995-08-29 | Nec Corporation | Method of forming a roughened surface capacitor with two etching steps |
US5483094A (en) * | 1993-09-20 | 1996-01-09 | Motorola, Inc. | Electrically programmable read-only memory cell |
US5396093A (en) * | 1994-02-14 | 1995-03-07 | Industrial Technology Research Institute | Vertical DRAM cross point memory cell and fabrication method |
US5451889A (en) * | 1994-03-14 | 1995-09-19 | Motorola, Inc. | CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage current |
US5574299A (en) * | 1994-03-28 | 1996-11-12 | Samsung Electronics Co., Ltd. | Semiconductor device having vertical conduction transistors and cylindrical cell gates |
US5502629A (en) * | 1994-03-31 | 1996-03-26 | Fujitsu Limited | DC-DC converter |
US5460988A (en) * | 1994-04-25 | 1995-10-24 | United Microelectronics Corporation | Process for high density flash EPROM cell |
US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
US5495441A (en) * | 1994-05-18 | 1996-02-27 | United Microelectronics Corporation | Split-gate flash memory cell |
US5563083A (en) * | 1994-06-17 | 1996-10-08 | Pein; Howard B. | Method of fabricating non-volatile sidewall memory cell |
US5432739A (en) * | 1994-06-17 | 1995-07-11 | Philips Electronics North America Corporation | Non-volatile sidewall memory cell method of fabricating same |
US5705415A (en) * | 1994-10-04 | 1998-01-06 | Motorola, Inc. | Process for forming an electrically programmable read-only memory cell |
US5508542A (en) * | 1994-10-28 | 1996-04-16 | International Business Machines Corporation | Porous silicon trench and capacitor structures |
US5646900A (en) * | 1995-01-12 | 1997-07-08 | Mitsubishi Denki Kabushiki Kaisha | Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device |
US5789967A (en) * | 1995-03-31 | 1998-08-04 | Nec Corporation | Semiconductor device with boost voltage supply means |
US5714793A (en) * | 1995-04-03 | 1998-02-03 | The United States Of America As Represented By The Secretary Of The Navy | Complementary vertical bipolar junction transistors formed in silicon-on-saphire |
US5528173A (en) * | 1995-05-10 | 1996-06-18 | Micron Technology, Inc. | Low power, high speed level shifter |
US5641545A (en) * | 1995-06-07 | 1997-06-24 | Micron Technology, Inc. | Method to deposit highly conformal CVD films |
US6221788B1 (en) * | 1995-08-01 | 2001-04-24 | Matsushita Electronics Corporation | Semiconductor and a method for manufacturing an oxide film on the surface of a semiconductor substrate |
US5879971A (en) * | 1995-09-28 | 1999-03-09 | Motorola Inc. | Trench random access memory cell and method of formation |
US5640342A (en) * | 1995-11-20 | 1997-06-17 | Micron Technology, Inc. | Structure for cross coupled thin film transistors and static random access memory cell |
US5640350A (en) * | 1996-05-01 | 1997-06-17 | Iga; Adam Sempa | Multi-bit dynamic random access memory cell storage |
US5760434A (en) * | 1996-05-07 | 1998-06-02 | Micron Technology, Inc. | Increased interior volume for integrated memory cell |
US5990820A (en) * | 1996-05-07 | 1999-11-23 | Telefonaktiebolaget Lm Ericsson | Current-mode pipelined ADC with time-interleaved sampling and mixed reference and residue scaling |
US5943267A (en) * | 1996-05-16 | 1999-08-24 | Altera Corporation | High-density nonvolatile memory cell |
US5691230A (en) * | 1996-09-04 | 1997-11-25 | Micron Technology, Inc. | Technique for producing small islands of silicon on insulator |
US5821796A (en) * | 1996-09-23 | 1998-10-13 | Texas Instruments Incorporated | Circuitry for providing a high impedance state when powering down a single port node |
US5874760A (en) * | 1997-01-22 | 1999-02-23 | International Business Machines Corporation | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
US5852375A (en) * | 1997-02-07 | 1998-12-22 | Silicon Systems Research Limited | 5v tolerant I/O circuit |
US5877061A (en) * | 1997-02-25 | 1999-03-02 | International Business Machines Corporation | Methods for roughening and volume expansion of trench sidewalls to form high capacitance trench cell for high density dram applications |
US5933717A (en) * | 1997-03-04 | 1999-08-03 | Advanced Micro Devices, Inc. | Vertical transistor interconnect structure and fabrication method thereof |
US5996011A (en) * | 1997-03-25 | 1999-11-30 | Unified Research Laboratories, Inc. | System and method for filtering data received by a computer system |
US6072209A (en) * | 1997-07-08 | 2000-06-06 | Micro Technology, Inc. | Four F2 folded bit line DRAM cell structure having buried bit and word lines |
US5909618A (en) * | 1997-07-08 | 1999-06-01 | Micron Technology, Inc. | Method of making memory cell with vertical transistor and buried word and body lines |
US5973356A (en) * | 1997-07-08 | 1999-10-26 | Micron Technology, Inc. | Ultra high density flash memory |
US6238976B1 (en) * | 1997-07-08 | 2001-05-29 | Micron Technology, Inc. | Method for forming high density flash memory |
US5936274A (en) * | 1997-07-08 | 1999-08-10 | Micron Technology, Inc. | High density flash memory |
US6172391B1 (en) * | 1997-08-27 | 2001-01-09 | Siemens Aktiengesellschaft | DRAM cell arrangement and method for the manufacture thereof |
US5914511A (en) * | 1997-10-06 | 1999-06-22 | Micron Technology, Inc. | Circuit and method for a folded bit line memory using trench plate capacitor cells with body bias contacts |
US6528837B2 (en) * | 1997-10-06 | 2003-03-04 | Micron Technology, Inc. | Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor |
US6255708B1 (en) * | 1997-10-10 | 2001-07-03 | Rengarajan Sudharsanan | Semiconductor P-I-N detector |
US6181196B1 (en) * | 1997-12-18 | 2001-01-30 | Texas Instruments Incorporated | Accurate bandgap circuit for a CMOS process without NPN devices |
US6208164B1 (en) * | 1998-08-04 | 2001-03-27 | Micron Technology, Inc. | Programmable logic array with vertical transistors |
US6181121B1 (en) * | 1999-03-04 | 2001-01-30 | Cypress Semiconductor Corp. | Low supply voltage BICMOS self-biased bandgap reference using a current summing architecture |
US6172535B1 (en) * | 1999-11-04 | 2001-01-09 | Analog Devices, Inc. | High-speed analog comparator structures and methods |
US6121084A (en) * | 2000-01-27 | 2000-09-19 | Micron Technology, Inc. | Semiconductor processing methods of forming hemispherical grain polysilicon layers, methods of forming capacitors, and capacitors |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010029077A1 (en) * | 1997-07-08 | 2001-10-11 | Micron Technology, Inc. | Ultra high density flash memory |
US20110163371A1 (en) * | 2005-09-15 | 2011-07-07 | Song Ki-Whan | Methods of fabricating nonvolatile semiconductor memory devices |
US8575672B2 (en) * | 2005-09-15 | 2013-11-05 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory devices |
US20080080249A1 (en) * | 2006-10-03 | 2008-04-03 | Powerchip Semiconductor Corp. | Non-volatile memory, fabricating method and operating method thereof |
US20080305593A1 (en) * | 2007-06-11 | 2008-12-11 | Ching-Nan Hsiao | Memory structure and method of making the same |
US7682902B2 (en) * | 2007-06-11 | 2010-03-23 | Nanya Technology Corp. | Memory structure and method of making the same |
US8686487B2 (en) | 2007-06-14 | 2014-04-01 | Micron Technology, Inc. | Semiconductor devices and electronic systems comprising floating gate transistors |
US20080308858A1 (en) * | 2007-06-14 | 2008-12-18 | Micron Technology, Inc. | Semiconductor devices and electronic systems comprising floating gate transistors and methods of forming the same |
US9356157B2 (en) | 2007-06-14 | 2016-05-31 | Micron Technology, Inc. | Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices |
US7781817B2 (en) | 2008-06-26 | 2010-08-24 | International Business Machines Corporation | Structures, fabrication methods, and design structures for multiple bit flash memory cells |
US20090321808A1 (en) * | 2008-06-26 | 2009-12-31 | International Business Machines Corporation | Structures, fabrication methods, and design structures for multiple bit flash memory cells |
WO2010083486A1 (en) * | 2009-01-19 | 2010-07-22 | Wms Gaming, Inc. | Transporting and using wagering game data |
US8523663B2 (en) | 2009-01-19 | 2013-09-03 | Wms Gaming, Inc | Transporting and using wagering game data |
US9324208B2 (en) | 2009-01-19 | 2016-04-26 | Bally Gaming, Inc. | Transporting and using wagering game data |
US20140061781A1 (en) * | 2012-08-31 | 2014-03-06 | SK Hynix Inc. | Semiconductor device and method of fabricating the same |
US9082848B2 (en) * | 2012-08-31 | 2015-07-14 | SK Hynix Inc. | Semiconductor device and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US20060255397A1 (en) | 2006-11-16 |
US20010029077A1 (en) | 2001-10-11 |
US6238976B1 (en) | 2001-05-29 |
US20070069281A1 (en) | 2007-03-29 |
US5973356A (en) | 1999-10-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6238976B1 (en) | Method for forming high density flash memory | |
US5936274A (en) | High density flash memory | |
US6211015B1 (en) | Ultra high density flash memory having vertically stacked devices | |
US7491608B2 (en) | Vertical transistor with horizontal gate layers | |
US5909618A (en) | Method of making memory cell with vertical transistor and buried word and body lines | |
US7307308B2 (en) | Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation | |
US6689660B1 (en) | 4 F2 folded bit line DRAM cell structure having buried bit and word lines | |
US6331465B1 (en) | Alternate method and structure for improved floating gate tunneling devices using textured surface | |
US7629640B2 (en) | Two bit/four bit SONOS flash memory cell | |
US7205198B2 (en) | Method of making a bi-directional read/program non-volatile floating gate memory cell | |
JP4053232B2 (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
US6476441B2 (en) | Method and structure for textured surfaces in floating gate tunneling oxide devices | |
US11315635B2 (en) | Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same | |
US6392927B2 (en) | Cell array, operating method of the same and manufacturing method of the same | |
CN111341776A (en) | Memory and forming method thereof, memory cell array and driving method thereof | |
JP2002261174A (en) | Manufacturing method of nonvolatile semiconductor memory | |
KR20060043534A (en) | Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation | |
US20070147123A1 (en) | Split gate type non-volatile memory device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: EXPRESSLY ABANDONED -- DURING EXAMINATION |