US20060223237A1 - Method of manufacturing enhanced thermal dissipation integrated circuit package - Google Patents

Method of manufacturing enhanced thermal dissipation integrated circuit package Download PDF

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Publication number
US20060223237A1
US20060223237A1 US11/367,708 US36770806A US2006223237A1 US 20060223237 A1 US20060223237 A1 US 20060223237A1 US 36770806 A US36770806 A US 36770806A US 2006223237 A1 US2006223237 A1 US 2006223237A1
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United States
Prior art keywords
heat sink
semiconductor die
integrated circuit
package
substrate
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Abandoned
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US11/367,708
Inventor
Edward Combs
Robert Sheppard
Tai Pun
Hau Ng
Chan Fan
Neil McLellan
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UTAC Hong Kong Ltd
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UTAC Hong Kong Ltd
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Publication date
Priority claimed from US09/902,878 external-priority patent/US6734552B2/en
Application filed by UTAC Hong Kong Ltd filed Critical UTAC Hong Kong Ltd
Priority to US11/367,708 priority Critical patent/US20060223237A1/en
Assigned to ASAT LIMITED reassignment ASAT LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COMBS, EDWARD G., PUN, TAI WAI, SHEPPARD, ROBERT P., FAN, CHUN HO, MCLELLAN, NEIL ROBERT, NG, HAU WAN
Publication of US20060223237A1 publication Critical patent/US20060223237A1/en
Assigned to UTAC HONG KONG LIMITED reassignment UTAC HONG KONG LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: ASAT LIMITED
Abandoned legal-status Critical Current

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Definitions

  • the present invention relates to integrated circuit packaging and manufacturing thereof, and more particularly, to integrated circuit packaging for enhanced dissipation of thermal energy.
  • a semiconductor device generates a great deal of heat during normal operation. As the speed of semiconductors has increased, so too has the amount of heat generated by them. It is desirable to dissipate this heat from an integrated circuit package in an efficient manner.
  • a heat sink is one type of device used to help dissipate heat from some integrated circuit packages.
  • Various shapes and sizes of heat sink devices have been incorporated onto, into or around integrated circuit packages for improving heat dissipation from the particular integrated circuit package.
  • U.S. Pat. No. 5,596,231 to Combs entitled “High Power Dissipation Plastic Encapsulated Package For Integrated Circuit Die,” discloses a selectively coated heat sink attached directly on to the integrated circuit die and to a lead frame for external electrical connections.
  • the invention features an integrated circuit package with a semiconductor die electrically connected to a substrate, a heat sink having a portion thereof exposed to the surroundings of the package, a thermally conductive element thermally coupled with and interposed between both the semiconductor die and the heat sink, wherein the thermally conductive element does not directly contact the semiconductor die, and an encapsulant material encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
  • the invention features an integrated circuit package with a semiconductor die electrically connected to a substrate, a heat sink having a portion thereof exposed to the surroundings of the package, means for thermally coupling the semiconductor die with the heat sink to dissipate heat from the semiconductor die to the surroundings of the package, wherein the means for thermally coupling is interposed between the semiconductor die and the heat sink but does not directly contact the semiconductor die, and means for encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
  • the invention features an integrated circuit package with a substrate having an upper face with an electrically conductive trace formed thereon and a lower face with a plurality of solder balls electrically connected thereto, wherein the trace and at least one of the plurality of solder balls are electrically connected, a semiconductor die mounted on the upper face of the substrate, wherein the semiconductor die is electrically connected to the trace, a heat sink having a top portion and a plurality of side portions, a thermally conductive element thermally coupled to but not in direct contact with the semiconductor die, wherein the thermally conductive element is substantially shaped as a right rectangular solid, is interposed between said semiconductor die and said heat sink, and is attached to said heat sink, and an encapsulant material formed to encapsulate the upper face of the substrate, the semiconductor die, the thermally conductive element and substantially all of the heat sink except the top portion and the side portions of the heat sink.
  • the invention features an integrated circuit package with a substrate having means for electrically interconnecting a semiconductor die and means for exchanging electrical signals with an outside device, a semiconductor die attached and electrically connected to the substrate by attachment means, a heat sink having means for dissipating thermal energy to the surroundings of the package, means for thermally coupling the semiconductor die to the heat sink to dissipate heat from said semiconductor die to the surroundings of said package, wherein said means for thermally coupling is interposed between said semiconductor die and said heat sink but does not directly contact the semiconductor die, and means for encapsulating said semiconductor die, said thermally conductive element and said heat sink such that said portion of said heat sink is exposed to the surroundings of said package but is substantially encapsulated.
  • the invention features a method of manufacturing an integrated circuit package including installing a carrier onto an upper surface of a substrate, wherein the carrier defines a cavity, attaching a semiconductor die to the upper surface of the substrate within the cavity of the carrier, aligning an assembly over the semiconductor die, wherein the assembly comprises a heat sink and a thermally conductive element, resting the assembly on the carrier such that the thermally conductive element does not directly contact the semiconductor die, and encapsulating the cavity to form a prepackage such that a portion of the heat sink is exposed to the surroundings of the package.
  • the invention features a method of manufacturing an integrated circuit package including installing a carrier onto a substrate, attaching a semiconductor die to the substrate, aligning an assembly over the semiconductor die, wherein the assembly has a heat sink and a thermally conductive element, resting the assembly on the carrier such that the thermally conductive element does not directly contact the semiconductor die, and encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
  • FIG. 1 is a simplified cross-sectional view of an integrated circuit package according to one embodiment of the present invention
  • FIG. 2 is a simplified cross-sectional view of a subassembly of the integrated circuit package shown in FIG. 1 , prior to encapsulation and singulation assembly steps;
  • FIG. 3 is a simplified cross-sectional view of an integrated circuit package according to another embodiment of the invention, which has a direct chip attachment;
  • FIG. 4A is a plan view of the subassembly of FIG. 2 having one type of heat sink assembly used in the integrated circuit package shown in FIG. 1 ;
  • FIG. 4B is a plan view of a subassembly of an integrated circuit package having a second type of heat sink capable of being used in the integrated circuit package shown in FIG. 1 ;
  • FIG. 5 is a plan view of the heat sink shown in the subassembly of FIG. 4A ;
  • FIG. 6 is a plan view of a heat sink assembly as shown in FIG. 4A , which becomes the heat sink shown in FIG. 5 once assembled into an integrated circuit package such as the embodiment shown in FIG. 1 ;
  • FIG. 7 is a plan view of a third type of heat sink capable of being used in the integrated circuit package shown in FIG. 1 ;
  • FIG. 8 is a plan view of a fourth type of heat sink capable of being used in the integrated circuit package shown in FIG. 1 ;
  • FIG. 9A is a plan view of a matrix frame containing a “3 ⁇ 3” matrix of heat sinks of the type shown in FIG. 5 ;
  • FIG. 9B is a plan view of another matrix frame containing a “2 ⁇ 3” matrix of heat sinks of the type shown in FIG. 4B ;
  • FIG. 10 is a simplified cross-sectional view along line A-A of the heat sink shown in FIG. 5 , and a thermally conductive element of one embodiment
  • FIG. 11 shows a flowchart of major steps performed in assembly of one embodiment of an integrated circuit package.
  • FIG. 1 shows certain components of an integrated circuit package according to one embodiment of the present invention displayed in their respective positions relative to one another.
  • the integrated circuit package depicted in FIG. 1 generally includes a substrate 100 , a heat sink 110 , an adapter assembly 120 , a semiconductor die 130 and an encapsulant 140 .
  • a substrate 100 of either a rigid material (e.g., BT, FR4, or ceramic) or a flexible material (e.g., polyimide) has circuit traces 102 onto which a semiconductor die 130 can be interconnected using, for example, wire bonding techniques, direct chip attachment, or tape automated bonding.
  • FIG. 1 shows a semiconductor die 130 connected to the traces 102 of the substrate 100 via a gold thermo-sonic wire bonding technique.
  • gold wires 104 interconnect the semiconductor die 130 to the traces of the substrate 100 .
  • the semiconductor die 130 is connected to the traces 102 via a direct chip attachment technique including solder balls 105 .
  • the substrate 100 may be produced in strip form to accommodate standard semiconductor manufacturing equipment and process flows, and may also be configured in a matrix format to accommodate high-density packaging.
  • the traces 102 are embedded photolithographically into the substrate 100 , and are electrically conductive to provide a circuit connection between the semiconductor die 130 and the substrate 100 . Such traces 102 also provide an interconnection between input and output terminals of the semiconductor die 130 and external terminals provided on the package.
  • the substrate 100 of the embodiment shown in FIG. 1 has a two-layer circuit trace 102 made of copper. A multilayer substrate may also be used in accordance with an embodiment.
  • the substrate 100 shown in FIG. 1 has several vias drilled into it to connect the top and bottom portions of each circuit trace 102 . Such vias are plated with copper to electrically connect the top and bottom portions of each trace 102 .
  • the substrate 100 shown in FIG. 1 also has a solder mask 107 on the top and bottom surfaces. The solder mask 107 of one embodiment electrically insulates the substrate and reduces wetting (i.e., reduces wanted flow of solder into the substrate 100 .)
  • the external terminals of the package of one embodiment of the present invention include an array of solder balls 106 .
  • the solder balls 106 function as leads capable of providing power, signal inputs and signal outputs to the semiconductor die 130 .
  • Those solder balls are attached to corresponding traces 102 using a reflow soldering process.
  • the solder balls 106 can be made of a variety of materials including lead (Pb) free solder.
  • Pb lead
  • Such a configuration may be referred to as a type of ball grid array. Absent the solder balls 106 , such a configuration may be referred to as a type of LAN grid array.
  • the semiconductor die 130 may be mounted or attached to the substrate 100 (step 1115 ) with an adhesive material 115 , such as epoxy.
  • an adhesive material 115 such as epoxy.
  • a solder reflow process or other suitable direct chip attachment technique may also be used as an alternative way to attach the semiconductor die 130 to the substrate 100 (step 1115 ).
  • the heat sink 110 is aligned with and positioned above the top surface of the semiconductor die 130 , but not in direct contact with any portion of the semiconductor die 130 .
  • the heat sink 110 is preferably made of a thermally conductive material such as copper or copper alloy.
  • FIG. 2 shows, in cross-sectional view, a carrier 200 installed onto the substrate 100 .
  • the carrier 200 can be mounted on the substrate 100 by mechanical fastening, adhesive joining or other suitable technique (step 1110 ).
  • the carrier 200 may have one or more recesses 202 sized to accept support structure 114 of a heat sink assembly (step 1125 ).
  • the carrier 200 is configured to accept either an individual heat sink assembly (as shown in FIGS. 4A and 4B ), or a matrix heat sink assembly 310 containing a number of heat sinks 110 (as shown in FIGS.
  • the support structure 114 helps to properly align the heat sink 110 during assembly (step 1120 ) and, accordingly, may be removed (as discussed below) in whole or in part prior to completion of an integrated circuit package. In one preferred embodiment, however, some portions of the support structure 114 remain in the final integrated circuit package and are exposed to the ambient environment. For example, in the embodiment depicted in FIG. 1 , portions of the support structure 114 serve as heat dissipation surfaces.
  • FIG. 4B Further details of the heat sink 110 of a subassembly shown in FIG. 4B include extending fingers 116 of the support structure 114 . As shown in plan view by FIG. 4B , the fingers 116 may be sized and shaped to engage matching wells or recesses 202 in the supporting walls of the carrier 200 (step 1125 ). Such fingers 116 in whole or in part support the heat sink 110 prior to encapsulation (step 1130 ) and align the heat sink 110 above the semiconductor die 130 .
  • FIGS. 4B, 5 , 7 and 8 each show a different geometry for a heat sink 110 .
  • the heat sink 110 may be sized and configured for use in a specific package arrangement.
  • the heat sink 110 may be sized for incorporation into a package having only a single semiconductor die 130 (see FIG. 1 ).
  • several heat sinks 110 may be arranged in a matrix configuration 300 to accommodate the assembly of several packages at once.
  • Such a matrix configuration 300 is selected to allow each heat sink 110 of the matrix to be aligned with the corresponding semiconductor die 130 and an underlying matrix package substrate 100 .
  • a 2 ⁇ 3 and a 3 ⁇ 3 matrix of heat sinks 110 within each matrix heat sink assembly 310 are shown in FIGS.
  • FIG. 9A shows a 3 ⁇ 3 matrix of heat sinks 110 , wherein each heat sink 110 has a geometry similar to that of an embodiment shown in FIGS. 4A, 5 and 6 .
  • FIG. 9B shows a 2 ⁇ 3 matrix of heat sinks 110 , wherein each heat sink 110 has a geometry similar to that of an embodiment shown in FIG. 4B .
  • the heat sink 110 has a raised portion 112 protruding above a primary plane of the heat sink 110 .
  • an exposed surface of the raised portion 112 may be plated with nickel 116 , and functions as a heat dissipation interface with the ambient environment.
  • the nickel plating 116 protects the heat sink 110 during environmental testing by resisting oxidation of certain heat sink materials, such as copper.
  • the raised portion 112 can be formed by removing the surrounding portion of the upper surface of the heat sink 110 , for example, by etching.
  • the heat sink 110 is also oxide coated to enhance the adhesion between the encapsulant material 140 and the heat sink 110 . The oxide coating may be achieved or applied by chemical reaction.
  • the adaptor assembly 120 shown in FIGS. 1 and 2 provides a thermal path between the semiconductor die 130 and the heat sink 110 .
  • Such an adaptor assembly 120 includes an adaptor element 122 made of a thermally conductive material (e.g., alumina (Al 2 O 3 ), aluminum nitride, beryllium oxide (BeO), ceramic material, copper, diamond compound, or metal) appropriate for heat transfer between the semiconductor die 130 and the heat sink 110 .
  • the adaptor element 122 is shaped as a right rectangular solid, such that its upper and lower faces have dimensions similar to the upper face of the semiconductor die 130 .
  • One dimension of the adaptor element 122 may be selected to match the area of the upper surface of the semiconductor die 130 .
  • the thickness of the adaptor element 122 may also be selected to accommodate size variations of the semiconductor die 130 and the heat sink 110 .
  • the adaptor assembly 120 reduces the thermal resistance of the die-to-sink interface.
  • the distance from the upper surface of the semiconductor die 130 to the adaptor element 122 is minimized to reduce the thermal resistance between the semiconductor die 130 and the heat sink 110 .
  • the adaptor element 122 does not directly contact the semiconductor 130 surface.
  • the distance between the adaptor element 122 and the semiconductor 130 surface is about five (5) mils or less.
  • An adhesive layer 119 having both high thermal conductivity and deformability to minimize stress, such as an elastomer, may be used to join the adaptor element 122 to the heat sink 110 .
  • an adhesive layer 119 is electrically and thermally conductive.
  • the adaptor assembly 120 may also include a polymeric thermal interface 124 between the semiconductor die 130 and the adaptor element 122 to further minimize the thermal resistance of the die-to-sink interface.
  • the coefficient of polymeric thermal expansion (CTE) of the thermal interface 124 is similar to that of silicon to minimize stress on the semiconductor die 130 .
  • a thermal interface 124 portion of the adaptor assembly 120 may be attached to the heat sink 110 to reduce the distance from the surface of the semiconductor die 130 to the heat sink 110 .
  • the semiconductor die 130 , adaptor assembly 120 and a portion of the heat sink 110 are encapsulated to form an integrated circuit package according to one embodiment of the present invention.
  • the encapsulant 140 may be an epoxy based material applied by, for example, either a liquid molding encapsulation process or a transfer molding technique.
  • the encapsulation step 1130 occurs after the carrier 200 is attached to the substrate 100 (step 1110 ), and the heat sink 110 is installed in the carrier 200 (step 1125 ). During such an encapsulation step 1130 , the cavity 204 of the carrier 200 is filled with encapsulant 140 .
  • Solder balls 106 are then attached to the traces 102 of the substrate 100 using a reflow soldering process. After such encapsulation and ball attachment assembly steps, the integrated circuit packages are removed from the strip and singulated into individual units using a saw singulation or punching technique (step 1135 ). Upon completion of these assembly steps, the top portion 112 and some portions of the support structure 114 of the heat sink 110 remain exposed to allow heat transfer and dissipation to the ambient environment of the integrated circuit package (see FIG. 1 ).

Abstract

The present invention relates to an integrated circuit package having a thermally conductive element thermally coupled to a semiconductor die and a heat sink, and a method of manufacturing said integrated circuit package. The thermally conductive element is integrated into the package to enhance thermal dissipation characteristics of the package.

Description

    FIELD OF THE INVENTION
  • The present invention relates to integrated circuit packaging and manufacturing thereof, and more particularly, to integrated circuit packaging for enhanced dissipation of thermal energy.
    • BACKGROUND OF THE INVENTION
  • A semiconductor device generates a great deal of heat during normal operation. As the speed of semiconductors has increased, so too has the amount of heat generated by them. It is desirable to dissipate this heat from an integrated circuit package in an efficient manner.
  • A heat sink is one type of device used to help dissipate heat from some integrated circuit packages. Various shapes and sizes of heat sink devices have been incorporated onto, into or around integrated circuit packages for improving heat dissipation from the particular integrated circuit package. For example, U.S. Pat. No. 5,596,231 to Combs, entitled “High Power Dissipation Plastic Encapsulated Package For Integrated Circuit Die,” discloses a selectively coated heat sink attached directly on to the integrated circuit die and to a lead frame for external electrical connections.
    • SUMMARY OF THE INVENTION
  • In one aspect, the invention features an integrated circuit package with a semiconductor die electrically connected to a substrate, a heat sink having a portion thereof exposed to the surroundings of the package, a thermally conductive element thermally coupled with and interposed between both the semiconductor die and the heat sink, wherein the thermally conductive element does not directly contact the semiconductor die, and an encapsulant material encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
  • In another aspect, the invention features an integrated circuit package with a semiconductor die electrically connected to a substrate, a heat sink having a portion thereof exposed to the surroundings of the package, means for thermally coupling the semiconductor die with the heat sink to dissipate heat from the semiconductor die to the surroundings of the package, wherein the means for thermally coupling is interposed between the semiconductor die and the heat sink but does not directly contact the semiconductor die, and means for encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
  • In yet another aspect, the invention features an integrated circuit package with a substrate having an upper face with an electrically conductive trace formed thereon and a lower face with a plurality of solder balls electrically connected thereto, wherein the trace and at least one of the plurality of solder balls are electrically connected, a semiconductor die mounted on the upper face of the substrate, wherein the semiconductor die is electrically connected to the trace, a heat sink having a top portion and a plurality of side portions, a thermally conductive element thermally coupled to but not in direct contact with the semiconductor die, wherein the thermally conductive element is substantially shaped as a right rectangular solid, is interposed between said semiconductor die and said heat sink, and is attached to said heat sink, and an encapsulant material formed to encapsulate the upper face of the substrate, the semiconductor die, the thermally conductive element and substantially all of the heat sink except the top portion and the side portions of the heat sink.
  • In a further aspect, the invention features an integrated circuit package with a substrate having means for electrically interconnecting a semiconductor die and means for exchanging electrical signals with an outside device, a semiconductor die attached and electrically connected to the substrate by attachment means, a heat sink having means for dissipating thermal energy to the surroundings of the package, means for thermally coupling the semiconductor die to the heat sink to dissipate heat from said semiconductor die to the surroundings of said package, wherein said means for thermally coupling is interposed between said semiconductor die and said heat sink but does not directly contact the semiconductor die, and means for encapsulating said semiconductor die, said thermally conductive element and said heat sink such that said portion of said heat sink is exposed to the surroundings of said package but is substantially encapsulated.
  • In another aspect, the invention features a method of manufacturing an integrated circuit package including installing a carrier onto an upper surface of a substrate, wherein the carrier defines a cavity, attaching a semiconductor die to the upper surface of the substrate within the cavity of the carrier, aligning an assembly over the semiconductor die, wherein the assembly comprises a heat sink and a thermally conductive element, resting the assembly on the carrier such that the thermally conductive element does not directly contact the semiconductor die, and encapsulating the cavity to form a prepackage such that a portion of the heat sink is exposed to the surroundings of the package.
  • In yet another aspect, the invention features a method of manufacturing an integrated circuit package including installing a carrier onto a substrate, attaching a semiconductor die to the substrate, aligning an assembly over the semiconductor die, wherein the assembly has a heat sink and a thermally conductive element, resting the assembly on the carrier such that the thermally conductive element does not directly contact the semiconductor die, and encapsulating the thermally conductive element and the heat sink such that a portion of the heat sink is exposed to the surroundings of the package.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing features and other aspects of the invention are explained in the following description taken in connection with the accompanying drawings, wherein:
  • FIG. 1 is a simplified cross-sectional view of an integrated circuit package according to one embodiment of the present invention;
  • FIG. 2 is a simplified cross-sectional view of a subassembly of the integrated circuit package shown in FIG. 1, prior to encapsulation and singulation assembly steps;
  • FIG. 3 is a simplified cross-sectional view of an integrated circuit package according to another embodiment of the invention, which has a direct chip attachment;
  • FIG. 4A is a plan view of the subassembly of FIG. 2 having one type of heat sink assembly used in the integrated circuit package shown in FIG. 1;
  • FIG. 4B is a plan view of a subassembly of an integrated circuit package having a second type of heat sink capable of being used in the integrated circuit package shown in FIG. 1;
  • FIG. 5 is a plan view of the heat sink shown in the subassembly of FIG. 4A;
  • FIG. 6 is a plan view of a heat sink assembly as shown in FIG. 4A, which becomes the heat sink shown in FIG. 5 once assembled into an integrated circuit package such as the embodiment shown in FIG. 1;
  • FIG. 7 is a plan view of a third type of heat sink capable of being used in the integrated circuit package shown in FIG. 1;
  • FIG. 8 is a plan view of a fourth type of heat sink capable of being used in the integrated circuit package shown in FIG. 1;
  • FIG. 9A is a plan view of a matrix frame containing a “3×3” matrix of heat sinks of the type shown in FIG. 5;
  • FIG. 9B is a plan view of another matrix frame containing a “2×3” matrix of heat sinks of the type shown in FIG. 4B;
  • FIG. 10 is a simplified cross-sectional view along line A-A of the heat sink shown in FIG. 5, and a thermally conductive element of one embodiment; and
  • FIG. 11 shows a flowchart of major steps performed in assembly of one embodiment of an integrated circuit package.
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Various embodiments of the integrated circuit package of the present invention will now be described with reference to the drawings.
  • FIG. 1 shows certain components of an integrated circuit package according to one embodiment of the present invention displayed in their respective positions relative to one another. The integrated circuit package depicted in FIG. 1 generally includes a substrate 100, a heat sink 110, an adapter assembly 120, a semiconductor die 130 and an encapsulant 140. Each of the foregoing will now be described in greater detail along with the manufacturing steps (shown in FIG. 11) associated with them.
  • A substrate 100 of either a rigid material (e.g., BT, FR4, or ceramic) or a flexible material (e.g., polyimide) has circuit traces 102 onto which a semiconductor die 130 can be interconnected using, for example, wire bonding techniques, direct chip attachment, or tape automated bonding. FIG. 1 shows a semiconductor die 130 connected to the traces 102 of the substrate 100 via a gold thermo-sonic wire bonding technique. In such an embodiment, gold wires 104 interconnect the semiconductor die 130 to the traces of the substrate 100. In another embodiment, shown in FIG. 3, the semiconductor die 130 is connected to the traces 102 via a direct chip attachment technique including solder balls 105. The substrate 100 may be produced in strip form to accommodate standard semiconductor manufacturing equipment and process flows, and may also be configured in a matrix format to accommodate high-density packaging.
  • In one embodiment, the traces 102 are embedded photolithographically into the substrate 100, and are electrically conductive to provide a circuit connection between the semiconductor die 130 and the substrate 100. Such traces 102 also provide an interconnection between input and output terminals of the semiconductor die 130 and external terminals provided on the package. In particular, the substrate 100 of the embodiment shown in FIG. 1 has a two-layer circuit trace 102 made of copper. A multilayer substrate may also be used in accordance with an embodiment. The substrate 100 shown in FIG. 1 has several vias drilled into it to connect the top and bottom portions of each circuit trace 102. Such vias are plated with copper to electrically connect the top and bottom portions of each trace 102. The substrate 100 shown in FIG. 1 also has a solder mask 107 on the top and bottom surfaces. The solder mask 107 of one embodiment electrically insulates the substrate and reduces wetting (i.e., reduces wanted flow of solder into the substrate 100.)
  • As shown in FIG. 1, the external terminals of the package of one embodiment of the present invention include an array of solder balls 106. In such an embodiment, the solder balls 106 function as leads capable of providing power, signal inputs and signal outputs to the semiconductor die 130. Those solder balls are attached to corresponding traces 102 using a reflow soldering process. The solder balls 106 can be made of a variety of materials including lead (Pb) free solder. Such a configuration may be referred to as a type of ball grid array. Absent the solder balls 106, such a configuration may be referred to as a type of LAN grid array.
  • As shown in FIGS. 1 and 2, the semiconductor die 130 may be mounted or attached to the substrate 100 (step 1115) with an adhesive material 115, such as epoxy. However, as shown in FIG. 3, a solder reflow process or other suitable direct chip attachment technique may also be used as an alternative way to attach the semiconductor die 130 to the substrate 100 (step 1115).
  • In the embodiment shown in FIG. 1, the heat sink 110 is aligned with and positioned above the top surface of the semiconductor die 130, but not in direct contact with any portion of the semiconductor die 130. The heat sink 110 is preferably made of a thermally conductive material such as copper or copper alloy.
  • One embodiment of an assembly process for manufacturing an integrated circuit package of the present invention uses a carrier 200 as shown in FIGS. 2, 4A and 4B. FIG. 2 shows, in cross-sectional view, a carrier 200 installed onto the substrate 100. The carrier 200 can be mounted on the substrate 100 by mechanical fastening, adhesive joining or other suitable technique (step 1110). The carrier 200 may have one or more recesses 202 sized to accept support structure 114 of a heat sink assembly (step 1125). In general, the carrier 200 is configured to accept either an individual heat sink assembly (as shown in FIGS. 4A and 4B), or a matrix heat sink assembly 310 containing a number of heat sinks 110 (as shown in FIGS. 9A and 9B) in order to align and install heat sinks 110 of either single semiconductor packages, or arrays of packages manufactured in a matrix configuration. The support structure 114 helps to properly align the heat sink 110 during assembly (step 1120) and, accordingly, may be removed (as discussed below) in whole or in part prior to completion of an integrated circuit package. In one preferred embodiment, however, some portions of the support structure 114 remain in the final integrated circuit package and are exposed to the ambient environment. For example, in the embodiment depicted in FIG. 1, portions of the support structure 114 serve as heat dissipation surfaces.
  • Further details of the heat sink 110 of a subassembly shown in FIG. 4B include extending fingers 116 of the support structure 114. As shown in plan view by FIG. 4B, the fingers 116 may be sized and shaped to engage matching wells or recesses 202 in the supporting walls of the carrier 200 (step 1125). Such fingers 116 in whole or in part support the heat sink 110 prior to encapsulation (step 1130) and align the heat sink 110 above the semiconductor die 130.
  • A number of types of heat sinks 110 may be used. FIGS. 4B, 5, 7 and 8 each show a different geometry for a heat sink 110. The heat sink 110 may be sized and configured for use in a specific package arrangement. For example, the heat sink 110 may be sized for incorporation into a package having only a single semiconductor die 130 (see FIG. 1). Alternatively, several heat sinks 110 may be arranged in a matrix configuration 300 to accommodate the assembly of several packages at once. Such a matrix configuration 300 is selected to allow each heat sink 110 of the matrix to be aligned with the corresponding semiconductor die 130 and an underlying matrix package substrate 100. Although a 2×3 and a 3×3 matrix of heat sinks 110 within each matrix heat sink assembly 310 are shown in FIGS. 9A and 9B, a number of matrix combinations and configurations are acceptable. FIG. 9A shows a 3×3 matrix of heat sinks 110, wherein each heat sink 110 has a geometry similar to that of an embodiment shown in FIGS. 4A, 5 and 6. FIG. 9B shows a 2×3 matrix of heat sinks 110, wherein each heat sink 110 has a geometry similar to that of an embodiment shown in FIG. 4B.
  • In one embodiment, the heat sink 110 has a raised portion 112 protruding above a primary plane of the heat sink 110. As shown in FIG. 10, an exposed surface of the raised portion 112 may be plated with nickel 116, and functions as a heat dissipation interface with the ambient environment. The nickel plating 116 protects the heat sink 110 during environmental testing by resisting oxidation of certain heat sink materials, such as copper. The raised portion 112 can be formed by removing the surrounding portion of the upper surface of the heat sink 110, for example, by etching. In a preferred embodiment, the heat sink 110 is also oxide coated to enhance the adhesion between the encapsulant material 140 and the heat sink 110. The oxide coating may be achieved or applied by chemical reaction.
  • The adaptor assembly 120 shown in FIGS. 1 and 2 provides a thermal path between the semiconductor die 130 and the heat sink 110. Such an adaptor assembly 120 includes an adaptor element 122 made of a thermally conductive material (e.g., alumina (Al2O3), aluminum nitride, beryllium oxide (BeO), ceramic material, copper, diamond compound, or metal) appropriate for heat transfer between the semiconductor die 130 and the heat sink 110. In one embodiment, the adaptor element 122 is shaped as a right rectangular solid, such that its upper and lower faces have dimensions similar to the upper face of the semiconductor die 130.
  • One dimension of the adaptor element 122 may be selected to match the area of the upper surface of the semiconductor die 130. The thickness of the adaptor element 122 may also be selected to accommodate size variations of the semiconductor die 130 and the heat sink 110. By reducing the distance between the semiconductor die 130 and the externally exposed heat sink 110, the adaptor assembly 120 reduces the thermal resistance of the die-to-sink interface.
  • In a preferred embodiment, the distance from the upper surface of the semiconductor die 130 to the adaptor element 122 is minimized to reduce the thermal resistance between the semiconductor die 130 and the heat sink 110. However, to avoid imparting stress to the semiconductor die 130, the adaptor element 122 does not directly contact the semiconductor 130 surface. In a preferred embodiment, the distance between the adaptor element 122 and the semiconductor 130 surface is about five (5) mils or less.
  • An adhesive layer 119, having both high thermal conductivity and deformability to minimize stress, such as an elastomer, may be used to join the adaptor element 122 to the heat sink 110. In a preferred embodiment, such an adhesive layer 119 is electrically and thermally conductive.
  • The adaptor assembly 120 may also include a polymeric thermal interface 124 between the semiconductor die 130 and the adaptor element 122 to further minimize the thermal resistance of the die-to-sink interface. In a preferred embodiment, the coefficient of polymeric thermal expansion (CTE) of the thermal interface 124 is similar to that of silicon to minimize stress on the semiconductor die 130. In one embodiment, a thermal interface 124 portion of the adaptor assembly 120 may be attached to the heat sink 110 to reduce the distance from the surface of the semiconductor die 130 to the heat sink 110.
  • As shown in FIG. 1, the semiconductor die 130, adaptor assembly 120 and a portion of the heat sink 110 are encapsulated to form an integrated circuit package according to one embodiment of the present invention. The encapsulant 140 may be an epoxy based material applied by, for example, either a liquid molding encapsulation process or a transfer molding technique. In one assembly method embodiment of the invention, the encapsulation step 1130 occurs after the carrier 200 is attached to the substrate 100 (step 1110), and the heat sink 110 is installed in the carrier 200 (step 1125). During such an encapsulation step 1130, the cavity 204 of the carrier 200 is filled with encapsulant 140. Solder balls 106 are then attached to the traces 102 of the substrate 100 using a reflow soldering process. After such encapsulation and ball attachment assembly steps, the integrated circuit packages are removed from the strip and singulated into individual units using a saw singulation or punching technique (step 1135). Upon completion of these assembly steps, the top portion 112 and some portions of the support structure 114 of the heat sink 110 remain exposed to allow heat transfer and dissipation to the ambient environment of the integrated circuit package (see FIG. 1).
  • Although specific embodiments of the present invention have been shown and described, it is to be understood that there are other embodiments which are equivalent to the described embodiments. Accordingly the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.

Claims (5)

1. A method of manufacturing an integrated circuit package, comprising:
installing a carrier onto an upper surface of a substrate, wherein said carrier defines a cavity;
attaching a semiconductor die to said upper surface of said substrate within said cavity of said carrier;
aligning an assembly over said semiconductor die, wherein said assembly comprises a heat sink and a thermally conductive element;
resting said assembly on said carrier such that said thermally conductive element does not directly contact said semiconductor die; and
encapsulating said cavity to form a prepackage such that a portion of said heat sink is exposed to the surroundings of said package.
2. The method of claim 1, wherein said assembly is rested on said carrier such that said thermally conductive element and said semiconductor die are separated by a distance of about five (5) mils or less.
3. The method of claim 1, wherein said attaching said semiconductor die to said upper surface of said substrate is by a direct chip attachment.
4. The method of claim 1, further comprising singulating said prepackage to form said package, wherein a top portion and a side portion of said heat sink are exposed to the surroundings of said package.
5. A method of manufacturing an integrated circuit package, comprising:
installing a carrier onto a substrate;
attaching a semiconductor die to said substrate;
aligning an assembly over said semiconductor die, wherein said assembly comprises a heat sink and a thermally conductive element;
resting said assembly on said carrier such that said thermally conductive element does not directly contact said semiconductor die; and
encapsulating said thermally conductive element and said heat sink such that a portion of said heat sink is exposed to the surroundings of said package.
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Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100059854A1 (en) * 2008-09-05 2010-03-11 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit
US20100127363A1 (en) * 2006-04-28 2010-05-27 Utac Thai Limited Very extremely thin semiconductor package
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US20110241189A1 (en) * 2010-04-02 2011-10-06 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US8125077B2 (en) 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US8367476B2 (en) 2009-03-12 2013-02-05 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US8368189B2 (en) 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US20140077350A1 (en) * 2012-09-20 2014-03-20 Sony Corporation Semiconductor device, method for manufacturing semiconductor device, and electronic device
US9000590B2 (en) 2012-05-10 2015-04-07 Utac Thai Limited Protruding terminals with internal routing interconnections semiconductor device
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9805955B1 (en) 2015-11-10 2017-10-31 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9947605B2 (en) 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
US20220028798A1 (en) * 2020-07-21 2022-01-27 UTAC Headquarters Pte. Ltd. Semiconductor packages with integrated shielding
US11328971B2 (en) * 2016-01-29 2022-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11355419B2 (en) * 2018-01-11 2022-06-07 Amosense Co., Ltd. Power semiconductor module
US20230326878A1 (en) * 2020-12-23 2023-10-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7015072B2 (en) * 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
US7550845B2 (en) * 2002-02-01 2009-06-23 Broadcom Corporation Ball grid array package with separated stiffener layer
US7863730B2 (en) * 2003-08-28 2011-01-04 St Assembly Test Services Ltd. Array-molded package heat spreader and fabrication method therefor
US7432586B2 (en) * 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7482686B2 (en) * 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US20070065984A1 (en) * 2005-09-22 2007-03-22 Lau Daniel K Thermal enhanced package for block mold assembly
US7582951B2 (en) * 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7656173B1 (en) * 2006-04-27 2010-02-02 Utac Thai Limited Strip socket having a recessed portions in the base to accept bottom surface of packaged semiconductor devices mounted on a leadframe for testing and burn-in
US7714453B2 (en) * 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) * 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US7808087B2 (en) * 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
MY142210A (en) * 2006-06-05 2010-11-15 Carsem M Sdn Bhd Multiple row exposed leads for mlp high density packages
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
TWI317998B (en) * 2006-08-14 2009-12-01 Advanced Semiconductor Eng Package structure and heat sink module thereof
TW200824074A (en) * 2006-11-24 2008-06-01 Siliconware Precision Industries Co Ltd Heat-dissipation semiconductor package and fabrication method thereof
US8183687B2 (en) * 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
US20090042339A1 (en) * 2007-08-10 2009-02-12 Texas Instruments Incorporated Packaged integrated circuits and methods to form a packaged integrated circuit
US8067256B2 (en) * 2007-09-28 2011-11-29 Intel Corporation Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method
US20090166844A1 (en) * 2007-12-26 2009-07-02 Xuejiao Hu Metal cover on flip-chip matrix-array (fcmx) substrate for low cost cpu assembly
US7998791B2 (en) * 2008-02-01 2011-08-16 National Semiconductor Corporation Panel level methods and systems for packaging integrated circuits with integrated heat sinks
US8390112B2 (en) * 2008-09-30 2013-03-05 Intel Corporation Underfill process and materials for singulated heat spreader stiffener for thin core panel processing
US8354740B2 (en) * 2008-12-01 2013-01-15 Alpha & Omega Semiconductor, Inc. Top-side cooled semiconductor package with stacked interconnection plates and method
US8334764B1 (en) 2008-12-17 2012-12-18 Utac Thai Limited Method and apparatus to prevent double semiconductor units in test socket
JP4881971B2 (en) * 2009-03-26 2012-02-22 株式会社豊田自動織機 Semiconductor device
US8184440B2 (en) * 2009-05-01 2012-05-22 Abl Ip Holding Llc Electronic apparatus having an encapsulating layer within and outside of a molded frame overlying a connection arrangement on a circuit board
US8013429B2 (en) * 2009-07-14 2011-09-06 Infineon Technologies Ag Air cavity package with copper heat sink and ceramic window frame
TWI401773B (en) * 2010-05-14 2013-07-11 Chipmos Technologies Inc Chip package device and manufacturing method thereof
JP2012033559A (en) * 2010-07-28 2012-02-16 J Devices:Kk Semiconductor device
US9559064B2 (en) 2013-12-04 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in package-on-package structures
CN105261598B (en) 2014-07-16 2018-11-13 恩智浦美国有限公司 Semiconductor devices with the radiator based on pipeline
JP6897141B2 (en) * 2017-02-15 2021-06-30 株式会社デンソー Semiconductor devices and their manufacturing methods
TWI761864B (en) * 2020-06-19 2022-04-21 海華科技股份有限公司 Chip scale package structure with heat-dissipating type
US20230067409A1 (en) * 2021-08-31 2023-03-02 Arista Networks, Inc. Damper system for a lidless integrated circuit

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4323914A (en) * 1979-02-01 1982-04-06 International Business Machines Corporation Heat transfer structure for integrated circuit package
US5596231A (en) * 1991-08-05 1997-01-21 Asat, Limited High power dissipation plastic encapsulated package for integrated circuit die
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
US5940271A (en) * 1997-05-02 1999-08-17 Lsi Logic Corporation Stiffener with integrated heat sink attachment
US6091603A (en) * 1999-09-30 2000-07-18 International Business Machines Corporation Customizable lid for improved thermal performance of modules using flip chips
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6236568B1 (en) * 1999-03-20 2001-05-22 Siliconware Precision Industries, Co., Ltd. Heat-dissipating structure for integrated circuit package
US6410981B2 (en) * 1997-10-24 2002-06-25 Nec Corporation Vented semiconductor device package having separate substrate, strengthening ring and cap structures
US20020125564A1 (en) * 2001-03-12 2002-09-12 Kazutaka Shibata Semiconductor device reinforced by a highly elastic member made of a synthetic resin
US6515360B2 (en) * 1999-07-28 2003-02-04 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device and manufacturing method thereof
US6734552B2 (en) * 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US6936919B2 (en) * 2002-08-21 2005-08-30 Texas Instruments Incorporated Heatsink-substrate-spacer structure for an integrated-circuit package
US7015072B2 (en) * 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package

Family Cites Families (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3942245A (en) 1971-11-20 1976-03-09 Ferranti Limited Related to the manufacture of lead frames and the mounting of semiconductor devices thereon
GB1339660A (en) 1971-11-20 1973-12-05 Ferranti Ltd Supports for semiconductor devices
US4501960A (en) 1981-06-22 1985-02-26 Motorola, Inc. Micropackage for identification card
US4701781A (en) 1984-07-05 1987-10-20 National Semiconductor Corporation Pre-testable semiconductor die package
FR2579798B1 (en) 1985-04-02 1990-09-28 Ebauchesfabrik Eta Ag METHOD FOR MANUFACTURING ELECTRONIC MODULES FOR MICROCIRCUIT CARDS AND MODULES OBTAINED ACCORDING TO THIS METHOD
AU2309388A (en) 1987-08-26 1989-03-31 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and method of producing the same
US5157475A (en) 1988-07-08 1992-10-20 Oki Electric Industry Co., Ltd. Semiconductor device having a particular conductive lead structure
EP0351581A1 (en) 1988-07-22 1990-01-24 Oerlikon-Contraves AG High-density integrated circuit and method for its production
US5184207A (en) 1988-12-07 1993-02-02 Tribotech Semiconductor die packages having lead support frame
FR2645680B1 (en) 1989-04-07 1994-04-29 Thomson Microelectronics Sa Sg ENCAPSULATION OF ELECTRONIC MODULES AND MANUFACTURING METHOD
US5023202A (en) 1989-07-14 1991-06-11 Lsi Logic Corporation Rigid strip carrier for integrated circuits
US5175612A (en) 1989-12-19 1992-12-29 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5172213A (en) * 1991-05-23 1992-12-15 At&T Bell Laboratories Molded circuit package having heat dissipating post
JPH0629452A (en) 1992-02-18 1994-02-04 Intel Corp Integrated circuit package and its manufacture
US5334857A (en) 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5482898A (en) 1993-04-12 1996-01-09 Amkor Electronics, Inc. Method for forming a semiconductor device having a thermal dissipator and electromagnetic shielding
US5420460A (en) 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
US6326678B1 (en) 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5366933A (en) 1993-10-13 1994-11-22 Intel Corporation Method for constructing a dual sided, wire bonded integrated circuit chip package
US5679978A (en) 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US5991156A (en) 1993-12-20 1999-11-23 Stmicroelectronics, Inc. Ball grid array integrated circuit package with high thermal conductivity
US6081028A (en) 1994-03-29 2000-06-27 Sun Microsystems, Inc. Thermal management enhancements for cavity packages
EP0683517B1 (en) 1994-05-09 2002-07-24 Nec Corporation Semiconductor device having semiconductor chip bonded to circuit board through bumps and process of mounting thereof
US5650593A (en) 1994-05-26 1997-07-22 Amkor Electronics, Inc. Thermally enhanced chip carrier package
MY112145A (en) 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
US5482736A (en) 1994-08-04 1996-01-09 Amkor Electronics, Inc. Method for applying flux to ball grid array package
US5766975A (en) * 1995-01-09 1998-06-16 Integrated Device Technology, Inc. Packaged integrated circuit having thermal enhancement and reduced footprint size
US5672909A (en) 1995-02-07 1997-09-30 Amkor Electronics, Inc. Interdigitated wirebond programmable fixed voltage planes
US5596485A (en) 1995-03-16 1997-01-21 Amkor Electronics, Inc. Plastic packaged integrated circuit with heat spreader
US5620928A (en) 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
KR0159987B1 (en) * 1995-07-05 1998-12-01 아남산업주식회사 Heat sink structure of ball grid array package
KR0159986B1 (en) * 1995-09-04 1998-12-01 아남산업주식회사 Manufacture for heat sink having semiconductor and the manufacture
KR100201380B1 (en) * 1995-11-15 1999-06-15 김규현 Heat radiation structure of bga semiconductor package
US5854511A (en) * 1995-11-17 1998-12-29 Anam Semiconductor, Inc. Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads
JPH09260550A (en) * 1996-03-22 1997-10-03 Mitsubishi Electric Corp Semiconductor device
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
US5986340A (en) 1996-05-02 1999-11-16 National Semiconductor Corporation Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same
US5847929A (en) 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
US5805430A (en) 1996-07-22 1998-09-08 International Business Machines Corporation Zero force heat sink
KR0185512B1 (en) 1996-08-19 1999-03-20 김광호 Column lead type package and method of making the same
US5886397A (en) 1996-09-05 1999-03-23 International Rectifier Corporation Crushable bead on lead finger side surface to improve moldability
US5789813A (en) 1996-09-30 1998-08-04 Lsi Logic Corporation Ball grid array package with inexpensive threaded secure locking mechanism to allow removal of a threaded heat sink therefrom
US6127724A (en) 1996-10-31 2000-10-03 Tessera, Inc. Packaged microelectronic elements with enhanced thermal conduction
US5981314A (en) 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US5736785A (en) 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
US5894108A (en) 1997-02-11 1999-04-13 National Semiconductor Corporation Plastic package with exposed die
US6117705A (en) 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
US6034429A (en) 1997-04-18 2000-03-07 Amkor Technology, Inc. Integrated circuit package
US6011304A (en) 1997-05-05 2000-01-04 Lsi Logic Corporation Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid
JP2924854B2 (en) 1997-05-20 1999-07-26 日本電気株式会社 Semiconductor device and manufacturing method thereof
US5796163A (en) 1997-05-23 1998-08-18 Amkor Technology, Inc. Solder ball joint
US5939784A (en) 1997-09-09 1999-08-17 Amkor Technology, Inc. Shielded surface acoustical wave package
US5867368A (en) 1997-09-09 1999-02-02 Amkor Technology, Inc. Mounting for a semiconductor integrated circuit device
US5962810A (en) 1997-09-09 1999-10-05 Amkor Technology, Inc. Integrated circuit package employing a transparent encapsulant
US5949655A (en) 1997-09-09 1999-09-07 Amkor Technology, Inc. Mounting having an aperture cover with adhesive locking feature for flip chip optical integrated circuit device
US6028354A (en) 1997-10-14 2000-02-22 Amkor Technology, Inc. Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package
US6049125A (en) 1997-12-29 2000-04-11 Micron Technology, Inc. Semiconductor package with heat sink and method of fabrication
US6097101A (en) 1998-01-30 2000-08-01 Shinko Electric Industries Co., Ltd. Package for semiconductor device having frame-like molded portion and producing method of the same
US6111324A (en) 1998-02-05 2000-08-29 Asat, Limited Integrated carrier ring/stiffener and method for manufacturing a flexible integrated circuit package
JP3285815B2 (en) 1998-03-12 2002-05-27 松下電器産業株式会社 Lead frame, resin-encapsulated semiconductor device and method of manufacturing the same
US6229200B1 (en) 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6294100B1 (en) 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US6498099B1 (en) 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
US6285075B1 (en) 1998-11-02 2001-09-04 Asat, Limited Integrated circuit package with bonding planes on a ceramic ring using an adhesive assembly
US5982621A (en) 1998-11-23 1999-11-09 Caesar Technology Inc. Electronic device cooling arrangement
US6162849A (en) * 1999-01-11 2000-12-19 Ferro Corporation Thermally conductive thermoplastic
US6433360B1 (en) 1999-01-15 2002-08-13 Xilinx, Inc. Structure and method of testing failed or returned die to determine failure location and type
US6265771B1 (en) * 1999-01-27 2001-07-24 International Business Machines Corporation Dual chip with heat sink
US6246566B1 (en) 1999-02-08 2001-06-12 Amkor Technology, Inc. Electrostatic discharge protection package and method
US6206997B1 (en) 1999-02-11 2001-03-27 International Business Machines Corporation Method for bonding heat sinks to overmolds and device formed thereby
US6191360B1 (en) * 1999-04-26 2001-02-20 Advanced Semiconductor Engineering, Inc. Thermally enhanced BGA package
US6396143B1 (en) 1999-04-30 2002-05-28 Mitsubishi Gas Chemical Company, Inc. Ball grid array type printed wiring board having exellent heat diffusibility and printed wiring board
US6219238B1 (en) 1999-05-10 2001-04-17 International Business Machines Corporation Structure for removably attaching a heat sink to surface mount packages
US6337228B1 (en) 1999-05-12 2002-01-08 Amkor Technology, Inc. Low-cost printed circuit board with integral heat sink for semiconductor package
US6165612A (en) 1999-05-14 2000-12-26 The Bergquist Company Thermally conductive interface layers
JP3398721B2 (en) 1999-05-20 2003-04-21 アムコー テクノロジー コリア インコーポレーティド Semiconductor package and manufacturing method thereof
US6229702B1 (en) * 1999-06-02 2001-05-08 Advanced Semiconductor Engineering, Inc. Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability
US6274927B1 (en) 1999-06-03 2001-08-14 Amkor Technology, Inc. Plastic package for an optical integrated circuit device and method of making
US6196002B1 (en) 1999-06-24 2001-03-06 Advanced Micro Devices, Inc. Ball grid array package having thermoelectric cooler
US6258629B1 (en) 1999-08-09 2001-07-10 Amkor Technology, Inc. Electronic device package and leadframe and method for making the package
US6208519B1 (en) 1999-08-31 2001-03-27 Micron Technology, Inc. Thermally enhanced semiconductor package
US6198163B1 (en) 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US6222263B1 (en) 1999-10-19 2001-04-24 International Business Machines Corporation Chip assembly with load-bearing lid in thermal contact with the chip
US6117193A (en) 1999-10-20 2000-09-12 Amkor Technology, Inc. Optical sensor array mounting and alignment
US6291884B1 (en) 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages
DE19957710A1 (en) 1999-11-30 2001-05-31 Asat Ag Applied Science & Tech Treating female type androgenetic or diffuse alopecia by topical administration of melatonin, causing e.g. reduction of telogen rate and increase of anagen rate, hair diameter and tensile strength
US6163458A (en) 1999-12-03 2000-12-19 Caesar Technology, Inc. Heat spreader for ball grid array package
US6266197B1 (en) 1999-12-08 2001-07-24 Amkor Technology, Inc. Molded window array for image sensor packages
US6452255B1 (en) 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
US6214644B1 (en) 2000-06-30 2001-04-10 Amkor Technology, Inc. Flip-chip micromachine package fabrication method
KR100347706B1 (en) 2000-08-09 2002-08-09 주식회사 코스타트반도체 New molded package having a implantable circuits and manufacturing method thereof
US6429048B1 (en) 2000-12-05 2002-08-06 Asat Ltd. Metal foil laminated IC package
US6458626B1 (en) * 2001-08-03 2002-10-01 Siliconware Precision Industries Co., Ltd. Fabricating method for semiconductor package
TW498516B (en) * 2001-08-08 2002-08-11 Siliconware Precision Industries Co Ltd Manufacturing method for semiconductor package with heat sink

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4323914A (en) * 1979-02-01 1982-04-06 International Business Machines Corporation Heat transfer structure for integrated circuit package
US5596231A (en) * 1991-08-05 1997-01-21 Asat, Limited High power dissipation plastic encapsulated package for integrated circuit die
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US5940271A (en) * 1997-05-02 1999-08-17 Lsi Logic Corporation Stiffener with integrated heat sink attachment
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
US6410981B2 (en) * 1997-10-24 2002-06-25 Nec Corporation Vented semiconductor device package having separate substrate, strengthening ring and cap structures
US6236568B1 (en) * 1999-03-20 2001-05-22 Siliconware Precision Industries, Co., Ltd. Heat-dissipating structure for integrated circuit package
US6515360B2 (en) * 1999-07-28 2003-02-04 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device and manufacturing method thereof
US6091603A (en) * 1999-09-30 2000-07-18 International Business Machines Corporation Customizable lid for improved thermal performance of modules using flip chips
US20020125564A1 (en) * 2001-03-12 2002-09-12 Kazutaka Shibata Semiconductor device reinforced by a highly elastic member made of a synthetic resin
US6734552B2 (en) * 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US7015072B2 (en) * 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
US6936919B2 (en) * 2002-08-21 2005-08-30 Texas Instruments Incorporated Heatsink-substrate-spacer structure for an integrated-circuit package

Cited By (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US20100127363A1 (en) * 2006-04-28 2010-05-27 Utac Thai Limited Very extremely thin semiconductor package
US9099317B2 (en) 2006-04-28 2015-08-04 Utac Thai Limited Method for forming lead frame land grid array
US8704381B2 (en) 2006-04-28 2014-04-22 Utac Thai Limited Very extremely thin semiconductor package
US8685794B2 (en) 2006-04-28 2014-04-01 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8652879B2 (en) 2006-04-28 2014-02-18 Utac Thai Limited Lead frame ball grid array with traces under die
US8575762B2 (en) 2006-04-28 2013-11-05 Utac Thai Limited Very extremely thin semiconductor package
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US8125077B2 (en) 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US9093486B2 (en) 2006-12-14 2015-07-28 Utac Thai Limited Molded leadframe substrate semiconductor package
US9899208B2 (en) 2006-12-14 2018-02-20 Utac Thai Limited Molded leadframe substrate semiconductor package
US9099294B1 (en) 2006-12-14 2015-08-04 Utac Thai Limited Molded leadframe substrate semiconductor package
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9196470B1 (en) 2006-12-14 2015-11-24 Utac Thai Limited Molded leadframe substrate semiconductor package
US9711343B1 (en) 2006-12-14 2017-07-18 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US8338922B1 (en) 2007-11-06 2012-12-25 Utac Thai Limited Molded leadframe substrate semiconductor package
US8071426B2 (en) 2008-05-22 2011-12-06 Utac Thai Limited Method and apparatus for no lead semiconductor package
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US9947605B2 (en) 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US8263437B2 (en) * 2008-09-05 2012-09-11 STATS ChiPAC, Ltd. Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit
US9269598B2 (en) 2008-09-05 2016-02-23 Stats Chippac, Ltd. Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit
US20100059854A1 (en) * 2008-09-05 2010-03-11 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit
US8431443B2 (en) 2009-03-12 2013-04-30 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US8569877B2 (en) 2009-03-12 2013-10-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US8367476B2 (en) 2009-03-12 2013-02-05 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8722461B2 (en) 2010-03-11 2014-05-13 Utac Thai Limited Leadframe based multi terminal IC package
US8871571B2 (en) * 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US20110241189A1 (en) * 2010-04-02 2011-10-06 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9000590B2 (en) 2012-05-10 2015-04-07 Utac Thai Limited Protruding terminals with internal routing interconnections semiconductor device
US9922914B2 (en) 2012-05-10 2018-03-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9922913B2 (en) 2012-05-10 2018-03-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9972563B2 (en) 2012-05-10 2018-05-15 UTAC Headquarters Pte. Ltd. Plated terminals with routing interconnections semiconductor device
US9397031B2 (en) 2012-06-11 2016-07-19 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US20140077350A1 (en) * 2012-09-20 2014-03-20 Sony Corporation Semiconductor device, method for manufacturing semiconductor device, and electronic device
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
US10096490B2 (en) 2015-11-10 2018-10-09 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10325782B2 (en) 2015-11-10 2019-06-18 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10163658B2 (en) 2015-11-10 2018-12-25 UTAC Headquarters PTE, LTD. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9922843B1 (en) 2015-11-10 2018-03-20 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US9805955B1 (en) 2015-11-10 2017-10-31 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10734247B2 (en) 2015-11-10 2020-08-04 Utac Headquarters PTE. Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10032645B1 (en) 2015-11-10 2018-07-24 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US11328971B2 (en) * 2016-01-29 2022-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
US11355419B2 (en) * 2018-01-11 2022-06-07 Amosense Co., Ltd. Power semiconductor module
US20220028798A1 (en) * 2020-07-21 2022-01-27 UTAC Headquarters Pte. Ltd. Semiconductor packages with integrated shielding
US11901308B2 (en) * 2020-07-21 2024-02-13 UTAC Headquarters Pte. Ltd. Semiconductor packages with integrated shielding
US20230326878A1 (en) * 2020-12-23 2023-10-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same

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