US20060211237A1 - Method and apparatus for planarizing gap-filling material - Google Patents
Method and apparatus for planarizing gap-filling material Download PDFInfo
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- US20060211237A1 US20060211237A1 US11/085,295 US8529505A US2006211237A1 US 20060211237 A1 US20060211237 A1 US 20060211237A1 US 8529505 A US8529505 A US 8529505A US 2006211237 A1 US2006211237 A1 US 2006211237A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
Definitions
- the present invention relates to methods and apparatus for fabricating an integrated circuit device, and more particularly, to methods and apparatus for planarizing a gap-filling material during fabrication of an integrated circuit device.
- connection points between conductive wires and integrated circuit devices are referred to as contacts, and connection points between conductive wires are referred to as plugs.
- dual damascene processes can be divided into self-aligned dual damascene (SADD) processes, trench first dual damascene (TFDD) processes and via-first dual damascene (VFDD) processes.
- SADD self-aligned dual damascene
- TFDD trench first dual damascene
- VFDD via-first dual damascene
- the via lithography is done first on top of the full stack.
- the trench photo step is done.
- the via opening is filled by a gap-filling material such as organic material.
- the gap-filling material prevents the entrance of any residual positive photoresist material into the via opening, whereby the via plug resistance and RC de-lay would be increased.
- the trench photo step is much more challenging, due to the topography variations, since a variety of feature widths and pitches are possible, and achieving a uniform filling material with a smooth flat surface is difficult.
- FIG. 1A shows schematic view of a substrate 10 having conductive features/structures comprising isolated 12 I, semi-isolated 12 II, and dense features 12 III.
- a passivation layer 22 , a first dielectric layer 24 , an etching stop layer 26 , a second dielectric layer 28 , and a cap layer 30 are sequentially formed over the substrate 10 .
- a positive photoresist layer (not shown) is formed over the cap layer 30 . Photolithographic and etching processes of the positive photoresist layer are conducted to form via openings 40 by removal of a portion of the cap layer 30 , the dielectric layer 28 , the etching stop layer 26 and the dielectric layer 24 .
- the via openings 40 exposes a portion of the passivation layer 22 .
- a gap-filling material 50 is deposited over the substrate 10 , completely filling the via openings 40 . After via openings filling, a rough topography is presented resulting in the following trench photo step difficult.
- U.S. Pat. No. 6,589,881 discloses a gap-filling material deposited over a substrate, completely filling the via opening.
- a back-etching operation is conducted to remove excess gap-filling material outside the via opening.
- back-etching operation can induce rough topography from dense to isolated features over 1500 ⁇ , resulting in non-linear metal line, via blind, and Cu damage during etch step due to poor gap-filling material protecting in dense areas.
- Methods and an apparatus for planarizing a gap-filling material during fabrication of an integrated circuit are provided. Im-planarization is introduced to planarize a gap-filling material during fabrication.
- Embodiments of the invention provide an apparatus for planarizing a gap-filling material on a substrate, comprising a support for the substrate; a template positioned opposite the support with a substantially planar surface; and a controller controlling movements of the template which exert a downward force on the substrate.
- Embodiments of the invention provide an apparatus for forming an interconnection structure on a substrate, comprising: a coater to apply a gap-filling material on the substrate; an apparatus for planarizing the gap-filling material on a substrate; an edge-bevel-removal to remove the gap-filling material -at the edge of the substrate; and a spin-dry-rinse cleaner to clean the surface of planarized gap-filling material and back of the substrate.
- Embodiments of the invention provide a method for fabricating a damascene interconnection structure, comprising: providing a substrate with a dielectric layer thereon, the dielectric layer having at least one opening therein; disposing a gap-filling material on the substrate filling the opening; and planarizing the gap-filling material to create a substantially planarized surface.
- FIGS. 1A and 1B are cross-sections of filling a gap-fill material in a conventional via-first damascene process
- FIG. 2A is a schematic view of substrate disposed on an substrate support apparatus
- FIG. 2B is a schematic view of a coater and the substrate and the substrate support apparatus of FIG. 2A ;
- FIG. 2C is a schematic view showing a gap-filling material disposed on the substrate of FIG. 2B ;
- FIG. 3 is schematic view of an exemplary embodiment of a solid plane-template apparatus that planarizes a gap-filling material
- FIG. 4 is schematic view of an exemplary embodiment of an im-planar system
- FIGS. 5A-5I are cross sections of an embodiment of dual damascene interconnect lines during various stages of a fabrication process.
- a substrate 100 such single crystalline silicon wafer with a patterned dielectric layer thereon is provided.
- the substrate 100 is placed on a support 210 which can move upward and downward onto a base 230 by a shaft 220 .
- a load robot (not shown) to move in and move out the wafer on the support, but not limited if other methods such as vacuum arm for moving wafers.
- a coater 200 comprises a dispenser 250 injecting gap-filling material 260 onto the substrate 100 .
- the gap-filling is then cured at a glass transition temperature T g , as shown in FIG. 2C .
- Different materials have different glass transition temperature.
- organic or spin on Si-containing materials are applied for gap filling material.
- the gap-filling material 260 is applied by plane-template apparatus and coater simultaneously as shown in FIG. 4 .
- the gap-filling material 260 is applied by the plane-template apparatus and coater separately. Since the plug materials 260 become hardened and not easy for planarization, a heating plate 150 is needed for baking step on coater step as shown in FIG. 3 .
- the gap-filling material 260 can be dispensed and heated at T g simultaneously.
- FIG. 3 is schematic view of an exemplary embodiment of a solid plane-template apparatus 300 for planarizing a gap-filling material 260 .
- a solid plane-template apparatus 300 comprises a template 350 positioned opposing the substrate 100 with a substantially planar surface.
- the template 350 exerts a downward force F on the gap-filling material 260 providing a substantially planarized surface thereof.
- the material of the template comprises Ni, Si, or other materials which have poor adhesion with plug material.
- the template 350 has a low adhesion such contact angle>70 degree (i.e., more hydrophobic) to the gap-filling material 260 so that the gap-filling material does not adhere to the template 350 as the template 350 is being withdrawn from the gap-filling material 260 , thereby leaving a generally planarized surface.
- the contact angle between the template 350 and the gap-filling material 260 is in the range of about less than 70 degree (i.e., more hydrophobic).
- a heater 150 is provided to heat the substrate insitu during planarization or post annealing.
- a controller 310 connects to the solid plane-template apparatus 300 to control linear forward/backward and rotational movements of the template 350 .
- FIG. 4 is schematic view of an exemplary embodiment of an im-planar system for planarizing a gap-filling material.
- the im-planar system 400 generally includes a loadlock station 420 , a coater 430 , a solid plane-template apparatus 440 , and spin-rinse-dry (SRD) and edge bevel removal (EBR) chambers 450 .
- the im-planar system 400 connects to a controller 410 that typically includes a programmable microprocessor and renders control signal to the im-planar system 400 .
- the loadlock station 420 provides wafers port for storage FOUP or lot. Typically, there are 25 cps/per lot (or FOUP).
- FIGS. 5A through 5I are schematic cross-sectionals showing the steps for producing a dual damascene structure according to one embodiment of the invention.
- a substrate 500 having a conductive line 501 therein (to simplify the figure, devices within the substrate 500 are not drawn) is provided.
- a passivation layer 510 , a first dielectric layer 520 , an etching stop layer 530 , a second dielectric layer 540 and a cap layer 550 are sequentially formed over the substrate 500 .
- the passivation layer 510 and the etching stop layer 530 can be a silicon nitride layer formed, for example, by chemical vapor deposition (CVD).
- the first dielectric layer 520 and the second dielectric layer 540 can be a low dielectric constant (with a dielectric constant less than about 3.9) material including, for example, poly-arylene ether (SiLK), fluorinated poly-arylene ether (FLARE) and hydrogen silsesquioxane (HSQ).
- SiLK poly-arylene ether
- FLARE fluorinated poly-arylene ether
- HSQ hydrogen silsesquioxane
- the first dielectric layer 520 and the second dielectric layer 540 are formed, for example, by spin-coating or chemical vapor deposition.
- the cap layer 550 is made from a material capable of serving as an anti-reflection coating for the exposure of a photoresist layer such as silicon oxynitride (SiON).
- the cap layer 550 is formed by chemical vapor deposition, for example.
- a first photoresist layer 560 is formed over the cap layer 550 .
- the first photoresist layer 560 can be a positive photoresist layer or a negative photoresist layer.
- the first photoresist layer 560 is patterned to form a via opening pattern. Using the patterned first photoresist layer 560 as a mask, a portion of the cap layer 550 , the second dielectric layer 540 , the etch stop layer 530 , the first dielectric layer 520 are sequentially removed to form a via opening 570 exposing a portion of the etching stop layer 510 .
- the first photoresist layer 560 is completely removed.
- a gap-filling material 580 is applied over the cap layer 550 , filling the via opening 570 .
- a template 585 is pressed against the gap-filling material 580 .
- a force is applied to the template such that the template 585 planarizes the gap-filling material.
- a second photoresist 590 such as negative photoresist is formed and patterned on the planarized gap-filling material 580 .
- the patterned second photoresist comprises a trench 595 pattern therein.
- a portion of gap-filling material 580 is removed from the trench 595 to expose a portion of the stop etch layer 530 .
- the cap layer 550 and the second photoresist layer 590 are removed along with the remaining gap-filling material 580 ′. Removing the remaining gap-filling material 580 ′ exposes a portion of the etch stop layer 530 and a portion of the passivation layer 510 . The exposed etch stop layer 530 and passivation layer 510 are also removed, for example, by anisotropic etching.
- a conformal barrier layer 610 is formed over the exposed portion of the substrate 501 .
- the barrier layer 610 can be a tantalum nitride (TaN), a titanium nitride (TiN) or a titanium silicon nitride (TiSiN) layer, for example.
- the barrier layer 610 is disposed on the exposed portion of the substrate 501 and on the exposed portions of the passivation layer 510 , the first dielectric layer 520 , the etch stop layer 530 , and the second dielectric layer 540 .
- a conductive layer 620 is formed over the barrier layer 610 .
- the conductive layer 620 fills the remainder of the opening 570 and the trench 595 .
- the conductive layer 620 can be a copper layer formed, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD) or sputtering.
- a chemical-mechanical polishing (CMP) operation is conducted to remove the metallic layer 620 and the barrier layer 610 outside the trench exposing the second dielectric layer 540 .
- CMP chemical-mechanical polishing
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Abstract
A method an apparatus for fabricating an interconnection structure. A substrate is provided with a dielectric layer thereon. The dielectric layer comprises at least one opening therein. A gap-filling material is applied on the substrate filling the at least one opening. The gap-filling material is planarized using a template to create a substantially planarized surface.
Description
- The present invention relates to methods and apparatus for fabricating an integrated circuit device, and more particularly, to methods and apparatus for planarizing a gap-filling material during fabrication of an integrated circuit device.
- In semiconductor fabrication, various devices are interconnected by conductive lines and plugs. In general, connection points between conductive wires and integrated circuit devices are referred to as contacts, and connection points between conductive wires are referred to as plugs.
- Typically, dual damascene processes can be divided into self-aligned dual damascene (SADD) processes, trench first dual damascene (TFDD) processes and via-first dual damascene (VFDD) processes. In the via-first dual damascene (VFDD), the via lithography is done first on top of the full stack. After via etching and stripping, the trench photo step is done. In some cases, the via opening is filled by a gap-filling material such as organic material. The gap-filling material prevents the entrance of any residual positive photoresist material into the via opening, whereby the via plug resistance and RC de-lay would be increased. The trench photo step, however, is much more challenging, due to the topography variations, since a variety of feature widths and pitches are possible, and achieving a uniform filling material with a smooth flat surface is difficult.
-
FIG. 1A shows schematic view of asubstrate 10 having conductive features/structures comprising isolated 12I, semi-isolated 12II, and dense features 12III. Apassivation layer 22, a firstdielectric layer 24, anetching stop layer 26, a seconddielectric layer 28, and acap layer 30 are sequentially formed over thesubstrate 10. A positive photoresist layer (not shown) is formed over thecap layer 30. Photolithographic and etching processes of the positive photoresist layer are conducted to form viaopenings 40 by removal of a portion of thecap layer 30, thedielectric layer 28, theetching stop layer 26 and thedielectric layer 24. Thevia openings 40 exposes a portion of thepassivation layer 22. - Referring
FIG. 1B , a gap-fillingmaterial 50 is deposited over thesubstrate 10, completely filling thevia openings 40. After via openings filling, a rough topography is presented resulting in the following trench photo step difficult. - U.S. Pat. No. 6,589,881 (Huang et. al.), the entirety of which is hereby incorporated by reference, discloses a gap-filling material deposited over a substrate, completely filling the via opening. A back-etching operation is conducted to remove excess gap-filling material outside the via opening. However, back-etching operation can induce rough topography from dense to isolated features over 1500 Å, resulting in non-linear metal line, via blind, and Cu damage during etch step due to poor gap-filling material protecting in dense areas.
- U.S. Pat. No. 6,680,252 (Chen et. al.), the entirety of which is hereby incorporated by reference, discloses a gap-filling material deposited over a substrate and planarized by chemical mechanical polishing (CMP). However, chemical slurry can damage the low-k dielectric layer and the CMP process is time consuming and tedious leading to high production cost and low throughput.
- Methods and an apparatus for planarizing a gap-filling material during fabrication of an integrated circuit are provided. Im-planarization is introduced to planarize a gap-filling material during fabrication.
- Embodiments of the invention provide an apparatus for planarizing a gap-filling material on a substrate, comprising a support for the substrate; a template positioned opposite the support with a substantially planar surface; and a controller controlling movements of the template which exert a downward force on the substrate.
- Embodiments of the invention provide an apparatus for forming an interconnection structure on a substrate, comprising: a coater to apply a gap-filling material on the substrate; an apparatus for planarizing the gap-filling material on a substrate; an edge-bevel-removal to remove the gap-filling material -at the edge of the substrate; and a spin-dry-rinse cleaner to clean the surface of planarized gap-filling material and back of the substrate.
- Embodiments of the invention provide a method for fabricating a damascene interconnection structure, comprising: providing a substrate with a dielectric layer thereon, the dielectric layer having at least one opening therein; disposing a gap-filling material on the substrate filling the opening; and planarizing the gap-filling material to create a substantially planarized surface.
- Methods and apparatus for planarizing a gap-filling material will become more fully understood from the description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
-
FIGS. 1A and 1B are cross-sections of filling a gap-fill material in a conventional via-first damascene process; -
FIG. 2A is a schematic view of substrate disposed on an substrate support apparatus; -
FIG. 2B is a schematic view of a coater and the substrate and the substrate support apparatus ofFIG. 2A ; -
FIG. 2C is a schematic view showing a gap-filling material disposed on the substrate ofFIG. 2B ; -
FIG. 3 is schematic view of an exemplary embodiment of a solid plane-template apparatus that planarizes a gap-filling material; -
FIG. 4 is schematic view of an exemplary embodiment of an im-planar system; -
FIGS. 5A-5I are cross sections of an embodiment of dual damascene interconnect lines during various stages of a fabrication process. - Methods and apparatus for planarizing a gap-filling material are provided. Embodiments of methods of fabricating dual damascene interconnect lines is described in greater detail by referring to the drawings that accompany the invention. It is noted that in the accompanying drawings, like and/or corresponding elements are referred to by like reference numerals.
- Referring to 2A, a
substrate 100 such single crystalline silicon wafer with a patterned dielectric layer thereon is provided. Thesubstrate 100 is placed on asupport 210 which can move upward and downward onto abase 230 by ashaft 220. According to various embodiments of the invention, it is easy for a load robot (not shown) to move in and move out the wafer on the support, but not limited if other methods such as vacuum arm for moving wafers. - Referring to
FIG. 2B , acoater 200 comprises adispenser 250 injecting gap-fillingmaterial 260 onto thesubstrate 100. The gap-filling is then cured at a glass transition temperature Tg, as shown inFIG. 2C . Different materials have different glass transition temperature. Generally, organic or spin on Si-containing materials are applied for gap filling material. The gap-fillingmaterial 260 is applied by plane-template apparatus and coater simultaneously as shown inFIG. 4 . Alternatively, the gap-fillingmaterial 260 is applied by the plane-template apparatus and coater separately. Since theplug materials 260 become hardened and not easy for planarization, aheating plate 150 is needed for baking step on coater step as shown inFIG. 3 . - Alternatively, the gap-filling
material 260 can be dispensed and heated at Tg simultaneously. -
FIG. 3 is schematic view of an exemplary embodiment of a solid plane-template apparatus 300 for planarizing a gap-fillingmaterial 260. A solid plane-template apparatus 300 comprises atemplate 350 positioned opposing thesubstrate 100 with a substantially planar surface. Thetemplate 350 exerts a downward force F on the gap-fillingmaterial 260 providing a substantially planarized surface thereof. - The material of the template comprises Ni, Si, or other materials which have poor adhesion with plug material. In some embodiments, the
template 350 has a low adhesion such contact angle>70 degree (i.e., more hydrophobic) to the gap-fillingmaterial 260 so that the gap-filling material does not adhere to thetemplate 350 as thetemplate 350 is being withdrawn from the gap-fillingmaterial 260, thereby leaving a generally planarized surface. Typically, the contact angle between thetemplate 350 and the gap-fillingmaterial 260 is in the range of about less than 70 degree (i.e., more hydrophobic). - A
heater 150 is provided to heat the substrate insitu during planarization or post annealing. Acontroller 310 connects to the solid plane-template apparatus 300 to control linear forward/backward and rotational movements of thetemplate 350. -
FIG. 4 is schematic view of an exemplary embodiment of an im-planar system for planarizing a gap-filling material. InFIG. 4 , the im-planar system 400 generally includes aloadlock station 420, acoater 430, a solid plane-template apparatus 440, and spin-rinse-dry (SRD) and edge bevel removal (EBR)chambers 450. The im-planar system 400 connects to acontroller 410 that typically includes a programmable microprocessor and renders control signal to the im-planar system 400. Theloadlock station 420 provides wafers port for storage FOUP or lot. Typically, there are 25 cps/per lot (or FOUP). -
FIGS. 5A through 5I are schematic cross-sectionals showing the steps for producing a dual damascene structure according to one embodiment of the invention. Referring toFIG. 5A , asubstrate 500 having aconductive line 501 therein (to simplify the figure, devices within thesubstrate 500 are not drawn) is provided. Apassivation layer 510, a firstdielectric layer 520, anetching stop layer 530, asecond dielectric layer 540 and acap layer 550 are sequentially formed over thesubstrate 500. - The
passivation layer 510 and theetching stop layer 530 can be a silicon nitride layer formed, for example, by chemical vapor deposition (CVD). Thefirst dielectric layer 520 and thesecond dielectric layer 540 can be a low dielectric constant (with a dielectric constant less than about 3.9) material including, for example, poly-arylene ether (SiLK), fluorinated poly-arylene ether (FLARE) and hydrogen silsesquioxane (HSQ). Thefirst dielectric layer 520 and thesecond dielectric layer 540 are formed, for example, by spin-coating or chemical vapor deposition. - The
cap layer 550 is made from a material capable of serving as an anti-reflection coating for the exposure of a photoresist layer such as silicon oxynitride (SiON). Thecap layer 550 is formed by chemical vapor deposition, for example. - A
first photoresist layer 560 is formed over thecap layer 550. Thefirst photoresist layer 560 can be a positive photoresist layer or a negative photoresist layer. Thefirst photoresist layer 560 is patterned to form a via opening pattern. Using the patternedfirst photoresist layer 560 as a mask, a portion of thecap layer 550, thesecond dielectric layer 540, theetch stop layer 530, thefirst dielectric layer 520 are sequentially removed to form a viaopening 570 exposing a portion of theetching stop layer 510. - Referring to
FIG. 5B , thefirst photoresist layer 560 is completely removed. A gap-fillingmaterial 580 is applied over thecap layer 550, filling the viaopening 570. - Referring to
FIG. 5C , atemplate 585 is pressed against the gap-fillingmaterial 580. A force is applied to the template such that thetemplate 585 planarizes the gap-filling material. - Referring to
FIG. 5D , asecond photoresist 590 such as negative photoresist is formed and patterned on the planarized gap-fillingmaterial 580. The patterned second photoresist comprises atrench 595 pattern therein. - Referring to
FIG. 5E , using thesecond photoresist layer 590 as a mask, a portion of gap-fillingmaterial 580 is removed from thetrench 595 to expose a portion of thestop etch layer 530. The portion of the gap-fillingmaterial 580′ which remains fills the viaopening 570. - Referring to
FIG. 5F , thecap layer 550 and thesecond photoresist layer 590 are removed along with the remaining gap-fillingmaterial 580′. Removing the remaining gap-fillingmaterial 580′ exposes a portion of theetch stop layer 530 and a portion of thepassivation layer 510. The exposedetch stop layer 530 andpassivation layer 510 are also removed, for example, by anisotropic etching. - Referring to
FIG. 5G , aconformal barrier layer 610 is formed over the exposed portion of thesubstrate 501. Thebarrier layer 610 can be a tantalum nitride (TaN), a titanium nitride (TiN) or a titanium silicon nitride (TiSiN) layer, for example. Thebarrier layer 610 is disposed on the exposed portion of thesubstrate 501 and on the exposed portions of thepassivation layer 510, thefirst dielectric layer 520, theetch stop layer 530, and thesecond dielectric layer 540. - Referring to
FIG. 5H , Aconductive layer 620 is formed over thebarrier layer 610. Theconductive layer 620 fills the remainder of theopening 570 and thetrench 595. Theconductive layer 620 can be a copper layer formed, for example, by physical vapor deposition (PVD), chemical vapor deposition (CVD) or sputtering. - Referring to
FIG. 5I , a chemical-mechanical polishing (CMP) operation is conducted to remove themetallic layer 620 and thebarrier layer 610 outside the trench exposing thesecond dielectric layer 540. Thus, adual damascene structure 600 is formed. - While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (18)
1. An apparatus for planarizing a gap-filling material on a substrate, comprising:
a support for the substrate;
a template positioned opposite the support, the template having a substantially planar surface; and
a controller controlling relative movements of the template which exert a force on the substrate.
2. The apparatus according to claim 1 , wherein the material of the template comprises Ni, or Si.
3. The apparatus according to claim 1 , wherein the material of the template comprises a material has a contact angle greater than 70 degree to the gap-filling material.
4. The apparatus according to claim 1 , further comprising a heater for heating the substrate.
5. The apparatus according to claim 1 , wherein the controller controls rotational movement of the template.
6. An apparatus for forming an interconnection structure on a substrate, comprising:
a coater to apply a gap-filling material on the substrate;
an edge-bevel-removal to remove the gap-filling material at the edge of the substrate; and
a spin-dry-rinse cleaner to clean the surface of planarized gap-filling material and back of the substrate;
a support for the substrate;
a template positioned opposite the support, the template having a substantially planar surface; and
a controller controlling relative movements of the template which exert a force on the substrate.
7. The apparatus according to claim 6 , further comprising a heater for heating the substrate.
8. A method for fabricating an integrated circuit device, comprising:
providing a substrate with a dielectric layer thereon, the dielectric layer having an opening therein;
disposing a gap-filling material on the substrate filling the opening; and
pressing a template against the gap-filling material to create a substantially planarized surface.
9. The method according to claim 8 , wherein the integrated circuit device comprises a dual-damascene interconnection.
10. The method according to claim 8 , wherein the gap-filling material comprises an organic spin-on polymer or spin-on Si containing materials.
11. The method according to claim 8 , wherein the template material comprises Ni or Si.
12. The method according to claim 8 , wherein the template material comprises a material has a contact angle greater than 70 degree to the gap-filling material.
13. The method according to claim 8 , wherein the template a low coefficient of adhesion to the gap-filling material.
14. The method according to claim 8 , further comprising baking the gap-filling material at a temperature equal to or exceeding glass transition temperature Tg for gap-filling materials selected from the group spin on organic and spin on Si containing materials.
15. The method according to claim 8 , further comprising applying a force on the substrate.
16. The method according to claim 15 , wherein the force accompanies a rotating force.
17. The method according to claim 8 , further comprising performing edge bevel removal (EBR) and spin-rinse-dry (SRD) on the substrate.
18. The method according to claim 8 , further comprising:
forming a patterned photoresist on the planarized gap-filling material with a trench pattern therein;
etching the dielectric layer to form a trench corresponding the opening using the patterned photoresist as a mask;
forming conductive layer filling in the trench and the opening.
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Cited By (2)
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US20080003826A1 (en) * | 2006-06-30 | 2008-01-03 | Thomas Werner | Method for increasing the planarity of a surface topography in a microstructure |
US8946782B2 (en) | 2012-04-19 | 2015-02-03 | International Business Machines Corporation | Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric |
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US20020164875A1 (en) * | 2001-05-04 | 2002-11-07 | Leong Lup San | Thermal mechanical planarization in integrated circuits |
US6589881B2 (en) * | 2001-11-27 | 2003-07-08 | United Microelectronics Corp. | Method of forming dual damascene structure |
US6680252B2 (en) * | 2001-05-15 | 2004-01-20 | United Microelectronics Corp. | Method for planarizing barc layer in dual damascene process |
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US5679610A (en) | 1994-12-15 | 1997-10-21 | Kabushiki Kaisha Toshiba | Method of planarizing a semiconductor workpiece surface |
JP3676030B2 (en) * | 1997-04-10 | 2005-07-27 | 株式会社東芝 | Polishing pad dressing method and semiconductor device manufacturing method |
US6516815B1 (en) | 1999-07-09 | 2003-02-11 | Applied Materials, Inc. | Edge bead removal/spin rinse dry (EBR/SRD) module |
JP3927768B2 (en) | 2000-11-17 | 2007-06-13 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
JP3494435B2 (en) * | 2001-02-27 | 2004-02-09 | 東京エレクトロン株式会社 | Substrate processing equipment |
JP2003142427A (en) * | 2001-11-06 | 2003-05-16 | Ebara Corp | Plating solution, semiconductor device, and its manufacturing method |
US6666749B2 (en) * | 2001-08-30 | 2003-12-23 | Micron Technology, Inc. | Apparatus and method for enhanced processing of microelectronic workpieces |
US7105446B2 (en) * | 2003-09-04 | 2006-09-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus for pre-conditioning CMP polishing pad |
JP2006013107A (en) * | 2004-06-25 | 2006-01-12 | Dainippon Screen Mfg Co Ltd | Substrate processing apparatus |
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- 2005-08-25 CN CNA2005100930393A patent/CN1838399A/en active Pending
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2007
- 2007-10-30 US US11/927,779 patent/US8132503B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020164875A1 (en) * | 2001-05-04 | 2002-11-07 | Leong Lup San | Thermal mechanical planarization in integrated circuits |
US6680252B2 (en) * | 2001-05-15 | 2004-01-20 | United Microelectronics Corp. | Method for planarizing barc layer in dual damascene process |
US6589881B2 (en) * | 2001-11-27 | 2003-07-08 | United Microelectronics Corp. | Method of forming dual damascene structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20080003826A1 (en) * | 2006-06-30 | 2008-01-03 | Thomas Werner | Method for increasing the planarity of a surface topography in a microstructure |
US8946782B2 (en) | 2012-04-19 | 2015-02-03 | International Business Machines Corporation | Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric |
US9087916B2 (en) | 2012-04-19 | 2015-07-21 | International Business Machines Corporation | Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric |
Also Published As
Publication number | Publication date |
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CN1838399A (en) | 2006-09-27 |
US8132503B2 (en) | 2012-03-13 |
US20080060534A1 (en) | 2008-03-13 |
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