US20060115035A1 - Clock and data recovery apparatus and method thereof - Google Patents
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- US20060115035A1 US20060115035A1 US11/126,452 US12645205A US2006115035A1 US 20060115035 A1 US20060115035 A1 US 20060115035A1 US 12645205 A US12645205 A US 12645205A US 2006115035 A1 US2006115035 A1 US 2006115035A1
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- 238000011084 recovery Methods 0.000 title claims abstract description 19
- 238000005070 sampling Methods 0.000 claims description 49
- 238000001514 detection method Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 abstract description 3
- 230000010363 phase shift Effects 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
Definitions
- the invention relates to a clock and data recovery apparatus and the method thereof, and more particularly to a clock and data recovery apparatus for burst mode clock and data recovery in a passive optical network.
- a transmitter continuous sends digital signals to a receiver. That is, each bit is transmitted within a fixed time. Therefore, the receiver uses a clock and data recovery (CDR) apparatus to generate a clock corresponding to the incoming data, thereby correctly retiming the incoming data. How to make a clock frequency exactly corresponding to a frequency of the incoming data is a very important issue.
- CDR clock and data recovery
- a conventional clock and data recovery apparatus includes a clock and data recovery circuit 110 and a phase-locked loop (PLL) 120 .
- the PLL 120 generates a system clock Sys CK according to a reference clock Ref CK, and imposes a voltage signal Sv to the clock and data recovery circuit 110 .
- the clock and data recovery circuit 110 generates a recovered clock CKr with an output frequency corresponding to the voltage signal Sv.
- the received data DATA are sampled by the recovered clock CKr as data DATAr.
- the frequency of the conventional CDR may be affected by process variation. Therefore, the output frequency from of CDR is not exactly equal to the data frequency fd, as shown in FIG. 2 (fnom ⁇ fd on the frequency axis). This frequency mismatch will result in a phase shift in each sampling. If the input data are consecutive identical bits, then the phase shifts will accumulate because of the lack of data transitions. In the end, the maximum allowable number of consecutive identical bits to be transmitted has to be restricted. Consequently, the bit error rate (BER) becomes worse when the input stream contains longer consecutive identical bits.
- BER bit error rate
- an objective of the invention is to provide a clock and data recovery (CDR) apparatus and the method thereof to solve the many restrictions and drawbacks existing in the prior art.
- the disclosed invention is to provide a CDR apparatus and the method thereof to solve the problem that the CDR circuit cannot accurately recover the clock signal of the data rate.
- the disclosed invention is to provide a CDR apparatus and the method thereof to be applied in a passive optical network (PON).
- PON passive optical network
- the disclosed invention is to provide a CDR apparatus and the method thereof to selectively generate two recovered clocks with different frequencies.
- the disclosed invention is to provide a CDR apparatus and the method thereof to adjust the frequency of the recovered clock using a controller.
- the disclosed CDR apparatus and the method thereof achieve at least an improved effect, which includes solving the restriction in maximum run length of the incoming data, increasing the high-frequency jitter tolerance, and improving the output jitter contributed by frequency mismatch.
- a CDR apparatus of the invention includes: a phase-locked circuit, a CDR circuit, and a controller, wherein all components connect with each other.
- the phase-locked circuit generates a first control signal and a first clock having a plurality of phases
- the CDR circuit receives an incoming data and generates a second clock according to the first control signal to sample the incoming data based on the second clock.
- the controller generates a second control signal according to the incoming data (or the recovered data), the first clock and the second clock to adjust the frequency of the second clock.
- the incoming data (or the recovered data) have a first frequency
- the frequency of the second clock is one of a second frequency and a third frequency.
- the first frequency is between the second and third frequencies.
- the controller includes: two or more flip-flops, a detector, a latch circuit, and a digital signal processing circuit.
- Each of the flip-flops is connected via the latch circuit to the digital signal processing circuit.
- the detector, the latch circuit, and the digital signal processing circuit are connected in series.
- the first clock has several phases.
- the first clock of each phase is outputted to each of the flip-flops, which samples the first clock based to the second clock to generate a first signal.
- the detector detects the bit edges of the incoming data (or the recovered data) and outputs an enable signal according to the detected result.
- the latch circuit outputs a second signal corresponding to the first signal from the flip-flops in response to the enable signal. Afterward the digital signal processing circuit generates a second control signal based on the second signal and the first signal from the flip-flops.
- the digital signal processing circuit includes: a multiplexer, at least four state maintaining processors, and a sum circuit.
- the multiplexer is connected to the sum circuit via each the state maintaining processors.
- the multiplexer outputs the first signal from each flip-flop into one of the state maintaining processors, which is corresponding to the second signal, according to the second signal.
- Each of the state maintaining processor generates a third control signal based on the state of receiving the first signal, and the sum circuit adds the third control signals from all the sate maintaining processors up to generate a second control signal.
- each of the state maintaining processors connects with the sum circuit via the multiplexer.
- each of the state maintaining processors receives the first signals from all the flip-flops and generates a third control signal based on the first signals.
- the multiplexer outputs the third control signals based on the second signal from the latch circuit.
- the sum circuit adds the third control signals from the multiplexer up to generate the second control signal.
- the invention discloses a clock and data recovery method including the steps of: receiving an incoming data with a first frequency; generating a second clock with a second frequency and sampling the incoming data based on the second clock; forming a sampling region based on a first clock with multiple phases; switching a frequency of the second clock from the second frequency to a third frequency when a sampling point of the incoming data is about to go beyond one edge of the sampling region; switching the frequency of the second clock from the third frequency back to the second frequency when the sampling point is about to go beyond another edge of the sampling region; and repeating the above two steps until sampling the incoming data is accomplished.
- the first frequency is between the second and the third frequencies.
- FIG. 1 shows the system structure of a conventional CDR apparatus
- FIG. 2 is a schematic view of the frequency error generated by the CDR apparatus in FIG. 1 ;
- FIG. 3 is a schematic view of the frequency error generated a clock and data recovery (CDR) apparatus according to the present invention
- FIG. 4 shows the system structure of the CDR apparatus according to an embodiment of the invention
- FIG. 5 shows the system structure of an embodiment of the CDR circuit in FIG. 4 ;
- FIG. 6 shows the system structure of an embodiment of the phase-locked circuit in FIG. 4 ;
- FIG. 7 shows the system structure of a first embodiment of the controller in FIG. 4 ;
- FIG. 8 shows the system structure of an embodiment of the digital signal processing circuit in FIG. 7 ;
- FIG. 9 shows the system structure of a second embodiment of the controller in FIG. 4 ;
- FIG. 10 shows the system structure of another embodiment of the digital signal processing circuit in FIG. 7 ;
- FIG. 11 shows the system structure of a third embodiment of the controller in FIG. 4 ;
- FIG. 12 shows how the CDR apparatus in an embodiment of the invention executes
- FIG. 13 shows the state diagram of the controller according to an embodiment of the invention in the state of FIG. 12 ;
- FIG. 14 shows the system structure of the CDR apparatus according to another embodiment of the invention.
- the invention uses a second and a third frequency (fnom ⁇ fbb) in the vicinity of the first frequency (fd) to correctly simulate the first frequency.
- the invention utilizes two major techniques.
- the oscillator in the CDR circuit can provide two frequencies (fnom ⁇ fbb).
- a controller is used to control the switch between the two frequencies (fnom ⁇ fbb) in order to obtain an output frequency almost equal to the first frequency fd.
- the first frequency is a frequency of an incoming data or a recovered data generated previously.
- the system includes: a CDR circuit 210 , a phase-locked circuit 220 , and a controller 230 .
- the CDR circuit 210 , the phase-locked circuit 220 , and the controller 230 connect with each other.
- the phase-locked circuit 220 When the CDR circuit 210 receives an incoming data DATA, the phase-locked circuit 220 generates a first control signal C 1 based on a reference signal SR for the CDR circuit 210 and a first clock CK 1 for the controller 230 .
- the CDR circuit 210 generates a second clock CK 2 according to the first control signal C 1 and samples the incoming data DATA based on the second clock CK 2 to obtain a recovered data DATAr.
- the controller 230 generates a second control signal C 2 according to the incoming data DATA, the first clock CK 1 and the second clock CK 2 , and the CDR circuit 210 adjust the frequency of the second clock CK 2 according to the second control signal C 2 .
- the incoming data DATA received by the CDR circuit 210 has a first frequency.
- the CDR circuit 210 generates one of two second clocks CK 2 with a second frequency and a third frequency respectively.
- the second control signal C 2 from the controller 230 is used to switch the second clock CK 2 , which is outputted by the CDR circuit 210 between the second and third frequencies.
- the first frequency is between the second and third frequencies.
- the relationship between the signal frequency (i.e. the first frequency) of the incoming data DATA and the signal frequency of the reference signal SR is a positive integer multiple.
- the signal frequency of the incoming data DATA is the positive integer multiple of the signal frequency of the reference signal SR.
- the signal frequency of the incoming data DATA is substantially the same as the signal frequency of the first clock CK 1 .
- the first clock CK 1 is a system clock.
- the CDR circuit 210 includes a gating control circuit 212 , a first gated voltage controller oscillator (GVCO) 214 , and a decision circuit 216 .
- GVCO gated voltage controller oscillator
- the gating control circuit 212 , the first GVCO 214 , and the decision circuit 216 are connected in series.
- the gating control circuit 212 provides the edge information for the first GVCO 214 .
- the first GVCO 214 generates a second clock CK 2 corresponding and synchronized with the incoming data DATA according to the first control signal C 1 from the PLL (not shown).
- the second clock CK 2 is provided for the decision circuit 216 and the controller 230 by the first GVCO 214 .
- the decision circuit 216 samples the incoming data DATA based on the second clock CK 2 to generate a recovered data DATAr.
- the first GVCO 214 produces the second clock CK 2 with the second frequency or with the third frequency depending on the second control signal C 2 provided by the controller.
- the phase-locked circuit is a PLL.
- the PLL 220 includes in sequence a phase-frequency detector (PFD) 221 , a charge pump (CP) 222 , a loop filter (LF) 223 , a second GVCO 224 , and a frequency divider 225 , in where they are connected in series into a loop, as shown in FIG. 6 .
- the PFD 221 compares the phase difference between a feedback signal Sf and a reference signal SR and outputs a phase difference signal accordingly.
- the CP 222 and the LF 223 is implemented according to the phase difference signal from the PFD 221 in order, and a first control signal C 1 is outputted.
- the first control signal C 1 is a voltage signal and its magnitude is related to the magnitude of the phase difference between the feedback signal Sf acquired by the first clock CK 1 whose frequency is divided and the reference signal SR.
- the second GVCO 224 outputs the first clock CK 1 according to the first control signal C 1 .
- the first clock CK 1 is divided by the frequency divider 225 to render a feedback signal Sf, and the feedback signal Sf is supplied for the PFD 221 .
- the phases of the feedback signal Sf and the reference signal SR are different, and therefore the PFD 221 generates a phase difference signal accordingly.
- the controller as shown in FIG. 7 contains at least two flip-flops 232 (i.e. 232 - 1 , 232 - 2 , etc), a detector 234 , a latch circuit 236 , and a digital signal processing circuit 238 .
- Each of the flip-flops 232 is connected to the latch circuit 236 and the digital signal processing circuit 238 .
- the detector 234 , the latch circuit 236 , and the digital signal processing circuit 238 are connected in series.
- the first clock CK 1 has several phases, i.e. CK 1 - 1 , CK 1 - 2 , etc.
- the first clock CK 1 with each of the phases and the second clock CK 2 are outputted into each of flip-flops 232 .
- Each of the flip-flops 232 samples the first clock CK 1 using the second clock CK 2 to generate one of first signals S 1 (i.e. S 1 - 1 or S 1 - 2 , etc).
- Each of the first signals S 1 is a “1” or a “0.”
- the detector 234 detects the bit edges of the incoming data DATA to obtain a detection result, according to which an enable signal ES is outputted. Once an edge is detected, the outputted enable signal ES is a pulse signal; otherwise, no pulse is outputted.
- the latch circuit 236 receives the enable signal ES outputted by the detector 234 and the first signals S 1 outputted by the flip-flops 232 . When the received enable signal ES appears, a second signal S 2 is outputted into the digital signal processing circuit 238 . Herein the latch circuit 236 outputs all the received first signals S 1 to generate the second signal S 2 when the enable signal ES appears.
- the digital signal processing circuit 238 receives the first signals S 1 from the flip-flops 232 and outputs a second control signal C 2 corresponding to the received first signals S 1 according to the second signal S 2 .
- the digital signal processing circuit 238 as shown in FIG. 8 contains a multiplexer 240 , at least four state maintaining processors 242 ( 242 - 1 , 242 - 2 , 242 - 3 , 242 - 4 , etc), and a sum circuit 244 .
- the multiplexer 240 is connected to the sum circuit 244 via the state maintaining processors 242 .
- the multiplexer 240 receives the first signals S 1 from all the flip-flops 232 and selectively transmits the first signal S 1 to one of the state maintaining processors 242 corresponding to the second signal S 2 .
- Each of the state maintaining processors 242 generates one of third control signals C 3 (C 3 - 1 , C 3 - 2 , C 3 - 3 , C 3 - 4 , etc) according to the state of received signal.
- the sum circuit 244 adds all the third control signals C 3 up to output a second control signal C 2 .
- the number of the state maintaining processors is twice that of the flip-flops in order to process the first signals outputted by the multiplexer.
- the first clock CK 1 is a plurality of single-ended signals each of which represents a phase or a plurality of differential signals each of which represents two phases
- the second clock CK 2 is a single-ended signal or a differential signal.
- the first clock CK 1 has eight different phases.
- the first clock CK 1 is the differential signals CK 1 - 1 , CK 1 - 2 , CK 1 - 3 and CK 1 - 4 each of which represents two phases
- the first clock CK 1 - 1 represents a phase which is 0 degree accompanying another phase which is 180 degrees
- the first clock CK 1 - 2 represents a phase which is 45 degrees accompanying another phase which is 225 degrees
- the first clock CK 1 - 3 represents a phase which is 90 degrees accompanying another phase which is 270 degrees
- the first clock CK 1 - 4 represents a phase which is 135 degrees accompanying another phase which is 315 degrees.
- the first clock CK 1 is the single-ended signals CK 1 - 1 , CK 1 - 2 , CK 1 - 3 , and CK 1 - 4 each of which represents one phase
- the first clock CK 1 - 1 represents a phase which is 0 degree
- the first clock CK 1 - 2 represents a phase which is 45 degrees
- the first clock CK 1 - 3 represents a phase which is 90 degrees
- the first clock CK 1 - 4 represents a phase which is 135 degrees.
- the first clock CK 1 - 1 and the second clock CK 2 are outputted into a flip-flop 232 - 1 , so that the flip-flop 232 - 1 generates a first signal S 1 - 1 corresponding to the first clock CK 1 - 1 according to the second clock CK 2 .
- the first signal S 1 - 1 is a digital signal of “1” or “0.”
- the flip-flops 232 - 2 , 232 - 3 , 2324 generate respectively a first signal S 1 - 2 corresponding to the first clock CK 1 - 2 , a first signal S 1 - 3 corresponding to the first clock CK 1 - 3 and a first signal S 1 - 4 corresponding to the first clock CK 1 - 4 according to the second clock CK 2 .
- the detector 234 When the detector 234 detects the transition of the incoming data DATA, it outputs an enable signal ES with a pulse signal.
- the latch circuit 236 receives the first signals S 1 - 1 ⁇ S 1 - 4 from the flip-flops 232 - 1 ⁇ 232 - 4 and outputs a second signal S 2 corresponding to the first signals S 1 - 1 ⁇ S 1 - 4 into the multiplexer 240 .
- the outputted second signal S 2 is a digital signal of “0011.”
- the multiplexer 240 has eight 4-bit logic signal channels (e.g. 0000, 0001, 0011, 0111, 1111, 1110, 1100, and 1000). Each channel is connected to one of the state maintaining processors 242 for processing one state of the logic signals.
- the multiplexer 240 When the multiplexer 240 receives the second signal S 2 , it outputs the first signals S 1 - 1 ⁇ S 1 - 4 to the associated state maintaining processor via the channel corresponding to the second signal S 2 . Each of the state maintaining processors 242 generates a third control signal C 3 according to the state of the received signal. The sum circuit 244 adds all the third control signals C 3 up to output a second control signal C 2 , thereby controlling the first GVCO to switch the frequency of the generated second clock.
- the state maintaining processors 242 - 1 ⁇ 242 - 8 are used to process the signals 0000 , 0001 , 0011 , 0111 , 1111 , 1110 , 1100 , and 1000 , respectively. Therefore, when the multiplexer 240 receives the second signal S 2 of “0011”, the multiplexer 240 output the first signal S 1 - 1 ⁇ S 1 - 4 into the associated state maintaining processor 242 - 3 via the channel of “0011”.
- the state maintaining processor 242 - 3 follows the states of the first signal S 1 - 1 ⁇ S 1 - 4 to output a third control signal C 3 - 3 of “1” or “0,” otherwise other state maintaining processors output the third control signals of “0.”
- the sum circuit 244 adds all the third control signals C 3 up to output a second control signal C 2 , thereby switching the output frequency of the second clock.
- the digital signal processing circuit 238 as shown in FIG. 10 includes a multiplexer 240 , at least four state maintaining processors 242 (i.e. 242 - 1 , 242 - 2 , 242 - 3 , 242 - 4 ) and a sum circuit 244 .
- Each of the state maintaining processors 242 is connected to the sum circuit 244 via the multiplexer 240 .
- each of the state maintaining processors 242 receives the first signals S 1 from all the flip-flops and generates a third control signal C 3 - 1 , C 3 - 2 , C 3 - 3 , or C 3 - 4 , etc based on the first signals S 1 . Then, the multiplexer 240 outputs the third control signals C 3 - 1 , C 3 - 2 , C 3 - 3 , or C 3 - 4 , etc based on the second signal S 2 from the latch circuit. Afterward, the sum circuit 244 adds the third control signals C 3 - 1 , C 3 - 2 , C 3 - 3 , C 3 - 4 , etc from the multiplexer 240 up to generate the second control signal C 2 .
- the first clock CK 1 generated by the phase-locked circuit has different phases I-Phase and Q-phase (differing by 90 degrees). If the first clock CK 1 has two single-ended signals (CK 1 - 1 , CK 1 - 2 ), then the first clock CK 1 - 1 represents a phase 0 degree, i.e. I-Phase, and the first clock CK 1 - 2 represents a phase 90 degrees, i.e. Q-phase. If the first clock CK 1 contains two differential signals (CK 1 - 1 , CK 1 - 2 ), then the first clock CK 1 - 1 represents the phases 0 degree along with 180 degrees, i.e. I-Phase, and the first clock CK 1 - 2 represents phases 90 degrees along with 270 degrees, i.e. Q-phase.
- composition of the controller is shown in FIG. 11 . Since the operations of components are substantially similar as those in FIG. 9 , we do not repeat their descriptions.
- the CDR circuit samples it based on the second clock CK 2 to obtain recovered data (not shown).
- the input frequency of the incoming data DATA is fd (i.e. the first frequency)
- the CDR circuit produces the second clock CK 2 with a second frequency which is fnom+fbb.
- fd is smaller than fnom+fbb
- the sampling point is shifted to the left. Therefore, in order to cover the sampling edge of the second clock CK 2 , the first clock CK 1 with multiple phases (I-Phase, Q-Phase) can form a sampling region W, which is smaller than 1 ⁇ 2 bit width.
- first and second predetermined sampling edges are generated in order to prevent the sampling edge of CK 2 from going beyond the edge of DATA.
- the frequency of the second clock CK 2 is switched to a third frequency which is fnom ⁇ fbb.
- the CDR circuit thus generates a second clock CK 2 with the third frequency (fnom ⁇ fbb), and fd is greater than fnom ⁇ fbb. In consequence the sampling point is shifted to the right.
- FIG. 13 Please refer to FIG. 13 for the functions of the controller in the state shown in FIG. 12 . If the initial sampling is “01”, the controller has to maintain its initial state in order to prevent the sampling state of the CDR circuit from jumping to “11” or “00.”
- the controller can produce a second clock CK 2 with the third frequency (fnom ⁇ fbb) and therefore the sampling point is shifted to the right.
- the second clock CK 2 has the third frequency (fnom ⁇ fbb)
- the sampling point is shifted to the right, meaning that the sampling state is shifted to “00.”
- the controller can produce a second clock CK 2 with the second frequency (fnom+fbb) and therefore the sampling point is shifted to the left. Recovering correctly the incoming data is achieved by repeating the above process.
- the input frequency is fd (i.e. the first frequency) and a recovered clock with the frequency which is fnom+fbb (i.e. the second frequency) is generated by the CDR circuit. Since fd ⁇ fnom+fbb, the sampling point is shifted to the left.
- a reference clock with multiple phases i.e. the first clock
- the frequency of the recovered clock jumps to fnom ⁇ fbb (i.e. the third clock) and fd>fnom ⁇ fbb.
- the sampling point is shifted to the right.
- the restriction in maximum run length of the incoming data is relieved by repeating the above process.
- the controller 230 generate a second control signal C 2 according to the first clock CK 1 outputted by the phase-locked circuit 220 , the recovered data DATAr and the second clock CK 2 which are outputted by the CDR circuit 210 .
- the second control signal C 2 is used to adjust the frequency of the second clock CK 2 output by the CDR circuit 210 .
- the recovered data DATAr has the first frequency and the second clock CK 2 has the second frequency or the third frequency.
- the controller 230 outputs the second control signal C 2 into the CDR circuit 210 according to the prior recovered data DATAr, and the first and second clocks CK 1 , CK 2 , so that the CDR circuit 210 switches the outputted frequency of the second clock CK 2 from the second frequency to the third frequency or from the third frequency to the second frequency, thereby sampling an incoming data to obtain the recovered data DATAr.
- a clock and data recovery method includes the steps of: receiving an incoming data with a first frequency; generating a second clock with a second frequency and sampling the incoming data based on the second clock; forming a sampling region based on a first clock with multiple phases; switching from the second frequency to a third frequency for the second clock when a sampling point of the incoming data is about to go beyond an edge of the sampling region; switching from the third frequency back to the second frequency for the second clock when the sampling point is about to go beyond another edge of the sampling region; and repeating the above two steps until sampling the incoming data is accomplished.
- the first frequency is between the second and third frequencies.
- the frequency difference between the second and the third frequencies is determined by the first frequency and the jitters of the incoming data.
- the sampling regions with different widths are formed by changing the number of phases in the first clock. This width of the sampling region is depended on the run length, the frequency and the jitters of the incoming data.
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Abstract
Description
- 1. Field of Invention
- The invention relates to a clock and data recovery apparatus and the method thereof, and more particularly to a clock and data recovery apparatus for burst mode clock and data recovery in a passive optical network.
- 2. Related Art
- During the process of data transmission, a transmitter continuous sends digital signals to a receiver. That is, each bit is transmitted within a fixed time. Therefore, the receiver uses a clock and data recovery (CDR) apparatus to generate a clock corresponding to the incoming data, thereby correctly retiming the incoming data. How to make a clock frequency exactly corresponding to a frequency of the incoming data is a very important issue.
- As shown in
FIG. 1 , a conventional clock and data recovery apparatus includes a clock anddata recovery circuit 110 and a phase-locked loop (PLL) 120. ThePLL 120 generates a system clock Sys CK according to a reference clock Ref CK, and imposes a voltage signal Sv to the clock anddata recovery circuit 110. In this case, the clock anddata recovery circuit 110 generates a recovered clock CKr with an output frequency corresponding to the voltage signal Sv. The received data DATA are sampled by the recovered clock CKr as data DATAr. This technique has been disclosed in, for example, the U.S. Pat. Nos. 5,237,290 and 6,259,326 B1. - Because of the lack of the feedback control system, the frequency of the conventional CDR may be affected by process variation. Therefore, the output frequency from of CDR is not exactly equal to the data frequency fd, as shown in
FIG. 2 (fnom≠fd on the frequency axis). This frequency mismatch will result in a phase shift in each sampling. If the input data are consecutive identical bits, then the phase shifts will accumulate because of the lack of data transitions. In the end, the maximum allowable number of consecutive identical bits to be transmitted has to be restricted. Consequently, the bit error rate (BER) becomes worse when the input stream contains longer consecutive identical bits. - In view of the foregoing, an objective of the invention is to provide a clock and data recovery (CDR) apparatus and the method thereof to solve the many restrictions and drawbacks existing in the prior art.
- The disclosed invention is to provide a CDR apparatus and the method thereof to solve the problem that the CDR circuit cannot accurately recover the clock signal of the data rate.
- The disclosed invention is to provide a CDR apparatus and the method thereof to be applied in a passive optical network (PON).
- The disclosed invention is to provide a CDR apparatus and the method thereof to selectively generate two recovered clocks with different frequencies.
- The disclosed invention is to provide a CDR apparatus and the method thereof to adjust the frequency of the recovered clock using a controller.
- The disclosed CDR apparatus and the method thereof achieve at least an improved effect, which includes solving the restriction in maximum run length of the incoming data, increasing the high-frequency jitter tolerance, and improving the output jitter contributed by frequency mismatch.
- To achieve the above objectives, a CDR apparatus of the invention includes: a phase-locked circuit, a CDR circuit, and a controller, wherein all components connect with each other.
- The phase-locked circuit generates a first control signal and a first clock having a plurality of phases, and the CDR circuit receives an incoming data and generates a second clock according to the first control signal to sample the incoming data based on the second clock. The controller generates a second control signal according to the incoming data (or the recovered data), the first clock and the second clock to adjust the frequency of the second clock.
- In this case, the incoming data (or the recovered data) have a first frequency, and the frequency of the second clock is one of a second frequency and a third frequency. The first frequency is between the second and third frequencies.
- In one embodiment, the controller includes: two or more flip-flops, a detector, a latch circuit, and a digital signal processing circuit. Each of the flip-flops is connected via the latch circuit to the digital signal processing circuit. The detector, the latch circuit, and the digital signal processing circuit are connected in series.
- The first clock has several phases. The first clock of each phase is outputted to each of the flip-flops, which samples the first clock based to the second clock to generate a first signal. The detector detects the bit edges of the incoming data (or the recovered data) and outputs an enable signal according to the detected result. The latch circuit outputs a second signal corresponding to the first signal from the flip-flops in response to the enable signal. Afterward the digital signal processing circuit generates a second control signal based on the second signal and the first signal from the flip-flops.
- The digital signal processing circuit includes: a multiplexer, at least four state maintaining processors, and a sum circuit.
- The multiplexer is connected to the sum circuit via each the state maintaining processors. The multiplexer outputs the first signal from each flip-flop into one of the state maintaining processors, which is corresponding to the second signal, according to the second signal. Each of the state maintaining processor generates a third control signal based on the state of receiving the first signal, and the sum circuit adds the third control signals from all the sate maintaining processors up to generate a second control signal.
- In another embodiment, the configuration is that each of the state maintaining processors connects with the sum circuit via the multiplexer. In this case, each of the state maintaining processors receives the first signals from all the flip-flops and generates a third control signal based on the first signals. Then, the multiplexer outputs the third control signals based on the second signal from the latch circuit. Afterward, the sum circuit adds the third control signals from the multiplexer up to generate the second control signal.
- Further, the invention discloses a clock and data recovery method including the steps of: receiving an incoming data with a first frequency; generating a second clock with a second frequency and sampling the incoming data based on the second clock; forming a sampling region based on a first clock with multiple phases; switching a frequency of the second clock from the second frequency to a third frequency when a sampling point of the incoming data is about to go beyond one edge of the sampling region; switching the frequency of the second clock from the third frequency back to the second frequency when the sampling point is about to go beyond another edge of the sampling region; and repeating the above two steps until sampling the incoming data is accomplished. The first frequency is between the second and the third frequencies.
- The invention will become more fully understood from the detailed description given hereinbelow illustration only, and thus are not limitative of the present invention, and wherein:
-
FIG. 1 shows the system structure of a conventional CDR apparatus; -
FIG. 2 is a schematic view of the frequency error generated by the CDR apparatus inFIG. 1 ; -
FIG. 3 is a schematic view of the frequency error generated a clock and data recovery (CDR) apparatus according to the present invention; -
FIG. 4 shows the system structure of the CDR apparatus according to an embodiment of the invention; -
FIG. 5 shows the system structure of an embodiment of the CDR circuit inFIG. 4 ; -
FIG. 6 shows the system structure of an embodiment of the phase-locked circuit inFIG. 4 ; -
FIG. 7 shows the system structure of a first embodiment of the controller inFIG. 4 ; -
FIG. 8 shows the system structure of an embodiment of the digital signal processing circuit inFIG. 7 ; -
FIG. 9 shows the system structure of a second embodiment of the controller inFIG. 4 ; -
FIG. 10 shows the system structure of another embodiment of the digital signal processing circuit inFIG. 7 ; -
FIG. 11 shows the system structure of a third embodiment of the controller inFIG. 4 ; -
FIG. 12 shows how the CDR apparatus in an embodiment of the invention executes; -
FIG. 13 shows the state diagram of the controller according to an embodiment of the invention in the state ofFIG. 12 ; and -
FIG. 14 shows the system structure of the CDR apparatus according to another embodiment of the invention. - We first explain the main idea of the invention using
FIG. 3 . The invention uses a second and a third frequency (fnom±fbb) in the vicinity of the first frequency (fd) to correctly simulate the first frequency. The invention utilizes two major techniques. The oscillator in the CDR circuit can provide two frequencies (fnom±fbb). A controller is used to control the switch between the two frequencies (fnom±fbb) in order to obtain an output frequency almost equal to the first frequency fd. Moreover, the first frequency is a frequency of an incoming data or a recovered data generated previously. - With reference to
FIG. 4 , the system according to an embodiment of the disclosed CDR apparatus includes: aCDR circuit 210, a phase-lockedcircuit 220, and acontroller 230. - The
CDR circuit 210, the phase-lockedcircuit 220, and thecontroller 230 connect with each other. When theCDR circuit 210 receives an incoming data DATA, the phase-lockedcircuit 220 generates a first control signal C1 based on a reference signal SR for theCDR circuit 210 and a first clock CK1 for thecontroller 230. TheCDR circuit 210 generates a second clock CK2 according to the first control signal C1 and samples the incoming data DATA based on the second clock CK2 to obtain a recovered data DATAr. Thecontroller 230 generates a second control signal C2 according to the incoming data DATA, the first clock CK1 and the second clock CK2, and theCDR circuit 210 adjust the frequency of the second clock CK2 according to the second control signal C2. - In this embodiment, the incoming data DATA received by the
CDR circuit 210 has a first frequency. TheCDR circuit 210 generates one of two second clocks CK2 with a second frequency and a third frequency respectively. Moreover, the second control signal C2 from thecontroller 230 is used to switch the second clock CK2, which is outputted by theCDR circuit 210 between the second and third frequencies. In particular, the first frequency is between the second and third frequencies. - The relationship between the signal frequency (i.e. the first frequency) of the incoming data DATA and the signal frequency of the reference signal SR is a positive integer multiple. The signal frequency of the incoming data DATA is the positive integer multiple of the signal frequency of the reference signal SR. Moreover, the signal frequency of the incoming data DATA is substantially the same as the signal frequency of the first clock CK1. In this case, the first clock CK1 is a system clock.
- With reference to
FIG. 5 , theCDR circuit 210 includes agating control circuit 212, a first gated voltage controller oscillator (GVCO) 214, and adecision circuit 216. - The
gating control circuit 212, thefirst GVCO 214, and thedecision circuit 216 are connected in series. - When an edge of the incoming data DATA appears, the
gating control circuit 212 provides the edge information for thefirst GVCO 214. Thefirst GVCO 214 generates a second clock CK2 corresponding and synchronized with the incoming data DATA according to the first control signal C1 from the PLL (not shown). The second clock CK2 is provided for thedecision circuit 216 and thecontroller 230 by thefirst GVCO 214. Thedecision circuit 216 samples the incoming data DATA based on the second clock CK2 to generate a recovered data DATAr. Herein thefirst GVCO 214 produces the second clock CK2 with the second frequency or with the third frequency depending on the second control signal C2 provided by the controller. - In this case, the phase-locked circuit is a PLL. The
PLL 220 includes in sequence a phase-frequency detector (PFD) 221, a charge pump (CP) 222, a loop filter (LF) 223, asecond GVCO 224, and afrequency divider 225, in where they are connected in series into a loop, as shown inFIG. 6 . - With reference to
FIG. 6 , thePFD 221 compares the phase difference between a feedback signal Sf and a reference signal SR and outputs a phase difference signal accordingly. TheCP 222 and theLF 223 is implemented according to the phase difference signal from thePFD 221 in order, and a first control signal C1 is outputted. Herein the first control signal C1 is a voltage signal and its magnitude is related to the magnitude of the phase difference between the feedback signal Sf acquired by the first clock CK1 whose frequency is divided and the reference signal SR. Thesecond GVCO 224 outputs the first clock CK1 according to the first control signal C1. The first clock CK1 is divided by thefrequency divider 225 to render a feedback signal Sf, and the feedback signal Sf is supplied for thePFD 221. The phases of the feedback signal Sf and the reference signal SR are different, and therefore thePFD 221 generates a phase difference signal accordingly. - In this embodiment, the controller as shown in
FIG. 7 contains at least two flip-flops 232 (i.e. 232-1, 232-2, etc), adetector 234, alatch circuit 236, and a digitalsignal processing circuit 238. - Each of the flip-flops 232 is connected to the
latch circuit 236 and the digitalsignal processing circuit 238. Thedetector 234, thelatch circuit 236, and the digitalsignal processing circuit 238 are connected in series. - The first clock CK1 has several phases, i.e. CK1-1, CK1-2, etc. The first clock CK1 with each of the phases and the second clock CK2 are outputted into each of flip-flops 232. Each of the flip-flops 232 samples the first clock CK1 using the second clock CK2 to generate one of first signals S1 (i.e. S1-1 or S1-2, etc). Each of the first signals S1 is a “1” or a “0.”
- The
detector 234 detects the bit edges of the incoming data DATA to obtain a detection result, according to which an enable signal ES is outputted. Once an edge is detected, the outputted enable signal ES is a pulse signal; otherwise, no pulse is outputted. Thelatch circuit 236 receives the enable signal ES outputted by thedetector 234 and the first signals S1 outputted by the flip-flops 232. When the received enable signal ES appears, a second signal S2 is outputted into the digitalsignal processing circuit 238. Herein thelatch circuit 236 outputs all the received first signals S1 to generate the second signal S2 when the enable signal ES appears. The digitalsignal processing circuit 238 receives the first signals S1 from the flip-flops 232 and outputs a second control signal C2 corresponding to the received first signals S1 according to the second signal S2. - The digital
signal processing circuit 238 as shown inFIG. 8 contains amultiplexer 240, at least four state maintaining processors 242 (242-1, 242-2, 242-3, 242-4, etc), and asum circuit 244. - The
multiplexer 240 is connected to thesum circuit 244 via the state maintaining processors 242. - The
multiplexer 240 receives the first signals S1 from all the flip-flops 232 and selectively transmits the first signal S1 to one of the state maintaining processors 242 corresponding to the second signal S2. Each of the state maintaining processors 242 generates one of third control signals C3 (C3-1, C3-2, C3-3, C3-4, etc) according to the state of received signal. Thesum circuit 244 adds all the third control signals C3 up to output a second control signal C2. - The number of the state maintaining processors is twice that of the flip-flops in order to process the first signals outputted by the multiplexer.
- Besides, the first clock CK1 is a plurality of single-ended signals each of which represents a phase or a plurality of differential signals each of which represents two phases, and the second clock CK2 is a single-ended signal or a differential signal.
- For example, as shown in
FIG. 9 , we assume that the first clock CK1 has eight different phases. - If the first clock CK1 is the differential signals CK1-1, CK1-2, CK1-3 and CK1-4 each of which represents two phases, the first clock CK1-1 represents a phase which is 0 degree accompanying another phase which is 180 degrees; the first clock CK1-2 represents a phase which is 45 degrees accompanying another phase which is 225 degrees; the first clock CK1-3 represents a phase which is 90 degrees accompanying another phase which is 270 degrees; and the first clock CK1-4 represents a phase which is 135 degrees accompanying another phase which is 315 degrees.
- If the first clock CK1 is the single-ended signals CK1-1, CK1-2, CK1-3, and CK1-4 each of which represents one phase, the first clock CK1-1 represents a phase which is 0 degree; the first clock CK1-2 represents a phase which is 45 degrees; the first clock CK1-3 represents a phase which is 90 degrees; and the first clock CK1-4 represents a phase which is 135 degrees.
- The first clock CK1-1 and the second clock CK2 are outputted into a flip-flop 232-1, so that the flip-flop 232-1 generates a first signal S1-1 corresponding to the first clock CK1-1 according to the second clock CK2. Herein the first signal S1-1 is a digital signal of “1” or “0.” Likewise, the flip-flops 232-2, 232-3, 2324 generate respectively a first signal S1-2 corresponding to the first clock CK1-2, a first signal S1-3 corresponding to the first clock CK1-3 and a first signal S1-4 corresponding to the first clock CK1-4 according to the second clock CK2.
- When the
detector 234 detects the transition of the incoming data DATA, it outputs an enable signal ES with a pulse signal. Thelatch circuit 236 receives the first signals S1-1˜S1-4 from the flip-flops 232-1˜232-4 and outputs a second signal S2 corresponding to the first signals S1-1˜S1-4 into themultiplexer 240. - Suppose the first signals S1-1˜S1-4 generated by the flip-flops 232-1232-4 are “0,” “0,” “1” and “1” The outputted second signal S2 is a digital signal of “0011.”
- In this example, the
multiplexer 240 has eight 4-bit logic signal channels (e.g. 0000, 0001, 0011, 0111, 1111, 1110, 1100, and 1000). Each channel is connected to one of the state maintaining processors 242 for processing one state of the logic signals. - When the
multiplexer 240 receives the second signal S2, it outputs the first signals S1-1˜S1-4 to the associated state maintaining processor via the channel corresponding to the second signal S2. Each of the state maintaining processors 242 generates a third control signal C3 according to the state of the received signal. Thesum circuit 244 adds all the third control signals C3 up to output a second control signal C2, thereby controlling the first GVCO to switch the frequency of the generated second clock. - As assumed above, the state maintaining processors 242-1˜242-8 are used to process the signals 0000, 0001, 0011, 0111, 1111, 1110, 1100, and 1000, respectively. Therefore, when the
multiplexer 240 receives the second signal S2 of “0011”, themultiplexer 240 output the first signal S1-1˜S1-4 into the associated state maintaining processor 242-3 via the channel of “0011”. The state maintaining processor 242-3 follows the states of the first signal S1-1˜S1-4 to output a third control signal C3-3 of “1” or “0,” otherwise other state maintaining processors output the third control signals of “0.” Thesum circuit 244 adds all the third control signals C3 up to output a second control signal C2, thereby switching the output frequency of the second clock. - In another embodiment, the digital
signal processing circuit 238 as shown inFIG. 10 includes amultiplexer 240, at least four state maintaining processors 242 (i.e. 242-1, 242-2, 242-3, 242-4) and asum circuit 244. - Each of the state maintaining processors 242 is connected to the
sum circuit 244 via themultiplexer 240. - The operation of each component is substantially similar as those in
FIG. 8 , and we therefore do not repeat their descriptions. In this case, each of the state maintaining processors 242 receives the first signals S1 from all the flip-flops and generates a third control signal C3-1, C3-2, C3-3, or C3-4, etc based on the first signals S1. Then, themultiplexer 240 outputs the third control signals C3-1, C3-2, C3-3, or C3-4, etc based on the second signal S2 from the latch circuit. Afterward, thesum circuit 244 adds the third control signals C3-1, C3-2, C3-3, C3-4, etc from themultiplexer 240 up to generate the second control signal C2. - Herein we briefly describe how the disclosed CDR apparatus functions. Suppose the first clock CK1 generated by the phase-locked circuit has different phases I-Phase and Q-phase (differing by 90 degrees). If the first clock CK1 has two single-ended signals (CK1-1, CK1-2), then the first clock CK1-1 represents a
phase 0 degree, i.e. I-Phase, and the first clock CK1-2 represents a phase 90 degrees, i.e. Q-phase. If the first clock CK1 contains two differential signals (CK1-1, CK1-2), then the first clock CK1-1 represents thephases 0 degree along with 180 degrees, i.e. I-Phase, and the first clock CK1-2 represents phases 90 degrees along with 270 degrees, i.e. Q-phase. - In this case, the composition of the controller is shown in
FIG. 11 . Since the operations of components are substantially similar as those inFIG. 9 , we do not repeat their descriptions. - With reference to
FIG. 12 , when the incoming data DATA enters, the CDR circuit samples it based on the second clock CK2 to obtain recovered data (not shown). Suppose the input frequency of the incoming data DATA is fd (i.e. the first frequency), then the CDR circuit produces the second clock CK2 with a second frequency which is fnom+fbb. When fd is smaller than fnom+fbb, the sampling point is shifted to the left. Therefore, in order to cover the sampling edge of the second clock CK2, the first clock CK1 with multiple phases (I-Phase, Q-Phase) can form a sampling region W, which is smaller than ½ bit width. That is, first and second predetermined sampling edges are generated in order to prevent the sampling edge of CK2 from going beyond the edge of DATA. When the sampling point is shifted to the left and reaches the first predetermined sampling edge, the frequency of the second clock CK2 is switched to a third frequency which is fnom−fbb. The CDR circuit thus generates a second clock CK2 with the third frequency (fnom−fbb), and fd is greater than fnom−fbb. In consequence the sampling point is shifted to the right. - Please refer to
FIG. 13 for the functions of the controller in the state shown inFIG. 12 . If the initial sampling is “01”, the controller has to maintain its initial state in order to prevent the sampling state of the CDR circuit from jumping to “11” or “00.” - As described above, if the second clock CK2 has the second frequency (fnom+fbb), the sampling point is shifted to the left, meaning that the sampling state is shifted to “11.” When the sampling state of the CDR circuit pre-jumps to “11,” the controller can produce a second clock CK2 with the third frequency (fnom−fbb) and therefore the sampling point is shifted to the right. On the other hand, if the second clock CK2 has the third frequency (fnom−fbb), the sampling point is shifted to the right, meaning that the sampling state is shifted to “00.” When the sampling state pre-jumps to “00,” the controller can produce a second clock CK2 with the second frequency (fnom+fbb) and therefore the sampling point is shifted to the left. Recovering correctly the incoming data is achieved by repeating the above process.
- For example, when an incoming data is entered, the input frequency is fd (i.e. the first frequency) and a recovered clock with the frequency which is fnom+fbb (i.e. the second frequency) is generated by the CDR circuit. Since fd<fnom+fbb, the sampling point is shifted to the left. A reference clock with multiple phases (i.e. the first clock) is then used to from a window that encloses the sampling edges of the recovered clock. When the sampling edge approximately arrives the predetermined edges, the frequency of the recovered clock jumps to fnom−fbb (i.e. the third clock) and fd>fnom−fbb. Herein the sampling point is shifted to the right. The restriction in maximum run length of the incoming data is relieved by repeating the above process.
- In yet another embodiment, with reference to
FIG. 14 , thecontroller 230 generate a second control signal C2 according to the first clock CK1 outputted by the phase-lockedcircuit 220, the recovered data DATAr and the second clock CK2 which are outputted by theCDR circuit 210. The second control signal C2 is used to adjust the frequency of the second clock CK2 output by theCDR circuit 210. In other words, the recovered data DATAr has the first frequency and the second clock CK2 has the second frequency or the third frequency. Thus thecontroller 230 outputs the second control signal C2 into theCDR circuit 210 according to the prior recovered data DATAr, and the first and second clocks CK1, CK2, so that theCDR circuit 210 switches the outputted frequency of the second clock CK2 from the second frequency to the third frequency or from the third frequency to the second frequency, thereby sampling an incoming data to obtain the recovered data DATAr. - Since the structure and configuration of the CDR circuit, phase-locked circuit, and controller are approximately the same as before, we do not provide further descriptions here.
- Based on the above, a clock and data recovery method according to an embodiment of the invention is provided, which includes the steps of: receiving an incoming data with a first frequency; generating a second clock with a second frequency and sampling the incoming data based on the second clock; forming a sampling region based on a first clock with multiple phases; switching from the second frequency to a third frequency for the second clock when a sampling point of the incoming data is about to go beyond an edge of the sampling region; switching from the third frequency back to the second frequency for the second clock when the sampling point is about to go beyond another edge of the sampling region; and repeating the above two steps until sampling the incoming data is accomplished.
- Herein the first frequency is between the second and third frequencies. Moreover, the frequency difference between the second and the third frequencies is determined by the first frequency and the jitters of the incoming data. Besides, the sampling regions with different widths are formed by changing the number of phases in the first clock. This width of the sampling region is depended on the run length, the frequency and the jitters of the incoming data.
- Certain variations would be apparent to those skilled in the art, which variations are considered within the spirit and scope of the claimed invention.
Claims (17)
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TW093137081A TWI242929B (en) | 2004-12-01 | 2004-12-01 | Clock and data recovery apparatus and method thereof |
TW93137081 | 2004-12-01 |
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US7450677B2 US7450677B2 (en) | 2008-11-11 |
Family
ID=36567384
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WO2013126440A3 (en) * | 2012-02-21 | 2013-10-31 | Qualcomm Incorporated | Automatic detection and compensation of frequency offset of a clock recovery |
US9077349B2 (en) | 2012-02-21 | 2015-07-07 | Qualcomm Incorporated | Automatic detection and compensation of frequency offset in point-to-point communication |
Also Published As
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US7450677B2 (en) | 2008-11-11 |
TWI242929B (en) | 2005-11-01 |
TW200620835A (en) | 2006-06-16 |
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