US20060104132A1 - Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system - Google Patents
Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system Download PDFInfo
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- US20060104132A1 US20060104132A1 US10/986,767 US98676704A US2006104132A1 US 20060104132 A1 US20060104132 A1 US 20060104132A1 US 98676704 A US98676704 A US 98676704A US 2006104132 A1 US2006104132 A1 US 2006104132A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
Definitions
- the present invention relates to a semiconductor memory system. More particularly, the present invention relates to a semiconductor memory system with at least one memory device, a memory controller unit and, an optional register unit. Each of these components comprises an interface circuit and a method for the transfer of write and read data signals among the interface circuits, the data signals each being transferred in signal bursts of a specific burst length.
- a separate ECC-module that can detect and possibly correct a channel error or a data error resulting from a DRAM error is provided for the detection or correction of errors in memory modules that are equipped with high-speed semiconductor memory devices.
- DIMM memory modules for desktop personal computers do not have the capability to detect and correct errors.
- An additional further module for the detection and/or correction of errors that is not used for the storing of data would excessively increase the cost of such a system.
- the clock recovery for a received data signal is achieved by transmitting an additional strobe signal, the so-called DQS signal, or by transmitting a synchronization burst via the data bus, because the semiconductor memory devices require a specific number of edge changes within a specific time interval to recover the clock cycle required for signal synchronization. Since it might collide with read data or write data, the synchronization burst disturbs the data traffic on the bus, and using the transfer of the separate DQS signal for synchronization is always difficult if data transfer rates are high.
- the present invention aims at facilitating a semiconductor memory system of the aforementioned type and a method for the transfer of write and read data signals among the interface circuits in such a semiconductor memory system, wherein the detection and/or correction of errors at least in the write data signals transferred is achieved without an increase in the number of pins on the semiconductor memory module and/or the memory controller. Additionally, it is possible to synchronize symbols without having to transfer an additional synchronization burst via the bus.
- a semiconductor memory system with at least one memory device comprises a memory controller unit and, optionally a register unit, each of which comprise an interface circuit, and with data transfer lines that run among the interface circuits and can each be used to transfer write and read data signals to and from the memory device from and to the memory controller unit and, optionally, from and to the register unit in signal bursts of a specific burst length.
- the interface circuits are adapted for the transfer of additional bits extending the burst length at least of the write data bursts together with at least every n th signal burst.
- This extension of the burst length proposed according to an aspect of the present invention allows the additional bits to be used as information on the detection or correction of errors.
- This design is of additional advantage in that it provides more time for the transfer of command and address information per burst and that, in a memory system with a point-to-point transfer of CA signals (what is called a P2P CA system), it is now, for example, possible to transfer 20 bits per burst per lane. This reduces the necessary number of CA lanes and the number of pins. Since it is important that a predetermined number of CA-commands can be transmitted through a P2P-CA-bus, the extended DQ burst length influences also the transmission on the CA-bus so that more information per burst can be transmitted.
- the read data may be treated only by an error detection algorithm, wherein the memory controller unit in case of a read error can simply repeat the read operation. Therefore, the extension of the burst length by means of the additional bits may be handled differently for write data and read data bursts so that more additional bits are included in the write data than in the read data bursts.
- the latter also includes a method wherein only the write data bursts are extended and not the read data bursts. However, it may simplify the circuit design of the interface circuits if the number of the additional bits is made equal for data read and write bursts.
- an additional aspect of the present invention allows the burst length to, for example, 20 bits and uses all or some of the additional bits as synchronization patterns. This permits easy compensation of the overhead caused by the increased operating speed of the interface. What is more, there is no additional synchronization burst that might collide with the write and/or read request burst.
- the measure proposed by the method according to the invention of extending the burst length by a number of additional bits that can be used as an ECC pattern and/or as a synchronization pattern can, on the one hand, achieve in the semiconductor memory system according to the invention an effective error detection and/or correction algorithm and, on the other hand, a simplified symbol synchronization that can do without the transfer of a DQS signal or an additional synchronization burst.
- the additional bits are, preferably, transferred with each signal burst and typically in the same number.
- the additional bits contain an error detection and/or correction code concerning the assigned data unit. If, for example, 128 data bits plus 32 additional bits are transferred via an X8 interface in such a semiconductor memory system, 32 bits are available for error correction, thus facilitating a quite effective error correction algorithm. Even if two additional bits are transferred with each burst, it is possible to achieve a highly effective error correction.
- the additional bits contain a specific minimum number of edge changes for symbol synchronization.
- the additional bits can form a specific synchronization pattern so that this information can be used on the DRAM memory chip, the memory controller module or the register for symbol synchronization by a clock data recovery circuit (CDR circuit).
- CDR circuit clock data recovery circuit
- FIG. 1 is a schematical view of a semiconductor memory system according to an embodiment of the present invention, comprising a semiconductor memory module and a memory controller module;
- FIG. 2 illustrates a graphical signal-time diagram according to a preferred method of the present invention for the transfer of write and read data signals in the semiconductor memory system
- FIG. 3 shows a graphical signal-time diagram of a conventional method for the transfer of write and read data signals in a semiconductor memory system.
- FIG. 3 illustrating a conventional method for the transfer of write and read data signals.
- the reference clock cycle (4N) f ref with a period length T per — ref that is shown in the fifth line E is generated according to a “4N” rule which means that the CA unit interval is four times the period length of the basic clock cycle shown in the second line of FIG. 3 .
- Either the reference clock f ref according to line C or the reference clock according to line E each specify the CA unit interval T per — CA specified in the lines D and F respectively, either according to the “2N” rule or according to the “4N” rule.
- FIG. 1 will be used to describe below a preferred embodiment of a semiconductor memory system according to a preferred embodiment of the present invention and FIG. 2 to describe its mode of operation and a preferred example of the method according to the invention.
- a semiconductor memory module 10 that may, for example, be a DIMM memory module contains, for example, four memory devices 11 , 12 , 13 , 14 and, optionally, a (dashed) register unit 15 a , each with interface circuits 1 , 2 , 3 , 4 , and 5 a .
- the register unit 15 a may also be arranged on a memory controller module 20 , in this case being referenced as 15 b and the interface circuit of that register unit ( 15 b ) being referenced 5 b .
- Command and address signals (CA) are transmitted from the memory controller 20 to the memory module 10 via a CA line system.
- Write and read data signals DQ are transferred from the memory controller 20 to the memory devices 11 - 14 arranged on the memory module 10 and from these memory devices 11 - 14 to the memory controller module 20 via a DQ line system.
- a DQ line system is also provided on the memory module 10 for the write and read data to be transferred.
- the present invention can employ the interface circuits 1 - 4 , 5 a (alternatively 5 b ) can be adapted for the transfer of additional bits extending the burst length at least of the write data together with at least every n th data signal burst.
- these additional bits are added to the read and write data signal bursts and can be used to detect and/or correct errors and/or to achieve a symbol synchronization in the particular receiving interface circuit.
- 2 or 4 additional bits are, for example, added, extending the burst length to 10 or 20 respectively, in contrast to the conventional burst length of 8 or 16 bits, as illustrated above by means of FIG. 3 .
- burst lengths of, for example, 40 or 70 etc. are possible, that is in general burst lengths (including the additional bits) of 2 k +x, with 2 k being the burst length without additional bits and x the number of additional bits.
- the extension of the burst length may be handled differently for write and read data bursts.
- the error detection and/or correction information provided by the additional bits can be used per lane or per burst. For example, 32 bits are available for error correction measures if 4 additional bits are transferred per burst and a total of 160 bits are transferred per burst via an X8 interface. This permits a highly effective error correction. With this transfer method, even two additional bits would permit a highly effective error correction.
- the additional bits that are added to the usual burst length allow a clock signal synchronization on reception of the data signals DQ in the particular interface circuits, thus making a separate transfer of synchronization bursts unnecessary.
- FIG. 2 shows the signals of FIG. 3 in part only and not as a whole.
- the fundamental clock f fd represented in the first line BI of FIG. 2 has been generated by doubling the frequency of the fundamental clock shown in line A of FIG. 3 , so that now a burst length BL of altogether 20 bits with 4 additional bits can, for example, be accommodated in the double period 2 ⁇ T per of the reference clock shown in the second line EI for the “4N” rule or in the period T per of the CA signal for the “4N” rule that is shown in the third line FI of FIG. 2 .
- These 20 bits of the burst extended in this manner are shown in the last line GI of FIG. 2 .
- the fundamental clock of the frequency f b1 is 800-1600 MHz (line A in FIG.
Abstract
Description
- The present invention relates to a semiconductor memory system. More particularly, the present invention relates to a semiconductor memory system with at least one memory device, a memory controller unit and, an optional register unit. Each of these components comprises an interface circuit and a method for the transfer of write and read data signals among the interface circuits, the data signals each being transferred in signal bursts of a specific burst length.
- At present, a separate ECC-module that can detect and possibly correct a channel error or a data error resulting from a DRAM error is provided for the detection or correction of errors in memory modules that are equipped with high-speed semiconductor memory devices. Typically, however, conventional DIMM memory modules for desktop personal computers do not have the capability to detect and correct errors. An additional further module for the detection and/or correction of errors that is not used for the storing of data would excessively increase the cost of such a system.
- In conventional semiconductor memory systems, the clock recovery for a received data signal is achieved by transmitting an additional strobe signal, the so-called DQS signal, or by transmitting a synchronization burst via the data bus, because the semiconductor memory devices require a specific number of edge changes within a specific time interval to recover the clock cycle required for signal synchronization. Since it might collide with read data or write data, the synchronization burst disturbs the data traffic on the bus, and using the transfer of the separate DQS signal for synchronization is always difficult if data transfer rates are high.
- The increased data transfer speeds of future generations of DRAMs will require a differential transfer of the data signals, which would almost double the number of pins on the memory module and at the module of the memory controller. Since, however, such a doubling of the pin number is impossible (routing, connector pin count, DRAM ball count, MCH ball count), employing an additional increase in transfer speed is an option. In this case, however, it is absolutely necessary that a capability of detecting and/or correcting errors be provided.
- Accordingly, the present invention aims at facilitating a semiconductor memory system of the aforementioned type and a method for the transfer of write and read data signals among the interface circuits in such a semiconductor memory system, wherein the detection and/or correction of errors at least in the write data signals transferred is achieved without an increase in the number of pins on the semiconductor memory module and/or the memory controller. Additionally, it is possible to synchronize symbols without having to transfer an additional synchronization burst via the bus.
- According to one aspect of the invention, a semiconductor memory system with at least one memory device comprises a memory controller unit and, optionally a register unit, each of which comprise an interface circuit, and with data transfer lines that run among the interface circuits and can each be used to transfer write and read data signals to and from the memory device from and to the memory controller unit and, optionally, from and to the register unit in signal bursts of a specific burst length.
- According to an additional aspect of the invention, the interface circuits are adapted for the transfer of additional bits extending the burst length at least of the write data bursts together with at least every nth signal burst. This extension of the burst length proposed according to an aspect of the present invention allows the additional bits to be used as information on the detection or correction of errors. This design is of additional advantage in that it provides more time for the transfer of command and address information per burst and that, in a memory system with a point-to-point transfer of CA signals (what is called a P2P CA system), it is now, for example, possible to transfer 20 bits per burst per lane. This reduces the necessary number of CA lanes and the number of pins. Since it is important that a predetermined number of CA-commands can be transmitted through a P2P-CA-bus, the extended DQ burst length influences also the transmission on the CA-bus so that more information per burst can be transmitted.
- It is to be noted that the read data may be treated only by an error detection algorithm, wherein the memory controller unit in case of a read error can simply repeat the read operation. Therefore, the extension of the burst length by means of the additional bits may be handled differently for write data and read data bursts so that more additional bits are included in the write data than in the read data bursts. The latter also includes a method wherein only the write data bursts are extended and not the read data bursts. However, it may simplify the circuit design of the interface circuits if the number of the additional bits is made equal for data read and write bursts.
- Furthermore, an additional aspect of the present invention allows the burst length to, for example, 20 bits and uses all or some of the additional bits as synchronization patterns. This permits easy compensation of the overhead caused by the increased operating speed of the interface. What is more, there is no additional synchronization burst that might collide with the write and/or read request burst.
- Thus, the measure proposed by the method according to the invention of extending the burst length by a number of additional bits that can be used as an ECC pattern and/or as a synchronization pattern, can, on the one hand, achieve in the semiconductor memory system according to the invention an effective error detection and/or correction algorithm and, on the other hand, a simplified symbol synchronization that can do without the transfer of a DQS signal or an additional synchronization burst.
- In the semiconductor memory system according to the present invention, the additional bits are, preferably, transferred with each signal burst and typically in the same number.
- For the purpose of detecting and/or correcting errors, the additional bits contain an error detection and/or correction code concerning the assigned data unit. If, for example, 128 data bits plus 32 additional bits are transferred via an X8 interface in such a semiconductor memory system, 32 bits are available for error correction, thus facilitating a quite effective error correction algorithm. Even if two additional bits are transferred with each burst, it is possible to achieve a highly effective error correction.
- In the semiconductor memory system according to the invention, it is, furthermore, preferably provided that the additional bits contain a specific minimum number of edge changes for symbol synchronization. Moreover, the additional bits can form a specific synchronization pattern so that this information can be used on the DRAM memory chip, the memory controller module or the register for symbol synchronization by a clock data recovery circuit (CDR circuit).
- As a matter of course, it is possible to combine the two proposed applications of the additional bits, that is, on the one hand, as error detection and/or correction bits and, on the other, as synchronization bits.
- The above and further aims and elements of the invention are illustrated in more detail in the description below and in relation to the enclosed figures.
- The above and still further aspects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of a specific embodiment thereof, particularly when taken in conjunction with the accompanying drawings wherein like reference numerals in the various figures are utilized to designate like components.
-
FIG. 1 is a schematical view of a semiconductor memory system according to an embodiment of the present invention, comprising a semiconductor memory module and a memory controller module; -
FIG. 2 illustrates a graphical signal-time diagram according to a preferred method of the present invention for the transfer of write and read data signals in the semiconductor memory system; and -
FIG. 3 shows a graphical signal-time diagram of a conventional method for the transfer of write and read data signals in a semiconductor memory system. - The following illustration of a preferred embodiment of the invention by means of
FIGS. 1 and 2 will be preceded by a description of the prior art signal-time diagram ofFIG. 3 illustrating a conventional method for the transfer of write and read data signals. According to this transfer method and on the basis of the fundamental clock of the frequency fb1 shown in the first line A, for example within a frequency range fb1=800-1600 MHz corresponding to a period length PPR— b1 of 1250-625 ps, and a fundamental clock of the frequency 1.5×fb1 that is shown in the second line B and is immediately derived from the fundamental clock according to line A, for example within a frequency range of 1333-2400 MHz corresponding to a period length of 750-416 ps, either a reference clock fref with a period length Tper— ref that is shown in the third line C is generated according to a “2N” rule which means that a CA unit interval is twice the period length of the fundamental clock according to the second line B. Alternatively, the reference clock cycle (4N) fref with a period length Tper— ref that is shown in the fifth line E is generated according to a “4N” rule which means that the CA unit interval is four times the period length of the basic clock cycle shown in the second line ofFIG. 3 . Either the reference clock fref according to line C or the reference clock according to line E each specify the CA unit interval Tper— CA specified in the lines D and F respectively, either according to the “2N” rule or according to the “4N” rule. - The bottommost line G illustrates the “normal” 16 bits of the data transfer burst with a burst length BL=16 or, if the 2N rule is used, a data transfer burst of a burst length BL=8, occurring in a period Tper
— CA of each of the CMD signals, such as they are represented in the forth line D and in the sixth line F respectively ofFIG. 3 .FIG. 1 will be used to describe below a preferred embodiment of a semiconductor memory system according to a preferred embodiment of the present invention andFIG. 2 to describe its mode of operation and a preferred example of the method according to the invention. Asemiconductor memory module 10 that may, for example, be a DIMM memory module contains, for example, fourmemory devices register unit 15 a, each withinterface circuits register unit 15 a may also be arranged on amemory controller module 20, in this case being referenced as 15 b and the interface circuit of that register unit (15 b) being referenced 5 b. Command and address signals (CA) are transmitted from thememory controller 20 to thememory module 10 via a CA line system. Write and read data signals DQ are transferred from thememory controller 20 to the memory devices 11-14 arranged on thememory module 10 and from these memory devices 11-14 to thememory controller module 20 via a DQ line system. A DQ line system is also provided on thememory module 10 for the write and read data to be transferred. - As has already been mentioned, the present invention can employ the interface circuits 1-4, 5 a (alternatively 5 b) can be adapted for the transfer of additional bits extending the burst length at least of the write data together with at least every nth data signal burst. In the preferred embodiment, these additional bits are added to the read and write data signal bursts and can be used to detect and/or correct errors and/or to achieve a symbol synchronization in the particular receiving interface circuit.
- Thus, according to the invention, 2 or 4 additional bits are, for example, added, extending the burst length to 10 or 20 respectively, in contrast to the conventional burst length of 8 or 16 bits, as illustrated above by means of
FIG. 3 . As a matter of course, burst lengths of, for example, 40 or 70 etc. are possible, that is in general burst lengths (including the additional bits) of 2k+x, with 2k being the burst length without additional bits and x the number of additional bits. - However, as already described above, the extension of the burst length may be handled differently for write and read data bursts.
- The error detection and/or correction information provided by the additional bits can be used per lane or per burst. For example, 32 bits are available for error correction measures if 4 additional bits are transferred per burst and a total of 160 bits are transferred per burst via an X8 interface. This permits a highly effective error correction. With this transfer method, even two additional bits would permit a highly effective error correction.
- Furthermore, the additional bits that are added to the usual burst length allow a clock signal synchronization on reception of the data signals DQ in the particular interface circuits, thus making a separate transfer of synchronization bursts unnecessary.
- In
FIG. 2 , a signal-time diagram illustrates how the burst length (e.g. BL=16) that is extended by the additional bits ZB is, in principle, generated in the interface circuits 1-4, 5 a, optionally 5 b inFIG. 1 . Herein,FIG. 2 shows the signals ofFIG. 3 in part only and not as a whole. - The fundamental clock ffd represented in the first line BI of
FIG. 2 has been generated by doubling the frequency of the fundamental clock shown in line A ofFIG. 3 , so that now a burst length BL of altogether 20 bits with 4 additional bits can, for example, be accommodated in thedouble period 2×Tper of the reference clock shown in the second line EI for the “4N” rule or in the period Tper of the CA signal for the “4N” rule that is shown in the third line FI ofFIG. 2 . These 20 bits of the burst extended in this manner are shown in the last line GI ofFIG. 2 . Assuming that, in the example, the fundamental clock of the frequency fb1 is 800-1600 MHz (line A inFIG. 3 ), the clock frequency of the fundamental clock ffd according to line BI ofFIG. 2 is twice as high, i.e. 1600-3200 MHz, corresponding to a period length Tper— fd of 625-313 ps, and the data transfer frequency achieved by the data signal burst of the bit length BL=20 is then 1600-3200 MHz. - The frequencies and period lengths specified are only an example and cannot be considered as limiting the invention. The number of additional bits and the total bit length BL are, likewise, only an example.
- Having described preferred embodiments of a new and improved method and apparatus for the transfer of write and read data signals in a semiconductor memory system, it is believed that other modifications, variations, and changes will be suggested to those skilled in the art in view of the teachings set forth herein. It is therefore to be understood that all such variations, modifications and changes are believed to fall within the scope of the present invention as defined by the appended claims.
-
-
- 1-4, 5 a, 5 b Interface circuits
- 10 Semiconductor memory module
- 11-14 Semiconductor memory devices
- 15 a, 15 b Register units
- DQ Write and read data signals
- CA Command and address signals
- fb1, TPER
— b1 Frequency and period length of the fundamental clock (line A) - 1.5 times fb1 1.5 times the frequency fb1 (line B)
- (2N) fref, TPER
— ref Reference clock frequency and period length according to the 2N rule - (2N) fCA, TPER
— CA Frequency and period length of the command signal CMD according to 2N rules - (4N) fref, TPER
— ref Frequency and period length of the reference clock according to the 4N rule - (4N) fCA, TPER
— CA Frequency and period length of the command signal CMD according to the 4N rule - BL Burst length
- ZB Additional bits
- ffd=2 fb1 Double fundamental clock frequency
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US20110016278A1 (en) * | 2008-03-31 | 2011-01-20 | Frederick Ware | Independent Threading of Memory Devices Disposed on Memory Modules |
US8023358B2 (en) * | 2008-04-02 | 2011-09-20 | International Business Machines Corporation | System and method for providing a non-power-of-two burst length in a memory system |
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US20020023191A1 (en) * | 2000-08-21 | 2002-02-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and memory system using the same |
US20030123320A1 (en) * | 1997-04-25 | 2003-07-03 | Wright Jeffrey P. | Synchronous dynamic random access memory device |
US6724685B2 (en) * | 2001-10-31 | 2004-04-20 | Infineon Technologies Ag | Configuration for data transmission in a semiconductor memory system, and relevant data transmission method |
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US20030123320A1 (en) * | 1997-04-25 | 2003-07-03 | Wright Jeffrey P. | Synchronous dynamic random access memory device |
US20020023191A1 (en) * | 2000-08-21 | 2002-02-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and memory system using the same |
US6724685B2 (en) * | 2001-10-31 | 2004-04-20 | Infineon Technologies Ag | Configuration for data transmission in a semiconductor memory system, and relevant data transmission method |
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