US20060050737A1 - System and method for checking validity of data transmission - Google Patents

System and method for checking validity of data transmission Download PDF

Info

Publication number
US20060050737A1
US20060050737A1 US11025557 US2555704A US2006050737A1 US 20060050737 A1 US20060050737 A1 US 20060050737A1 US 11025557 US11025557 US 11025557 US 2555704 A US2555704 A US 2555704A US 2006050737 A1 US2006050737 A1 US 2006050737A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
data
checksum
shift operation
check
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11025557
Other versions
US7463649B2 (en )
Inventor
Chun-Pin Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hon Hai Precision Industry Co Ltd
Original Assignee
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/095Error detection codes other than CRC and single parity bit codes
    • H03M13/096Checksums
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0059Convolutional codes
    • H04L1/006Trellis-coded modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0061Error detection codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/08Arrangements for detecting or preventing errors in the information received by repeating transmission, e.g. Verdan system

Abstract

A system for checking the validity of data transmission includes a data transmitting computer (1), a data receiving computer (2), and a network (3). The data transmitting computer is used for generating a check-code of original data, and sending a data packet, which includes the original data and the check-code, to the data receiving computer via the network. The data transmitting computer includes a shift operation unit (111), an addition operation (112) unit, a complement operation unit (113), and a control unit (114). The data receiving computer is used for receiving the data packet from the data transmitting computer, and determining whether the data packet is valid. The data receiving computer includes a shift operation unit (211), an addition operation unit (212), and a control unit (213). A related method is also disclosed.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to systems and methods for checking the validity of electronic data transmission, and particularly to a system and method for checking the validity of data transmission through a network according to a checksum mechanism.
  • 2. Prior art of the invention
  • In any communication system, it is desirable to detect data transmission errors. Each packet transmitted across a communications network between nodes contain data and a header that describes the data. In a typical communications system utilizing Internet Protocol (IP), a sending computer or node transmits the header and the data to one or more receiving computers or nodes. The header contains a checksum and other components. The checksum generated by the sending node is for examining the data, and the receiving node uses it to determine whether any errors were introduced into the data during transmission. In order to generate the header, the sending node must read all the data. This usually requires the sending node to examine every byte of the data twice, once to generate the checksum and again to transmit the data.
  • Presently, a checksum mechanism is usually used to check whether the data have been interfered with during the data transmission. For example, the transmission communication protocol (TCP) uses a checksum to protect the data which is transmitted. This checksum is located in the TCP header of the Internet datagram packet. As described above, all of the data must be examined before the data can begin to be transmitted. This results in two adverse consequences. First, all of the bytes of data must be read twice, once to generate the checksum, and again to transmit the data. This cuts down the maximum throughput possible for this protocol. Second, the beginning of the data cannot be transmitted until the end of the data is known. This adds to the latency of transmission.
  • U.S. Pat. No. 5,815,516 issued on Sep. 29, 1998 and entitled “Method And Apparatus For Producing Transmission Control Protocol Checksums Using Internet Protocol Fragmentation” discloses a method and apparatus for producing transmission control protocol (TCP) checksums using IP fragmentation. The TCP uses a checksum to protect the data which is transmitted. This checksum is located in the TCP header of the Internet datagram packet. In the disclosed method, a TCP module receives a data packet to be transmitted, and prepares a first IP data fragment without a checksum for the received data packet. The first IP data fragment is transmitted. During the transmission of the first IP data fragment, a checksum is generated. Then an IP header fragment including the generated checksum is transmitted.
  • However, there is nothing known in the art which can check error data generated when data bits exchange places; that is, when data in two or more data bytes is out of order. This can occur when the data transmission through the network is interfered with in some way. The above-mentioned solutions cannot reliably check for such error data. A system and method for checking the validity of data transmission which can overcome the above-mentioned problem is desired.
  • SUMMARY OF THE INVENTION
  • Accordingly, a main objective of the present invention is to provide a system and method for checking the validity of data transmission, and particularly for checking whether data are out of order due to interference occurring during transmission of the data over a network.
  • To accomplish the above objective, a system for checking the validity of data transmission in accordance with a preferred embodiment of the present invention comprises a data transmitting computer, a data receiving computer, and a network.
  • The data transmitting computer is provided for generating a check-code of original data, and sending a data packet, which comprises the original data and the check-code, to the data receiving computer via the network. The data transmitting computer comprises a Central Processing Unit (CPU), a Peripheral Component Interface (PCI) bus, and a memory. The CPU comprises: a shift operation unit for performing a shift operation on data units of the original data; an addition operation unit for adding data in all data units after the shift operation to obtain a checksum1, according to an addition rule: adding each bit of one data unit to corresponding each bit of another data unit; a complement operation unit for calculating a 2's complement of the last 2m bytes of the checksum1 to obtain a check-code, wherein “m” represents the number “0” or any natural number; and a control unit for reading the original data from the memory via the PCI bus, and sending a data packet including the original data and the check-code to the data receiving computer. The memory stores the original data to be sent to the data transmitting computer.
  • The data receiving computer is provided for receiving the data packet from the data transmitting computer, and checking and determining whether the data packet is valid. The data receiving computer comprises a CPU. The CPU comprises: a shift operation unit for performing a shift operation on the data units of the original data unpacked from the received data packet; an addition operation unit for adding the data units after the shift operation to obtain a checksum2, and adding the last 2m bytes of the checksum2 to the check-code from the received data packet to obtain a checksum3; and a control unit for determining whether the data packet from the data transmitting computer is valid by checking whether the last 2m bytes of the checksum3 equal “0.”
  • Further, the present invention provides a method for checking the validity of data transmission using the above-described system, the method comprising the steps of: (a) reading original data; (b) performing a shift operation on data units of the original data according to a shift operation rule; (c) adding all data of the data units after the shift operation to obtain a checksum1; (d) regarding the last 2m bytes of the checksum1 as a checksum11, and calculating a 2's complement of the checksum11 to obtain a check-code; (e) packing the check-code with the original data into a data packet; (f) sending the data packet to the data receiving computer via the network; (g) receiving the data packet from the data transmitting sending computer; (h) unpacking the data packet to obtain the original data and the check-code; (i) performing a shift operation on data units of the unpacked original data according to the shift operation rule; (j) adding all data of the data units after the shift operation of the immediately preceding step to obtain a checksum2; (k) regarding the last 2m bytes of the checksum2 as a checksum22, and adding the checksum22 to the check-code from the data packet to obtain a checksum3; (1) regarding the last 2m bytes of the checksum3 as a checksum33; (m) determining whether the data packet from the data transmitting computer is valid by checking whether the checksum33 equals “0”; and (n) accepting the valid data packet if the checksum33 equals “0”; or sending a request for resending of the data packet to the data transmitting computer if the checksum33 does not equal “0.”
  • In summary, the system and method for checking the validity of data transmission can reliably check whether the data are valid. That is, whether of not interfering factors during transmission through the network have caused any data bits to exchange places.
  • Other objects, advantages and novel features of the present invention will be drawn from the following detailed description with reference to the attached drawings, in which:
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram of hardware infrastructure of a system for checking the validity of data transmission in accordance with the preferred embodiment of the present invention;
  • FIG. 2 is a schematic diagram of data structures of original data, any one data unit, any one data byte, a data packet, and a corresponding data packet having errors;
  • FIG. 3 is a schematic diagram of performing a left shift operation to obtain a one-byte sized check-code in a data transmitting computer of the system of FIG. 1;
  • FIG. 4 is a schematic diagram of performing a right shift operation to obtain a one-byte sized check-code in the data transmitting computer of the system of FIG. 1; and
  • FIG. 5 is a flowchart of a preferred method for implementing the system of FIG. 1.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 is a block diagram of hardware infrastructure of a system for checking the validity of data transmission (hereinafter, “the system”) in accordance with the preferred embodiment of the present invention. The system comprises a data transmitting computer 1, a data receiving computer 2, and a network 3. The data transmitting computer 1 is connected to the data receiving computer 2 via the network 3. The data transmitting computer 1 comprises a Central Processing Unit (CPU) 11, a Peripheral Component Interface (PCI) bus 12, and a memory 13. The CPU 11 is connected to the memory 13 via the PCI bus 12. The memory 13 stores original data which need to be sent to the data receiving computer 2. The original data comprise N data units (symbolically depicted as data unit0, data unit1, data unit2, . . . , and data unit(N-1) in FIG. 2). Each data unit contains 2m bytes (symbolically depicted as byte0, byte1, . . . , and byte(2 m -1)), wherein “m” represents the number “0” or any natural number. Each byte comprises 8 bits symbolically depicted as b0, b1, b2, . . . , and b7. Each bit comprises a binary number “0” or “1.” The network 3 is an electronic communications network that supports a transmission control protocol or an Internet protocol (TCP/IP). The network 3 may be an intranet, the Internet, or any other suitable type of communications network. The CPU 11 comprises a shift operation unit 111, an addition operation unit 112, a complement operation unit 113, and a control unit 114. The shift operation unit 111 performs a shift operation on the data units of the original data. The shift operation may be either a left shift operation or a right shift operation. The addition operation unit 112 adds data in all data units after the shift operation to obtain a checksum1. The complement operation unit 113 calculates a 2's complement of the last 2m bytes of the checksum1 to obtain a check-code. The control unit 114 reads the original data from the memory 13 via the PCI bus 12, and sends a data packet to the data receiving computer 2. The data packet comprises the original data and the check-code.
  • The check-code contains 2m bytes, wherein “m” represents the number “0” or any natural number. That is, the check-code may be 1 byte, 2 bytes, 4 bytes, etc. In such case, the shift operation unit 111 shifts all the data units with a cycle of “2m” bytes, namely 8*2m bits. The shift operation may be either a left shift operation or a right shift operation. The left shift operation on the data unit(N-1) can be expressed as “2mByte(N-1)<<Mod (N−1, 8*2m),” in which the operator “<<” represents the left shift operation, and “Mod” is the abbreviation of “modulus.” Mod (N−1, 8*2m) represents a remainder produced by N−1 being divided by 8*2m, and means a digit by which the data unit(N-1) is left shifted. In comparison, the right shift operation on the data unit(N-1) can be expressed as “2m Byte(N-1)>>Mod(N−1, 8*2m),” in which the operator “>>” represents the right shift operation.
  • The data receiving computer 2 receives and checks the data packet from the data transmitting computer 1, in order to determine whether the data packet is valid. The data receiving computer 2 comprises a CPU 21. The CPU 21 comprises a shift operation unit 211, an addition operation unit 212, and a control unit 213. The shift operation unit 211 performs a shift operation on unpacked data units of the original data of the received data packet. The shift operation may be either a left shift operation or a right shift operation. The addition operation unit 212 adds the data units after the shift operation to obtain a checksum2, and further adds the last 2m bytes of the checksum2 to the check-code from the data packet to obtain a checksum3. The control unit 213 determines whether the data packet from the data transmitting computer 1 is valid by checking whether the last 2m bytes of the checksum3 equal “0.” If the last 2m bytes of the checksum3 equal “0,” the data receiving computer 2 accepts the data packet. In contrast, if the last 2m bytes of the checksum3 do not equal “0,” the data receiving computer 2 considers the data packet as being invalid, and sends a request for resending of the data packet to the data transmitting computer 1.
  • FIG. 2 is a schematic diagram of data structures of the original data, any one data unit, any one data byte, the data packet, and an error data packet. The original data comprise N data units: data unit0, data unit1, data unit2, . . . , data unit7, data unit8, . . . , and data unit(N-1). Each data unit comprises 2m data bytes: byte0, byte1, . . . , and byte(2m-1). Each data byte comprises 8 bits: b0, b1, b2, . . . , and b7. The data packet comprises the original data and a corresponding check-code. The error data packet comprises replacement original data and a corresponding check-code. The replacement original data means that one or more data units of the original data are changed or replaced, due to factors such as interference occurring during the transmission of the data through the network 3. In FIG. 2, data unit1 of the data package has been changed.
  • FIG. 3 is a schematic diagram of performing a left shift operation to obtain a one-byte sized check-code in the data transmitting computer 1. For simplicity, the following description assumes that the check-code has a size of 1 byte (8 bits); that is, m equals “0.” The control unit 114 reads original data from the memory 13. The original data comprises N data units. Each data unit comprises one byte. The shift operation unit 111 left shifts byte(N-1) by a digit of Mod ((N−1), 8). According to this rule, data unit0 (byte0 in FIG. 3) remains unchanged because Mod (0, 8) is “0.” Byte1 is left shifted by 1 digit because Mod (1, 8) is “1.” Therefore, byte8 remains unchanged, and byte9 is left shifted by 1 digit. After the shift operation is performed, the addition operation unit 112 adds all the data units to obtain a checksum1 symbolically depicted as “ck . . . c8c7c6c5c4c3c2c1c0,” and regards the last 8 bits (one byte) of the checksum1 “c7c6c5c4c3c2c1c0” as a checksum11. The complement operation unit 113 calculates a 2's complement of the checksum11 to obtain a check-code symbolically depicted as “d7d6d5d4d3d2d1d0.” The data transmitting computer 1 sends the check-code together with the original data as the data packet to the data receiving computer 2.
  • FIG. 4 is a schematic diagram of performing a right shift operation to obtain a one-byte sized check-code in the data transmitting computer 1. The procedures are the same as those described above in relation to FIG. 3, except for replacing the left shift operation by the right shift operation.
  • FIG. 5 is a flowchart of a preferred method for implementing the system. In step S100, the CPU 11 reads original data from the memory 13 via the PCI bus 12. The shift operation unit 111 left/right shifts the data in the data units of the original data according to the appropriate shift operation rule described above. The addition operation unit 112 adds all data of the data units after the shift operation to obtain a checksum1. In step S101, the control unit 114 regards the last 8 bits of the checksum1 as a checksum11. In step S102, the complement operation unit 113 calculates a 2's complement of the checksum11 to obtain a check-code. In step S103, the control unit 114 packs the check-code with the original data into a data packet, and sends the data packet to the data receiving computer 2 via the network 3. In step S104, the data receiving computer 2 unpacks the data packet so that the contents thereof reverts to the original data and the check-code. The shift operation unit 211 left/right shifts the data units of the original data according to the shift operation performed by the shift operation unit 111. This means that, for example, if the shift operation unit 111 performed a left shift operation, the shift operation unit 211 also performs a left shift operation. The addition operation unit 212 adds all data in the data units after the shift operation to obtain a checksum2. In step S105, the control unit 213 regards the last 8 bits of the checksum2 as a checksum22. In step S106, the addition operation unit 212 adds the checksum22 to the check-code from the data packet to obtain a checksum3. In step 107, the control unit 213 regards the last 8 bits of the checksum 3 as a checksum33, and determines whether the checksum33 equals “0.” If the checksum33 equals “0,” the control unit 213 determines that the received data packet is valid. Then in step 108, the data receiving computer 2 accepts the valid data packet, whereupon the procedure is finished. If the checksum33 does not equal “0,” the control unit 213 determines that the received data packet is invalid. Then in step 109, the data receiving computer 2 sends a request for resending of the data packet to the data transmitting computer 1, whereupon the procedure returns to step S100 described above.
  • The following describes an example of implementing the system. A plurality of the following data bytes are ready to be sent: “45h,” “7Eh,” “33h,” “51h,” “BCh,” “20h,” “11h,” “08h,” “6Fh,” “4Ah,” “59h” and “09h” (h expresses a hexadecimal number). First, the shift operation unit 111 left shifts the data bytes. That is, 45h<<0, 7Eh<<1, 33h<<2, 51h<<3, BCh<<4, 20h<<5, 11h<<6, 08h<<7, 6Fh<<0, 4Ah<<1, 59h<<2, and 09h<<3. The addition operation unit 112 adds the data bytes to obtain a checksum1. That is, the checksum1=45h<<0+7Eh<<1+33h<<2+51h<<3+BCh<<4+20h<<5+11 h<<6+08h<<7+6Fh<<0+4Ah<<1+59h<<2+0 9h<<3=55Eh. The control unit 114 regards the last 8 bits of the checksum1 as a checksum11; that is, the checksum11=5Eh. The complement operation unit 113 calculates a 2's complement of the checksum11 to obtain a check-code. In this example, the check-code=A2h. Then, the control unit 114 packs the data bytes and the check-code “A2h” into a data packet, and sends the data packet to the data receiving computer 2 via the network 3. Now assume that the data bytes “33h” and “20h,” and the data bytes “7Eh” and “09h,” exchange places during the transmission. This can occur due to one or more factors such as interference on the network 3.
  • The data receiving computer 2 receives and unpacks the received data packet to obtain the data bytes and the check-code: “45h,” “09h,” “20h,” “51h,” “BCh,” “33h,” “11h,” “08h,” “6Fh,” “4Ah,” “59h,” “7Eh,” and “A2h.” The shift operation unit 211 left shifts the data bytes to obtain a checksum2. That is, the checksum2=45h<<0+09h<<1+20h<<2+51 h<<3+BCh<<4+33h<<5+11 h<<6+08h<<7+6Fh<<0+4Ah<<1+59h<<2+7Eh<<3=4 35h. The control unit 213 regards the last 8 bits of the checksum2 as a checksum22; that is, the checksum22=35h. The addition operation unit 212 adds the check-code and the checksum22 to obtain a checksum3; that is, the checksum3=check-code+checksum22=A2h+35h=D7h. Obviously, the last 8 bits of the checksum3 do not equal “0.” Therefore the control unit 213 regards the received data packet as being invalid. Then, the receiving computer 2 sends a request for resending of the data packet to the data transmitting computer 1.
  • Although the present invention has been specifically described on the basis of a preferred embodiment and preferred method, the invention is not to be construed as being limited thereto. Various changes or modifications may be made to the embodiment and method without departing from the scope and spirit of the invention.

Claims (16)

  1. 1. A system for checking the validity of data transmission, the system comprising a data transmitting computer, a data receiving computer, and a network, wherein:
    the data transmitting computer is provided for generating a check-code of original data, and sending a data packet, which comprises the original data and the check-code, to the data receiving computer via the network, the data transmitting computer comprising a Central Processing Unit (CPU), a Peripheral Component Interface (PCI) bus, and a memory, the CPU of the data transmitting computer comprising:
    a shift operation unit for performing a shift operation on data units of the original data;
    an addition operation unit for adding data in all data units after the shift operation to obtain a checksum1;
    a complement operation unit for calculating a 2's complement of the last 2m bytes of the checksum1 to obtain a check-code; and
    a control unit for reading the original data from the memory via the PCI bus, and sending a data packet including the original data and the check-code to the data receiving computer; and
    the data receiving computer is provided for receiving the data packet from the data transmitting computer, checking and determining whether the data packet is valid, the data receiving computer comprising a CPU, the CPU of the data receiving computer comprising:
    a shift operation unit for performing a shift operation on the data units of the original data unpacked from the received data packet;
    an addition operation unit for adding the data units after the shift operation to obtain a checksum2, and adding the last 2m bytes of the checksum2 to the check-code from the received data packet to obtain a checksum3; and
    a control unit for determining whether the data packet from the data transmitting computer is valid by checking whether the last 2m bytes of the checksum3 equals “0;”
    wherein “m” represents the number “0” or any natural number.
  2. 2. The system according to claim 1, wherein the memory is used for storing the original data to be sent to the data receiving computer.
  3. 3. The system according to claim 1, wherein the shift operation performed by the shift operation units of the data transmitting computer and the data receiving computer is a left shift operation.
  4. 4. The system according to claim 1, wherein the shift operation performed by the shift operation units of the data transmitting computer and the data receiving computer is a right shift operation.
  5. 5. The system according to claim 1, wherein each of the data units comprises 2m bytes of the original data.
  6. 6. A computer-based method for checking the validity of data transmission from a data transmitting computer to a data receiving computer through a network, the method comprising the steps of:
    reading original data;
    performing a shift operation on data units of the original data according to a shift operation rule;
    adding all data of the data units after the shift operation to obtain a checksum1;
    regarding the last 2m bytes of the checksum1 as a checksum 11;
    calculating a 2's complement of the checksum11 to obtain a check-code;
    packing the check-code with the original data into a data packet;
    sending the data packet to the data receiving computer via the network;
    unpacking the data packet to obtain the original data and the check-code;
    performing a shift operation on the data units of the unpacked original data according to the shift operation rule;
    adding all data of the data units after the shift operation of the immediately preceding step to obtain a checksum2;
    regarding the last 2m bytes of the checksum2 as a checksum22;
    adding the checksum22 to the check-code from the data packet to obtain a checksum3;
    regarding the last 2m bytes of the checksum3 as a checksum33;
    determining whether the data packet from the data transmitting computer is valid by checking whether the checksum33 equals “0;” and
    accepting the valid data packet if the checksum33 equals “0;”
    wherein “m” represents the number “0” or any natural number.
  7. 7. The method according to claim 6, further comprising the step of sending a request for resending of the data packet to the data transmitting computer if the checksum33 does not equal “0.”
  8. 8. The method according to claim 6, wherein each of the data units comprises 2m bytes of the original data.
  9. 9. The method according to claim 6, wherein the shift operation rule is either a left shift operation rule or a right shift operation rule.
  10. 10. A method for checking validity of data transmission from a data transmitting computer to a data receiving computer through a network, the method comprising the steps of:
    reading data from said data transmitting computer;
    retrieving a first checksum value based on said data;
    retrieving a first check code based on parts of said first checksum value;
    transmitting said data and said first check code to said data receiving computer through said network;
    retrieving a second checksum value based on said transmitted data;
    retrieving a second check code based on parts of said second checksum value; and
    evaluating said validity of said data transmission according to said first and second check codes.
  11. 11. The method according to claim 10, wherein said first and second checksum values are retrieved in a same way, and said parts of said first checksum value used to create said first check code have a binary length same as said parts of said second checksum value used to create said second check code.
  12. 12. The method according to claim 10, wherein at least one of said first and second checksum values is retrieved by performing a shift operation on said data first and adding up said data.
  13. 13. The method according to claim 10, wherein at least one of said first and second check codes is retrieved by selecting the last 2m bytes of said first and second checksum value correspondingly.
  14. 14. The method according to claim 10, wherein said first check code is retrieved by calculating a 2's complement of said parts of said first checksum value.
  15. 15. The method according to claim 10, wherein said second check code is retrieved by directly use said parts of said second checksum value as said second check code.
  16. 16. The method according to claim 10, wherein parts of a sum of said first and second check codes are evaluated to decide said validity of said data transmission.
US11025557 2004-04-09 2004-12-29 System and method for checking validity of data transmission Expired - Fee Related US7463649B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW93109875 2004-04-09
TW93109875 2004-09-04

Publications (2)

Publication Number Publication Date
US20060050737A1 true true US20060050737A1 (en) 2006-03-09
US7463649B2 US7463649B2 (en) 2008-12-09

Family

ID=35996141

Family Applications (1)

Application Number Title Priority Date Filing Date
US11025557 Expired - Fee Related US7463649B2 (en) 2004-04-09 2004-12-29 System and method for checking validity of data transmission

Country Status (1)

Country Link
US (1) US7463649B2 (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080049259A1 (en) * 2006-08-22 2008-02-28 Konica Minolta Business Technologies, Inc., Image processing method carrying out verification of correctness of embedment data and identification of embedment data, data detection method, image processing apparatus, and recording medium recording computer program therefor
US20090003228A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Bad data packet capture device
US20090007141A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Message passing with a limited number of dma byte counters
US20090006810A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Mechanism to support generic collective communication across a variety of programming models
US20090006762A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Method and apparatus of prefetching streams of varying prefetch depth
US20090006769A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Programmable partitioning for high-performance coherence domains in a multiprocessor system
US7793038B2 (en) 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
US7802025B2 (en) 2007-06-26 2010-09-21 International Business Machines Corporation DMA engine for repeating communication patterns
US7827391B2 (en) 2007-06-26 2010-11-02 International Business Machines Corporation Method and apparatus for single-stepping coherence events in a multiprocessor system under software control
US7886084B2 (en) 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US8010875B2 (en) 2007-06-26 2011-08-30 International Business Machines Corporation Error correcting code with chip kill capability and power saving enhancement
US8108738B2 (en) 2007-06-26 2012-01-31 International Business Machines Corporation Data eye monitor method and apparatus
US8140925B2 (en) 2007-06-26 2012-03-20 International Business Machines Corporation Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
US8230433B2 (en) 2007-06-26 2012-07-24 International Business Machines Corporation Shared performance monitor in a multiprocessor system
US8458282B2 (en) 2007-06-26 2013-06-04 International Business Machines Corporation Extended write combining using a write continuation hint flag
US8468416B2 (en) 2007-06-26 2013-06-18 International Business Machines Corporation Combined group ECC protection and subgroup parity protection
US8509255B2 (en) 2007-06-26 2013-08-13 International Business Machines Corporation Hardware packet pacing using a DMA in a parallel computer
US8756350B2 (en) 2007-06-26 2014-06-17 International Business Machines Corporation Method and apparatus for efficiently tracking queue entries relative to a timestamp
US20160241361A1 (en) * 2015-02-17 2016-08-18 Sk Hynix Memory Solutions Inc. Embedded system and method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7571377B2 (en) * 2005-12-22 2009-08-04 International Business Machines Corporation Method and apparatus for transmitting data in an integrated circuit

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563746A (en) * 1994-11-17 1996-10-08 Cirrus Logic, Inc. Real time media defect scanning in a sampled amplitude read channel
US5600663A (en) * 1994-11-16 1997-02-04 Lucent Technologies Inc. Adaptive forward error correction system
US5815516A (en) * 1996-04-05 1998-09-29 International Business Machines Corporation Method and apparatus for producing transmission control protocol checksums using internet protocol fragmentation
US6128763A (en) * 1998-09-01 2000-10-03 Motorola, Inc. Dynamically changing forward error correction and automatic request for repetition
US6279140B1 (en) * 1999-01-07 2001-08-21 International Business Machines Corporation Method and apparatus for checksum verification with receive packet processing
US6587526B1 (en) * 1999-10-12 2003-07-01 Lucent Technologies Inc. Apparatus and method for timing synchronization in OFDM-based wireless systems
US6792049B1 (en) * 2000-06-15 2004-09-14 Mitsubishi Electric Research Laboratories, Inc. Digital transceiver system with adaptive channel pre-coding in an asymmetrical communications network
US6952454B1 (en) * 2000-03-22 2005-10-04 Qualcomm, Incorporated Multiplexing of real time services and non-real time services for OFDM systems
US7036065B2 (en) * 2002-03-18 2006-04-25 Harris Corporation ARQ combining holdoff system and method
US7296057B2 (en) * 2002-01-08 2007-11-13 International Business Machines Corporation Method for user-specified error correction in an instant messaging system

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5600663A (en) * 1994-11-16 1997-02-04 Lucent Technologies Inc. Adaptive forward error correction system
US5563746A (en) * 1994-11-17 1996-10-08 Cirrus Logic, Inc. Real time media defect scanning in a sampled amplitude read channel
US5815516A (en) * 1996-04-05 1998-09-29 International Business Machines Corporation Method and apparatus for producing transmission control protocol checksums using internet protocol fragmentation
US6128763A (en) * 1998-09-01 2000-10-03 Motorola, Inc. Dynamically changing forward error correction and automatic request for repetition
US6279140B1 (en) * 1999-01-07 2001-08-21 International Business Machines Corporation Method and apparatus for checksum verification with receive packet processing
US6587526B1 (en) * 1999-10-12 2003-07-01 Lucent Technologies Inc. Apparatus and method for timing synchronization in OFDM-based wireless systems
US6952454B1 (en) * 2000-03-22 2005-10-04 Qualcomm, Incorporated Multiplexing of real time services and non-real time services for OFDM systems
US6792049B1 (en) * 2000-06-15 2004-09-14 Mitsubishi Electric Research Laboratories, Inc. Digital transceiver system with adaptive channel pre-coding in an asymmetrical communications network
US7296057B2 (en) * 2002-01-08 2007-11-13 International Business Machines Corporation Method for user-specified error correction in an instant messaging system
US7036065B2 (en) * 2002-03-18 2006-04-25 Harris Corporation ARQ combining holdoff system and method

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080049259A1 (en) * 2006-08-22 2008-02-28 Konica Minolta Business Technologies, Inc., Image processing method carrying out verification of correctness of embedment data and identification of embedment data, data detection method, image processing apparatus, and recording medium recording computer program therefor
US8010875B2 (en) 2007-06-26 2011-08-30 International Business Machines Corporation Error correcting code with chip kill capability and power saving enhancement
US20090007141A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Message passing with a limited number of dma byte counters
US20090006810A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Mechanism to support generic collective communication across a variety of programming models
US20090006762A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Method and apparatus of prefetching streams of varying prefetch depth
US20090006769A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Programmable partitioning for high-performance coherence domains in a multiprocessor system
US7701846B2 (en) * 2007-06-26 2010-04-20 International Business Machines Corporation Bad data packet capture device
US7793038B2 (en) 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
US7802025B2 (en) 2007-06-26 2010-09-21 International Business Machines Corporation DMA engine for repeating communication patterns
US7827391B2 (en) 2007-06-26 2010-11-02 International Business Machines Corporation Method and apparatus for single-stepping coherence events in a multiprocessor system under software control
US7877551B2 (en) 2007-06-26 2011-01-25 International Business Machines Corporation Programmable partitioning for high-performance coherence domains in a multiprocessor system
US7886084B2 (en) 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US7984448B2 (en) 2007-06-26 2011-07-19 International Business Machines Corporation Mechanism to support generic collective communication across a variety of programming models
US20090003228A1 (en) * 2007-06-26 2009-01-01 International Business Machines Corporation Bad data packet capture device
US8032892B2 (en) 2007-06-26 2011-10-04 International Business Machines Corporation Message passing with a limited number of DMA byte counters
US8103832B2 (en) 2007-06-26 2012-01-24 International Business Machines Corporation Method and apparatus of prefetching streams of varying prefetch depth
US8108738B2 (en) 2007-06-26 2012-01-31 International Business Machines Corporation Data eye monitor method and apparatus
US8140925B2 (en) 2007-06-26 2012-03-20 International Business Machines Corporation Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
US8230433B2 (en) 2007-06-26 2012-07-24 International Business Machines Corporation Shared performance monitor in a multiprocessor system
US8458282B2 (en) 2007-06-26 2013-06-04 International Business Machines Corporation Extended write combining using a write continuation hint flag
US8468416B2 (en) 2007-06-26 2013-06-18 International Business Machines Corporation Combined group ECC protection and subgroup parity protection
US8509255B2 (en) 2007-06-26 2013-08-13 International Business Machines Corporation Hardware packet pacing using a DMA in a parallel computer
US8756350B2 (en) 2007-06-26 2014-06-17 International Business Machines Corporation Method and apparatus for efficiently tracking queue entries relative to a timestamp
US8904392B2 (en) 2007-06-26 2014-12-02 International Business Machines Corporation Shared performance monitor in a multiprocessor system
US9252814B2 (en) 2007-06-26 2016-02-02 International Business Machines Corporation Combined group ECC protection and subgroup parity protection
US20160241361A1 (en) * 2015-02-17 2016-08-18 Sk Hynix Memory Solutions Inc. Embedded system and method thereof

Also Published As

Publication number Publication date Type
US7463649B2 (en) 2008-12-09 grant

Similar Documents

Publication Publication Date Title
Plummer Ethernet Address Resolution Protocol: Or converting network protocol addresses to 48. bit Ethernet address for transmission on Ethernet hardware
US6363479B1 (en) System and method for signing markup language data
US6625764B1 (en) Testing using test packets containing random data
US7804862B1 (en) Token ID mechanism for network data transfer
EP0464562B1 (en) Method and apparatus for decryption of an information packet having a format subject to modification
US6252891B1 (en) System and method to insert timestamp information in a protocol neutral manner
US20030108044A1 (en) Stateless TCP/IP protocol
US20040218623A1 (en) Hardware calculation of encapsulated IP, TCP and UDP checksums by a switch fabric channel adapter
US20060059400A1 (en) System and method for in-line consistency checking of packetized data
US6061741A (en) Method and apparatus for synchronization of connectionless applications across a network by using simple encryption tokens
US20040017806A1 (en) Method and apparatus for round trip delay measurement in a bi-directional, point-to-point, serial data channel
US20060088060A1 (en) Signature field in a latency measurement frame
US5058109A (en) Exclusionary network adapter apparatus and related method
US6289023B1 (en) Hardware checksum assist for network protocol stacks
US6412092B1 (en) Method and apparatus to reduce the cost of preparing the checksum for out bound data in network communication protocols by caching
US6643818B1 (en) Storing and using the history of data transmission errors to assure data integrity
US20030066016A1 (en) Methodology for detecting lost packets
US6819681B1 (en) Systems and methods for predicting data fields in layered protocols
US6922785B1 (en) Apparatus and a method for secure communications for network computers
US20030152036A1 (en) Apparatus and method of splitting a data stream over multiple transport control protocol/internet protocol (TCP/IP) connections
US6697366B1 (en) Ethernet memory management system and methods for operation thereof
US20030110279A1 (en) Apparatus and method of generating an XML schema to validate an XML document used to describe network protocol packet exchanges
US6445717B1 (en) System for recovering lost information in a data stream
US7249306B2 (en) System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
US20050034048A1 (en) Reliable communication between multi-processor clusters of multi-cluster computer systems

Legal Events

Date Code Title Description
AS Assignment

Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HSU, CHUN-PIN;REEL/FRAME:016139/0734

Effective date: 20041210

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Expired due to failure to pay maintenance fee

Effective date: 20161209