US20050188198A1 - Managing a secure platform using a hierarchical executive architecture in isolated execution mode - Google Patents

Managing a secure platform using a hierarchical executive architecture in isolated execution mode Download PDF

Info

Publication number
US20050188198A1
US20050188198A1 US11/115,829 US11582905A US2005188198A1 US 20050188198 A1 US20050188198 A1 US 20050188198A1 US 11582905 A US11582905 A US 11582905A US 2005188198 A1 US2005188198 A1 US 2005188198A1
Authority
US
United States
Prior art keywords
isolated
processor
initialization software
pe
execution mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/115,829
Inventor
Carl Ellison
Roger Golliver
Howard Herbert
Derrick Lin
Francis McKeen
Gilbert Neiger
Ken Reneris
James Sutton
Shreekant Thakkar
Millind Mittal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US09/539,344 priority Critical patent/US6957332B1/en
Priority to US09/668,585 priority patent/US6941458B1/en
Application filed by Intel Corp filed Critical Intel Corp
Priority to US11/115,829 priority patent/US20050188198A1/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITTAL, MILLIND, LIN, DERRICK C., ELLISON, CARL, THAKKAR, SHREEKANT S., MCKEEN, FRANCIS X., RENERIS, KEN, GOLLIVER, ROGER, NEIGER, GILBERT, HERBERT, HOWARD C., SUTTON, JAMES A.
Publication of US20050188198A1 publication Critical patent/US20050188198A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14Protection against unauthorised use of memory or access to memory
    • G06F12/1458Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1491Protection against unauthorised use of memory or access to memory by checking the subject access rights in a hierarchical protection system, e.g. privilege levels, memory rings
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode

Abstract

An example processing system comprises a processor to execute in an isolated execution mode in a ring 0 operating mode. The processor also supports one or more higher ring operating modes, as well as a normal execution mode. The processing system also comprises memory, as well as a machine-accessible medium having instructions. When the processing system executes the instructions, the processing system configures the processor to run in the isolated execution mode, configures the processing system to establish an isolated memory area in the memory, and loads initialization software into the isolated memory area. The processing system may provide a manifest that represents the initialization software. The initialization software may be verified, based at least in part on the manifest.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • This is a continuation-in-part of U.S. patent application Ser. No. 09/539,344 filed Mar. 31, 2000.
  • BACKGROUND
  • 1. Field of the Invention
  • This invention relates to microprocessors. In particular, the invention relates to processor security.
  • 2. Description of Related Art
  • Advances in microprocessor and communication technologies have opened up many opportunities for applications that go beyond the traditional ways of doing business. Electronic commerce (E-commerce) and business-to-business (B2B) transactions are now becoming popular, reaching the global markets at a fast rate. Unfortunately, while modern microprocessor systems provide users convenient and efficient methods of doing business, communicating and transacting, they are also vulnerable for unscrupulous attacks. Examples of these attacks include theft of data, virus, intrusion, security breach, and tampering, to name a few. Computer security, therefore, is becoming more and more important to protect the integrity of the computer systems and increase the trust of users.
  • Threats caused by unscrupulous attacks may be in a number of forms. An invasive remote-launched attack by hackers may disrupt the normal operation of a system connected to thousands or even millions of users. A virus program may corrupt code and/or data of a single-user platform.
  • Existing techniques to protect against attacks have a number of drawbacks. Anti-virus programs can only scan and detect known viruses. Security co-processors or smart cards using cryptographic or other security techniques have limitations in speed performance, memory capacity, and flexibility. Redesigning operating systems creates software compatibility issues and causes tremendous investment in development efforts.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:
  • FIG. 1A is a diagram illustrating a logical architecture according to one embodiment of the invention.
  • FIG. 1B is a diagram illustrating accessibility of various elements in the operating system and the processor according to one embodiment of the invention.
  • FIG. 1C is a diagram illustrating a computer system in which one embodiment of the invention can be practiced.
  • FIG. 2 is a diagram illustrating an executive subsystem according to one embodiment of the invention.
  • FIG. 3 is a diagram illustrating a processor executive handler shown in FIG. 2 according to one embodiment of the invention.
  • FIG. 4 is a diagram illustrating a processor executive shown in FIG. 2 according to one embodiment of the invention.
  • FIG. 5 is a diagram illustrating an operating system executive shown in FIG. 2 according to one embodiment of the invention.
  • FIG. 6 is a diagram illustrating a boot-up code shown in FIG. 2 according to one embodiment of the invention.
  • FIG. 7 is a flowchart illustrating a process to manage a secure platform according to one embodiment of the invention.
  • FIG. 8 is a flowchart illustrating a process to boot up platform according to one embodiment of the invention.
  • FIG. 9 is a flowchart illustrating a process to execute an isolated create instruction according to one embodiment of the invention.
  • FIG. 10 is a flowchart illustrating a process to handle a processor executive according to one embodiment of the invention.
  • FIG. 11 is a flowchart illustrating a process to handle an operating system executive according to one embodiment of the invention.
  • DESCRIPTION
  • The present invention is a method and apparatus to manage a secure platform. A processor executive (PE) handles an operating system executive (OSE) in a secure environment. The secure environment has a platform key (PK) and is associated with an isolated memory area in the platform. The OSE manages a subset of an operating system (OS) running on the platform. The platform has a processor operating in one of a normal execution mode and an isolated execution mode. The isolated memory area is accessible to the processor in the isolated execution mode. A PE supplement supplements the PE with a PE manifest representing the PE and a PE identifier to identify the PE. A PE handler handles the PE using the PK and the PE supplement.
  • A boot-up code boots up the platform following a power on. The secure environment includes an OSE supplement to supplement the OSE with an OSE manifest representing the OSE and an OSE identifier to identify the OSE. The PE handler includes a PE loader, a PE manifest verifier, a PE verifier, a PE key generator, a PE identifier logger, and a PE entrance/exit handler. The PE loader loads the PE and the PE supplement from a PE memory into the isolated memory area using a parameter block provided by the boot-up code. The PE manifest verifier verifies the PE manifest. The PE verifier verifies the PE using the PE manifest and a constant derived from the PK. The PE key generator generates a PE key using the PK. The PE key generator includes a PE key combiner to combine the PE identifier and the PK. The combined PE identifier and the PK correspond to the PE key. The PE identifier logger logs the PE identifier in a storage. The PE entrance/exit handler handles a PE entry and a PE exit.
  • The OSE handler includes an OSE loader, an OSE manifest verifier, an OSE verifier, an OSE key generator, an OSE identifier logger, and an OSE entrance/exit handler. The OSE loader loads the OSE and the OSE supplement into the isolated memory area. The OSE manifest verifier verifies the OSE manifest. The OSE verifier verifies the OSE. The OSE key generator generates an OSE key. The OSE identifier logger logs the OSE identifier in a storage. The OSE entrance/exit handler handles an OSE entry and an OSE exit. The OSE key generator includes a binding key generator and an OSE key combiner. The binding key generator generates a binding key (BK) using the PE key. The OSE key combiner combines the OSE identifier and the BK. The combined OSE identifier and the BK correspond to the OSE key.
  • The OSE includes a module loader and evictor, a key binder and unbinder, a page manager, an interface handler, a scheduler and balancer, and an interrupt handler. The module loader and evictor loads and evicts a module into and out of the isolated memory area, respectively. The module is one of an application module, an applet module, and a support module. The page manager manages paging in the isolated memory area. The interface handler handles interface with the OS. The key binder and unbinder includes an applet key generator to generate an applet key associating with the applet module. The applet key generator includes an applet key combiner to combine the OSE key with an applet identifier identifying the applet module. The combined OSE key and the applet identifier correspond to the applet key.
  • The boot up code includes a PE locator, a PE recorder, and an instruction invoker. The PE locator locates the PE and the PE supplement. The PE locator transfers the PE and the PE supplement into the PE memory at a PE address. The PE recorder records the PE address in the parameter block. The instruction invoker executes an isolated create instruction which loads the PE handler into the isolated memory area. The isolated create instruction performs an atomic non-interruptible sequence. The atomic sequence includes a number of operations: a physical memory operation, an atomic read-and-increment operation, an isolated memory area control operation, a processor isolated execution operation, an PE handler loading operation, a PE handler verification, and an exit operation. The physical memory operation verifies if the processor is in a flat physical page mode. The atomic read-and-increment operation reads and increments a thread count register in a chipset. The read-and-increment operation determines if the processor is the first processor in the isolated execution mode. The isolated memory area control operation configures the chipset using a configuration storage. The processor isolated execution operation configures the processor in the isolated execution mode. The processor isolated execution operation includes a chipset read operation and a processor configuration operation. The chipset read operation reads the configuration storage in the chipset when the processor is not a first processor in the isolated execution mode. The processor configuration operation configures the processor according to the configuration storage when the processor is not a first processor in the isolated execution mode. The PE handler loading operation loads the PE handler into the isolated memory area. The PE handler verification verifies the loaded PE handler. The exit operation transfers control to the loaded PE handler.
  • The chipset includes at least one of a memory controller hub (MCH) and an input/output controller hub (ICH). The storage is in an input/output controller hub (ICH) external to the processor.
  • In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention.
  • Architecture Overview
  • One principle for providing security in a computer system or platform is the concept of an isolated execution architecture. The isolated execution architecture includes logical and physical definitions of hardware and software components that interact directly or indirectly with an operating system of the computer system or platform. An operating system and the processor may have several levels of hierarchy, referred to as rings, corresponding to various operational modes. A ring is a logical division of hardware and software components that are designed to perform dedicated tasks within the operating system. The division is typically based on the degree or level of privilege, namely, the ability to make changes to the platform. For example, a ring-0 is the innermost ring, being at the highest level of the hierarchy. Ring-0 encompasses the most critical, privileged components. In addition, modules in Ring-0 can also access to lesser privileged data, but not vice versa. Ring-3 is the outermost ring, being at the lowest level of the hierarchy. Ring-3 typically encompasses users or applications level and executes the least trusted code. It is noted that the level of the ring hierarchy is independent to the level of the security protection of that ring.
  • FIG. 1A is a diagram illustrating a logical operating architecture 50 according to one embodiment of the invention. The logical operating architecture 50 is an abstraction of the components of an operating system and the processor. The logical operating architecture 50 includes ring-0 10, ring-1 20, ring-2 30, ring-3 40, and a processor nub loader 52. The processor nub loader 52 is an instance of a processor executive (PE) handler. The PE handler is used to handle and/or manage a processor executive (PE) as will be discussed later. The logical operating architecture 50 has two modes of operation: normal execution mode and isolated execution mode. Each ring in the logical operating architecture 50 can operate in both modes. The processor nub loader 52 operates only in the isolated execution mode.
  • Ring-0 10 includes two portions: a normal execution Ring-0 11 and an isolated execution Ring-0 15. The normal execution Ring-0 11 includes software modules that are critical for the operating system, usually referred to as kernel. These software modules include primary operating system (e.g., kernel) 12, software drivers 13, and hardware drivers 14. The isolated execution Ring-0 15 includes an operating system (OS) nub 16 and a processor nub 18. The OS nub 16 and the processor nub 18 are instances of an OS executive (OSE) and processor executive (PE), respectively. The OSE and the PE are part of executive entities that operate in a secure environment associated with the isolated area 70 and the isolated execution mode. The processor nub loader 52 is a protected bootstrap loader code held within a chipset in the system and is responsible for loading the processor nub 18 from the processor or chipset into an isolated area as will be explained later.
  • Similarly, ring-1 20, ring-2 30, and ring-3 40 include normal execution ring-1 21, ring-2 31, ring-3 41, and isolated execution ring-1 25, ring-2 35, and ring-3 45, respectively. In particular, normal execution ring-3 includes N applications 42 1 to 42 N and isolated execution ring-3 includes K applets 46 1 to 46 K.
  • One concept of the isolated execution architecture is the creation of an isolated region in the system memory, referred to as an isolated area, which is protected by both the processor and chipset in the computer system. Portions of the isolated region may also be in cache memory. Access to this isolated region is permitted only from a front side bus (FSB) of the processor, using special bus (e.g., memory read and write) cycles, referred to as isolated read and write cycles. The special bus cycles are also used for snooping. The isolated read and write cycles are issued by the processor executing in an isolated execution mode when accessing the isolated area. The isolated execution mode is initialized using a privileged instruction in the processor, combined with the processor nub loader 52. The processor nub loader 52 verifies and loads a ring-0 nub software module (e.g., processor nub 18) into the isolated area. The processor nub 18 provides hardware-related services for the isolated execution.
  • One task of the processor nub loader 52 and processor nub 18 is to verify and load the ring-0 OS nub 16 into the isolated area, and to generate the root of a key hierarchy unique to a combination of the platform, the processor nub 18, and the operating system nub 16. The operating system nub 16 provides links to services in the primary OS 12 (e.g., the unprotected operating system), provides page management within the isolated area, and has the responsibility for loading ring-3 application modules 45, including applets 46 1 to 46 K, into protected pages allocated in the isolated area. The operating system nub 16 may also load ring-0 supporting modules.
  • The operating system nub 16 may choose to support paging of data between the isolated area and ordinary (e.g., non-isolated) memory. If so, then the operating system nub 16 is also responsible for encrypting and hashing the isolated area pages before evicting the page to the ordinary memory, and for checking the page contents upon restoration of the page. The isolated mode applets 46 1 to 46 K and their data are tamper-resistant and monitor-resistant from all software attacks from other applets, as well as from non-isolated-space applications (e.g., 42 1 to 42 N), drivers and even the primary operating system 12. The only software that can interfere with or monitor the applet's execution is the processor nub loader 52, processor nub 18 or the operating system nub 16.
  • FIG. 1B is a diagram illustrating accessibility of various elements in the operating system 10 and the processor according to one embodiment of the invention. For illustration purposes, only elements of ring-0 10 and ring-3 40 are shown. The various elements in the logical operating architecture 50 access an accessible physical memory 60 according to their ring hierarchy and the execution mode.
  • The accessible physical memory 60 includes an isolated area 70 and a non-isolated area 80. The isolated area 70 includes applet pages 72 and nub pages 74. The non-isolated area 80 includes application pages 82 and operating system pages 84. The isolated area 70 is accessible only to elements of the operating system and processor operating in isolated execution mode. The non-isolated area 80 is accessible to all elements of the ring-0 operating system and to the processor.
  • The normal execution ring-0 11 including the primary OS 12, the software drivers 13, and the hardware drivers 14, can access both the OS pages 84 and the application pages 82. The normal execution ring-3, including applications 42 1 to 42 N, can access only to the application pages 82. Generally applications can only access to their own pages, however, the OS typically provides services for sharing memory in controlled methods. Both the normal execution ring-0 11 and ring-3 41, however, cannot access the isolated area 70.
  • The isolated execution ring-0 15, including the OS nub 16 and the processor nub 18, can access to both of the isolated area 70, including the applet pages 72 and the nub pages 74, and the non-isolated area 80, including the application pages 82 and the OS pages 84. The isolated execution ring-3 45, including applets 46 1 to 46 K, can access only applet pages 72. The applets 46 1 to 46 K reside in the isolated area 70. In general, applets can only access their own pages; however, the OS nub 16 can also provides services for the applet to share memory (e.g., share memory with other applets or with non-isolated area applications).
  • FIG. 1C is a diagram illustrating a computer system 100 in which one embodiment of the invention can be practiced. The computer system 100 includes a processor 110, a host bus 120, a memory controller hub (MCH) 130, a system memory 140, an input/output controller hub (ICH) 150, a non-volatile memory, or system flash, 160, a mass storage device 170, input/output devices 175, a token bus 180, a motherboard (MB) token 182, a reader 184, and a token 186. The MCH 130 may be integrated into a chipset that integrates multiple functionalities such as the isolated execution mode, host-to-peripheral bus interface, memory control. Similarly, the ICH 150 may also be integrated into a chipset together or separate from the MCH 130 to perform I/O functions. For clarity, not all the peripheral buses are shown. It is contemplated that the system 100 may also include peripheral buses such as Peripheral Component Interconnect (PCI), accelerated graphics port (AGP), Industry Standard Architecture (ISA) bus, and Universal Serial Bus (USB), etc. The “token bus” may be part of the USB bus, e.g., it may be hosted on the USB bus.
  • The processor 110 represents a central processing unit of any type of architecture, such as complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture. In one embodiment, the processor 110 is compatible with an Intel Architecture (IA) processor, such as the Pentium™ series, the IA-32™ and the IA-64™. The processor 110 includes a normal execution mode 112 and an isolated execution circuit 115. The normal execution mode 112 is the mode in which the processor 110 operates in a non-secure environment, or a normal environment without the security features provided by the isolated execution mode. The isolated execution circuit 115 provides a mechanism to allow the processor 110 to operate in an isolated execution mode. The isolated execution circuit 115 provides hardware and software support for the isolated execution mode. This support includes configuration for isolated execution, definition of an isolated area, definition (e.g., decoding and execution) of isolated instructions, generation of isolated access bus cycles, and access checking.
  • In one embodiment, the computer system 100 can be a single processor system, such as a desktop computer, which has only one main central processing unit, e.g. processor 110. In other embodiments, the computer system 100 can include multiple processors, e.g. processors 110, 110 a, 110 b, etc., as shown in FIG. 1C. Thus, the computer system 100 can be a multi-processor computer system having any number of processors. For example, the multi-processor computer system 100 can operate as part of a server or workstation environment. The basic description and operation of processor 110 will be discussed in detail below. It will be appreciated by those skilled in the art that the basic description and operation of processor 110 applies to the other processors 110 a and 110 b, shown in FIG. 1C, as well as any number of other processors that may be utilized in the multi-processor computer system 100 according to one embodiment of the present invention.
  • The processor 110 may also have multiple logical processors. A logical processor, sometimes referred to as a thread, is a functional unit within a physical processor having an architectural state and physical resources allocated according to some partitioning policy. Within the context of the present invention, the terms “thread” and “logical processor” are used to mean the same thing. A multi-threaded processor is a processor having multiple threads or multiple logical processors. A multi-processor system (e.g., the system comprising the processors 110, 110 a, and 110 b) may have multiple multi-threaded processors.
  • The host bus 120 provides interface signals to allow the processor 110 or processors 110, 100 a, and 110 b to communicate with other processors or devices, e.g., the MCH 130. In addition to normal mode, the host bus 120 provides an isolated access bus mode with corresponding interface signals for memory read and write cycles. The isolated access bus mode is asserted on memory accesses initiated while the processor 110 is in the isolated execution mode and it is accessing memory within the isolated area. The isolated access bus mode is also asserted on instruction pre-fetch and cache write-back cycles if the address is within the isolated area address range. The isolated access bus mode is configured within the processor 110. The processor 110 responds to a snoop cycle to a cached address when the isolated access bus mode on the FSB matches the mode of the cached address.
  • The MCH 130 provides control and configuration of system memory 140. The MCH 130 provides interface circuits to recognize and service isolated access assertions on memory reference bus cycles, including isolated memory read and write cycles. In addition, the MCH 130 has memory range registers (e.g., base and length registers) to represent the isolated area in the system memory 140. Once configured, the MCH 130 aborts any access to the isolated area that does not have the isolated access bus mode asserted.
  • The system memory 140 stores system code and data. The system memory 140 is typically implemented with dynamic random access memory (DRAM) or static random access memory (SRAM). The system memory 140 includes the accessible physical memory 60 (shown in FIG. 1B). The accessible physical memory includes a loaded operating system 142, the isolated area 70 (shown in FIG. 1B), and an isolated control and status space 148. The loaded operating system 142 is the portion of the operating system that is loaded into the system memory 140. The loaded OS 142 is typically loaded from a mass storage device via some boot code in a boot storage such as a boot read only memory (ROM). The isolated area 70, as shown in FIG. 1B, is the memory area that is defined by the processor 110 when operating in the isolated execution mode. Access to the isolated area 70 is restricted and is enforced by the processor 110 and/or the MCH 130 or other chipset that integrates the isolated area functionalities. The isolated control and status space 148 is an input/output (I/O)-like, independent address space defined by the processor 110. The isolated control and status space 148 contains mainly the isolated execution control and status registers. The isolated control and status space 148 does not overlap any existing address space and is accessed using the isolated bus cycles. The system memory 140 may also include other programs or data that are not shown.
  • The ICH 150 represents a known single point in the system having the isolated execution functionality. For clarity, only one ICH 150 is shown. The system 100 may have many ICH's similar to the ICH 150. When there are multiple ICH's, a designated ICH is selected to control the isolated area configuration and status. In one embodiment, this selection is performed by an external strapping pin. As is known by one skilled in the art, other methods of selecting can be used, including using programmable configuring registers. The ICH 150 has a number of functionalities that are designed to support the isolated execution mode in addition to the traditional I/O functions. In particular, the ICH 150 includes an isolated bus cycle interface 152, the processor nub loader 52 (shown in FIG. 1A), a digest memory 154, a cryptographic key storage 155, an isolated execution logical processor manager 156, and a token bus interface 159.
  • The isolated bus cycle interface 152 includes circuitry to interface to the isolated bus cycle signals to recognize and service isolated bus cycles, such as the isolated read and write bus cycles. The processor nub loader 52, as shown in FIG. 1A, includes a processor nub loader code and its digest (e.g., cryptographic hash) value. The processor nub loader 52 is invoked by execution of an appropriate isolated instruction (e.g., Iso_Init) and is transferred to the isolated area 70. From the isolated area 80, the processor nub loader 52 copies the processor nub 18 from the system flash memory (e.g., the processor nub code 18 in non-volatile memory 160) into the isolated area 70, verifies and logs its integrity, and manages a symmetric key used to protect the processor nub's secrets. In one embodiment, the processor nub loader 52 is implemented in read only memory (ROM). For security purposes, the processor nub loader 52 is unchanging, tamper-resistant and non-substitutable. The digest memory 154, typically implemented in RAM, stores the digest (e.g., cryptographic hash) values of the loaded processor nub 18, the operating system nub 16, and any other supervisory modules (e.g., ring-0 modules) loaded into the isolated execution space. The cryptographic key storage 155 holds a symmetric encryption/decryption key that is unique for the platform of the system 100. In one embodiment, the cryptographic key storage 155 includes internal fuses that are programmed at manufacturing. Alternatively, the cryptographic key storage 155 may also be created during manufacturing with a cryptographic random number generator. The isolated execution logical processor manager 156 manages the operation of logical processors configuring their isolated execution mode support. In one embodiment, the isolated execution logical processor manager 156 includes a logical processor count register that tracks the number of logical processors participating in the isolated execution mode. The token bus interface 159 interfaces to the token bus 180. A combination of the processor nub loader digest, the processor nub digest, the operating system nub digest, and optionally additional digests, represents the overall isolated execution digest, referred to as isolated digest. The isolated digest is a fingerprint identifying the all supervisory code involved in controlling the isolated execution configuration and operation. The isolated digest is used to attest or prove the state of the current isolated execution environment.
  • The non-volatile memory 160 stores non-volatile information. Typically, the non-volatile memory 160 is implemented in flash memory. In one embodiment, the non-volatile memory 160 includes the processor nub 18. The processor nub 18 provides set-up and low-level management of the isolated area 70 (in the system memory 140), including verification, loading, and logging of the operating system nub 16, and the management of the symmetric key used to protect the operating system nub's secrets. The processor nub loader 52 performs some part of the setup and manages/updates the symmetric key before the processor nub 18 and the OS nub 16 are loaded. The processor nub 18 The processor nub 18 may also provide interface abstractions to low-level security services provided by other hardware. The processor nub 18 may also be distributed by the original equipment manufacturer (OEM) or operating system vendor (OSV).
  • The mass storage device 170 stores archive information such as code (e.g., processor nub 18), programs, files, data, applications (e.g., applications 42 1 to 42 N), applets (e.g., applets 46 1 to 46 K) and operating systems. The mass storage device 170 may include compact disk (CD) ROM 172, floppy diskettes 174, and hard drive 176, and any other storage devices. The mass storage device 170 provides a mechanism to read machine-readable media. When implemented in software, the elements of the present invention are the code segments to perform the necessary tasks. The program or code segments can be stored in a processor readable medium or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium. The “processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable programmable ROM (EPROM), a floppy diskette, a compact disk CD-ROM, an optical disk, a hard disk, a fiber optical medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, an Intranet, etc.
  • I/O devices 175 may include any I/O devices to perform I/O functions. Examples of I/O devices 175 include a controller for input devices (e.g., keyboard, mouse, trackball, pointing device), media card (e.g., audio, video, graphics), a network card, and any other peripheral controllers.
  • The token bus 180 provides an interface between the ICH 150 and various tokens in the system. A token is a device that performs dedicated input/output functions with security functionalities. A token has characteristics similar to a smart card, including at least one reserved-purpose public/private key pair and the ability to sign data with the private key. Examples of tokens connected to the token bus 180 include a motherboard token 182, a token reader 184, and other portable tokens 186 (e.g., smart card). The token bus interface 159 in the ICH 150 connects through the token bus 180 to the ICH 150 and ensures that when commanded to prove the state of the isolated execution, the corresponding token (e.g., the motherboard token 182, the token 186) signs only valid isolated digest information. For purposes of security, the token should be connected to the digest memory via the token bus 180.
  • A Hierarchical Executive Architecture to Manage a Secure Platform
  • The overall architecture discussed above provides a basic insight into a hierarchical executive architecture to manage a secure platform. The elements shown in FIGS. 1A, 1B, and 1C are instances of an abstract model of this hierarchical executive architecture. The implementation of this hierarchical executive architecture is a combination of hardware and software. In what follows, the processor executive, the processor executive handler, and the operating system executive are abstract models of the processor nub 18, the processor nub loader 52, and the operating system nub 16 (FIGS. 1A, 1B, and 1C), respectively.
  • FIG. 2 is a diagram illustrating an executive subsystem 200 according to one embodiment of the invention. The executive subsystem 200 includes a processor executive (PE) 210, a PE supplement 220, a PE handler 230, a boot-up code 240, and a secure environment 250.
  • The processor executive (PE) 210 handles an operating system executive (OSE) 270 in the secure environment 250. The PE supplement 220 supplements the PE with a PE manifest 222 representing the PE and a PE identifier 224 to identify the PE. The PE handler 230 handles the PE 210 using a platform key (PK) 260 in the secure environment 250 and the PE supplement 220. The PE 210 and the PE supplement 220 are located in a PE memory 215. The PE memory 215 is located in the non-isolated memory area 80.
  • The PE handler 230 handles the PE 210 using the PK 260 and the PE supplement 220. The PE handler 230 obtains information to locate the PE memory 215 via a parameter block 242 provided by the boot-up code 240.
  • The boot-up code 240 boots up the platform following a power on. The boot-up code 240 obtains an original PE 246 and an original PE supplement 248 from a system ROM (e.g., system flash 160 as shown in FIG. 1C)
  • The secure environment 250 includes a platform key (PK) 260, an operating system executive (OSE) 270, and an OSE supplement 280. The OSE supplement 280 supplements the OSE 270 with an OSE manifest 282 representing the OSE and an OSE identifier 284 to identify the OSE. The secure environment 250 is associated with an isolated memory area 70 (FIG. 1C) in the platform. The OSE 270 manages a subset 295 of an operating system (OS) 290 running on the platform. The platform has a processor 110 operating in one of a normal execution mode 112 and an isolated execution mode 115 as shown in FIG. 1C. The isolated memory area 70 is accessible to the processor 110 in the isolated execution mode 115.
  • FIG. 3 is a diagram illustrating the PE handler 230 shown in FIG. 2 according to one embodiment of the invention. The PE handler 230 includes a PE loader 310, a PE manifest verifier 320, a PE verifier 330, a PE Error Generator 340, a Constant Driver 350, a PE key generator 360, a PE identifier logger 370, and a PE entrance/exit handler 380.
  • The PE loader 310 loads the PE 210 and the PE supplement 220 from the PE memory 215 (FIG. 2) into the isolated memory area 70 using a PE address in the parameter block 242 (FIG. 2) provided by the boot-up code 240. The PE loader 310 provides a loaded PE manifest 322 and a loaded PE 312 located in the isolated memory area 70 and corresponding to the PE manifest 322 and the PE 312, respectively.
  • The PE manifest verifier 320 verifies the PE manifest 222 by comparing the PE manifest 222 with the loaded PE manifest 322 and generates a result to a PE error generator 340. If the verification fails, the error generator 340 generates a failure or fault condition with an error code associated with the PE manifest verification.
  • The PE verifier 330 verifies the PE 210 using the verified loaded PE manifest 322 and a constant 355 derived from the PK 260 by a constant deriver 350. Essentially, the PE verifier 330 compares the PE 210 with the loaded PE 312. In addition, the PE verifier 330 determines a manifest of the loaded PE 312 using the constant 355 and compares the determined PE manifest with the verified loaded PE manifest 322. The PE verifier 330 then generates a result to the PE error generator 340. If the verification fails, the error generator 340 generates a failure or fault condition with an error code associated with the PE verification.
  • The PE key generator 360 generates a PE key 365 using the PK 260. The PE key generator 360 includes a PE key combiner 364 to combine the PE identifier 224 and the PK 260. The combined PE identifier 224 and the PK 260 correspond to the PE key 365.
  • The PE identifier logger 370 logs the PE identifier 224 in a storage 375. The PE identifier logger 370 writes the PE identifier 224 into the storage 375. The storage 375 is a register located inside a chipset such as the ICH 150 shown in FIG. 1C.
  • The PE entrance/exit handler 380 handles a PE entrance and a PE exit. The PE entrance includes obtaining the entry point in the configuration buffer of the processor 110 to represent the PE's entry handler. The PE exit returns control to the boo-up code 240.
  • FIG. 4 is a diagram illustrating the PE 210 shown in FIG. 2 according to one embodiment of the invention. The PE 210 includes an OSE loader 410, an OSE manifest verifier 420, an OSE verifier 430, an OSE Error Generator 440, an OSE key generator 460, an OSE identifier logger 470, and an OSE entrance/exit handler 480.
  • The OSE loader 410loads the OSE 270 and the OSE supplement 280 into the isolated memory area 70 as shown in FIG. 2 using an OSE parameter block 405 provided by the OS 290. The OSE loader 410 provides a loaded OSE manifest 422 and a loaded OSE 412 located in the isolated memory area 70 and corresponding to the OSE manifest 282 and the OSE 270, respectively.
  • The OSE manifest verifier 420 verifies the OSE manifest 282 by comparing the OSE manifest 282 with the loaded OSE manifest 422. The OSE manifest verifier 420 generates a result to an OSE error generator 440. If the verification fails, the OSE error generator 440 generates a failure or fault condition with an error code associated with the OSE manifest verification.
  • The OSE verifier 430 verifies the OSE 270. Essentially, the OSE verifier 430 compares the OSE 270 with the loaded OSE 412. In addition, the OSE verifier 430 determines a manifest of the loaded OSE 412 using a root key and compares the determined OSE manifest with the verified loaded OSE manifest 422. The OSE verifier 430 then generates a result to the OSE error generator 440. If the verification fails, the OSE error generator 440 generates a failure or fault condition with an error code associated with the OSE verification.
  • The OSE key generator 460 generates an OSE key 465. The OSE key generator 460 includes a binding key (BK) generator 462 and an OSE key combiner 464. The binding key generator 462 generates a binding key (BK) 463 using the PE key 365 (FIG. 3). The OSE key combiner 464 combines the OSE identifier 284 and the BK 463. The combined OSE identifier 284 and the BK 463 correspond to the OSE key 465.
  • The OSE identifier logger 470 logs the OSE identifier 284 in the storage 375. The storage 375 is a register located inside a chipset such as the ICH 150 shown in FIG. 1C.
  • The OSE entrance/exit handler 480 handles an OSE entrance and an OSE exit. The OSE entrance initializes parameters in a frame buffer and saves appropriate control parameters and transfers control to an entrance handler. The OSE exit clears and creates appropriate return parameters and then transfers control to the exit handler,
  • FIG. 5 is a diagram illustrating the OSE 270 shown in FIG. 2 according to one embodiment of the invention. The OSE 270 includes a module loader and evictor 510, a page manager 520, an interface handler 530, a key binder and unbinder 540, a scheduler and balancer 550, and an interrupt handler 560.
  • The module loader and evictor 510 loads and evicts a module into and out of the isolated memory area 70, respectively. The module is one of an application module 512, an applet module 514, and a support module 516. The page manager 520 manages paging in the isolated memory area 70. The interface handler 530 handles interface with the subset 295 in the OS 290 (FIG. 2). The key binder and unbinder 540 includes an applet key generator 542 to generate an applet key 545 associated with the applet module 514. The applet key generator 542 includes an applet key combiner 544 combines the OSE key 465 (FIG. 4) with an applet identifier 518 identifying the applet module 514. The combined OSE key 465 and the applet identifier 518 correspond to the applet key 545.
  • The scheduler and balancer 550 schedules execution of the loaded modules and balances the load of the isolated execution mode. The interrupt handler 560 handles interrupts and exceptions generated in the isolated execution mode.
  • FIG. 6 is a diagram illustrating a boot-up code shown in FIG. 2 according to one embodiment of the invention. The boot up code includes a PE locator 610, a PE recorder 620, and an instruction invoker 630.
  • The PE locator 610 locates the original PE 246 and the original PE supplement 248. The PE locator 610 transfers the original PE 246 and the original PE supplement 248 into the PE memory 215 at a PE address 625. The PE recorder 620 records the PE address 625 in the PE parameter block 242. As discussed above, the PE handler 230 obtains the PE address 625 from the PE parameter block 242 to locate the PE 210 and the PE supplement 220 in the PE memory 215.
  • The instruction invoker 630 invokes and executes an isolated create instruction 632 which loads the PE handler 230 into the isolated memory area 70. The isolated create instruction 632 performs an atomic non-interruptiblle sequence 640. The atomic sequence 640 includes a number of operations: a physical memory operation 652, an atomic read-and-increment operation 654, an isolated memory area control operation 656, a processor isolated execution operation 658, an PE handler loading operation 663, a PE handler verification 664, and an exit operation 666.
  • The physical memory operation 652 verifies if the processor is in a flat physical page mode. The atomic read-and-increment operation 654 reads and increments a thread count register in a chipset. The read-and-increment operation 654 determines if the processor is the first processor in the isolated execution mode. The isolated memory area control operation 656 configures the chipset using a configuration storage. The processor isolated execution operation 658 configures the processor in the isolated execution mode. The processor isolated execution operation 658 includes a chipset read operation 672 and a processor configuration operation 674. The chipset read operation 672 reads the configuration storage in the chipset when the processor is not a first processor in the isolated execution mode. The processor configuration operation 674 configures the processor according to the configuration storage read by the chipset read operation 672 when the processor is not a first processor in the isolated execution mode. The PE handler loading operation 662 loads the PE handler 230 into the isolated memory area 70. The PE handler verification 664 verifies the loaded PE handler. The exit operation 666 transfers control to the loaded PE handler.
  • FIG. 7 is a flowchart illustrating a process 700 to manage a secure platform according to one embodiment of the invention.
  • Upon START, the process 700 boots up the platform following power on (Block 710). The platform has a secure environment. The secure environment includes a platform key, an operating system executive (OSE), and an OSE supplement. The details of the Block 710 are shown in FIG. 8. Then, the process 700 handles a processor executive (PE) using the platform key and the PE supplement (Block 720). The details of the Block 720 are shown in FIG. 10. Then, the process 700 handles the OSE in the secure environment (Block 730). The details of the Block 730 are shown in FIG. 11.
  • Next, the process 700 manages a subset of an operating system running on the platform (Block 740). The process 700 is then terminated.
  • FIG. 8 is a flowchart illustrating the process 710 to boot up platform according to one embodiment of the invention.
  • Upon START, the process 710 locates the PE and the PE supplement (Block 810). Then, the process 710 transfers the PE and the PE supplement into the PE memory at a PE address (Block 820). Next, the process 710 records the PE address in a PE parameter block (Block 830). Then, the process 710 executes the isolated create instruction (Block 840). The details of the Block 840 are shown in FIG. 9. The process 710 is then terminated.
  • FIG. 9 is a flowchart illustrating the process 840 to execute an isolated create instruction according to one embodiment of the invention.
  • Upon START, the process 840 determines if the processor is in a flat physical page mode (Block 910). If not, the process 840 sets the processor in the flat physical page mode (Block 915) and proceeds to Block 920. Otherwise, the process 840 determines if the thread count register is zero (Block 920). This is done by reading the thread count register in the chipset to determine if the processor is the first processor in the isolated execution mode. If not, the process 840 determines that the processor is not the first processor in the system to be in the isolated execution mode. The process 840 then reads the configuration storage from the chipset (Block 925). Then, the process 840 configured the processor using the chipset configuration storage (Block 930). Then, the process 840 proceeds to Block 960.
  • If the thread count register is zero, the process 840 determines that the processor is the first processor in the system to be booted up with isolated execution mode. The process 840 then increments the thread count register to inform to other processors that there is already a processor being booted up in isolated execution mode (Block 935). Then, the process 840 configures the chipset and the processor in isolated execution mode by writing appropriate setting values (e.g., isolated mask and base values) in the chipset and processor configuration storage (Block 940). To configure the processor, the process 840 may also need to set up the isolated execution mode word in the control register of the processor.
  • Next, the process 840 loads the PE handler from the ROM internal to the chipset to the isolated memory area (Block 945). Then, the process 840 determines if the loaded PE handler is the same as the original PE handler in the ROM (Block 950). If not, the process 840 generates a failure or fault condition with an appropriate error code (Block 955) and is then terminated. Otherwise, the process 840 transfers control to the loaded PE handler (Block 960). The process 840 is then terminated.
  • FIG. 10 is a flowchart illustrating the process 720 to handle a processor executive according to one embodiment of the invention.
  • Upon START, the process 720 loads the PE and the PE supplement from a PE memory into the isolated memory area using a parameter block provided by the boot-up code (Block 1010). Next, the process 720 determines if the loaded PE manifest is the same as the original PE manifest (Block 1015). If not, the process 720 generates a failure or fault condition with appropriate error code (Block 1020) and is then terminated. Otherwise, the process 720 determines if the loaded PE has the same manifest as the loaded PE manifest (Block 1025). If not, the process 720 goes to Block 1020 and is then terminated. Otherwise, the process 720 generates a PE key using the platform key in the secure environment (Block 1030).
  • Then, the process 720 logs the PE identifier in a storage (Block 1035). This log storage is typically a register in an ICH. Then, the process 720 changes the entry point in the configuration buffer of the processor to prepare for an OSE entrance (Block 1040). Then, the process 720 returns to the boot-up code (Block 1045). The process 720 is then terminated.
  • FIG. 11 is a flowchart illustrating the process 730 to handle the OSE according to one embodiment of the invention.
  • Upon START, the OS boots and locates the OSE and the OSE supplement in the OSE memory at an OSE address (Block 1110). Then the OS records the OSE address in an OSE parameter block (Block 1115). Next, the process 730 determines if an OSE has already been loaded (Block 1120). If yes, the process 730 is terminated. Otherwise, the process 730 loads the OSE and the OSE supplement into the isolated memory area (Block 1125).
  • Next, the process 730 determines if the loaded OSE manifest is the same as the original OSE manifest (Block 1130). If not, the process 730 generates a failure or fault condition with an appropriate error code (Block 1135) and is then terminated. Otherwise, the process 730 determines if the loaded OSE has the same manifest as the loaded OSE manifest (Block 1140). If not, the process 730 goes to block 1135 and is then terminated. Otherwise, the process 730 generates the OSE key using the PE key and the OSE identifier (Block 1145).
  • Then, the process 730 logs the OSE identifier in a storage (Block 1150). Typically, this log storage is a register in a chipset such as the ICH. Next, the process 730 clears any PE secrets or services that are not needed (Block 1155). Then, the process 730 returns to the PE's exit handler (Block 1160). The process 730 is then terminated.
  • While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.

Claims (26)

1. A processing system, comprising:
a processor to execute in an isolated execution mode in a ring 0 operating mode, wherein the processor also supports one or more higher ring operating modes, as well as a normal execution mode in at least the ring 0 operating mode;
memory responsive to the processor; and
a machine-accessible medium responsive to the processor, the machine-accessible medium having instructions which, when executed by the processor, result in the processing system performing operations comprising:
configuring the processor to run in the isolated execution mode;
configuring the processing system to establish an isolated memory area in the memory, wherein the processing system does not allow access to the isolated memory area if the processor is not in the isolated execution mode;
loading initialization software into the isolated memory area; and
providing a manifest for the initialization software, wherein the manifest represents the initialization software.
2. A processing system according to claim 1, wherein the operations performed by the processing system further comprise:
verifying the initialization software, based at least in part on the manifest for the initialization software.
3. A processing system according to claim 2, wherein:
the processing system comprises a platform key (PK); and
verification of the initialization software is based at least in part on the PK.
4. A processing system according to claim 3, wherein the PK comprises an encryption/decryption key that is substantially uniquely assigned to the processing system.
5. A processing system according to claim 1, wherein the operations performed by the processing system further comprise:
verifying the initialization software, based at least in part on the manifest for the initialization software; and
after verifying the initialization software, launching the initialization software.
6. A processing system according to claim 5, wherein the operation of launching the initialization software comprises:
launching the initialization software to run in the isolated execution mode.
7. A processing system according to claim 1, wherein the operations performed by the processing system further comprise:
executing an isolated create instruction during a process of booting the processing system, wherein execution of the isolated create instruction launches an atomic sequence of operations, the atomic sequence being non-interruptible, the atomic sequence of operations comprising:
configuring the processor in the isolated execution mode;
verifying at least part of the initialization software; and
after successful verification, transferring control to the initialization software.
8. A method comprising:
in a platform with a processor and a memory, configuring the processor to run in an isolated execution mode in a ring 0 operating mode, wherein the processor also supports one or more higher ring operating modes, as well as a normal execution mode in at least the ring 0 operating mode;
configuring the platform to establish an isolated memory area in the memory, wherein the platform does not allow access to the isolated memory area if the processor is not in the isolated execution mode;
loading initialization software into the isolated memory area; and
providing a manifest for the initialization software, wherein the manifest represents the initialization software.
9. A method according to claim 8, further comprising:
verifying the initialization software, based at least in part on the manifest for the initialization software.
10. A method according to claim 9, further comprising:
verifying the initialization software during a process of booting the platform.
11. A method according to claim 10, wherein:
the platform comprises a platform key (PK); and
verification of the initialization software is based at least in part on the PK.
12. A method according to claim 11, wherein the PK comprises an encryption/decryption key that is substantially uniquely assigned to the platform.
13. A method according to 11, further comprising:
generating at least one additional key, based at least in part on
14. A method according to claim 8, further comprising:
verifying the initialization software, based at least in part on the manifest for the initialization software; and
after verifying the initialization software, launching the initialization software.
15. A method according to claim 12, wherein the operation of launching the initialization software comprises:
launching the initialization software to run in the isolated execution mode. the PK.
16. A method according to claim 1, wherein the operation of loading initialization software comprises loading software to perform operations comprising at least one operation from the group consisting of:
managing paging in the isolated memory area; and
interfacing with an operating system (OS).
17. A method according to claim 1, wherein the initialization software performs operations comprising:
generating an applet key associated with an applet module.
18. A method according to claim 1, further comprising:
executing an isolated create instruction during a process of booting the platform, wherein execution of the isolated create instruction launches an atomic sequence of operations, the atomic sequence being non-interruptible, the atomic sequence of operations comprising:
configuring the processor in the isolated execution mode;
verifying at least part of the initialization software; and
after successful verification, transferring control to the initialization software.
19. An article comprising a machine-accessible media having instructions which, when executed by a machine, result in the machine performing operations comprising:
configuring a processor in the machine to run in an isolated execution mode in a ring 0 operating mode, wherein the processor also supports one or more higher ring operating modes, as well as a normal execution mode in at least the ring 0 operating mode;
configuring the machine to establish an isolated memory area in a memory in the machine, wherein the machine does not allow access to the isolated memory area if the processor is not in the isolated execution mode;
loading initialization software into the isolated memory area; and
providing a manifest for the initialization software, wherein the manifest represents the initialization software.
20. An article according to claim 19, wherein the operations performed by the machine when executing the instructions further comprise:
verifying the initialization software, based at least in part on the manifest for the initialization software.
21. An article according to claim 20, wherein:
the platform comprises a platform key (PK); and
verification of the initialization software is based at least in part on the PK.
22. An article according to claim 21, wherein the PK comprises an encryption/decryption key that is substantially uniquely assigned to the platform.
23. An article according to claim 19, wherein the operations performed by the machine when executing the instructions further comprise:
verifying the initialization software, based at least in part on the manifest for the initialization software; and
after verifying the initialization software, launching the initialization software.
24. An article according to claim 23, wherein the operation of launching the initialization software comprises:
launching the initialization software to run in the isolated execution mode.
25. A method comprising:
in a platform with a processor and a memory, configuring the processor to run in an isolated execution mode in a ring 0 operating mode, wherein the processor also supports one or more higher ring operating modes, as well as a normal execution mode in at least the ring 0 operating mode;
configuring the platform to establish an isolated memory area in the memory, wherein the platform does not allow access to the isolated memory area if the processor is not in the isolated execution mode;
loading initialization software into the isolated memory area; and
providing a digest for the initialization software, the digest based at least in part on a hash value derived from initialization software.
26. A method according to claim 25, further comprising:
verifying the initialization software, based at least in part on the digest for the initialization software.
US11/115,829 2000-03-31 2005-04-26 Managing a secure platform using a hierarchical executive architecture in isolated execution mode Abandoned US20050188198A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US09/539,344 US6957332B1 (en) 2000-03-31 2000-03-31 Managing a secure platform using a hierarchical executive architecture in isolated execution mode
US09/668,585 US6941458B1 (en) 2000-03-31 2000-09-22 Managing a secure platform using a hierarchical executive architecture in isolated execution mode
US11/115,829 US20050188198A1 (en) 2000-03-31 2005-04-26 Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/115,829 US20050188198A1 (en) 2000-03-31 2005-04-26 Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/668,585 Continuation US6941458B1 (en) 2000-03-31 2000-09-22 Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Publications (1)

Publication Number Publication Date
US20050188198A1 true US20050188198A1 (en) 2005-08-25

Family

ID=34885941

Family Applications (3)

Application Number Title Priority Date Filing Date
US09/539,344 Active US6957332B1 (en) 2000-03-31 2000-03-31 Managing a secure platform using a hierarchical executive architecture in isolated execution mode
US09/668,585 Active 2022-10-01 US6941458B1 (en) 2000-03-31 2000-09-22 Managing a secure platform using a hierarchical executive architecture in isolated execution mode
US11/115,829 Abandoned US20050188198A1 (en) 2000-03-31 2005-04-26 Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US09/539,344 Active US6957332B1 (en) 2000-03-31 2000-03-31 Managing a secure platform using a hierarchical executive architecture in isolated execution mode
US09/668,585 Active 2022-10-01 US6941458B1 (en) 2000-03-31 2000-09-22 Managing a secure platform using a hierarchical executive architecture in isolated execution mode

Country Status (1)

Country Link
US (3) US6957332B1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060015719A1 (en) * 2000-03-31 2006-01-19 Herbert Howard C Platform and method for remote attestation of a platform
US7380278B2 (en) 2000-03-31 2008-05-27 Intel Corporation Protecting software environment in isolated execution
US20090038017A1 (en) * 2007-08-02 2009-02-05 David Durham Secure vault service for software components within an execution environment
US8499151B2 (en) 2005-06-30 2013-07-30 Intel Corporation Secure platform voucher service for software components within an execution environment
EP2765530A1 (en) * 2013-02-11 2014-08-13 Intel Corporation Securing display output data against malicious software attacks

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI115257B (en) * 2001-08-07 2005-03-31 Nokia Corp A method for processing information in an electronic device, a system, an electronic device and a processor block
US7130951B1 (en) * 2002-04-18 2006-10-31 Advanced Micro Devices, Inc. Method for selectively disabling interrupts on a secure execution mode-capable processor
US7451324B2 (en) * 2002-05-31 2008-11-11 Advanced Micro Devices, Inc. Secure execution mode exceptions
US7103914B2 (en) * 2002-06-17 2006-09-05 Bae Systems Information Technology Llc Trusted computer system
US20050010752A1 (en) * 2003-06-23 2005-01-13 Nokia, Inc. Method and system for operating system anti-tampering
US20050021977A1 (en) * 2003-06-25 2005-01-27 Microsoft Corporation Expression-based access control
US8468330B1 (en) * 2003-06-30 2013-06-18 Oracle International Corporation Methods, systems, and data structures for loading and authenticating a module
US20050044408A1 (en) * 2003-08-18 2005-02-24 Bajikar Sundeep M. Low pin count docking architecture for a trusted platform
US7137016B2 (en) * 2003-09-10 2006-11-14 Intel Corporation Dynamically loading power management code in a secure environment
US7496958B2 (en) * 2003-10-29 2009-02-24 Qualcomm Incorporated System for selectively enabling operating modes of a device
US20060048222A1 (en) * 2004-08-27 2006-03-02 O'connor Clint H Secure electronic delivery seal for information handling system
US7752436B2 (en) * 2005-08-09 2010-07-06 Intel Corporation Exclusive access for secure audio program
US10063523B2 (en) * 2005-09-14 2018-08-28 Oracle International Corporation Crafted identities
US20070179802A1 (en) * 2005-09-14 2007-08-02 Novell, Inc. Policy enforcement via attestations
US8214296B2 (en) * 2006-02-14 2012-07-03 Microsoft Corporation Disaggregated secure execution environment
US20070192824A1 (en) * 2006-02-14 2007-08-16 Microsoft Corporation Computer hosting multiple secure execution environments
US8429429B1 (en) * 2009-10-23 2013-04-23 Secure Vector, Inc. Computer security system and method
US10242182B2 (en) 2009-10-23 2019-03-26 Secure Vector, Llc Computer security system and method
US9454652B2 (en) 2009-10-23 2016-09-27 Secure Vector, Llc Computer security system and method
US8775802B1 (en) 2009-10-23 2014-07-08 Secure Vector Computer security system and method
US8843732B2 (en) * 2009-12-21 2014-09-23 Intel Corporation Mechanism for detecting a no-processor swap condition and modification of high speed bus calibration during boot
US8938796B2 (en) 2012-09-20 2015-01-20 Paul Case, SR. Case secure computer architecture
CN105899872A (en) 2013-12-10 2016-08-24 斯维尔博专利有限公司 A swivelling joint

Citations (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4037214A (en) * 1976-04-30 1977-07-19 International Business Machines Corporation Key register controlled accessing system
US4162536A (en) * 1976-01-02 1979-07-24 Gould Inc., Modicon Div. Digital input/output system and method
US4207609A (en) * 1978-05-08 1980-06-10 International Business Machines Corporation Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system
US4247905A (en) * 1977-08-26 1981-01-27 Sharp Kabushiki Kaisha Memory clear system
US4276594A (en) * 1978-01-27 1981-06-30 Gould Inc. Modicon Division Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same
US4278837A (en) * 1977-10-31 1981-07-14 Best Robert M Crypto microprocessor for executing enciphered programs
US4319323A (en) * 1980-04-04 1982-03-09 Digital Equipment Corporation Communications device for data processing system
US4319233A (en) * 1978-11-30 1982-03-09 Kokusan Denki Co., Ltd. Device for electrically detecting a liquid level
US4430709A (en) * 1980-09-13 1984-02-07 Robert Bosch Gmbh Apparatus for safeguarding data entered into a microprocessor
US4521852A (en) * 1982-06-30 1985-06-04 Texas Instruments Incorporated Data processing device formed on a single semiconductor substrate having secure memory
US4571672A (en) * 1982-12-17 1986-02-18 Hitachi, Ltd. Access control method for multiprocessor systems
US4759064A (en) * 1985-10-07 1988-07-19 Chaum David L Blind unanticipated signature systems
US4795893A (en) * 1986-07-11 1989-01-03 Bull, Cp8 Security device prohibiting the function of an electronic data processing unit after a first cutoff of its electrical power
US4802084A (en) * 1985-03-11 1989-01-31 Hitachi, Ltd. Address translator
US5007082A (en) * 1988-08-03 1991-04-09 Kelly Services, Inc. Computer software encryption apparatus
US5022077A (en) * 1989-08-25 1991-06-04 International Business Machines Corp. Apparatus and method for preventing unauthorized access to BIOS in a personal computer system
US5079737A (en) * 1988-10-25 1992-01-07 United Technologies Corporation Memory management unit for the MIL-STD 1750 bus
US5187802A (en) * 1988-12-26 1993-02-16 Hitachi, Ltd. Virtual machine system with vitual machine resetting store indicating that virtual machine processed interrupt without virtual machine control program intervention
US5188257A (en) * 1987-10-15 1993-02-23 The Coca-Cola Company Supply of controlled, medium-pressure carbon dioxide gas in simple, convenient disposable packaging
US5230069A (en) * 1990-10-02 1993-07-20 International Business Machines Corporation Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system
US5287363A (en) * 1991-07-01 1994-02-15 Disk Technician Corporation System for locating and anticipating data storage media failures
US5293424A (en) * 1992-10-14 1994-03-08 Bull Hn Information Systems Inc. Secure memory card
US5295251A (en) * 1989-09-21 1994-03-15 Hitachi, Ltd. Method of accessing multiple virtual address spaces and computer system
US5303378A (en) * 1991-05-21 1994-04-12 Compaq Computer Corporation Reentrant protected mode kernel using virtual 8086 mode interrupt service routines
US5317705A (en) * 1990-10-24 1994-05-31 International Business Machines Corporation Apparatus and method for TLB purge reduction in a multi-level machine system
US5319760A (en) * 1991-06-28 1994-06-07 Digital Equipment Corporation Translation buffer for virtual machines with address space match
US5386552A (en) * 1991-10-21 1995-01-31 Intel Corporation Preservation of a computer system processing state in a mass storage device
US5421006A (en) * 1992-05-07 1995-05-30 Compaq Computer Corp. Method and apparatus for assessing integrity of computer system software
US5437033A (en) * 1990-11-16 1995-07-25 Hitachi, Ltd. System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode
US5504922A (en) * 1989-06-30 1996-04-02 Hitachi, Ltd. Virtual machine with hardware display controllers for base and target machines
US5506975A (en) * 1992-12-18 1996-04-09 Hitachi, Ltd. Virtual machine I/O interrupt control method compares number of pending I/O interrupt conditions for non-running virtual machines with predetermined number
US5511217A (en) * 1992-11-30 1996-04-23 Hitachi, Ltd. Computer system of virtual machines sharing a vector processor
US5522075A (en) * 1991-06-28 1996-05-28 Digital Equipment Corporation Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces
US5604805A (en) * 1994-02-28 1997-02-18 Brands; Stefanus A. Privacy-protected transfer of electronic information
US5606617A (en) * 1994-10-14 1997-02-25 Brands; Stefanus A. Secret-key certificates
US5615263A (en) * 1995-01-06 1997-03-25 Vlsi Technology, Inc. Dual purpose security architecture with protected internal operating system
US5628022A (en) * 1993-06-04 1997-05-06 Hitachi, Ltd. Microcomputer with programmable ROM
US5633929A (en) * 1995-09-15 1997-05-27 Rsa Data Security, Inc Cryptographic key escrow system having reduced vulnerability to harvesting attacks
US5706469A (en) * 1994-09-12 1998-01-06 Mitsubishi Denki Kabushiki Kaisha Data processing system controlling bus access to an arbitrary sized memory area
US5717903A (en) * 1995-05-15 1998-02-10 Compaq Computer Corporation Method and appartus for emulating a peripheral device to allow device driver development before availability of the peripheral device
US5729760A (en) * 1996-06-21 1998-03-17 Intel Corporation System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode
US5737604A (en) * 1989-11-03 1998-04-07 Compaq Computer Corporation Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
US5737760A (en) * 1995-10-06 1998-04-07 Motorola Inc. Microcontroller with security logic circuit which prevents reading of internal memory by external program
US5740178A (en) * 1996-08-29 1998-04-14 Lucent Technologies Inc. Software for controlling a reliable backup memory
US5752046A (en) * 1993-01-14 1998-05-12 Apple Computer, Inc. Power management system for computer device interconnection bus
US5758124A (en) * 1994-11-18 1998-05-26 Seiko Epson Corporation Computer emulator
US5757919A (en) * 1996-12-12 1998-05-26 Intel Corporation Cryptographically protected paging subsystem
US5764969A (en) * 1995-02-10 1998-06-09 International Business Machines Corporation Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization
US5872994A (en) * 1995-11-10 1999-02-16 Nec Corporation Flash memory incorporating microcomputer having on-board writing function
US5890189A (en) * 1991-11-29 1999-03-30 Kabushiki Kaisha Toshiba Memory management and protection system for virtual memory in computer system
US5898883A (en) * 1994-01-25 1999-04-27 Hitachi, Ltd. Memory access mechanism for a parallel processing computer system with distributed shared memory
US5901225A (en) * 1996-12-05 1999-05-04 Advanced Micro Devices, Inc. System and method for performing software patches in embedded systems
US5919257A (en) * 1997-08-08 1999-07-06 Novell, Inc. Networked workstation intrusion detection system
US6014745A (en) * 1997-07-17 2000-01-11 Silicon Systems Design Ltd. Protection for customer programs (EPROM)
US6035374A (en) * 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6044478A (en) * 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6055637A (en) * 1996-09-27 2000-04-25 Electronic Data Systems Corporation System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential
US6058478A (en) * 1994-09-30 2000-05-02 Intel Corporation Apparatus and method for a vetted field upgrade
US6061794A (en) * 1997-09-30 2000-05-09 Compaq Computer Corp. System and method for performing secure device communications in a peer-to-peer bus architecture
US6075938A (en) * 1997-06-10 2000-06-13 The Board Of Trustees Of The Leland Stanford Junior University Virtual machine monitors for scalable multiprocessors
US6085296A (en) * 1997-11-12 2000-07-04 Digital Equipment Corporation Sharing memory pages and page tables among computer processes
US6173417B1 (en) * 1998-04-30 2001-01-09 Intel Corporation Initializing and restarting operating systems
US6175925B1 (en) * 1996-06-13 2001-01-16 Intel Corporation Tamper resistant player for scrambled contents
US6175924B1 (en) * 1997-06-20 2001-01-16 International Business Machines Corp. Method and apparatus for protecting application data in secure storage areas
US6178509B1 (en) * 1996-06-13 2001-01-23 Intel Corporation Tamper resistant methods and apparatus
US6182089B1 (en) * 1997-09-23 2001-01-30 Silicon Graphics, Inc. Method, system and computer program product for dynamically allocating large memory pages of different sizes
US6192455B1 (en) * 1998-03-30 2001-02-20 Intel Corporation Apparatus and method for preventing access to SMRAM space through AGP addressing
US6199152B1 (en) * 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US6205550B1 (en) * 1996-06-13 2001-03-20 Intel Corporation Tamper resistant methods and apparatus
US6212635B1 (en) * 1997-07-18 2001-04-03 David C. Reardon Network security system allowing access and modification to a security subsystem after initial installation when a master token is in place
US6222923B1 (en) * 1996-11-28 2001-04-24 Deutsche Telekom Ag Method for securing system protected by a key hierarchy
US6226749B1 (en) * 1995-07-31 2001-05-01 Hewlett-Packard Company Method and apparatus for operating resources under control of a security module or other secure processor
US20010003745A1 (en) * 1996-11-25 2001-06-14 Azriel Schmidt Combination of an agent that binds to the androgen receptor and a bisphosphonic acid in the prevention and/or treatment of diseases involving calcium or phosphate metabolism
US6249872B1 (en) * 1996-02-09 2001-06-19 Intel Corporation Method and apparatus for increasing security against unauthorized write access to a protected memory
US6252650B1 (en) * 1999-09-09 2001-06-26 Nikon Corporation Exposure apparatus, output control method for energy source, laser device using the control method, and method of producing microdevice
US6339816B1 (en) * 1997-08-19 2002-01-15 Siemens Noxdorf Informationssysteme Aktiengesellschaft Method for improving controllability in data processing system with address translation
US6339815B1 (en) * 1998-08-14 2002-01-15 Silicon Storage Technology, Inc. Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space
US6357004B1 (en) * 1997-09-30 2002-03-12 Intel Corporation System and method for ensuring integrity throughout post-processing
US6363485B1 (en) * 1998-09-09 2002-03-26 Entrust Technologies Limited Multi-factor biometric authenticating device and method
US6374317B1 (en) * 1999-10-07 2002-04-16 Intel Corporation Method and apparatus for initializing a computer interface
US6374286B1 (en) * 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6378072B1 (en) * 1998-02-03 2002-04-23 Compaq Computer Corporation Cryptographic system
US6378068B1 (en) * 1991-05-17 2002-04-23 Nec Corporation Suspend/resume capability for a protected mode microprocesser
US6389537B1 (en) * 1999-04-23 2002-05-14 Intel Corporation Platform and method for assuring integrity of trusted agent communications
US6397242B1 (en) * 1998-05-15 2002-05-28 Vmware, Inc. Virtualization system including a virtual machine monitor for a computer with a segmented architecture
US6397379B1 (en) * 1999-01-28 2002-05-28 Ati International Srl Recording in a program execution profile references to a memory-mapped active device
US6412035B1 (en) * 1997-02-03 2002-06-25 Real Time, Inc. Apparatus and method for decreasing the response times of interrupt service routines
US6505279B1 (en) * 1998-08-14 2003-01-07 Silicon Storage Technology, Inc. Microcontroller system having security circuitry to selectively lock portions of a program memory address space
US6507904B1 (en) * 2000-03-31 2003-01-14 Intel Corporation Executing isolated mode instructions in a secure system running in privilege rings
US6515988B1 (en) * 1997-07-21 2003-02-04 Xerox Corporation Token-based document transactions
US6529909B1 (en) * 1999-08-31 2003-03-04 Accenture Llp Method for translating an object attribute converter in an information services patterns environment
US6535988B1 (en) * 1999-09-29 2003-03-18 Intel Corporation System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate
US6557104B2 (en) * 1997-05-02 2003-04-29 Phoenix Technologies Ltd. Method and apparatus for secure processing of cryptographic keys
US6560627B1 (en) * 1999-01-28 2003-05-06 Cisco Technology, Inc. Mutual exclusion at the record level with priority inheritance for embedded systems using one semaphore
US6678825B1 (en) * 2000-03-31 2004-01-13 Intel Corporation Controlling access to multiple isolated memories in an isolated execution environment
US6684326B1 (en) * 1999-03-31 2004-01-27 International Business Machines Corporation Method and system for authenticated boot operations in a computer system of a networked computing environment
US6701284B1 (en) * 1998-04-17 2004-03-02 Ge Fanuc Automation North America, Inc. Methods and apparatus for maintaining a programmable logic control revision history
US20060015719A1 (en) * 2000-03-31 2006-01-19 Herbert Howard C Platform and method for remote attestation of a platform

Family Cites Families (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699532A (en) 1970-04-21 1972-10-17 Singer Co Multiprogramming control for a data handling system
US3996449A (en) 1975-08-25 1976-12-07 International Business Machines Corporation Operating system authenticator
US4307678A (en) 1978-03-30 1981-12-29 Rousselle Jr Birney A Hydraulic quick release system for tub/barge connections
JPS5725860B2 (en) 1978-12-01 1982-06-01
US4307447A (en) 1979-06-19 1981-12-22 Gould Inc. Programmable controller
US4419724A (en) * 1980-04-14 1983-12-06 Sperry Corporation Main bus interface package
US4366537A (en) 1980-05-23 1982-12-28 International Business Machines Corp. Authorization mechanism for transfer of program control or data between different address spaces having different storage protect keys
US4403283A (en) 1980-07-28 1983-09-06 Ncr Corporation Extended memory system and method
US4975836A (en) 1984-12-19 1990-12-04 Hitachi, Ltd. Virtual computer system
JPH02208740A (en) 1989-02-09 1990-08-20 Fujitsu Ltd Virtual computer control system
US5781753A (en) * 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
CA2010591C (en) 1989-10-20 1999-01-26 Phillip M. Adams Kernels, description tables and device drivers
US5075842A (en) 1989-12-22 1991-12-24 Intel Corporation Disabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechanism
US5108590A (en) 1990-09-12 1992-04-28 Disanto Dennis Water dispenser
US5255379A (en) 1990-12-28 1993-10-19 Sun Microsystems, Inc. Method for automatically transitioning from V86 mode to protected mode in a computer system using an Intel 80386 or 80486 processor
US5455909A (en) 1991-07-05 1995-10-03 Chips And Technologies Inc. Microprocessor with operation capture facility
US5574936A (en) 1992-01-02 1996-11-12 Amdahl Corporation Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system
US5237616A (en) 1992-09-21 1993-08-17 International Business Machines Corporation Secure computer system having privileged and unprivileged memories
US5668971A (en) 1992-12-01 1997-09-16 Compaq Computer Corporation Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer
US5469557A (en) 1993-03-05 1995-11-21 Microchip Technology Incorporated Code protection in microcontroller with EEPROM fuses
FR2703800B1 (en) 1993-04-06 1995-05-24 Bull Cp8 The process of signing a computer file and device for setting Óoeuvre.
US5555385A (en) 1993-10-27 1996-09-10 International Business Machines Corporation Allocation of address spaces within virtual machine compute system
US5825880A (en) 1994-01-13 1998-10-20 Sudia; Frank W. Multi-step digital signature method and system
US5459869A (en) 1994-02-17 1995-10-17 Spilo; Michael L. Method for providing protected mode services for device drivers and other resident software
US5684881A (en) 1994-05-23 1997-11-04 Matsushita Electric Industrial Co., Ltd. Sound field and sound image control apparatus and method
US5539828A (en) 1994-05-31 1996-07-23 Intel Corporation Apparatus and method for providing secured communications
US5978481A (en) 1994-08-16 1999-11-02 Intel Corporation Modem compatible method and apparatus for encrypting data that is transparent to software applications
US5473692A (en) 1994-09-07 1995-12-05 Intel Corporation Roving software license for a hardware agent
DE69534757D1 (en) 1994-09-15 2006-04-13 Ibm System and method for secure storage and distribution of data using digital signatures
US5564040A (en) 1994-11-08 1996-10-08 International Business Machines Corporation Method and apparatus for providing a server function in a logically partitioned hardware machine
US5560013A (en) 1994-12-06 1996-09-24 International Business Machines Corporation Method of using a target processor to execute programs of a source architecture that uses multiple address spaces
US5555414A (en) 1994-12-14 1996-09-10 International Business Machines Corporation Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals
JP3451595B2 (en) 1995-06-07 2003-09-29 インターナショナル・ビジネス・マシーンズ・コーポレーション Microprocessor with an architecture mode control capable of supporting extensions to two separate instruction set architecture
US5684948A (en) 1995-09-01 1997-11-04 National Semiconductor Corporation Memory management circuit which provides simulated privilege levels
US6093213A (en) 1995-10-06 2000-07-25 Advanced Micro Devices, Inc. Flexible implementation of a system management mode (SMM) in a processor
IL116708A (en) 1996-01-08 2000-12-06 Smart Link Ltd Real-time task manager for a personal computer
US5657445A (en) 1996-01-26 1997-08-12 Dell Usa, L.P. Apparatus and method for limiting access to mass storage devices in a computer system
US5978892A (en) * 1996-05-03 1999-11-02 Digital Equipment Corporation Virtual memory allocation in a virtual address space having an inaccessible gap
US5809546A (en) * 1996-05-23 1998-09-15 International Business Machines Corporation Method for managing I/O buffers in shared storage by structuring buffer table having entries including storage keys for controlling accesses to the buffers
US5937063A (en) 1996-09-30 1999-08-10 Intel Corporation Secure boot
US5844986A (en) 1996-09-30 1998-12-01 Intel Corporation Secure BIOS
US5935242A (en) 1996-10-28 1999-08-10 Sun Microsystems, Inc. Method and apparatus for initializing a device
JPH10134008A (en) 1996-11-05 1998-05-22 Mitsubishi Electric Corp Semiconductor device and computer system
US5852717A (en) 1996-11-20 1998-12-22 Shiva Corporation Performance optimizations for computer networks utilizing HTTP
US5950221A (en) 1997-02-06 1999-09-07 Microsoft Corporation Variably-sized kernel memory stacks
US5953502A (en) 1997-02-13 1999-09-14 Helbig, Sr.; Walter A Method and apparatus for enhancing computer system security
JP4000654B2 (en) 1997-02-27 2007-10-31 セイコーエプソン株式会社 Semiconductor device and electronic equipment
US5987557A (en) 1997-06-19 1999-11-16 Sun Microsystems, Inc. Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU)
US5978475A (en) 1997-07-18 1999-11-02 Counterpane Internet Security, Inc. Event auditing system
US5935247A (en) 1997-09-18 1999-08-10 Geneticware Co., Ltd. Computer system having a genetic code that cannot be directly accessed and a method of maintaining the same
US6148379A (en) * 1997-09-19 2000-11-14 Silicon Graphics, Inc. System, method and computer program product for page sharing between fault-isolated cells in a distributed shared memory system
US5970147A (en) 1997-09-30 1999-10-19 Intel Corporation System and method for configuring and registering a cryptographic device
US6272533B1 (en) * 1999-02-16 2001-08-07 Hendrik A. Browne Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device
US6321314B1 (en) * 1999-06-09 2001-11-20 Ati International S.R.L. Method and apparatus for restricting memory access
US6301646B1 (en) * 1999-07-30 2001-10-09 Curl Corporation Pointer verification system and method
US6292874B1 (en) * 1999-10-19 2001-09-18 Advanced Technology Materials, Inc. Memory management method and apparatus for partitioning homogeneous memory and restricting access of installed applications to predetermined memory ranges

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4162536A (en) * 1976-01-02 1979-07-24 Gould Inc., Modicon Div. Digital input/output system and method
US4037214A (en) * 1976-04-30 1977-07-19 International Business Machines Corporation Key register controlled accessing system
US4247905A (en) * 1977-08-26 1981-01-27 Sharp Kabushiki Kaisha Memory clear system
US4278837A (en) * 1977-10-31 1981-07-14 Best Robert M Crypto microprocessor for executing enciphered programs
US4276594A (en) * 1978-01-27 1981-06-30 Gould Inc. Modicon Division Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same
US4207609A (en) * 1978-05-08 1980-06-10 International Business Machines Corporation Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system
US4319233A (en) * 1978-11-30 1982-03-09 Kokusan Denki Co., Ltd. Device for electrically detecting a liquid level
US4319323A (en) * 1980-04-04 1982-03-09 Digital Equipment Corporation Communications device for data processing system
US4430709A (en) * 1980-09-13 1984-02-07 Robert Bosch Gmbh Apparatus for safeguarding data entered into a microprocessor
US4521852A (en) * 1982-06-30 1985-06-04 Texas Instruments Incorporated Data processing device formed on a single semiconductor substrate having secure memory
US4571672A (en) * 1982-12-17 1986-02-18 Hitachi, Ltd. Access control method for multiprocessor systems
US4802084A (en) * 1985-03-11 1989-01-31 Hitachi, Ltd. Address translator
US4759064A (en) * 1985-10-07 1988-07-19 Chaum David L Blind unanticipated signature systems
US4795893A (en) * 1986-07-11 1989-01-03 Bull, Cp8 Security device prohibiting the function of an electronic data processing unit after a first cutoff of its electrical power
US5188257A (en) * 1987-10-15 1993-02-23 The Coca-Cola Company Supply of controlled, medium-pressure carbon dioxide gas in simple, convenient disposable packaging
US5007082A (en) * 1988-08-03 1991-04-09 Kelly Services, Inc. Computer software encryption apparatus
US5079737A (en) * 1988-10-25 1992-01-07 United Technologies Corporation Memory management unit for the MIL-STD 1750 bus
US5187802A (en) * 1988-12-26 1993-02-16 Hitachi, Ltd. Virtual machine system with vitual machine resetting store indicating that virtual machine processed interrupt without virtual machine control program intervention
US5504922A (en) * 1989-06-30 1996-04-02 Hitachi, Ltd. Virtual machine with hardware display controllers for base and target machines
US5022077A (en) * 1989-08-25 1991-06-04 International Business Machines Corp. Apparatus and method for preventing unauthorized access to BIOS in a personal computer system
US5295251A (en) * 1989-09-21 1994-03-15 Hitachi, Ltd. Method of accessing multiple virtual address spaces and computer system
US5737604A (en) * 1989-11-03 1998-04-07 Compaq Computer Corporation Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
US5230069A (en) * 1990-10-02 1993-07-20 International Business Machines Corporation Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system
US5317705A (en) * 1990-10-24 1994-05-31 International Business Machines Corporation Apparatus and method for TLB purge reduction in a multi-level machine system
US5437033A (en) * 1990-11-16 1995-07-25 Hitachi, Ltd. System for recovery from a virtual machine monitor failure with a continuous guest dispatched to a nonguest mode
US6378068B1 (en) * 1991-05-17 2002-04-23 Nec Corporation Suspend/resume capability for a protected mode microprocesser
US5303378A (en) * 1991-05-21 1994-04-12 Compaq Computer Corporation Reentrant protected mode kernel using virtual 8086 mode interrupt service routines
US5319760A (en) * 1991-06-28 1994-06-07 Digital Equipment Corporation Translation buffer for virtual machines with address space match
US5522075A (en) * 1991-06-28 1996-05-28 Digital Equipment Corporation Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces
US5287363A (en) * 1991-07-01 1994-02-15 Disk Technician Corporation System for locating and anticipating data storage media failures
US5386552A (en) * 1991-10-21 1995-01-31 Intel Corporation Preservation of a computer system processing state in a mass storage device
US5890189A (en) * 1991-11-29 1999-03-30 Kabushiki Kaisha Toshiba Memory management and protection system for virtual memory in computer system
US5421006A (en) * 1992-05-07 1995-05-30 Compaq Computer Corp. Method and apparatus for assessing integrity of computer system software
US5293424A (en) * 1992-10-14 1994-03-08 Bull Hn Information Systems Inc. Secure memory card
US5511217A (en) * 1992-11-30 1996-04-23 Hitachi, Ltd. Computer system of virtual machines sharing a vector processor
US5506975A (en) * 1992-12-18 1996-04-09 Hitachi, Ltd. Virtual machine I/O interrupt control method compares number of pending I/O interrupt conditions for non-running virtual machines with predetermined number
US5752046A (en) * 1993-01-14 1998-05-12 Apple Computer, Inc. Power management system for computer device interconnection bus
US5628022A (en) * 1993-06-04 1997-05-06 Hitachi, Ltd. Microcomputer with programmable ROM
US5898883A (en) * 1994-01-25 1999-04-27 Hitachi, Ltd. Memory access mechanism for a parallel processing computer system with distributed shared memory
US5604805A (en) * 1994-02-28 1997-02-18 Brands; Stefanus A. Privacy-protected transfer of electronic information
US5706469A (en) * 1994-09-12 1998-01-06 Mitsubishi Denki Kabushiki Kaisha Data processing system controlling bus access to an arbitrary sized memory area
US6058478A (en) * 1994-09-30 2000-05-02 Intel Corporation Apparatus and method for a vetted field upgrade
US5606617A (en) * 1994-10-14 1997-02-25 Brands; Stefanus A. Secret-key certificates
US5758124A (en) * 1994-11-18 1998-05-26 Seiko Epson Corporation Computer emulator
US5615263A (en) * 1995-01-06 1997-03-25 Vlsi Technology, Inc. Dual purpose security architecture with protected internal operating system
US5764969A (en) * 1995-02-10 1998-06-09 International Business Machines Corporation Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization
US5717903A (en) * 1995-05-15 1998-02-10 Compaq Computer Corporation Method and appartus for emulating a peripheral device to allow device driver development before availability of the peripheral device
US6226749B1 (en) * 1995-07-31 2001-05-01 Hewlett-Packard Company Method and apparatus for operating resources under control of a security module or other secure processor
US5633929A (en) * 1995-09-15 1997-05-27 Rsa Data Security, Inc Cryptographic key escrow system having reduced vulnerability to harvesting attacks
US5737760A (en) * 1995-10-06 1998-04-07 Motorola Inc. Microcontroller with security logic circuit which prevents reading of internal memory by external program
US5872994A (en) * 1995-11-10 1999-02-16 Nec Corporation Flash memory incorporating microcomputer having on-board writing function
US6249872B1 (en) * 1996-02-09 2001-06-19 Intel Corporation Method and apparatus for increasing security against unauthorized write access to a protected memory
US6205550B1 (en) * 1996-06-13 2001-03-20 Intel Corporation Tamper resistant methods and apparatus
US6175925B1 (en) * 1996-06-13 2001-01-16 Intel Corporation Tamper resistant player for scrambled contents
US6178509B1 (en) * 1996-06-13 2001-01-23 Intel Corporation Tamper resistant methods and apparatus
US5729760A (en) * 1996-06-21 1998-03-17 Intel Corporation System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode
US6199152B1 (en) * 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US5740178A (en) * 1996-08-29 1998-04-14 Lucent Technologies Inc. Software for controlling a reliable backup memory
US6055637A (en) * 1996-09-27 2000-04-25 Electronic Data Systems Corporation System and method for accessing enterprise-wide resources by presenting to the resource a temporary credential
US20010003745A1 (en) * 1996-11-25 2001-06-14 Azriel Schmidt Combination of an agent that binds to the androgen receptor and a bisphosphonic acid in the prevention and/or treatment of diseases involving calcium or phosphate metabolism
US6222923B1 (en) * 1996-11-28 2001-04-24 Deutsche Telekom Ag Method for securing system protected by a key hierarchy
US5901225A (en) * 1996-12-05 1999-05-04 Advanced Micro Devices, Inc. System and method for performing software patches in embedded systems
US5757919A (en) * 1996-12-12 1998-05-26 Intel Corporation Cryptographically protected paging subsystem
US6412035B1 (en) * 1997-02-03 2002-06-25 Real Time, Inc. Apparatus and method for decreasing the response times of interrupt service routines
US6557104B2 (en) * 1997-05-02 2003-04-29 Phoenix Technologies Ltd. Method and apparatus for secure processing of cryptographic keys
US6044478A (en) * 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6075938A (en) * 1997-06-10 2000-06-13 The Board Of Trustees Of The Leland Stanford Junior University Virtual machine monitors for scalable multiprocessors
US6175924B1 (en) * 1997-06-20 2001-01-16 International Business Machines Corp. Method and apparatus for protecting application data in secure storage areas
US6035374A (en) * 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6014745A (en) * 1997-07-17 2000-01-11 Silicon Systems Design Ltd. Protection for customer programs (EPROM)
US6212635B1 (en) * 1997-07-18 2001-04-03 David C. Reardon Network security system allowing access and modification to a security subsystem after initial installation when a master token is in place
US6515988B1 (en) * 1997-07-21 2003-02-04 Xerox Corporation Token-based document transactions
US5919257A (en) * 1997-08-08 1999-07-06 Novell, Inc. Networked workstation intrusion detection system
US6339816B1 (en) * 1997-08-19 2002-01-15 Siemens Noxdorf Informationssysteme Aktiengesellschaft Method for improving controllability in data processing system with address translation
US6182089B1 (en) * 1997-09-23 2001-01-30 Silicon Graphics, Inc. Method, system and computer program product for dynamically allocating large memory pages of different sizes
US6357004B1 (en) * 1997-09-30 2002-03-12 Intel Corporation System and method for ensuring integrity throughout post-processing
US6061794A (en) * 1997-09-30 2000-05-09 Compaq Computer Corp. System and method for performing secure device communications in a peer-to-peer bus architecture
US6085296A (en) * 1997-11-12 2000-07-04 Digital Equipment Corporation Sharing memory pages and page tables among computer processes
US6378072B1 (en) * 1998-02-03 2002-04-23 Compaq Computer Corporation Cryptographic system
US6192455B1 (en) * 1998-03-30 2001-02-20 Intel Corporation Apparatus and method for preventing access to SMRAM space through AGP addressing
US6374286B1 (en) * 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6701284B1 (en) * 1998-04-17 2004-03-02 Ge Fanuc Automation North America, Inc. Methods and apparatus for maintaining a programmable logic control revision history
US6173417B1 (en) * 1998-04-30 2001-01-09 Intel Corporation Initializing and restarting operating systems
US6397242B1 (en) * 1998-05-15 2002-05-28 Vmware, Inc. Virtualization system including a virtual machine monitor for a computer with a segmented architecture
US6505279B1 (en) * 1998-08-14 2003-01-07 Silicon Storage Technology, Inc. Microcontroller system having security circuitry to selectively lock portions of a program memory address space
US6339815B1 (en) * 1998-08-14 2002-01-15 Silicon Storage Technology, Inc. Microcontroller system having allocation circuitry to selectively allocate and/or hide portions of a program memory address space
US6363485B1 (en) * 1998-09-09 2002-03-26 Entrust Technologies Limited Multi-factor biometric authenticating device and method
US6397379B1 (en) * 1999-01-28 2002-05-28 Ati International Srl Recording in a program execution profile references to a memory-mapped active device
US6560627B1 (en) * 1999-01-28 2003-05-06 Cisco Technology, Inc. Mutual exclusion at the record level with priority inheritance for embedded systems using one semaphore
US6684326B1 (en) * 1999-03-31 2004-01-27 International Business Machines Corporation Method and system for authenticated boot operations in a computer system of a networked computing environment
US6389537B1 (en) * 1999-04-23 2002-05-14 Intel Corporation Platform and method for assuring integrity of trusted agent communications
US6529909B1 (en) * 1999-08-31 2003-03-04 Accenture Llp Method for translating an object attribute converter in an information services patterns environment
US6252650B1 (en) * 1999-09-09 2001-06-26 Nikon Corporation Exposure apparatus, output control method for energy source, laser device using the control method, and method of producing microdevice
US6535988B1 (en) * 1999-09-29 2003-03-18 Intel Corporation System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate
US6374317B1 (en) * 1999-10-07 2002-04-16 Intel Corporation Method and apparatus for initializing a computer interface
US6678825B1 (en) * 2000-03-31 2004-01-13 Intel Corporation Controlling access to multiple isolated memories in an isolated execution environment
US6507904B1 (en) * 2000-03-31 2003-01-14 Intel Corporation Executing isolated mode instructions in a secure system running in privilege rings
US20060015719A1 (en) * 2000-03-31 2006-01-19 Herbert Howard C Platform and method for remote attestation of a platform
US6990579B1 (en) * 2000-03-31 2006-01-24 Intel Corporation Platform and method for remote attestation of a platform

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060015719A1 (en) * 2000-03-31 2006-01-19 Herbert Howard C Platform and method for remote attestation of a platform
US7254707B2 (en) 2000-03-31 2007-08-07 Intel Corporation Platform and method for remote attestation of a platform
US7380278B2 (en) 2000-03-31 2008-05-27 Intel Corporation Protecting software environment in isolated execution
US9547772B2 (en) 2005-06-30 2017-01-17 Intel Corporation Secure vault service for software components within an execution environment
US8499151B2 (en) 2005-06-30 2013-07-30 Intel Corporation Secure platform voucher service for software components within an execution environment
US9361471B2 (en) 2005-06-30 2016-06-07 Intel Corporation Secure vault service for software components within an execution environment
US8839450B2 (en) * 2007-08-02 2014-09-16 Intel Corporation Secure vault service for software components within an execution environment
US20090038017A1 (en) * 2007-08-02 2009-02-05 David Durham Secure vault service for software components within an execution environment
EP2765530A1 (en) * 2013-02-11 2014-08-13 Intel Corporation Securing display output data against malicious software attacks
US9158942B2 (en) 2013-02-11 2015-10-13 Intel Corporation Securing display output data against malicious software attacks

Also Published As

Publication number Publication date
US6941458B1 (en) 2005-09-06
US6957332B1 (en) 2005-10-18

Similar Documents

Publication Publication Date Title
Cho A Framework for Alternate Queueing: Towards Traffic Management by PC-UNIX Based Routers.
DE10196005B4 (en) Means and methods for isolated execution of commands Isolated
JP3689431B2 (en) Method and apparatus for secure processing of cryptographic keys
US7603550B2 (en) Computer system including a secure execution mode-capable CPU and a security services processor connected via a secure communication path
Crandall et al. Minos: Control data attack prevention orthogonal to memory model
CN101176100B (en) Methods and apparatus for generating endorsement credentials for software-based security coprocessors
US8522018B2 (en) Method and system for implementing a mobile trusted platform module
Ghormley et al. SLIC: An Extensibility System for Commodity Operating Systems.
US7974416B2 (en) Providing a secure execution mode in a pre-boot environment
JP5455318B2 (en) Dynamic trust management
US8407476B2 (en) Method and apparatus for loading a trustable operating system
US8924699B2 (en) BIOS protection device
DE10195999B3 (en) Computer system having a contained in a chipset memory controller for controlling accesses to an isolated store for isolated execution
JP4073913B2 (en) Open generic tamper-resistant cpu and application systems
KR101093124B1 (en) A computer system employing a trusted execution environment including a memory controller configured to clear memory
JP6053786B2 (en) Arm (R) Trusted Zone firmware infrastructure Trusted Platform Module for implementation (tpm)
DE10196006B4 (en) Generating a key hierarchy for use in an isolated execution environment
JP4846660B2 (en) Reordering the system management interrupt, by generating a virtual machine container, the protective method for the untrusted system management code
EP1759261B1 (en) Method and apparatus for providing secure virtualization of a trusted platform module
US20160085965A1 (en) Execution of a secured environment initialization instruction on a point-to-point interconnect system
US6978018B2 (en) Technique to support co-location and certification of executable content from a pre-boot space into an operating system runtime environment
US8458801B2 (en) High-assurance secure boot content protection
US8024564B2 (en) Automating configuration of software applications
CN101263473B (en) Processing unit enclosed operating system
Champagne et al. Scalable architectural support for trusted software

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ELLISON, CARL;GOLLIVER, ROGER;HERBERT, HOWARD C.;AND OTHERS;REEL/FRAME:016515/0128;SIGNING DATES FROM 20000724 TO 20000905