US20050164489A1 - Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material - Google Patents

Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material Download PDF

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US20050164489A1
US20050164489A1 US11/045,447 US4544705A US2005164489A1 US 20050164489 A1 US20050164489 A1 US 20050164489A1 US 4544705 A US4544705 A US 4544705A US 2005164489 A1 US2005164489 A1 US 2005164489A1
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layer
hard mask
electron beam
air gap
sacrificial
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Grant Kloster
Jihperng Leu
Hyun-Mog Park
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the invention relate to the field of semiconductor, and more specifically, to semiconductor fabrication.
  • Low dielectric constant (low-k) materials are used in interlayer dielectrics (ILD) in semiconductor devices to reduce propagation delay and improve device performance.
  • ILD interlayer dielectrics
  • the dielectric constant of the material between the metal lines should decrease to maintain the improvement.
  • One major problem with air gap technology is the removal of sacrificial material to fabricate multi-layer structures.
  • FIG. 1 is a diagram illustrating a dual damascene structure in which one embodiment of the invention can be practiced.
  • FIG. 2 is a diagram illustrating formation of an air gap according to one embodiment of the invention.
  • FIG. 3 is a diagram illustrating deposit of barrier layer according to one embodiment of the invention.
  • FIG. 4 is a diagram illustrating deposit of sacrificial layer according to one embodiment of the invention.
  • FIG. 5 is a diagram illustrating deposit of hard mask layer according to one embodiment of the invention.
  • FIG. 6 is a diagram illustrating formation of opening according to one embodiment of the invention.
  • FIG. 7 is a diagram illustrating deposit of metal according to one embodiment of the invention.
  • FIG. 8 is a diagram illustrating removal of excess metal according to one embodiment of the invention.
  • FIG. 9 is a diagram illustrating formation of air gap according to one embodiment of the invention.
  • FIG. 10 is a flowchart illustrating a process to create an air gap according to one embodiment of the invention.
  • FIG. 11 is a flowchart illustrating a process to form a dual damascene structure according to one embodiment of the invention.
  • An embodiment of the present invention includes a method to form an air gap in a multi-layer structure.
  • a dual damascene structure is formed on a substrate.
  • the dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer.
  • the sacrificial layer is made of a sacrificial material having substantial thermal stability and decomposable by an electron beam.
  • the sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.
  • One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a procedure, a method of manufacturing or fabrication, etc.
  • FIG. 1 is a diagram illustrating a dual damascene structure 100 in which one embodiment of the invention can be practiced.
  • the dual damascene structure 100 includes a substrate 110 , a barrier layer 120 , a sacrificial layer 130 , a hard mask layer 140 , and metallization layer 150 .
  • the dual damascene is a multi-level interconnection process in which, in addition to the opening or channels of single damascene, the conductive via openings are also formed.
  • the substrate 110 is any suitable substrate for the device fabrication such as silicon.
  • the barrier layer 120 is deposited on the substrate 110 .
  • the barrier layer 120 may be an etch stop or a diffusion layer such as silicon oxide (SiO 2 ) or silicon nitride (Si 3 N 4 ).
  • the sacrificial layer 130 is formed by depositing a sacrificial material on the barrier layer 120 .
  • the sacrificial material has substantial thermal stability and decomposable by electron beam (e-beam). Thermal stability here refers to the ability to sustain the temperature range in the fabrication process.
  • the sacrificial material may be one of a low-k dielectric and an e-beam photo resist material.
  • E-beam photo-resists are not stable enough to withstand thermal conditions during normal device fabrication, but materials based on their composition could be designed for optimal decomposition by e-beam.
  • the positive tone e-beam positive such as ZEP-520TM (by Nippon Zeon), ALEX-ETM, or (poly(methyl methacrylate)) (PMMA) are based on styrene, or butene, acrylate. These components can be incorporated in a cross-linked aromatic polymer to produce a thermally stable material that is susceptible to chain scission by e-beam.
  • the hard mask layer 140 is deposited on the sacrificial layer 130 by any conventional methods such as plasma enhanced vapor deposition, chemical vapor deposition, and physical vapor deposition.
  • the hard mask layer 140 may be porous or non-porous and may be made by materials such as silicon oxide, silicon nitride, carbon-doped silicon nitride (SICN x ), silicon oxy-nitride, sputtered silicon, amorphous silicon, or amorphous carbon.
  • the hard mask layer 140 may be a porous interlevel dielectric (ILD).
  • the hard mask layer 140 , the sacrificial layer 130 , and the barrier layer 120 are then patterned and etched to form an opening, groove, or channel.
  • the metallization layer 150 is then formed by filling the opening with metal such as copper or copper-aluminum alloys.
  • a chemical mechanical polishing (CMP) process removes the excess metal and polishes the metallization layer 150 .
  • CMP chemical mechanical polishing
  • FIG. 2 is a diagram illustrating formation 200 of an air gap according to one embodiment of the invention.
  • the dual damascene structure 100 is then subjected to e-beam processing to create the air gap.
  • E-beam is known to interact with materials destructively. For example, silsesquioxane materials undergo carbon depletion and film shrinkage upon e-beam treatment. Polymers can be completely decomposed by e-beam exposure at relatively low energies, as observed in scanning electron microscopy (SEM) samples not coated with metal surface layers, and in e-beam lithography with positive e-beam photo-resists.
  • SEM scanning electron microscopy
  • the sacrificial layer 130 is made of a sacrificial material that has thermal stability and is decomposable by e-beam, the e-beam decomposes the sacrificial material into volatile components such as carbon dioxide, hydrocarbons, aldehydes, etc. These volatile components are then removed by mild thermal processing. In one embodiment, the temperature range for the thermal processing may be between 100° C. to 200° C. The volatile components can diffuse out of the device through the hard mask layer 140 . The sacrificial layer 130 then becomes an air gap that provides a dielectric constant of close to 1.
  • FIG. 3 is a diagram illustrating deposit 300 of barrier layer according to one embodiment of the invention.
  • a barrier layer 310 is deposited on the dual damascene structure 200 .
  • the barrier layer 310 may be an etch stop or a diffusion layer such as SiO 2 or Si 3 N 4 .
  • a Co shunt may be deposited as a barrier, then a porous etch-stop layer is deposited. Then, the sacrificial material is removed by e-beam. The Co shunt would act as a diffusion barrier.
  • FIG. 4 is a diagram illustrating deposit 400 of sacrificial layer according to one embodiment of the invention.
  • a sacrificial layer 410 is deposited on the barrier layer 310 .
  • the sacrificial layer 410 is made of material similar to that of the sacrificial layer 130 shown in FIG. 1 .
  • the sacrificial layer 410 is made of material having substantial thermal stability and decomposable by e-beam. Separate sacrificial materials may be deposited for the via and trench levels.
  • FIG. 5 is a diagram illustrating deposit 500 of hard mask layer according to one embodiment of the invention.
  • a hard mask layer 510 is deposited on the sacrificial layer 410 by any conventional methods such as plasma enhanced vapor deposition, chemical vapor deposition, and physical vapor deposition.
  • the hard mask layer 510 in essence is similar to the hard mask layer 140 shown in FIG. 1 .
  • it may be porous or non-porous and may be made by materials such as silicon oxide, silicon nitride, carbon-doped silicon nitride (SICN x ), silicon oxy-nitride, sputtered silicon, amorphous silicon, or amorphous carbon.
  • the hard mask layer 510 may be a porous interlevel dielectric (ILD).
  • ILD interlevel dielectric
  • FIG. 6 is a diagram illustrating formation 600 of opening according to one embodiment of the invention.
  • the hard mask layer 510 is patterned for the metal interconnects.
  • the hard mask layer 510 , the sacrificial layer 410 , and the barrier layer 310 are then etched, ashed, and cleaned to form a groove, void, or opening 610 .
  • FIG. 7 is a diagram illustrating deposit 700 of metal according to one embodiment of the invention.
  • Barrier, seed, and metal are deposited to fill the opening 610 .
  • Any suitable metal material can be used.
  • copper is used as the metal material.
  • a metallization layer 710 is formed.
  • FIG. 8 is a diagram illustrating removal 800 of excess metal according to one embodiment of the invention.
  • a chemical mechanical planarization or polishing (CMP) process is then performed to remove excess metal and to polish the metallization layer 710 to form a polished metallization layer 810 .
  • CMP chemical mechanical planarization or polishing
  • a low-down force CMP process is typically used.
  • FIG. 9 is a diagram illustrating formation 900 of air gap according to one embodiment of the invention.
  • the e-beam is then used to penetrate through the hard mask layer 510 to decompose the sacrificial material of the sacrificial layer 410 into volatile components which diffuse out of the hard mask layer 510 by mild thermal processing as discussed earlier.
  • An air gap 910 is then formed between the hard mask layer 510 and the barrier layer 310 and between the metal lines of the metallization layers in the multi-layer device.
  • the air gap 910 provides a dielectric layer having a dielectric constant of close to 1.
  • FIGS. 2 through 9 The process as shown from FIGS. 2 through 9 can be repeated for additional layers built upon the dual damascene structure 100 shown in FIG. 1 .
  • FIG. 10 is a flowchart illustrating a process 1000 to create an air gap according to one embodiment of the invention.
  • the process 1000 forms a substrate (Block 1010 ). Then, the process 1000 forms a dual damascene structure on the previous structure (Block 1020 ).
  • the previous structure is the substrate.
  • the previous structure is the dual damascene structure formed in the previous iteration.
  • the dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer.
  • the sacrificial layer is made of a sacrificial material that has substantial thermal stability and decomposable by electron beam.
  • the Block 1020 is described in more detail in FIG. 11 .
  • the process 1000 decomposes the sacrificial material of the sacrificial layer by electron beam into volatile components or fragments (Block 1030 ). Then, the process 1000 diffuses the volatile components through the hard mask layer by thermal processing (Block 1040 ). The sacrificial layer then becomes an air gap. Next, the process 1000 determines if more layer is needed in the fabrication (Block 1050 ). If so, the process 1000 returns to Block 1020 to continue building an additional structure. Otherwise, the process 1000 is terminated.
  • FIG. 11 is a flowchart illustrating the process 1020 to form a dual damascene structure according to one embodiment of the invention.
  • the process 1020 deposits the barrier layer on the previous structure (Block 1110 ).
  • the previous structure may be the substrate or the previous layer.
  • the process 1020 deposits the sacrificial layer on the barrier layer (Block 1120 ).
  • the process 1020 deposits the hard mask layer on the sacrificial layer (Block 1130 ).
  • the process 1020 patterns and etches the barrier layer, the sacrificial layer, and the hard mask layer to form an opening for the metal deposition (Block 1140 ).
  • the process 1020 fills the opening with the metal material (Block 1150 ).
  • the process 1020 polishes and removes excess metal material by a CMP processing (Block 1160 ). The process 1020 is then terminated.

Abstract

An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.

Description

    BACKGROUND
  • 1. Field of the Invention
  • Embodiments of the invention relate to the field of semiconductor, and more specifically, to semiconductor fabrication.
  • 2. Description of Related Art
  • Low dielectric constant (low-k) materials are used in interlayer dielectrics (ILD) in semiconductor devices to reduce propagation delay and improve device performance. As device sizes continue to shrink, the dielectric constant of the material between the metal lines should decrease to maintain the improvement. The eventual limit for the dielectric constant is k=1, which is the value for vacuum. This can be achieved by producing a void space between the metal lines, effectively creating an air gap. Air itself has a dielectric constant very close to 1. One major problem with air gap technology is the removal of sacrificial material to fabricate multi-layer structures.
  • Existing techniques to remove sacrificial material have a number of drawbacks. Use of plasmas may be destructive to the metal lines. Wet etches have many problems, including capillary forces that can break the lines apart, the difficulty in removing material from small features, and the difficulty in removing the wet etch chemical once it has been introduced. Thermal decomposition presents problems in that the sacrificial material must remain stable during high temperature fabrications stages, but it may decompose rapidly at normal temperatures that will not destroy the device.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
  • FIG. 1 is a diagram illustrating a dual damascene structure in which one embodiment of the invention can be practiced.
  • FIG. 2 is a diagram illustrating formation of an air gap according to one embodiment of the invention.
  • FIG. 3 is a diagram illustrating deposit of barrier layer according to one embodiment of the invention.
  • FIG. 4 is a diagram illustrating deposit of sacrificial layer according to one embodiment of the invention.
  • FIG. 5 is a diagram illustrating deposit of hard mask layer according to one embodiment of the invention.
  • FIG. 6 is a diagram illustrating formation of opening according to one embodiment of the invention.
  • FIG. 7 is a diagram illustrating deposit of metal according to one embodiment of the invention.
  • FIG. 8 is a diagram illustrating removal of excess metal according to one embodiment of the invention.
  • FIG. 9 is a diagram illustrating formation of air gap according to one embodiment of the invention.
  • FIG. 10 is a flowchart illustrating a process to create an air gap according to one embodiment of the invention.
  • FIG. 11 is a flowchart illustrating a process to form a dual damascene structure according to one embodiment of the invention.
    • DESCRIPTION
  • An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.
  • In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in order not to obscure the understanding of this description.
  • One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a procedure, a method of manufacturing or fabrication, etc.
  • FIG. 1 is a diagram illustrating a dual damascene structure 100 in which one embodiment of the invention can be practiced. The dual damascene structure 100 includes a substrate 110, a barrier layer 120, a sacrificial layer 130, a hard mask layer 140, and metallization layer 150.
  • The dual damascene is a multi-level interconnection process in which, in addition to the opening or channels of single damascene, the conductive via openings are also formed. The substrate 110 is any suitable substrate for the device fabrication such as silicon. The barrier layer 120 is deposited on the substrate 110. The barrier layer 120 may be an etch stop or a diffusion layer such as silicon oxide (SiO2) or silicon nitride (Si3N4). The sacrificial layer 130 is formed by depositing a sacrificial material on the barrier layer 120. The sacrificial material has substantial thermal stability and decomposable by electron beam (e-beam). Thermal stability here refers to the ability to sustain the temperature range in the fabrication process. The sacrificial material may be one of a low-k dielectric and an e-beam photo resist material. E-beam photo-resists are not stable enough to withstand thermal conditions during normal device fabrication, but materials based on their composition could be designed for optimal decomposition by e-beam. The positive tone e-beam positive such as ZEP-520™ (by Nippon Zeon), ALEX-E™, or (poly(methyl methacrylate)) (PMMA) are based on styrene, or butene, acrylate. These components can be incorporated in a cross-linked aromatic polymer to produce a thermally stable material that is susceptible to chain scission by e-beam. The hard mask layer 140 is deposited on the sacrificial layer 130 by any conventional methods such as plasma enhanced vapor deposition, chemical vapor deposition, and physical vapor deposition. The hard mask layer 140 may be porous or non-porous and may be made by materials such as silicon oxide, silicon nitride, carbon-doped silicon nitride (SICNx), silicon oxy-nitride, sputtered silicon, amorphous silicon, or amorphous carbon. Alternatively, the hard mask layer 140 may be a porous interlevel dielectric (ILD). The hard mask layer 140, the sacrificial layer 130, and the barrier layer 120 are then patterned and etched to form an opening, groove, or channel. The metallization layer 150 is then formed by filling the opening with metal such as copper or copper-aluminum alloys. A chemical mechanical polishing (CMP) process removes the excess metal and polishes the metallization layer 150.
  • FIG. 2 is a diagram illustrating formation 200 of an air gap according to one embodiment of the invention. The dual damascene structure 100 is then subjected to e-beam processing to create the air gap.
  • A number of e-beam sources exist and are used in tools for device fabrication. E-beam is known to interact with materials destructively. For example, silsesquioxane materials undergo carbon depletion and film shrinkage upon e-beam treatment. Polymers can be completely decomposed by e-beam exposure at relatively low energies, as observed in scanning electron microscopy (SEM) samples not coated with metal surface layers, and in e-beam lithography with positive e-beam photo-resists.
  • Since the sacrificial layer 130 is made of a sacrificial material that has thermal stability and is decomposable by e-beam, the e-beam decomposes the sacrificial material into volatile components such as carbon dioxide, hydrocarbons, aldehydes, etc. These volatile components are then removed by mild thermal processing. In one embodiment, the temperature range for the thermal processing may be between 100° C. to 200° C. The volatile components can diffuse out of the device through the hard mask layer 140. The sacrificial layer 130 then becomes an air gap that provides a dielectric constant of close to 1.
  • FIG. 3 is a diagram illustrating deposit 300 of barrier layer according to one embodiment of the invention. To prepare for an additional layer, a barrier layer 310 is deposited on the dual damascene structure 200. The barrier layer 310 may be an etch stop or a diffusion layer such as SiO2 or Si3N4. Alternatively, a Co shunt may be deposited as a barrier, then a porous etch-stop layer is deposited. Then, the sacrificial material is removed by e-beam. The Co shunt would act as a diffusion barrier.
  • FIG. 4 is a diagram illustrating deposit 400 of sacrificial layer according to one embodiment of the invention. A sacrificial layer 410 is deposited on the barrier layer 310. The sacrificial layer 410 is made of material similar to that of the sacrificial layer 130 shown in FIG. 1. In essence, the sacrificial layer 410 is made of material having substantial thermal stability and decomposable by e-beam. Separate sacrificial materials may be deposited for the via and trench levels.
  • FIG. 5 is a diagram illustrating deposit 500 of hard mask layer according to one embodiment of the invention. A hard mask layer 510 is deposited on the sacrificial layer 410 by any conventional methods such as plasma enhanced vapor deposition, chemical vapor deposition, and physical vapor deposition. The hard mask layer 510 in essence is similar to the hard mask layer 140 shown in FIG. 1. In other words, it may be porous or non-porous and may be made by materials such as silicon oxide, silicon nitride, carbon-doped silicon nitride (SICNx), silicon oxy-nitride, sputtered silicon, amorphous silicon, or amorphous carbon. Alternatively, the hard mask layer 510 may be a porous interlevel dielectric (ILD).
  • FIG. 6 is a diagram illustrating formation 600 of opening according to one embodiment of the invention. The hard mask layer 510 is patterned for the metal interconnects. The hard mask layer 510, the sacrificial layer 410, and the barrier layer 310 are then etched, ashed, and cleaned to form a groove, void, or opening 610.
  • FIG. 7 is a diagram illustrating deposit 700 of metal according to one embodiment of the invention. Barrier, seed, and metal are deposited to fill the opening 610. Any suitable metal material can be used. In one embodiment, copper is used as the metal material. A metallization layer 710 is formed.
  • FIG. 8 is a diagram illustrating removal 800 of excess metal according to one embodiment of the invention. A chemical mechanical planarization or polishing (CMP) process is then performed to remove excess metal and to polish the metallization layer 710 to form a polished metallization layer 810. To avoid crushing the metal lines, a low-down force CMP process is typically used.
  • FIG. 9 is a diagram illustrating formation 900 of air gap according to one embodiment of the invention. The e-beam is then used to penetrate through the hard mask layer 510 to decompose the sacrificial material of the sacrificial layer 410 into volatile components which diffuse out of the hard mask layer 510 by mild thermal processing as discussed earlier. An air gap 910 is then formed between the hard mask layer 510 and the barrier layer 310 and between the metal lines of the metallization layers in the multi-layer device. The air gap 910 provides a dielectric layer having a dielectric constant of close to 1.
  • The process as shown from FIGS. 2 through 9 can be repeated for additional layers built upon the dual damascene structure 100 shown in FIG. 1.
  • FIG. 10 is a flowchart illustrating a process 1000 to create an air gap according to one embodiment of the invention.
  • Upon START, the process 1000 forms a substrate (Block 1010). Then, the process 1000 forms a dual damascene structure on the previous structure (Block 1020). For the first iteration, the previous structure is the substrate. For subsequent iterations corresponding to subsequent layers, the previous structure is the dual damascene structure formed in the previous iteration. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a sacrificial material that has substantial thermal stability and decomposable by electron beam. The Block 1020 is described in more detail in FIG. 11.
  • Next, the process 1000 decomposes the sacrificial material of the sacrificial layer by electron beam into volatile components or fragments (Block 1030). Then, the process 1000 diffuses the volatile components through the hard mask layer by thermal processing (Block 1040). The sacrificial layer then becomes an air gap. Next, the process 1000 determines if more layer is needed in the fabrication (Block 1050). If so, the process 1000 returns to Block 1020 to continue building an additional structure. Otherwise, the process 1000 is terminated.
  • FIG. 11 is a flowchart illustrating the process 1020 to form a dual damascene structure according to one embodiment of the invention.
  • Upon START, the process 1020 deposits the barrier layer on the previous structure (Block 1110). As described earlier, the previous structure may be the substrate or the previous layer. Then, the process 1020 deposits the sacrificial layer on the barrier layer (Block 1120). Next, the process 1020 deposits the hard mask layer on the sacrificial layer (Block 1130).
  • Then, the process 1020 patterns and etches the barrier layer, the sacrificial layer, and the hard mask layer to form an opening for the metal deposition (Block 1140). Next, the process 1020 fills the opening with the metal material (Block 1150). Then, the process 1020 polishes and removes excess metal material by a CMP processing (Block 1160). The process 1020 is then terminated.
  • While the invention has been described in terms of several embodiments, those of ordinary skill in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Claims (9)

1-21. (canceled)
22. A device comprising:
a barrier layer on a substrate;
a hard mask layer;
an air gap between the barrier layer and the hard mask layer, the air gap being formed by removing a sacrificial layer using an electron beam, the sacrificial sacrifical layer being made of a sacrificial material having substantial thermal stability and decomposable by the electron beam; and
a metallization layer through the barrier layer, the air gap, and the hard mask layer, the metallization layer being formed by a dual damascene process.
23. The device of claim 22 wherein the sacrificial material is one of a low-k dielectric and an electron beam photo resist material.
24. The device of claim 23 wherein the electron beam photo resist material is produced from a cross-linked aromatic polymer incorporated with a positive tone electron beam photo resist, the electron beam photo resist being based on one of acrylate, styrene, and butene.
25. The device of claim 22 wherein the barrier layer is one of an etch stop and a diffusion layer.
26. The device of claim 25 wherein the diffusion layer is silicon oxide or silicon nitride.
27. The device of claim 22 wherein the hard mask layer is porous and non-porous.
28. The device of claim 22 wherein the hard mask layer is made by one of silicon oxide, silicon nitride, carbon-doped silicon nitride, silicon oxy-nitride, sputtered silicon, amorphous silicon, and amorphous carbon.
29. The device of claim 22 wherein the hard mask layer is a porous interlevel dielectric (ILD).
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US20080254600A1 (en) * 2007-04-10 2008-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming interconnect structures
US20100210111A1 (en) * 2005-03-15 2010-08-19 Round Rock Research, Llc Pitch reduced patterns relative to photolithography features
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