US20050105538A1 - Switching system with distributed switching fabric - Google Patents

Switching system with distributed switching fabric Download PDF

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Publication number
US20050105538A1
US20050105538A1 US10/965,444 US96544404A US2005105538A1 US 20050105538 A1 US20050105538 A1 US 20050105538A1 US 96544404 A US96544404 A US 96544404A US 2005105538 A1 US2005105538 A1 US 2005105538A1
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Prior art keywords
switch
elements
ingress
egress
protocol
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Abandoned
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US10/965,444
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English (en)
Inventor
Ananda Perera
Edwin Hoffman
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Raptor Networks Technology Inc
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Individual
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Priority to US10/965,444 priority Critical patent/US20050105538A1/en
Assigned to RAPTOR NETWORKS TECHNOLOGY, INC. reassignment RAPTOR NETWORKS TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOFFMAN, EDWIN, PERERA, ANANDA
Publication of US20050105538A1 publication Critical patent/US20050105538A1/en
Priority to US11/248,708 priority patent/US20060029072A1/en
Priority to US11/248,639 priority patent/US20060029055A1/en
Priority to US11/248,111 priority patent/US20060039369A1/en
Priority to US11/248,711 priority patent/US20060029057A1/en
Priority to US11/248,710 priority patent/US20060029056A1/en
Priority to US11/248,707 priority patent/US20060029071A1/en
Assigned to BRIDGE BANK N.A., AGILITY CAPITAL, LLC reassignment BRIDGE BANK N.A. SECURITY AGREEMENT Assignors: RAPTOR NETWORKS TECHNOLOGY, INC.
Assigned to AGILITY CAPITAL, LLC, BRIDGE BANK N.A. reassignment AGILITY CAPITAL, LLC SECURITY AGREEMENT Assignors: RAPTOR NETWORKS TECHNOLOGY INC.
Assigned to RAPTOR NETWORKS TECHNOLOGY, INC. reassignment RAPTOR NETWORKS TECHNOLOGY, INC. SECURITY AGREEMENT Assignors: AGILITY CAPITAL, LLC, BRIDGE BANK N.A.
Assigned to RAPTOR NETWORKS TECHNOLOGY INC., RAPTOR NETWORKS TECHNOLOGY, INC. reassignment RAPTOR NETWORKS TECHNOLOGY INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: AGILITY CAPITAL, LLC, BRIDGE BANK N.A.
Priority to US11/610,281 priority patent/US7352745B2/en
Assigned to CASTLERIGG MASTER INVESTMENTS LTD., AS COLLATERAL AGENT reassignment CASTLERIGG MASTER INVESTMENTS LTD., AS COLLATERAL AGENT GRANT OF SECURITY INTEREST Assignors: RAPTOR NETWORKS TECHNOLOGY, INC.
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/35—Switches specially adapted for specific applications
    • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring

Definitions

  • the field of the invention is network switches.
  • Modern computer networks typically communicate using discrete packets or frames of data according to predefined protocols. There are multiple such standards, including the ubiquitous TCP and IP standards. For all but the simplest local topologies, networks employ intermediate nodes between the end-devices. Bridges, switches, and/or routers, are all examples of intermediate nodes.
  • a network switch is any intermediate device that forwards packets between end-devices and/or other intermediate devices. Switches operate at the data link layer (layer 2) and sometimes the network layer (layer 3) of the OSI Reference Model, and therefore typically support any packet protocol.
  • a switch has a plurality of input and output ports. Although a typical switch has only 8, 16, or other relatively small number of ports, it is known to connect switches together to provide large numbers of inputs and outputs.
  • Prior art FIG. 1 shows a typical arrangement of switch modules into a large switch that provides 128 inputs and 128 outputs.
  • U.S. Pat. No. 6,256,546 to Beshai (March 2002) describes a protocol that uses an adaptive packet header to simplify packet routing and increase transfer speed among switch modules.
  • Beshai's system is advantageous because it is not limited to a fixed cell length, such as the 53 byte length of an Asynchronous Transfer Mode (ATM) system, and because it reportedly has better quality of service and higher throughput that an Internetworking Protocol (IP) switched network.
  • ATM Asynchronous Transfer Mode
  • IP Internetworking Protocol
  • pluralities of edge modules are interconnected by a passive core 120 .
  • Each of the ingress modules 110 A-D accept data packets in multiple formats, adds a standardized header that indicates a destination for the packet, and switches the packets to the appropriate egress modules 130 A-D through the passive core 120 .
  • the header is removed from the packet, and the packet is transferred to a sink in its native format.
  • the solid lines of 112 A- 112 D depict unencapsulated information arriving to circuit ports, ATM ports, frame relay ports, IP ports, and UTM ports.
  • the solid lines of 132 A-D depict unencapsulated information exiting to the various ports in the native format of the information.
  • the dotted lines of core 120 and facing portions of the ingress 110 A-D and egress 130 A-D modules depict information that is contained UTM headed packets.
  • the entire system 100 operates as a single distributed switch, in which all switching is done at the edge (ingress and egress modules).
  • Beshai's solution in the '546 patent has significant drawbacks.
  • the system is described as a multi-service switch (with circuit ports, ATM ports, frame relay ports, IP ports, and UTM ports), there is no contemplation of using the switch as an Ethernet switch. Ethernet offers significant advantages over other protocols, including connectionless stateful communication.
  • a second drawback is that the optical core is contemplated to be entirely passive. The routes need to be set up and torn down before packets are switched across the core. As such Beshai does not propose a distributed switching fabric, he only discloses a distributed edge fabric with optical cross-connected cores.
  • a third, related disadvantage is that Beshai's concept only supports a single channel from one module to another. All of those deficiencies reduce functionality.
  • Beshai publication no. 2001/0006522 resolves one of the deficiencies of the '546 patent, namely the single channel limitation between modules.
  • Beshai teaches a switching system having packet-switching edge modules and channel switching core modules.
  • traffic entering the system through ports 162 A is sorted at each edge module 160 A-D, and switched to various core elements 180 A-C via paths 170 .
  • the core elements switch the traffic to other destination edge modules 180 A-C, for delivery to final destinations.
  • Beshai contemplates that the core elements can use channel switching to minimize the potential wasted time in a pure TDM (time division mode) system, and that the entire system can use time counter co-ordination to realize harmonious reconfiguration of edge modules and core modules.
  • the channel switching core of the '522 application provides nothing more than virtual channels between edge devices. It does not switch individual packets of data.
  • the '522 application incorporates by reference Beshai's Ser. No. 09/244,824 application regarding. High-Capacity Packet Switch (issued as 6721271 in April 2004)
  • the '522 application still fails to teach, suggest, or motivate one of ordinary skill to provide a fully distributed network (edge and core) that acts as a single switch.
  • the present invention provides apparatus, systems, and methods in which the switching takes place both at the distributed edge nodes and within a distributed core, and where the entire system acts as a single switch through encapsulation of information using a special header that is added by the system upon ingress, and removed by the system upon egress.
  • the routing header includes as least a destination element address, and preferably also includes a destination port address, a source element address. Where the system is configured to address clusters of elements, the header also preferably includes a destination cluster address and a source cluster address.
  • the ingress and egress elements preferably support Ethernet or other protocol providing connectionless media with a stateful connection. At least some of the ingress and egress elements preferably have least 8 input ports and 8 output ports, and communicate at a speed of at least one, and more preferably at least 10 Gbs.
  • Preferred switches include management protocols for discovering which elements are connected, for constructing appropriate connection tables, for designating a master element, and for resolving failures and off-line conditions among the switches.
  • Secure data protocol (SDP), port to port (PTP) protocol, and active/active protection service (AAPS) are all preferably implemented.
  • SRT Strict Ring Topology
  • Other topologies can be can alternatively or additionally employed.
  • Components of a distributed switching fabric can be geographically separated by at least one kilometer, and in some cases by over 150 kilometers.
  • FIG. 1A is a schematic of a prior art arrangement of switch modules that cooperate to act as a single switch.
  • FIG. 1B is a schematic of a prior art arrangement of switch modules connected by an active core, but where the modules operate independently of one another.
  • FIG. 2 is a schematic of a true distributed fabric switching system, in which edge elements add or remove headers, and the core actively switches packets according to the headers.
  • FIG. 3 is a schematic of a routing header.
  • FIG. 4 shows a high level design of a preferred combination Ingress/Egress element
  • FIG. 5 shows a high level design of a preferred core element
  • FIG. 6 is a schematic of a RaptorTM 1010 switch.
  • FIG. 7 is a schematic of a RaptorTM 1808 switch.
  • FIG. 8 is a schematic of an exemplary distributed switching system according to preferred aspects of the present invention.
  • FIG. 9 is a schematic of a super fabric implementation of a distributed switching fabric.
  • a switching system 200 generally includes ingress elements 210 A-C, egress elements 230 A-C, core switching elements 220 A-C and connector elements 240 A-C.
  • the ingress elements encapsulate incoming packets with a routing header (see FIG. 3 ), and perform initial switching. The encapsulated packets then enter the core elements for further switching.
  • the intermediate elements facilitate communication between core elements.
  • the egress elements remove the header, and deliver the packets to a sink or final destination.
  • switching (encapsulation) header must, at a bare minimum, include at least a destination element address.
  • the header also includes destination port ID, and where elements are clustered and optional destination cluster ID.
  • an “ID” is something that is the same as, or can be resolved into an address.
  • a preferred switching header 300 generally includes a Destination Cluster ID 310 , a Destination Element ID 320 , a Destination Port ID 330 , a Source Cluster ID 340 and a Source Element ID 350 .
  • the each of the fields has a length of at least 1 byte and up to 2 bytes.
  • header is used here as in a euphemistic sense to mean any additional routing data that is included in a package that encapsulates other information.
  • the header need not be located at the head end of the frame or packet.
  • Ingress 210 A-C and egress 230 A-C elements are shown in FIG. 2 as distinct elements. In fact, they are similar in construction, and they may be implemented as a single device. Such elements can have any suitable number of ports, and can operate using any suitable logic.
  • Currently preferred chips to implement the design are Broadcom'sTM BCM5690, BCM5670, and BCM5464S chips, according to the detailed schematics included in one or more of the priority provisional applications.
  • FIG. 4 shows a high level design of a preferred combination ingress/egress element 400 , which can be utilized for any of the ingress 210 A-C and egress 230 A-C elements.
  • Ingress/Egress element 400 generally includes a logical switching frame 410 , Ethernet ingress/egress ports 420 A-L, encapsulated packet I/O port 430 , layer 2 table(s) 440 , layer 3 table(s) 450 , and access control table(s) 460 .
  • Ingress/egress elements are the only elements that are typically assigned element IDs.
  • the destination MAC address is searched in the layer 2 MAC table 440 , where the destination element ID and destination port ID are already stored. Once matched, the element and port IDs are placed into the switching header, along with the destination cluster ID, and source element ID. The resulting frame is then sent out to the core element.
  • the ID is checked to make sure the packet is targeted to the particular element at which it arrived. If there is a discrepancy, the frame is checked to determine whether it is a multicast or broadcast frame. If it is a multicast frame, the internal switching header is stripped and the resulting packet is copied to all interested parties (registered IGMP “Internet Group Management Protocol” joiners). If it is a broadcast frame, the RAST header is stripped, and the resulting packet is copied to all ports except the incoming port over which the frame arrived. If the frame is a unicast frame, the element ID is stripped off, and the packet is cut through to the corresponding physical port.
  • ingress/egress elements could be single port, in preferred embodiments they would typically have multiple ports, including at least one encapsulated packet port, and at least one standards based port (such as Gigabit Ethernet).
  • standards based port such as Gigabit Ethernet
  • preferred ingress/egress elements include 1 Gigabit Ethernet multi-port modules, and 10 Gigabit Ethernet single port modules.
  • an ingress/egress element may be included in the same physical device with a core element. In that case the device comprises a hybrid core-ingress/egress device. See FIGS. 6 and 7 .
  • FIG. 5 shows a high level design of a preferred core element 500 , which can be utilized for any of the core switching elements 220 A-C.
  • Core element 500 generally includes a logical switching frame 510 , a plurality of ingress and/or egress ports 520 A-H, one or more unicast tables 530 , one or more multicast tables 540 .
  • the unicast table contains a list of all registered element IDs that are known to the core element. Elements become registered during the MDP (Management Discovery Protocol) phase of startup.
  • the multicast table contains element IDs that are registered during the “discovery phase” of a multicast protocol's joining sequence. This is where the multicast protocol evidences an interested party, and uses these IDs to decide which ports take part in the hardware copy of the frames. If the element ID is not known to this core element, or the frame is designated a broadcast frame, the frame floods all egress ports.
  • Connector elements 240 A-C are low level devices that allow the core elements to communicate with other core elements over cables or fibers. They assist in enforcing protocols, but have no switching functions. Examples of such elements are XAU1 over copper connectors XAU1/XGmil over fiber connectors using MSA XFP.
  • FIG. 6 is a schematic of a preferred commercial embodiment of a hybrid core-ingress device, designated as a RaptorTM 1010 switch.
  • the switch 600 generally includes two 10 GBase ingress elements 610 A-B, two ingress elements other than 10 GBase 615 A-B, a core element 620 , and intermediate connector elements 630 A-D.
  • the system is capable of providing 12.5 Gbps throughput.
  • FIG. 7 is a schematic of a preferred commercial embodiment of a hybrid core-ingress device, designated as a Raptomm 1808 switch.
  • the switch 700 could include eight 10 GBase ingress elements 710 A-D, a core element 720 , or eight intermediate connector elements 730 A-D, or any combination of elements up to a total of eight.
  • a switching system 800 includes two of the RaptorTM 1010 switches 600 A-B and four of the RaptorTM 1808 switches 700 A-D, as well as connecting optical or other lines 810 .
  • the lines preferably comprise a 10 GB or greater backplane.
  • the links between the 1010 switches can be 10-40 km at present, and possibly greater lengths in the future.
  • the links between the core switches can be over 40 km.
  • a major advantage of the inventive subject matter is that it implements switching of Ethernet packets using a distributed switching fabric.
  • Contemplated embodiments are not strictly limited to Ethernet, however. It is contemplated, for example, that an ingress element can convert SONET to Ethernet, encapsulate and route the packets as described above, and then convert back from Ethernet to SONET.
  • Switching systems contemplated herein can use any suitable topology.
  • the distributed switch fabric contemplated herein can even support a mixture of ring, mesh, star and bus topologies, with looping controlled via Spanning Tree Avoidance algorithms.
  • the presently preferred topology is a Strict Ring Topology (SRT), in which there is only one physical or logical link between elements.
  • SRT Strict Ring Topology
  • each source element address is checked upon ingress via any physical or logical link into a core element. If the source element address is the one that is directly connected to the core element, the data stream will be blocked. If the source element address is not the one that is directly connected to this core element, the package will be forwarded using the normal rules.
  • a break in the ring can be handled in any of several known ways, including reversion to a straight bus topology, which would cause an element table update to all elements.
  • EMU element manager unit
  • MDP Management Discovery Protocol
  • Each element transmits an initial MDP establish message containing its MAC address and user assigned priority number (if assigned 0 used if not set). Each element also listens for incoming MDP messages, containing such information. As each element receives the MDP messages, one of two decisions is made. If the received MAC address is lower than the MAC address assigned to the receiving element, the message is forwarded to all active links with the original MAC address, the link number it was received on, and the MAC address of the system that is forwarding the message. If a priority is set, the lowest priority (greater than 0) is deemed as lowest MAC address and processed as such. If on the other hand the received MAC address is higher than the MAC address assigned to the receiving element, then the message is not forwarded. If a priority is set that is higher than the received priority, the same process is carried out.
  • the system identifies the MAC address of the master unit, and creates a connection matrix based on the MAC addresses of the elements discovered, the active port numbers, and the MAC addresses of each of the elements, as well as each of their ports.
  • This matrix is distributed to all elements, and forms the base of the distributed switch fabric.
  • the matrix can be any reasonable size, including the presently preferred support for a total of 1024 elements.
  • each new element As each new element joins an established cluster, it issues a MDP initialization message, which is answered by a stored copy of the adjacency table.
  • the new element insert its own information into the table, and issues an update element message to the master, which in turn will check the changes and issue an element update message to all elements.
  • Heart Beat Protocol enables the detection of a faked element. If an element fails or is removed from the matrix, a Heart Beat Protocol (HBP) can be used to signal that a particular link to an element is not in service. Whatever system is running the HBP sends an element update message to the master, which then reformats the table, and issues an element update message to all elements.
  • HBP Heart Beat Protocol
  • Traffic Load factors can be calculated in any suitable manner.
  • traffic load is calculated by local management units and periodically communicated in element load messages to the master. It is contemplated that such information can be used to load balance multiple physical or logical links between elements.
  • Element messages are preferably sent using a secure data protocol (SDP), which performs an ACK/NAK function on all messages to ensure their delivery.
  • SDP is preferably operated as a layer 2 secure data protocol that also includes the ability to encrypt element messages between elements.
  • element messages and SDP can also be used to communicate other data between elements, and thereby support desired management features.
  • element messages can be used to support Port To Port Protocol (PTPP), which provides a soft permanent virtual connection to exist between element/port pairs.
  • PTPP Port To Port Protocol
  • PTPP is simply an element-to-element message that sets default encapsulation to a specific element address/port address for source and destination.
  • MPLS Multiprotocol Label Switching
  • PTPP allows for extremely convenient routing around failures, provided that another link is available at both the originating (ingress) side and the terminating (egress) side, and there is no other blockage in the intervening links (security/Access Control List (ACL)/Quality of Service (QoS), etc),
  • AAPS Active/Active Protection Service
  • the method is analogous to multicasting in that the hardware copies data from the master link to the secondary link.
  • the receiving end of the AAPS will only forward the first copy of any data received (correctly) to the end node.
  • cluster enabled elements are simply normal elements, but with one or more links that are capable of adding/subtracting cluster address numbers.
  • a system that utilizes clusters in this manner is referred to herein as a super fabric.
  • Super fabrics can be designed to any reasonable size, including especially a current version of super fabric that allows up to 255 clusters of 1024 elements to be connected in a “single” switch system.
  • the management unit operating in super fabric mode retains details about all clusters, but does not MAC address data. Inter-cluster communication is via dynamic Virtual LAN (VLAN) tunnels which are created when a cluster level ACL detects a matched sequence that has been predefined.
  • VLAN Virtual LAN
  • matches include any of: (a) a MAC address or MAC address pairs; (b) VLAN ID pairs; (c) IP subnet or subnet pair; (d) TCP/UDP Protocol numbers or pairs, ranges etc; (e) protocol number(s); and (f) layer 2-7 match of specific data.
  • the management unit can also keep a list of recent broadcasts, and perform a matching operation on broadcasts received. Forwarding of previously sent broadcasts can thereby be prevented, so that after a learning period only new broadcasts will forwarded to other links.
  • clusters are managed by a management unit, they can continue to operate upon failure of the master. If the master management unit fails, a new master is selected and the cluster continues to operate. In preferred embodiments, any switch unit can be the master unit. In cases where only the previous management has failed, the ingress/egress elements and core element are manageable by the new master over an inband connection.
  • Inter-cluster communication is preferably via a strict PTPP based matrix of link addresses.
  • MDP discovers this link
  • HBP checks the link for health
  • SDP allows communication between management elements to keep the cluster informed of any changes. If all of the above is properly implemented, a cluster of switch elements can act as a single logical Gigabit Ethernet or 10 Gigabit Ethernet LAN switch, with all standards based switch functions available over the entire logical switch.
  • a super fabric implementation 900 of a distributed switching fabric generally includes four 20 Gbps pipes 910 A-D, each of which is connected to a corresponding cluster 920 A-D that includes a control element 922 A-D that understand the cluster messaging structure.
  • each cluster there are numerous ingress/egress elements 400 coupled together.
  • each of the control elements 922 A-D has two 10 Gbps pipes that connect the ingress/egress elements 400 for intra-cluster communication.
  • inter-cluster pipes 930 A-D which in this instance also communicate at 10 Gbps.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
US10/965,444 2003-10-14 2004-10-12 Switching system with distributed switching fabric Abandoned US20050105538A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US10/965,444 US20050105538A1 (en) 2003-10-14 2004-10-12 Switching system with distributed switching fabric
US11/248,708 US20060029072A1 (en) 2003-10-14 2005-10-11 Switching system for virtual LANs
US11/248,639 US20060029055A1 (en) 2003-10-14 2005-10-11 VLAN fabric network
US11/248,111 US20060039369A1 (en) 2003-10-14 2005-10-11 Multiplexing system having an automatically configured topology
US11/248,711 US20060029057A1 (en) 2003-10-14 2005-10-11 Time division multiplexing system
US11/248,710 US20060029056A1 (en) 2003-10-14 2005-10-11 Virtual machine task management system
US11/248,707 US20060029071A1 (en) 2003-10-14 2005-10-11 Multiplexing system that supports a geographically distributed subnet
US11/610,281 US7352745B2 (en) 2003-10-14 2006-12-13 Switching system with distributed switching fabric

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US51102103P 2003-10-14 2003-10-14
US51114203P 2003-10-14 2003-10-14
US51114103P 2003-10-14 2003-10-14
US51114503P 2003-10-14 2003-10-14
US51114303P 2003-10-14 2003-10-14
US51114003P 2003-10-14 2003-10-14
US51113803P 2003-10-14 2003-10-14
US51114403P 2003-10-14 2003-10-14
US51113903P 2003-10-14 2003-10-14
US56326204P 2004-04-16 2004-04-16
US10/965,444 US20050105538A1 (en) 2003-10-14 2004-10-12 Switching system with distributed switching fabric

Related Child Applications (7)

Application Number Title Priority Date Filing Date
US11/248,639 Division US20060029055A1 (en) 2003-10-14 2005-10-11 VLAN fabric network
US11/248,111 Division US20060039369A1 (en) 2003-10-14 2005-10-11 Multiplexing system having an automatically configured topology
US11/248,711 Division US20060029057A1 (en) 2003-10-14 2005-10-11 Time division multiplexing system
US11/248,707 Division US20060029071A1 (en) 2003-10-14 2005-10-11 Multiplexing system that supports a geographically distributed subnet
US11/248,710 Division US20060029056A1 (en) 2003-10-14 2005-10-11 Virtual machine task management system
US11/248,708 Division US20060029072A1 (en) 2003-10-14 2005-10-11 Switching system for virtual LANs
US11/610,281 Continuation US7352745B2 (en) 2003-10-14 2006-12-13 Switching system with distributed switching fabric

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US20050105538A1 true US20050105538A1 (en) 2005-05-19

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US10/965,444 Abandoned US20050105538A1 (en) 2003-10-14 2004-10-12 Switching system with distributed switching fabric
US11/248,710 Abandoned US20060029056A1 (en) 2003-10-14 2005-10-11 Virtual machine task management system
US11/248,708 Abandoned US20060029072A1 (en) 2003-10-14 2005-10-11 Switching system for virtual LANs
US11/248,707 Abandoned US20060029071A1 (en) 2003-10-14 2005-10-11 Multiplexing system that supports a geographically distributed subnet
US11/248,111 Abandoned US20060039369A1 (en) 2003-10-14 2005-10-11 Multiplexing system having an automatically configured topology
US11/248,711 Abandoned US20060029057A1 (en) 2003-10-14 2005-10-11 Time division multiplexing system
US11/248,639 Abandoned US20060029055A1 (en) 2003-10-14 2005-10-11 VLAN fabric network
US11/610,281 Active US7352745B2 (en) 2003-10-14 2006-12-13 Switching system with distributed switching fabric

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US11/248,710 Abandoned US20060029056A1 (en) 2003-10-14 2005-10-11 Virtual machine task management system
US11/248,708 Abandoned US20060029072A1 (en) 2003-10-14 2005-10-11 Switching system for virtual LANs
US11/248,707 Abandoned US20060029071A1 (en) 2003-10-14 2005-10-11 Multiplexing system that supports a geographically distributed subnet
US11/248,111 Abandoned US20060039369A1 (en) 2003-10-14 2005-10-11 Multiplexing system having an automatically configured topology
US11/248,711 Abandoned US20060029057A1 (en) 2003-10-14 2005-10-11 Time division multiplexing system
US11/248,639 Abandoned US20060029055A1 (en) 2003-10-14 2005-10-11 VLAN fabric network
US11/610,281 Active US7352745B2 (en) 2003-10-14 2006-12-13 Switching system with distributed switching fabric

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EP (1) EP1673683A4 (fr)
JP (1) JP2007507990A (fr)
WO (1) WO2005038599A2 (fr)

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US7983194B1 (en) * 2008-11-14 2011-07-19 Qlogic, Corporation Method and system for multi level switch configuration
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US20070071014A1 (en) 2007-03-29
US20060029072A1 (en) 2006-02-09
WO2005038599A3 (fr) 2006-09-08
US20060029055A1 (en) 2006-02-09
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US7352745B2 (en) 2008-04-01
US20060039369A1 (en) 2006-02-23
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US20060029057A1 (en) 2006-02-09

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