US20050070058A1 - Ild stack with improved cmp results - Google Patents
Ild stack with improved cmp results Download PDFInfo
- Publication number
- US20050070058A1 US20050070058A1 US10/672,769 US67276903A US2005070058A1 US 20050070058 A1 US20050070058 A1 US 20050070058A1 US 67276903 A US67276903 A US 67276903A US 2005070058 A1 US2005070058 A1 US 2005070058A1
- Authority
- US
- United States
- Prior art keywords
- layer
- depositing
- thickness
- angstroms
- cmp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 103
- 230000008569 process Effects 0.000 claims abstract description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 15
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 15
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 15
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 15
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 15
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 22
- 229910052721 tungsten Inorganic materials 0.000 claims description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- 238000004140 cleaning Methods 0.000 claims description 14
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000012861 aquazol Substances 0.000 claims description 3
- 229920006187 aquazol Polymers 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 76
- 235000012431 wafers Nutrition 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Definitions
- This invention generally relates to semiconductor processing methods including formation of metallization plugs and more particularly to an ILD stack and method for forming the same to with improved CMP thickness control and reduced metal residue following plug formation process.
- Metallization interconnects are critical to the proper electronic function of semiconductor devices.
- Several advances in semiconductor processing have been aimed at improving signal transport speed by reducing metal interconnect resistivities and improving resistance to electromigration effects.
- Copper has increasingly become a metal of choice in, for example, upper levels of metallization in a multi-level semiconductor device due to its low resistivity and higher resistance to electromigration.
- Tungsten (W) is still preferred for use in the lower metallization layers adjacent to the silicon substrate since it provides an effective diffusion barrier to metal diffusion from overlying metallization layers to react with the silicon substrate.
- Tungsten further has high resistance to electromigration and can effectively be used to fill high aspect ratio vias by chemical vapor deposition (CVD) processes.
- CVD chemical vapor deposition
- an oxide layer referred to as a first layer oxide or an inter-layer dielectric (ILD) is deposited following forming of CMOS transistors with protruding polysilicon gate electrodes.
- the first ILD layer fills the gaps between the polysilicon electrodes, followed by a CMP process to planarize the layer prior to forming tungsten plugs.
- Problems with prior art processes include the practice of using a doped oxide, for example doped with phosphorous or boron to provide a binary glass which improved the dielectric properties and which be heated and flowed following deposition to improved the topography planarity of the surface.
- Problems with using binary glasses is that they are frequently much softer than SiO 2 and have a high removal rate in a CMP process thereby making control of a final thickness of the first ILD layer including tungsten plugs difficult to control.
- the present invention provides an ILD dielectric layer stack and method for forming the same to allow improved control over thickness and reduced metallic residue.
- the method includes providing a semiconductor substrate including CMOS transistors including gate electrode portions; depositing a first layer including phosphorous doped SiO 2 over the semiconductor substrate to a thickness sufficient to fully cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO 2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and, forming metal filled local interconnects extending through a thickness portion of the first and second layers.
- CMP oxide chemical mechanical polish
- FIGS. 1A-1E are cross sectional side view representations of a portion of a semiconductor wafer at stages in device manufacture according to the method of the present invention.
- FIG. 2 is a process flow diagram including several embodiments of the present invention.
- FIGS. 1A-1E in an exemplary embodiment of the method of the present invention, side view portions of a semiconductor device are shown at stages in a semiconductor device integrated circuit manufacturing process.
- a conventional semiconductor substrate 12 for example silicon, including CMOS transistors 14 A and 14 B with protruding polysilicon gate electrode portions, e.g., 14 C and including adjacent source and drain regions e.g., 15 A and 15 B, as well as shallow trench isolation (STI) structures e.g., 16 A 16 B, and 16 C, all formed by conventional processes.
- STI shallow trench isolation
- a layer of silicon nitride 18 is deposited by conventional processes, for example LPCVD over active regions of the device to protect the CMOS transistor features and semiconductor substrate surface from diffusion of dopants included in a subsequently deposited overlying first ILD layer, also referred to as a local interconnect (LI) dielectric.
- LI local interconnect
- a first layer 20 A of an ILD layer stack is deposited to a thickness at least thick enough to cover a height of the protruding polysilicon electrode gate portions e.g., 14 C and fill intervening gaps between CMOS transistors 14 A and 14 B.
- the first ILD layer 20 A is deposited to a thickness of between about 4000 Angstroms and about 6000 Angstroms, more preferably about 5500 Angstroms to fill the gaps between protruding polysilicon electrodes e.g., 14 C of the CMOS transistors e.g., 14 A and 14 B.
- the first ILD layer portion 20 A is formed of a phosphorous doped SiO 2 according to a conventional HDP-CVD process using phosphine (PH 3 ) or TMP, more preferably PH 3 , at a temperature of about 550° C. to about 650° C. to form phosphosilicate glass (PSG).
- the PSG layer has a phosphorous doping level of about 2.5 weight % to about 4.5 weight % of phosphorous, more preferably from about 3.0 to about 4.0 weight % phosphorous.
- a second ILD layer 20 B of the ILD stack formed of undoped SiO 2 is deposited over the first ILD layer (PSG layer) at a thickness such that a subsequent CMP planarization process leaves from about 500 Angstroms to about 1000 Angstroms of the second ILD layer 20 B.
- the thickness of the second ILD layer 20 B is preferably between about 4000 Angstroms to about 6000 Angstroms.
- the second ILD layer 20 B is preferably formed in-situ by an HDP-CVD process where the phosphorous precursor flow, e.g., PH 3 is stopped to formed undoped silicate glass (USG), but may be formed in a separate PECVD process using silane and oxygen precursor or TEOS precursors to respectively form PEOX and PETEOS Oxide.
- a conventional CMP oxide process is carried out to remove the USG layer 20 B to leave from about 500 Angstroms to about 1000 Angstroms of the USG layer 20 B remaining overlying the PSG layer 20 A.
- conventional processes including photolithographically patterning and RIE etching the ILD layer stack including layers 20 A and 20 B is carried out to form trenches followed by deposition of a barrier layer e.g., Ti/TiN (not shown), and sputter deposition of tungsten (W) to fill the trenches to form local interconnects e.g., 22 A, 22 B, 22 C, and 22 D.
- a conventional W CMP process including an optional oxide buffing process is carried out to polish the tungsten back to expose the USG layer 20 B.
- the batch wafer cleaning process includes dipping a plurality, or batch of process wafers in an HF containing solution, for example, including about 5 wt. % to about 1.5 wt. % of 99.99% HF in deionized water with respect to a cleaning solution volume.
- the various and numerous advantages realized over prior art processes include better control over an ILD layer thickness following the CMP process while realizing the advantages of superior gap fill ability of the PSG layer.
- the removal rate of PSG material in a CMP process has found to depend strongly on the amount of phosphorous in the ILD layer. Since the wt % of phosphorous in the PSG film, and therefore the removal rate in a CMP process tends to vary from wafer to wafer, controlling the final ILD layer thickness of a PSG ILD layer has been found to be difficult to control.
- the ILD layer stack including the USG layer stack according to the present invention provides improved ILD layer thickness control and therefore reliability and reproducibility of an ILD layer thickness following an ILD layer CMP process while maintaining the gap filling ability of PSG in the first layer of the ILD layer stack.
- Yet another advantage realized by the present invention over prior art processes is that it has been found that the amount of residual metal, from both the tungsten plugs and residual CMP slurry particles (e.g., Fe, Ni, Co, W) adhering to the exposed upper portion of the ILD layer following tungsten CMP and oxide buffing is reduced by providing the undoped SiO 2 capping layer according to preferred embodiments. It is believed that the reason for reduction of metallic residue is due to the decreased electrostatic charge induced in the USG layer compared to PSG layer by the W CMP process. For example, it has been found that the PSG develops an electrostatic surface charge that is about 10 times that of USG which develops about zero electrostatic charge following a typical W CMP process.
- residual CMP slurry particles e.g., Fe, Ni, Co, W
- the wet cleaning (etching) process following W CMP allows a batch wafer cleaning process to be carried out as opposed to a single wafer process according to the prior art.
- variation in wet etching rates of PSG layer produced in the post W CMP cleaning process require single wafer cleaning processes to reduce wafer to wafer variation.
- a wet etching rate of the USG layer occurring in the cleaning process is relatively more uniform between wafers compared to a PSG layer, thereby allowing a wafer batch cleaning process to be undertaken which advantageously increases throughput by about 30 %.
- a semiconductor substrate including CMOS transistors having protruding polysilicon electrode portions is provided.
- a first PSG ILD layer of an ILD layer stack is deposited by an HDP-CVD process to a thickness greater than the height of the protruding polysilicon electrode portions.
- a second layer of the ILD layer stack a capping layer of USG is deposited over the PSG layer.
- an oxide CMP process is carried out to planarize the ILD layer stack leaving a thickness portion of the USG layer overlying the PSG layer.
- tungsten plugs are formed.
- a W CMP process and oxide buffing process is carried out to expose the USG layer.
- a wafer batch wet cleaning process is carried out.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
An ILD dielectric layer stack and method for forming the same, the method includes a semiconductor substrate including CMOS transistors with gate electrode portions; depositing a first layer including phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and forming metal filled local interconnects extending through a thickness portion of the first and second layers.
Description
- This invention generally relates to semiconductor processing methods including formation of metallization plugs and more particularly to an ILD stack and method for forming the same to with improved CMP thickness control and reduced metal residue following plug formation process.
- Metallization interconnects are critical to the proper electronic function of semiconductor devices. Several advances in semiconductor processing have been aimed at improving signal transport speed by reducing metal interconnect resistivities and improving resistance to electromigration effects. Copper has increasingly become a metal of choice in, for example, upper levels of metallization in a multi-level semiconductor device due to its low resistivity and higher resistance to electromigration. Tungsten (W), however, n is still preferred for use in the lower metallization layers adjacent to the silicon substrate since it provides an effective diffusion barrier to metal diffusion from overlying metallization layers to react with the silicon substrate. Tungsten further has high resistance to electromigration and can effectively be used to fill high aspect ratio vias by chemical vapor deposition (CVD) processes.
- According to prior art processes, an oxide layer, referred to as a first layer oxide or an inter-layer dielectric (ILD) is deposited following forming of CMOS transistors with protruding polysilicon gate electrodes. The first ILD layer fills the gaps between the polysilicon electrodes, followed by a CMP process to planarize the layer prior to forming tungsten plugs. Problems with prior art processes include the practice of using a doped oxide, for example doped with phosphorous or boron to provide a binary glass which improved the dielectric properties and which be heated and flowed following deposition to improved the topography planarity of the surface. Problems with using binary glasses is that they are frequently much softer than SiO2 and have a high removal rate in a CMP process thereby making control of a final thickness of the first ILD layer including tungsten plugs difficult to control.
- Therefore, there is a need in the semiconductor processing art to develop an improved ILD layer stack to maintain the advantages of doped oxide binary glasses while improving a structural stability including improved CMP thickness control.
- It is therefore an object of the invention to provide an improved ILD layer stack to maintain the advantages of doped oxide binary glasses while improving a structural stability including improved CMP thickness control, while overcoming other shortcomings of the prior art.
- To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides an ILD dielectric layer stack and method for forming the same to allow improved control over thickness and reduced metallic residue.
- In a first embodiment, the method includes providing a semiconductor substrate including CMOS transistors including gate electrode portions; depositing a first layer including phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to fully cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and, forming metal filled local interconnects extending through a thickness portion of the first and second layers.
- These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
-
FIGS. 1A-1E are cross sectional side view representations of a portion of a semiconductor wafer at stages in device manufacture according to the method of the present invention. -
FIG. 2 is a process flow diagram including several embodiments of the present invention. - Although the method of the present invention is explained by reference to formation of a first ILD layer, it will be appreciated that the process may be equally applied to subsequent overlying ILD layers including a tungsten plug formation process.
- Referring to
FIGS. 1A-1E , in an exemplary embodiment of the method of the present invention, side view portions of a semiconductor device are shown at stages in a semiconductor device integrated circuit manufacturing process. Referring toFIG. 1A , is shown aconventional semiconductor substrate 12, for example silicon, includingCMOS transistors 16 A - Still referring to
FIG. 1A , a layer ofsilicon nitride 18 is deposited by conventional processes, for example LPCVD over active regions of the device to protect the CMOS transistor features and semiconductor substrate surface from diffusion of dopants included in a subsequently deposited overlying first ILD layer, also referred to as a local interconnect (LI) dielectric. - Referring to
FIG. 1B , following deposition of thesilicon nitride layer 18, according to an aspect of the present invention, afirst layer 20A of an ILD layer stack is deposited to a thickness at least thick enough to cover a height of the protruding polysilicon electrode gate portions e.g., 14C and fill intervening gaps betweenCMOS transistors first ILD layer 20A is deposited to a thickness of between about 4000 Angstroms and about 6000 Angstroms, more preferably about 5500 Angstroms to fill the gaps between protruding polysilicon electrodes e.g., 14C of the CMOS transistors e.g., 14A and 14B. Preferably, the firstILD layer portion 20A is formed of a phosphorous doped SiO2 according to a conventional HDP-CVD process using phosphine (PH3) or TMP, more preferably PH3, at a temperature of about 550° C. to about 650° C. to form phosphosilicate glass (PSG). Preferably, the PSG layer has a phosphorous doping level of about 2.5 weight % to about 4.5 weight % of phosphorous, more preferably from about 3.0 to about 4.0 weight % phosphorous. - Referring to
FIG. 1C , according to another aspect of the present invention, asecond ILD layer 20B of the ILD stack, formed of undoped SiO2 is deposited over the first ILD layer (PSG layer) at a thickness such that a subsequent CMP planarization process leaves from about 500 Angstroms to about 1000 Angstroms of thesecond ILD layer 20B. - For example, the thickness of the
second ILD layer 20B is preferably between about 4000 Angstroms to about 6000 Angstroms. Thesecond ILD layer 20B is preferably formed in-situ by an HDP-CVD process where the phosphorous precursor flow, e.g., PH3 is stopped to formed undoped silicate glass (USG), but may be formed in a separate PECVD process using silane and oxygen precursor or TEOS precursors to respectively form PEOX and PETEOS Oxide. - Referring to
FIG. 1D , according to another aspect of the present invention, following deposition of thecapping USG layer 20B, a conventional CMP oxide process is carried out to remove theUSG layer 20B to leave from about 500 Angstroms to about 1000 Angstroms of theUSG layer 20B remaining overlying thePSG layer 20A. - Referring to
FIG. 1E , conventional processes including photolithographically patterning and RIE etching the ILD layerstack including layers USG layer 20B. - Following the W CMP process, a batch wafer cleaning process is carried out. For example, the batch wafer cleaning process includes dipping a plurality, or batch of process wafers in an HF containing solution, for example, including about 5 wt. % to about 1.5 wt. % of 99.99% HF in deionized water with respect to a cleaning solution volume.
- According to the present invention, the various and numerous advantages realized over prior art processes include better control over an ILD layer thickness following the CMP process while realizing the advantages of superior gap fill ability of the PSG layer. For example, the removal rate of PSG material in a CMP process has found to depend strongly on the amount of phosphorous in the ILD layer. Since the wt % of phosphorous in the PSG film, and therefore the removal rate in a CMP process tends to vary from wafer to wafer, controlling the final ILD layer thickness of a PSG ILD layer has been found to be difficult to control. For example small variations in phosphorus content in a PSG layer between about 2.0 wt % and about 5.0 wt % results in a removal rate variation of about 100 Angstroms/minute for a change of about 0.5 wt % phosphorous, and removal rates varying between about 1400 Angstroms/min and about 2000 Angstroms/min. By contrast, USG or undoped SiO2 has a relatively lower and uniform material removal rate from wafer to wafer.
- By providing the undoped SiO2, e.g., USG capping layer according to the present invention, improved structural stability and a relatively uniform CMP etching rate from wafer to wafer are achieved. The ILD layer stack including the USG layer stack according to the present invention provides improved ILD layer thickness control and therefore reliability and reproducibility of an ILD layer thickness following an ILD layer CMP process while maintaining the gap filling ability of PSG in the first layer of the ILD layer stack.
- Yet another advantage realized by the present invention over prior art processes is that it has been found that the amount of residual metal, from both the tungsten plugs and residual CMP slurry particles (e.g., Fe, Ni, Co, W) adhering to the exposed upper portion of the ILD layer following tungsten CMP and oxide buffing is reduced by providing the undoped SiO2 capping layer according to preferred embodiments. It is believed that the reason for reduction of metallic residue is due to the decreased electrostatic charge induced in the USG layer compared to PSG layer by the W CMP process. For example, it has been found that the PSG develops an electrostatic surface charge that is about 10 times that of USG which develops about zero electrostatic charge following a typical W CMP process.
- Yet an additional advantage realized by the present invention, is that the wet cleaning (etching) process following W CMP, allows a batch wafer cleaning process to be carried out as opposed to a single wafer process according to the prior art. For example, similar to the variability of the material removal rate for PSG in a CMP process, variation in wet etching rates of PSG layer produced in the post W CMP cleaning process, require single wafer cleaning processes to reduce wafer to wafer variation. By using a USG capping layer over the PSG layer, a wet etching rate of the USG layer occurring in the cleaning process is relatively more uniform between wafers compared to a PSG layer, thereby allowing a wafer batch cleaning process to be undertaken which advantageously increases throughput by about 30 %.
- Referring to
FIG. 2 is a process flow diagram including several embodiments of the present invention. In afirst process 201, a semiconductor substrate including CMOS transistors having protruding polysilicon electrode portions is provided. Inprocess 203, a first PSG ILD layer of an ILD layer stack is deposited by an HDP-CVD process to a thickness greater than the height of the protruding polysilicon electrode portions. Inprocess 205, a second layer of the ILD layer stack, a capping layer of USG is deposited over the PSG layer. Inprocess 207, an oxide CMP process is carried out to planarize the ILD layer stack leaving a thickness portion of the USG layer overlying the PSG layer. Inprocess 209, tungsten plugs are formed. Inprocess 211, a W CMP process and oxide buffing process is carried out to expose the USG layer. Inprocess 213, a wafer batch wet cleaning process is carried out. - The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.
Claims (24)
1. A method of forming an ILD dielectric layer stack to allow improved local interconnect formation comprising the steps of:
providing a semiconductor substrate comprising CMOS transistors comprising gate electrode portions;
depositing a first layer comprising phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to fully cover the gate electrode portions including intervening gaps;
depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process;
carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and,
forming metal filled local interconnects extending through a thickness portion of the first and second layers.
2. The method of claim 1 , wherein the step of forming metal filled local interconnects comprises:
forming local interconnect trenches;
depositing tungsten or an alloy thereof to fill the local interconnect trenches;
carrying out a tungsten CMP process to expose the second layer; and,
carrying out a batch wafer cleaning process.
3. The method of claim 2 , wherein the batch wafer cleaning process comprises an HF containing solution.
4. The method of claim 1 , wherein the metal is formed of tungsten or an alloy thereof.
5. The method of claim 1 , wherein the step of depositing a first layer comprises an HDP-CVD process comprising phosphine (PH3) source gas.
6. The method of claim 1 , wherein the step of depositing a second layer comprises a CVD process selected from the group consisting of PECVD and HDP-CVD.
7. The method of claim 1 , wherein the wherein the step of depositing a second layer comprises an in-situ HDP-CVD process with respect to the step of depositing a first layer.
8. The method of claim 1 , wherein the first layer is formed with a phosphorous content of from about 2.5 weight % to about 4.5 weight %.
9. The method of claim 1 , wherein the second layer comprises undoped SiO2 selected from the group consisting of USG, PEOX, and PETEOS oxide.
10. The method of claim 1 , wherein the first layer is deposited to a thickness of about 4000 to about 6000 Angstroms.
11. The method of claim 1 , wherein the second layer is deposited to a thickness of about 4000 to about 6000 Angstroms.
12. The method of claim 1 , wherein the second layer thickness portion is from about 500 Angstroms to about 1000 Angstroms.
13. A method of forming local interconnect (LI) dielectric layer stack to allow improved control over thickness and reduced metallic residue comprising the steps of:
providing a semiconductor substrate comprising CMOS transistors comprising gate electrode portions;
depositing a first layer comprising phosphosilicate glass (PSG) over the semiconductor substrate to a thickness sufficient to fully cover the gate electrode portions including intervening gaps;
depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process;
carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion;
forming LI trenches extending through a thickness of the first and second layers;
depositing tungsten to fill the LI trenches; and,
carrying out a tungsten CMP process to expose the second layer.
14. The method of claim 13 , further comprising carrying out a batch wafer cleaning process.
15. The method of claim 14 , wherein the batch wafer cleaning process comprises etching a portion of the second layer.
16. The method of claim 1 , wherein the step of depositing a first layer comprises an HDP-CVD process comprising phosphine (PH3) source gas.
17. The method of claim 1 , wherein the wherein the step of depositing a second layer comprises an in-situ HDP-CVD process with respect to the step of depositing a first layer.
18. The method of claim 1 , wherein the step of depositing a second layer comprises a PECVD process.
19. The method of claim 1 , wherein the first layer is formed with a phosphorous content of from about 2.5 weight % to about 4.5 weight %.
20. The method of claim 1 , wherein the second layer comprises undoped SiO2 selected from the group consisting of USG, PEOX, and PETEOS oxide.
21. The method of claim 1 , wherein the first layer is deposited to a thickness of about 4000 to about 6000 Angstroms.
22. The method of claim 1 , wherein the second layer is deposited to a thickness of about 4000 to about 6000 Angstroms.
23. The method of claim 1 , wherein the second layer thickness portion is from about 500 Angstroms to about 1000 Angstroms.
24.-28. (canceled)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/672,769 US6869836B1 (en) | 2003-09-26 | 2003-09-26 | ILD stack with improved CMP results |
TW093117017A TWI240369B (en) | 2003-09-26 | 2004-06-14 | ILD and LI dielectric layer stack forming method and LI dielectric stack |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/672,769 US6869836B1 (en) | 2003-09-26 | 2003-09-26 | ILD stack with improved CMP results |
Publications (2)
Publication Number | Publication Date |
---|---|
US6869836B1 US6869836B1 (en) | 2005-03-22 |
US20050070058A1 true US20050070058A1 (en) | 2005-03-31 |
Family
ID=34274780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/672,769 Expired - Lifetime US6869836B1 (en) | 2003-09-26 | 2003-09-26 | ILD stack with improved CMP results |
Country Status (2)
Country | Link |
---|---|
US (1) | US6869836B1 (en) |
TW (1) | TWI240369B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060148237A1 (en) * | 2004-12-30 | 2006-07-06 | Jang Sung H | Method for fabricating a semiconductor device |
CN100463136C (en) * | 2005-08-30 | 2009-02-18 | 东部电子有限公司 | Chemical mechanical polishing and method for manufacturing semiconductor device using the same |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140057439A1 (en) * | 2012-08-21 | 2014-02-27 | Jiandong Zhang | Method of Forming Interlayer Dielectrics |
CN109950136B (en) * | 2019-03-26 | 2022-03-18 | 上海华力集成电路制造有限公司 | Method for improving water mark generated by cleaning after nitrogen-doped carbide stacking |
CN112342531A (en) * | 2020-10-19 | 2021-02-09 | 绍兴同芯成集成电路有限公司 | Wafer manufacturing process for preparing ILD insulating layer by using low-frequency radio frequency plasma |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5895239A (en) * | 1998-09-14 | 1999-04-20 | Vanguard International Semiconductor Corporation | Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts |
US5950102A (en) * | 1997-02-03 | 1999-09-07 | Industrial Technology Research Institute | Method for fabricating air-insulated multilevel metal interconnections for integrated circuits |
US6274424B1 (en) * | 1997-11-03 | 2001-08-14 | Motorola, Inc. | Method for forming a capacitor electrode |
-
2003
- 2003-09-26 US US10/672,769 patent/US6869836B1/en not_active Expired - Lifetime
-
2004
- 2004-06-14 TW TW093117017A patent/TWI240369B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5950102A (en) * | 1997-02-03 | 1999-09-07 | Industrial Technology Research Institute | Method for fabricating air-insulated multilevel metal interconnections for integrated circuits |
US6274424B1 (en) * | 1997-11-03 | 2001-08-14 | Motorola, Inc. | Method for forming a capacitor electrode |
US5895239A (en) * | 1998-09-14 | 1999-04-20 | Vanguard International Semiconductor Corporation | Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060148237A1 (en) * | 2004-12-30 | 2006-07-06 | Jang Sung H | Method for fabricating a semiconductor device |
CN100463136C (en) * | 2005-08-30 | 2009-02-18 | 东部电子有限公司 | Chemical mechanical polishing and method for manufacturing semiconductor device using the same |
Also Published As
Publication number | Publication date |
---|---|
TWI240369B (en) | 2005-09-21 |
US6869836B1 (en) | 2005-03-22 |
TW200512873A (en) | 2005-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6200897B1 (en) | Method for manufacturing even dielectric layer | |
US5716890A (en) | Structure and method for fabricating an interlayer insulating film | |
US8552522B2 (en) | Dishing-free gap-filling with multiple CMPs | |
US6677247B2 (en) | Method of increasing the etch selectivity of a contact sidewall to a preclean etchant | |
US6191050B1 (en) | Interlayer dielectric with a composite dielectric stack | |
US7670946B2 (en) | Methods to eliminate contact plug sidewall slit | |
US7224068B2 (en) | Stable metal structure with tungsten plug | |
KR20100014714A (en) | A first inter-layer dielectric stack for non-volatile memory | |
US8236678B2 (en) | Tunable spacers for improved gapfill | |
US7109557B2 (en) | Sacrificial dielectric planarization layer | |
US7274049B2 (en) | Semiconductor assemblies | |
US6551901B1 (en) | Method for preventing borderless contact to well leakage | |
JP2003124144A (en) | Processing method for semiconductor chip | |
US6869836B1 (en) | ILD stack with improved CMP results | |
US6930040B2 (en) | Method of forming a contact on a silicon-on-insulator wafer | |
US6339027B1 (en) | Process for borderless stop in tin via formation | |
US6861352B2 (en) | Semiconductor structure having an improved pre-metal dielectric stack and method for forming the same | |
TWI240375B (en) | Integrated circuit structure and method of fabrication | |
US20050095843A1 (en) | Method for improving reliability of copper interconnects | |
EP1008175A1 (en) | Capped interlayer dielectric for chemical mechanical polishing | |
US6911395B1 (en) | Method of making borderless contacts in an integrated circuit | |
US6054397A (en) | BPSG planarization method having improved planarity and reduced chatter mark defects | |
US20050269709A1 (en) | Interconnect structure including tungsten nitride and a method of manufacture therefor | |
US6818555B2 (en) | Method for metal etchback with self aligned etching mask | |
TWI483407B (en) | Integrated circuits including barrier polish stop layers and methods for the manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD., TAIWA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSIAW, HAN-TI;JENG, SHWANG-MING;WANG, SHIH-MING;AND OTHERS;REEL/FRAME:014551/0005 Effective date: 20030901 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |