US20050040495A1 - Horizontal current bipolar transistor and fabrication method - Google Patents

Horizontal current bipolar transistor and fabrication method Download PDF

Info

Publication number
US20050040495A1
US20050040495A1 US10/677,643 US67764303A US2005040495A1 US 20050040495 A1 US20050040495 A1 US 20050040495A1 US 67764303 A US67764303 A US 67764303A US 2005040495 A1 US2005040495 A1 US 2005040495A1
Authority
US
United States
Prior art keywords
junction
recited
semiconductor
junction device
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/677,643
Other versions
US7038249B2 (en
Inventor
Tomislav Suligoj
Petar Biljanovic
Kang Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of California
Original Assignee
University of California
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of California filed Critical University of California
Priority to US10/677,643 priority Critical patent/US7038249B2/en
Assigned to REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE reassignment REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BILJANOVIC, PETAR, SULIGOJ, TOMISLAV, WANG, KANG L.
Publication of US20050040495A1 publication Critical patent/US20050040495A1/en
Application granted granted Critical
Publication of US7038249B2 publication Critical patent/US7038249B2/en
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6625—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H01L29/1008—Base region of bipolar transistors of lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

Definitions

  • the present invention pertains generally to bipolar transistor structures, and more particularly to bipolar transistor structures incorporated into integrated circuits.
  • mainstream silicon bipolar transistor structures are typically processed using self-aligned, double polysilicon, trench-isolated technology. Although improved over the years, with many new materials and processes introduced, those transistor structures are still based on similar geometry as the first double-diffused, pn-junction isolated, silicon bipolar devices; that is, the placement of electrodes, vertical current flow and interconnection system are basically the same. Heterojunction bipolar transistors are based on the same geometry, as well, although the technology is much different than that of Si/SiGe based devices.
  • LBTs lateral bipolar transistors
  • SOI silicon-on-insulator
  • CMOS-process-incorporated npn transistors There are LBT's processed in Si-substrate technology, but they are either lateral pnp transistors or CMOS-process-incorporated npn transistors.
  • Lateral pnp transistors are non-optimized devices processed in npn-based technology with inferior electrical characteristics compared to mainstream npn transistors.
  • CMOS compatible npn LBT's are also non-optimized devices, processed in CMOS-based technology with poor electrical characteristics.
  • bipolar transistor structure that overcomes some of traditional bipolar transistor disadvantages (e.g. complicated technology, large transistor area, inability to scale down), and which can extend the market of bipolar technology.
  • the present invention satisfies those needs, as well as others, and overcomes deficiencies in current bipolar transistor technology.
  • the present invention comprises a new type of bipolar transistor for use in integrated circuits, which we refer to as a Horizontal Current Bipolar Transistor (HCBT).
  • HCBT Horizontal Current Bipolar Transistor
  • This inventive HCBT which is processed by an inventive fabrication method, consumes a smaller area of chip surface, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size.
  • the active device is processed on the sidewall of an n-hill so that the HCBT surface footprint does not depend on the desired area of active device region (emitter area). Therefore, large current driving capabilities can be obtained with the minimal consumption of chip surface.
  • Surface reduction is due to the higher ratio of active to total device area, which is approximately 20% to approximately 30% in the HCBT of the present invention compared to approximately 2% to approximately 5% in state of the art vertical current transistors. This ratio cannot be decreased by lithography resolution shrinkage, and in an HCBT it will be improved by a factor of ⁇ 2 with resolution scaling down by a factor of ⁇ .
  • the active device is extended in depth.
  • the device area in 0.25/0.1 (resolution/alignment margin) lithography rules is only 2.73 ⁇ m 2 for an emitter area of 0.7 ⁇ m 2 .
  • HCBT's high frequency characteristics are improved by the reduction of capacitances due to the reduced pn-junction areas and by doping profile engineering. More particularly, the collector-base (C BC ) and collector-substrate (C CS ) capacitances are decreased in an HCBT, thereby improving high frequency characteristics of transistor. Additionally, the same doping profiles of the active transistor region can be obtained as in vertical current devices.
  • HCBT structure is planar and its collector and emitter n + polysilicon layer enables simple integration and device interconnection.
  • a typical embodiment of a HCBT fabrication process according to the present invention requires only five lithography masks up to one layer of metallization, compared to the six to eight masks typically required by state of art vertical current devices. Furthermore, the present invention offers the possibility of fabricating a self-aligned bipolar device with only three to four masks with the same or even improved electrical performances.
  • HCBT fabrication requires fewer technological steps that with conventional transistors. For example, an HCBT according to the invention is processed with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires about ten fewer etching processes and one or two fewer thermal oxidations than in a typical SST process. This leads to lower production costs and simpler fabrication.
  • An HCBT structure according to the present invention can extend the applications of silicon bipolar technology to very high-speed circuits. Also, decreased device size and simpler fabrication technology make an HCBT attractive to other applications, which are not typically bipolar. For example, high packing density makes an HCBT attractive for VLSI/ULSI high density digital circuits, which are currently CMOS exclusive. The horizontal current concept will improve I 2 L circuit characteristics considerably, increasing speed and possible replacement of CMOS with I 2 L. Since this technology overcomes some of traditional bipolar transistor disadvantages (e.g. complicated technology, large transistor area, inability to scale down), it can extend the market of bipolar technology.
  • FIG. 1 is a schematic side view in cross-section of a Horizontal Current Bipolar Transistor (HCBT) according to the present invention.
  • HCBT Horizontal Current Bipolar Transistor
  • FIG. 2 is an SEM picture of an actual Horizontal Current Bipolar Transistor (HCBT) according to the invention in 1 ⁇ m technology, where the passivation oxide has been etched away to expose the active sidewalls of the n-hill.
  • HCBT Horizontal Current Bipolar Transistor
  • FIG. 3 is a diagram of a simulated Horizontal Current Bipolar Transistor (HCBT) according to the present invention in 0.25 ⁇ m technology.
  • HCBT Horizontal Current Bipolar Transistor
  • FIG. 6A through FIG. 6F is a flow diagram schematically illustrating an embodiment of a fabrication process for the Horizontal Current Bipolar Transistor (HCBT) shown in FIG. 1 .
  • HCBT Horizontal Current Bipolar Transistor
  • FIG. 1 through FIG. 6 for illustrative purposes the present invention is embodied in the apparatus and methods generally shown and described in FIG. 1 through FIG. 6 . It will be appreciated that the apparatus may vary as to configuration and as to details of the parts, and that the method may vary as to the specific steps and their sequence, without departing from the basic concepts as disclosed herein.
  • FIG. 1 an embodiment of a Horizontal Current Bipolar Transistor (HCBT) 10 according to the present invention is schematically shown.
  • the device comprises p-type substrate 12 , p-channel stoppers 14 a, 14 b, n-hill 16 with p-region 18 , isolation silicon dioxide 20 a, 20 b, n + polysilicon 22 a, 22 b, collector 24 , base 26 , emitter 28 , and surrounding passivation oxide 30 .
  • FIG. 2 shows an SEM picture of such an HCBT in 1 ⁇ m lithography resolution and provides a perspective view of the device with the passivation oxide etched away so that the active sidewalls are exposed.
  • the base metal extends over one sidewall and a portion of the upper surface of the n-hill, and the emitter metal and collector metal is deposited over the n + polysilicon regions.
  • FIG. 3 shows an HCBT according to the present invention simulated in 0.25 ⁇ m lithography resolution.
  • the electrical characteristics of the HCBT was examined and compared to a modern, state of art Super-Self Aligned Transistor (SST), simulated assuming the same design rules and doping profiles of the active transistor region.
  • Simulation model parameters were set according to experimental data and are applied to both the HCBT and SST structures. Gummel plots of both structures are depicted in FIG. 4 .
  • the base is one-side contacted, and the base resistance (R B ) is higher than in two-side contacted SST structure. The influence of higher base resistance can be observed at higher currents in FIG. 4 .
  • C BC collector-base capacitance
  • f T and f max are higher for the HCBT structure than those of the SST.
  • the compensation of the increased RB by reduced CBC is even more pronounced in the three-dimensional considerations of HCBT and SST structures since parasitic parts have smaller volume in HCBT. Also, this effect will be more pronounced by further lithography scaling.
  • R B can be decreased by contacting the base at the front and back sides of emitter n + polysilicon.
  • This technology called a self-aligned HCBT will decrease R B to the same value as in SST structures. It would result, in addition to reduced C BC , in superior high frequency characteristics, still maintaining other HCBT advantages.
  • HCBT structure of the present invention can be processed by different technological steps and parameters (use of different processes, process parameters, and the sequence of process steps) that can vary depending on transistor's purpose, desired device properties, process complexity, etc.
  • TSUPREM 4 a two-dimensional process simulation program, assuming lithography resolution in the range of 1 ⁇ m to 0.25 ⁇ m and mask alignment tolerances in the range of 1 ⁇ m to 0.1 ⁇ m.
  • lithography resolution in the range of 1 ⁇ m to 0.25 ⁇ m
  • mask alignment tolerances in the range of 1 ⁇ m to 0.1 ⁇ m.
  • different structures were experimentally verified by applying 1 ⁇ m lithography resolution and alignment tolerances in the range of 1 ⁇ m to 0.3 ⁇ m.
  • the HCBT of the present invention is preferably fabricated using a commercially available p-type wafer with resistivity of approximately 1-20 ⁇ -cm as the p-substrate 12 for the device.
  • a collector n-region is established by conventional high-energy phosphorus ion implantation.
  • an oxide buffer layer 50 is formed over the surface of the wafer by thermal oxidation at approximately 850° C. for approximately six minutes in a dry O 2 atmosphere.
  • the wafer is then additionally annealed at high temperature ( ⁇ 1050° C.), so that the phosphorus atoms are redistributed.
  • parameters of the foregoing phosphorus ion implantation and annealing steps are set to achieve the desired doping profile in the collector region, taking into account that it affects device performance and should be designed in accordance with particular device application. These steps are equivalent to buried layer ion implantation, epitaxial growth and selective collector implantation in conventional Super Self-Aligned Transistor (SST) fabrication.
  • SST Super Self-Aligned Transistor
  • n-hill cap layer is then formed by deposition of a silicon nitride film 52 over the oxide layer 50 .
  • other cap layer materials can be used as well, such as polysilicon, oxinitride, metals, etc., with or without buffer oxide.
  • Photoresist 54 is then deposited over the nitride layer and patterned by a lithography mask. The nitride-oxide double layer is then selectively removed, and the n-doped silicon is anisotropically etched in a way that p-substrate 12 is reached and the isolated n-hill 14 is established.
  • p-channel stoppers 14 a, 14 b are formed by, for example, implanting boron ions at zero degrees, to increase p-type doping in the field around the n-hill to prevent inversion channel formation and collector-collector shorts.
  • the n-hill is protected from ion penetration during the channel stopper formation by the nitride-oxide cap layer that remains due to selective patterning.
  • sidewall roughness is minimized by several means: (i) the optimization of photoresist treatment (thickness, baking, exposure and development parameters), (ii) the use of wet etching processes (both crystallographic dependent or isotropic), or (iii) thermal oxidation. Satisfactory roughness levels for shallow junctions processing has been obtained in this manner.
  • isolation oxide 56 e.g., silicon dioxide
  • CVD chemical vapor deposition
  • CMP chemically-mechanically planarized
  • SOI silicon-on-insulator
  • the revealed sidewall surface of the n-hill defines the active transistor region area and could be adjusted according to desired transistor applications.
  • isolation oxide densification can be carried out either after deposition or after the etch-back step.
  • Photoresist is then deposited and patterned by a second lithography mask.
  • This photoresist defines intrinsic and extrinsic base regions 62 , 64 , respectively, which are both ion implanted, so the photoresist process steps should be designed to ensure good implantation masking properties.
  • the intrinsic base region 62 is angle-implanted and segment 66 of p-region 18 is formed on one side on the n-hill 16 , as shown in FIG. 6C .
  • the process is self-aligned by adjusting wafer tilt and rotation angles to protect the back and front sides of n-hill 16 from p-type doping.
  • angled ion implantation is advantageous since the larger volume of neutral base is formed beneath the level of isolation oxide, protecting the structure from the formation of depletion or inversion channels near the Si—SiO 2 interface and emitter-collector punchthrough in that region.
  • boron diffusion can also be used as base-doping process. In that case, additional ion implantation can be done to increase the doping in the bottom of base.
  • the intrinsic base can be grown on the n-hill sidewall by an epitaxial process. If the intrinsic base is ion-implanted, it can be done prior to the deposition of photoresist since this process is self-aligned to the n-hill sidewall anyway. In that way, the possible contamination from photoresist during implantation is avoided.
  • the extrinsic base region 64 is implanted on the upper surface of n-hill 16 using the same mask, but the boron concentration on the top of n-hill 16 is increased to reduce base resistance.
  • segment 68 of p-region 18 is formed on the top of the n-hill 16 , as shown in FIG. 6D .
  • a wafer is angled in opposite direction than for the intrinsic base implant to protect intrinsic base sidewall from additional doping.
  • photoresist 60 is then removed and the collector and emitter polysilicon is deposited.
  • Either in-situ doped or ion implanted doping methods can be used for the collector and emitter n + polysilicon layers.
  • a thin polysilicon layer 70 is first deposited and the collector and emitter regions are separately implanted at symmetrical tilt angles 72 a, 72 b, respectively.
  • additional undoped polysilicon 74 is deposited.
  • the deposition-implantation-deposition process can be repeated to improve uniformity of n + polysilicon doping profile, e.g., for relatively thicker active polysilicon films.
  • Such a multi-step approach improves perimeter depletion and emitter plug effects and enables the same emitter doping profile at different heights on the n-hill sidewall.
  • in-situ doping technique only one deposition is required.
  • the polysilicon is chemically-mechanically planarized and etched-back thereby defining the collector and emitter n + polysilicon layers 76 a, 76 b, respectively.
  • the etching process has to be selective to the p-type monocrystalline base region. Both dry and wet selective etch chemistries can be used to remove surrounding polysilicon film and leave the base intact.
  • the final polysilicon thickness determines the electrical parameters of transistor, such as, active device area, emitter resistance, base resistance, emitter-base capacitance and breakdown voltage. Note that better controllability of emitter-extrinsic base distance can be achieved if another CMP is performed after a passivation oxide deposition.
  • the emitter-extrinsic base distance is determined by the passivation oxide thickness and the extrinsic base is implanted after that CMP.
  • the final device application and the optimization of certain device parameters dictate polysilicon thickness and technology, as well as other process parameters.
  • a third mask is used to remove polysilicon from the front and back sides of the n-hill 16 and to define the emitter and collector active regions.
  • Either hard mask (e.g. oxide, nitride) or photoresist can be employed.
  • oxide layer 50 and nitride film 52 can be etched away and passivation oxide 30 deposited. Annealing and emitter drive-in diffusion is then carried out. Then, fourth and fifth masks are used for contact hole definition and metallization to yield the device illustrated in FIG. 1 .
  • suicides can be used in self-aligned process to decrease the extrinsic base, emitter and collector sheet resistances before metallization using sidewall spacer on the n-hill sidewalls.
  • hydrogen passivation can be carried out to improve Si—SiO 2 interface properties. This is useful in an HCBT structure to decrease Shockley-Read-Hall recombination current at the intrinsic base sidewall surface since the intrinsic base is not completely surrounded by highly doped extrinsic base.
  • a (110) silicon wafer can be used as a substrate, which makes it possible to use crystallographic dependant etching for the minimization of the n-hill sidewall roughness.
  • the flat and smooth sidewalls can be obtained, corresponding to the (111) crystal planes, that are perpendicular to the surface in (110) wafers. Accordingly, this embodiment beneficially offers decreased sidewall roughness and further offers etch protection of the sidewall.
  • the active sidewall can be aligned to (100) crystal plane as well, which is also perpendicular to the surface in (110) wafers.
  • the HCBT structure can be processed without nitride layer, if the extrinsic base p+ region is implanted and activated before the deposition or doping of polysilicon.
  • the p+ extrinsic base protects the n-hill, if crystallographic dependant etchant is used for polysilicon etch, since it etches p+ silicon/polysilicon extremely slowly.
  • Such a structure can result in the reduced collector-base capacitance and increased breakdown voltage if a part of the n-hill is etched from the top during polysilicon etching.
  • the fabrication process is compatible with Silicon-On-Insulator (SOI) substrates.
  • SOI Silicon-On-Insulator
  • the buried oxide in SOI serves as the isolation oxide, which is processed by the CMP and etch-back in the presented process.
  • the base which is implanted in the n-hill sidewall, can be processed by the epitaxial growth, either silicon or silicon-germanium, either before or after isolation oxide process.
  • the high-quality films can be formed by the epitaxial growth due to the low-defect (111) sidewalls when (110) wafers are used as HCBT substrate. Such a process can offer a further degree of optimization of HCBT structure.
  • the HCBT technology of the present invention is suitable for the integration with pillar-like CMOS devices and other devices to achieve system-on-chip and/or BiCMOS integration.
  • the active sidewalls of the CMOS transistors can be aligned either to (100) or to (111) crystal planes thus achieving optimized device performance, e.g. pMOS to (111) crystal planes and nMOS to (100) crystal planes for the maximum channel mobility.
  • this invention can be used in all of the applications of existing bipolar junction devices. For example, in addition to silicon IC's, the invention can be applied to SiGe and other compound semiconductor technologies.
  • junction devices can be fabricated in this way, including pn, npn, pnp, pin, pip junction devices and the like by simply selecting the desired materials (e.g., Group II, III, IV, V, and VI and quaternaries and tertiaries thereof) and corresponding dopants.
  • Typical bipolar applications include high speed digital (ECL, CML, I 2 L) circuits, wireless and communication technologies, high frequency electronics, BiCMOS, analog circuits, etc.
  • the invention can be applied to MOS technology-based circuits since the HCBT technology described herein overcomes some of the traditional bipolar technology disadvantages, such as: complicated and expensive technology, large foot print of transistor, unimprovement of device performance with shrinking lithography resolution.
  • HCBT technology can reach higher device per area and logic function per area density in comparison to today's dominant CMOS technology, still maintaining bipolar advantages that is higher speed of operation. Furthermore, HCBT technology is suitable for vertical BiCMOS circuits. This can offer many improvements to BiCMOS circuits used currently in all high-speed communication applications.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

A bipolar transistor structure for use in integrated circuits where the active device is processed on the sidewall of an n-hill so that the surface footprint does not depend on the desired area of active device region (emitter area). This structure, which is referred to as a Horizontal Current Bipolar Transistor (HCBT), consumes a smaller area of chip surface than conventional devices, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size. The device is fabricated with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires fewer etching processes and thermal oxidations than in conventional devices.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to, and is a 35 U.S.C. §111 (a) and 37 C.F.R. §1.53(b) continuation-in-part of, co-pending PCT international application serial number PCT/US02/10402 filed on Apr. 1, 2002 which designates the U.S., incorporated herein by reference in its entirety, and which claims priority to U.S. provisional application Ser. No. 60/281,005 filed on Apr. 2, 2001, incorporated herein by reference in its entirety.
    • STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
  • Not Applicable
    • REFERENCE TO A COMPUTER PROGRAM APPENDIX
  • Not Applicable
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention pertains generally to bipolar transistor structures, and more particularly to bipolar transistor structures incorporated into integrated circuits.
  • 2. Description of the Background Art
  • In the current state of the art, mainstream silicon bipolar transistor structures are typically processed using self-aligned, double polysilicon, trench-isolated technology. Although improved over the years, with many new materials and processes introduced, those transistor structures are still based on similar geometry as the first double-diffused, pn-junction isolated, silicon bipolar devices; that is, the placement of electrodes, vertical current flow and interconnection system are basically the same. Heterojunction bipolar transistors are based on the same geometry, as well, although the technology is much different than that of Si/SiGe based devices.
  • Another family of bipolar structures, those with horizontal current flow, are primarily fabricated in silicon technology and are called lateral bipolar transistors (LBTs). LBTs are mainly processed using silicon-on-insulator (SOI) technology. Those transistors often exhibit inferior high-frequency characteristics compared to state-of-art silicon substrate devices. There are LBT's processed in Si-substrate technology, but they are either lateral pnp transistors or CMOS-process-incorporated npn transistors. Lateral pnp transistors are non-optimized devices processed in npn-based technology with inferior electrical characteristics compared to mainstream npn transistors. CMOS compatible npn LBT's are also non-optimized devices, processed in CMOS-based technology with poor electrical characteristics.
  • Therefore, there is a need for a bipolar transistor structure that overcomes some of traditional bipolar transistor disadvantages (e.g. complicated technology, large transistor area, inability to scale down), and which can extend the market of bipolar technology. The present invention satisfies those needs, as well as others, and overcomes deficiencies in current bipolar transistor technology.
    • BRIEF SUMMARY OF THE INVENTION
  • The present invention comprises a new type of bipolar transistor for use in integrated circuits, which we refer to as a Horizontal Current Bipolar Transistor (HCBT). This inventive HCBT, which is processed by an inventive fabrication method, consumes a smaller area of chip surface, thereby enabling higher packing density of devices and/or the reduction of integrated circuit die size.
  • By way of example, and not of limitation, in accordance with the present invention the active device is processed on the sidewall of an n-hill so that the HCBT surface footprint does not depend on the desired area of active device region (emitter area). Therefore, large current driving capabilities can be obtained with the minimal consumption of chip surface. Surface reduction is due to the higher ratio of active to total device area, which is approximately 20% to approximately 30% in the HCBT of the present invention compared to approximately 2% to approximately 5% in state of the art vertical current transistors. This ratio cannot be decreased by lithography resolution shrinkage, and in an HCBT it will be improved by a factor of λ2 with resolution scaling down by a factor of λ. By optimizing an HCBT for minimum area, the smallest practical footprint for a given lithography resolution can be achieved. In such a case, the active device is extended in depth. For example, the device area in 0.25/0.1 (resolution/alignment margin) lithography rules is only 2.73 μm2 for an emitter area of 0.7 μm2.
  • An HCBT's high frequency characteristics are improved by the reduction of capacitances due to the reduced pn-junction areas and by doping profile engineering. More particularly, the collector-base (CBC) and collector-substrate (CCS) capacitances are decreased in an HCBT, thereby improving high frequency characteristics of transistor. Additionally, the same doping profiles of the active transistor region can be obtained as in vertical current devices. HCBT structure is planar and its collector and emitter n+ polysilicon layer enables simple integration and device interconnection.
  • A typical embodiment of a HCBT fabrication process according to the present invention requires only five lithography masks up to one layer of metallization, compared to the six to eight masks typically required by state of art vertical current devices. Furthermore, the present invention offers the possibility of fabricating a self-aligned bipolar device with only three to four masks with the same or even improved electrical performances. In addition, HCBT fabrication requires fewer technological steps that with conventional transistors. For example, an HCBT according to the invention is processed with a single polysilicon layer, without an epitaxial process, without demanding trench isolation technology, and with reduced thermal budget. Fabrication requires about ten fewer etching processes and one or two fewer thermal oxidations than in a typical SST process. This leads to lower production costs and simpler fabrication.
  • An HCBT structure according to the present invention can extend the applications of silicon bipolar technology to very high-speed circuits. Also, decreased device size and simpler fabrication technology make an HCBT attractive to other applications, which are not typically bipolar. For example, high packing density makes an HCBT attractive for VLSI/ULSI high density digital circuits, which are currently CMOS exclusive. The horizontal current concept will improve I2L circuit characteristics considerably, increasing speed and possible replacement of CMOS with I2L. Since this technology overcomes some of traditional bipolar transistor disadvantages (e.g. complicated technology, large transistor area, inability to scale down), it can extend the market of bipolar technology.
  • Further advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be more fully understood by reference to the following drawings which are for illustrative purposes only:
  • FIG. 1 is a schematic side view in cross-section of a Horizontal Current Bipolar Transistor (HCBT) according to the present invention.
  • FIG. 2 is an SEM picture of an actual Horizontal Current Bipolar Transistor (HCBT) according to the invention in 1 μm technology, where the passivation oxide has been etched away to expose the active sidewalls of the n-hill.
  • FIG. 3 is a diagram of a simulated Horizontal Current Bipolar Transistor (HCBT) according to the present invention in 0.25 μm technology.
  • FIG. 4 is a graph showing collector (IC) and base (IB) currents versus base-emitter voltage (VBE) for an SST and the HCBT simulation of FIG. 3 for the same emitter area, per emitter length of the HCBT, at a collector-emitter voltage UCE=1 V.
  • FIG. 5 is a graph showing cutoff frequency (fT) and maximum frequency of oscillations (fmax) versus collector current (IC) of an SST and the HCBT simulation of FIG. 3, at collector-emitter voltage UCE=1V, where the emitter height of the HCBT is hE=0.3 μm and the emitter width of the SST is wE=0.25 μm.
  • FIG. 6A through FIG. 6F is a flow diagram schematically illustrating an embodiment of a fabrication process for the Horizontal Current Bipolar Transistor (HCBT) shown in FIG. 1.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Referring more specifically to the drawings, for illustrative purposes the present invention is embodied in the apparatus and methods generally shown and described in FIG. 1 through FIG. 6. It will be appreciated that the apparatus may vary as to configuration and as to details of the parts, and that the method may vary as to the specific steps and their sequence, without departing from the basic concepts as disclosed herein.
  • Referring first to FIG. 1, an embodiment of a Horizontal Current Bipolar Transistor (HCBT) 10 according to the present invention is schematically shown. In the embodiment shown, the device comprises p-type substrate 12, p- channel stoppers 14 a, 14 b, n-hill 16 with p-region 18, isolation silicon dioxide 20 a, 20 b, n+ polysilicon 22 a, 22 b, collector 24, base 26, emitter 28, and surrounding passivation oxide 30. FIG. 2 shows an SEM picture of such an HCBT in 1 μm lithography resolution and provides a perspective view of the device with the passivation oxide etched away so that the active sidewalls are exposed. As can be seen, the base metal extends over one sidewall and a portion of the upper surface of the n-hill, and the emitter metal and collector metal is deposited over the n+ polysilicon regions.
  • FIG. 3 shows an HCBT according to the present invention simulated in 0.25 μm lithography resolution. The electrical characteristics of the HCBT was examined and compared to a modern, state of art Super-Self Aligned Transistor (SST), simulated assuming the same design rules and doping profiles of the active transistor region. Simulation model parameters were set according to experimental data and are applied to both the HCBT and SST structures. Gummel plots of both structures are depicted in FIG. 4. In the HCBT structure, note that the base is one-side contacted, and the base resistance (RB) is higher than in two-side contacted SST structure. The influence of higher base resistance can be observed at higher currents in FIG. 4.
  • To justify the effect of base resistance, high-frequency characteristics have been simulated. FIG. 5 shows that the same cut-off frequency (fT) and maximum frequency of oscillations (fmax) are obtained for the HCBT's emitter height hE=0.3 μm, which is larger than SST's emitter width (wE=0.25 μm). This means that reduction of collector-base capacitance (CBC) is dominant over the increase of RB. For smaller emitter heights, fT and fmax are higher for the HCBT structure than those of the SST. The compensation of the increased RB by reduced CBC is even more pronounced in the three-dimensional considerations of HCBT and SST structures since parasitic parts have smaller volume in HCBT. Also, this effect will be more pronounced by further lithography scaling.
  • Additionally, RB can be decreased by contacting the base at the front and back sides of emitter n+ polysilicon. This technology, called a self-aligned HCBT will decrease RB to the same value as in SST structures. It would result, in addition to reduced CBC, in superior high frequency characteristics, still maintaining other HCBT advantages.
  • One of the advantages of the HCBT structure of the present invention is that it can be processed by different technological steps and parameters (use of different processes, process parameters, and the sequence of process steps) that can vary depending on transistor's purpose, desired device properties, process complexity, etc. In developing a preferred fabrication process, different HCBT technologies were examined using TSUPREM 4, a two-dimensional process simulation program, assuming lithography resolution in the range of 1 μm to 0.25 μm and mask alignment tolerances in the range of 1 μm to 0.1 μm. Moreover, different structures were experimentally verified by applying 1 μm lithography resolution and alignment tolerances in the range of 1 μm to 0.3 μm.
  • Referring now to FIG. 6A through FIG. 6F, an embodiment of a process for fabricating the HCBT device shown in FIG. 1 can be seen. Referring first to FIG. 6A, the HCBT of the present invention is preferably fabricated using a commercially available p-type wafer with resistivity of approximately 1-20 Ω-cm as the p-substrate 12 for the device. As an initial step in the process, a collector n-region is established by conventional high-energy phosphorus ion implantation. Next, an oxide buffer layer 50 is formed over the surface of the wafer by thermal oxidation at approximately 850° C. for approximately six minutes in a dry O2 atmosphere. The wafer is then additionally annealed at high temperature (≈1050° C.), so that the phosphorus atoms are redistributed.
  • Note that parameters of the foregoing phosphorus ion implantation and annealing steps are set to achieve the desired doping profile in the collector region, taking into account that it affects device performance and should be designed in accordance with particular device application. These steps are equivalent to buried layer ion implantation, epitaxial growth and selective collector implantation in conventional Super Self-Aligned Transistor (SST) fabrication.
  • An n-hill cap layer is then formed by deposition of a silicon nitride film 52 over the oxide layer 50. However, other cap layer materials can be used as well, such as polysilicon, oxinitride, metals, etc., with or without buffer oxide. Photoresist 54 is then deposited over the nitride layer and patterned by a lithography mask. The nitride-oxide double layer is then selectively removed, and the n-doped silicon is anisotropically etched in a way that p-substrate 12 is reached and the isolated n-hill 14 is established. Next, p- channel stoppers 14 a, 14 b are formed by, for example, implanting boron ions at zero degrees, to increase p-type doping in the field around the n-hill to prevent inversion channel formation and collector-collector shorts. The n-hill is protected from ion penetration during the channel stopper formation by the nitride-oxide cap layer that remains due to selective patterning.
  • At this point, the structure appears as shown in FIG. 6A where portions of the layers of oxide 50, nitride 52 and photoresist 54 cap the n-hill 16.
  • Note that special attention has been paid to processing a high-quality sidewall surface on the n-hill where the active transistor region will be formed. Note that the photoresist's edge roughness is transferred to the n-hill sidewall by the etching process. A photoresist edge is inherently rough due to the finite dimensions of polymers that form photoresist. Such roughness is amplified by polymer aggregation process and presents limitation of HCBT, as well as of all pillar-like devices. In addition, in dry etching, sidewall defects could be caused by ions striking the sidewall surface. Accordingly, in the HCBT fabrication process of the present invention, sidewall roughness is minimized by several means: (i) the optimization of photoresist treatment (thickness, baking, exposure and development parameters), (ii) the use of wet etching processes (both crystallographic dependent or isotropic), or (iii) thermal oxidation. Satisfactory roughness levels for shallow junctions processing has been obtained in this manner.
  • Next, isolation oxide 56 (e.g., silicon dioxide) is deposited using chemical vapor deposition (CVD) or the like and chemically-mechanically planarized (CMP) to the area of line 58 as shown in FIG. 6B, and etched back as shown in FIG. 6C. In this “CMP and etch-back” technique, isolation between n-hills is achieved without the use of silicon-on-insulator (SOI) substrates. Note that the CMP step can be eliminated in the case of high packing density and closer placement of the n-hills or by using some other planarization technique. Furthermore, the revealed sidewall surface of the n-hill defines the active transistor region area and could be adjusted according to desired transistor applications.
  • At this point, protection thermal oxidation can be carried out. Note, however, that isolation oxide densification can be carried out either after deposition or after the etch-back step.
  • Photoresist is then deposited and patterned by a second lithography mask. This photoresist defines intrinsic and extrinsic base regions 62, 64, respectively, which are both ion implanted, so the photoresist process steps should be designed to ensure good implantation masking properties.
  • Next, the intrinsic base region 62 is angle-implanted and segment 66 of p-region 18 is formed on one side on the n-hill 16, as shown in FIG. 6C. The process is self-aligned by adjusting wafer tilt and rotation angles to protect the back and front sides of n-hill 16 from p-type doping. Also, angled ion implantation is advantageous since the larger volume of neutral base is formed beneath the level of isolation oxide, protecting the structure from the formation of depletion or inversion channels near the Si—SiO2 interface and emitter-collector punchthrough in that region. Analysis has shown that boron diffusion can also be used as base-doping process. In that case, additional ion implantation can be done to increase the doping in the bottom of base. Alternatively, the intrinsic base can be grown on the n-hill sidewall by an epitaxial process. If the intrinsic base is ion-implanted, it can be done prior to the deposition of photoresist since this process is self-aligned to the n-hill sidewall anyway. In that way, the possible contamination from photoresist during implantation is avoided.
  • Next, the extrinsic base region 64 is implanted on the upper surface of n-hill 16 using the same mask, but the boron concentration on the top of n-hill 16 is increased to reduce base resistance. In this way, segment 68 of p-region 18 is formed on the top of the n-hill 16, as shown in FIG. 6D. For this process, a wafer is angled in opposite direction than for the intrinsic base implant to protect intrinsic base sidewall from additional doping.
  • Referring now to FIG. 6E, photoresist 60 is then removed and the collector and emitter polysilicon is deposited. Either in-situ doped or ion implanted doping methods can be used for the collector and emitter n+ polysilicon layers. In the case of ion implanted polysilicon, a thin polysilicon layer 70 is first deposited and the collector and emitter regions are separately implanted at symmetrical tilt angles 72 a, 72 b, respectively. Then additional undoped polysilicon 74 is deposited. Occasionally, the deposition-implantation-deposition process can be repeated to improve uniformity of n+ polysilicon doping profile, e.g., for relatively thicker active polysilicon films. Such a multi-step approach improves perimeter depletion and emitter plug effects and enables the same emitter doping profile at different heights on the n-hill sidewall. In the case of in-situ doping technique, only one deposition is required.
  • Next, as shown in FIG. 6F, the polysilicon is chemically-mechanically planarized and etched-back thereby defining the collector and emitter n+ polysilicon layers 76 a, 76 b, respectively. Note that the etching process has to be selective to the p-type monocrystalline base region. Both dry and wet selective etch chemistries can be used to remove surrounding polysilicon film and leave the base intact. The final polysilicon thickness determines the electrical parameters of transistor, such as, active device area, emitter resistance, base resistance, emitter-base capacitance and breakdown voltage. Note that better controllability of emitter-extrinsic base distance can be achieved if another CMP is performed after a passivation oxide deposition. In this case, the emitter-extrinsic base distance is determined by the passivation oxide thickness and the extrinsic base is implanted after that CMP. The final device application and the optimization of certain device parameters dictate polysilicon thickness and technology, as well as other process parameters.
  • A third mask is used to remove polysilicon from the front and back sides of the n-hill 16 and to define the emitter and collector active regions. Either hard mask (e.g. oxide, nitride) or photoresist can be employed.
  • Next, oxide layer 50 and nitride film 52 can be etched away and passivation oxide 30 deposited. Annealing and emitter drive-in diffusion is then carried out. Then, fourth and fifth masks are used for contact hole definition and metallization to yield the device illustrated in FIG. 1.
  • Note that, in order to decrease the series resistances, suicides can be used in self-aligned process to decrease the extrinsic base, emitter and collector sheet resistances before metallization using sidewall spacer on the n-hill sidewalls. Additionally, hydrogen passivation can be carried out to improve Si—SiO2 interface properties. This is useful in an HCBT structure to decrease Shockley-Read-Hall recombination current at the intrinsic base sidewall surface since the intrinsic base is not completely surrounded by highly doped extrinsic base.
  • Although the description above contains many details of the invention, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. It will be appreciated from the foregoing that alternative embodiments are contemplated within the scope of the invention as well.
  • For example, a (110) silicon wafer can be used as a substrate, which makes it possible to use crystallographic dependant etching for the minimization of the n-hill sidewall roughness. The flat and smooth sidewalls can be obtained, corresponding to the (111) crystal planes, that are perpendicular to the surface in (110) wafers. Accordingly, this embodiment beneficially offers decreased sidewall roughness and further offers etch protection of the sidewall.
  • Furthermore, the active sidewall can be aligned to (100) crystal plane as well, which is also perpendicular to the surface in (110) wafers.
  • Also, the HCBT structure can be processed without nitride layer, if the extrinsic base p+ region is implanted and activated before the deposition or doping of polysilicon. The p+ extrinsic base protects the n-hill, if crystallographic dependant etchant is used for polysilicon etch, since it etches p+ silicon/polysilicon extremely slowly. Such a structure can result in the reduced collector-base capacitance and increased breakdown voltage if a part of the n-hill is etched from the top during polysilicon etching.
  • Note also that the fabrication process is compatible with Silicon-On-Insulator (SOI) substrates. In that case, the buried oxide in SOI serves as the isolation oxide, which is processed by the CMP and etch-back in the presented process.
  • Additionally, the base, which is implanted in the n-hill sidewall, can be processed by the epitaxial growth, either silicon or silicon-germanium, either before or after isolation oxide process. The high-quality films can be formed by the epitaxial growth due to the low-defect (111) sidewalls when (110) wafers are used as HCBT substrate. Such a process can offer a further degree of optimization of HCBT structure.
  • Based on the foregoing description, it will also be appreciated that the HCBT technology of the present invention is suitable for the integration with pillar-like CMOS devices and other devices to achieve system-on-chip and/or BiCMOS integration. The active sidewalls of the CMOS transistors can be aligned either to (100) or to (111) crystal planes thus achieving optimized device performance, e.g. pMOS to (111) crystal planes and nMOS to (100) crystal planes for the maximum channel mobility. Note also that this invention can be used in all of the applications of existing bipolar junction devices. For example, in addition to silicon IC's, the invention can be applied to SiGe and other compound semiconductor technologies. Also, various types of junction devices can be fabricated in this way, including pn, npn, pnp, pin, pip junction devices and the like by simply selecting the desired materials (e.g., Group II, III, IV, V, and VI and quaternaries and tertiaries thereof) and corresponding dopants. Typical bipolar applications include high speed digital (ECL, CML, I2L) circuits, wireless and communication technologies, high frequency electronics, BiCMOS, analog circuits, etc. Furthermore, the invention can be applied to MOS technology-based circuits since the HCBT technology described herein overcomes some of the traditional bipolar technology disadvantages, such as: complicated and expensive technology, large foot print of transistor, unimprovement of device performance with shrinking lithography resolution. Moreover, HCBT technology can reach higher device per area and logic function per area density in comparison to today's dominant CMOS technology, still maintaining bipolar advantages that is higher speed of operation. Furthermore, HCBT technology is suitable for vertical BiCMOS circuits. This can offer many improvements to BiCMOS circuits used currently in all high-speed communication applications.
  • Therefore, it will be appreciated that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, and their legal equivalents, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural, chemical, and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for.”

Claims (91)

1. A semiconductor junction device, comprising:
a substrate;
a first material extending substantially vertically from said substrate;
said first material having a sidewall and an upper surface; and
a second material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
2. A semiconductor junction device as recited in claim 1, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
3. A semiconductor junction device as recited in claim 1, wherein said junction comprises a pn junction.
4. A semiconductor junction device as recited in claim 1, wherein said junction comprises an in junction.
5. A semiconductor junction device as recited in claim 1, wherein said junction comprises a pi junction.
6. A semiconductor junction device, comprising:
a substrate;
a first material extending substantially vertically from said substrate;
said first material comprising a semiconductor material;
said first material having a sidewall and an upper surface; and
a second material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
7. A semiconductor junction device as recited in claim 6, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
8. A semiconductor junction device as recited in claim 6, wherein said junction comprises a pn junction.
9. A semiconductor junction device as recited in claim 6, wherein said junction comprises an in junction.
10. A semiconductor junction device as recited in claim 6, wherein said junction comprises a pi junction.
11. A semiconductor junction device, comprising:
a substrate;
a first material extending substantially vertically from said substrate;
said first material having a sidewall and an upper surface; and
a second material;
said second material comprising a semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
12. A semiconductor junction device as recited in claim 11, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
13. A semiconductor junction device as recited in claim 11, wherein said junction comprises a pn junction.
14. A semiconductor junction device as recited in claim 11, wherein said junction comprises an in junction.
15. A semiconductor junction device as recited in claim 11, wherein said junction comprises a pi junction.
16. A semiconductor junction device, comprising:
a substrate;
a first semiconductor material extending substantially vertically from said substrate;
said first material having a sidewall and an upper surface; and
a second semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
17. A semiconductor junction device as recited in claim 16, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
18. A semiconductor junction device as recited in claim 16, wherein said junction comprises a pn junction.
19. A semiconductor junction device as recited in claim 16, wherein said junction comprises an in junction.
20. A semiconductor junction device as recited in claim 16, wherein said junction comprises a pi junction.
21. A semiconductor junction device, comprising:
a substrate;
a first material extending substantially vertically from said substrate;
said first material comprising a doped semiconductor material;
said first material having a sidewall and an upper surface; and
a second material;
said second material comprising a semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
22. A semiconductor junction device as recited in claim 21, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
23. A semiconductor junction device as recited in claim 21, wherein said junction comprises a pn junction.
24. A semiconductor junction device as recited in claim 21, wherein said junction comprises an in junction.
25. A semiconductor junction device as recited in claim 21, wherein said junction comprises a pi junction.
26. A semiconductor junction device, comprising:
a substrate;
a first material extending substantially vertically from said substrate;
said first material comprising a semiconductor material;
said first material having a sidewall and an upper surface; and
a second material;
said second material comprising a doped semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
27. A semiconductor junction device as recited in claim 26, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
28. A semiconductor junction device as recited in claim 26, wherein said junction comprises a pn junction.
29. A semiconductor junction device as recited in claim 26, wherein said junction comprises an in junction.
30. A semiconductor junction device as recited in claim 26, wherein said junction comprises a pi junction.
31. A semiconductor junction device, comprising:
a substrate;
a first doped semiconductor material extending substantially vertically from said substrate;
said first material having a sidewall and an upper surface; and
a second doped semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
32. A semiconductor junction device as recited in claim 31, further comprising:
a first electrical contact connected to said first material; and
a second electrical contact connected to said second material.
33. A semiconductor junction device as recited in claim 31, wherein said junction comprises a pn junction.
34. A semiconductor junction device, comprising:
a substrate;
a first semiconductor material extending substantially vertically from said substrate;
said first material having a sidewall and an upper surface;
a second semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first semiconductor material; and
a third semiconductor material;
said third material joined to at least a portion of said second material;
wherein a first junction is formed between said first and second materials;
wherein a second junction is formed between said second and third materials; and
wherein said first material is electrically isolated from said third material.
35. A semiconductor junction device as recited in claim 34, further comprising:
a first electrical contact connected to said first material;
a second electrical contact connected to said second material; and
a third electrical contact connected to said third material.
36. A semiconductor junction device as recited in claim 34, wherein said first junction comprises a pn junction.
37. A semiconductor junction device as recited in claim 34, wherein said first junction comprises an in junction.
38. A semiconductor junction device as recited in claim 34, wherein said first junction comprises a pi junction.
39. A semiconductor junction device as recited in claim 34, wherein said second junction comprises a pn junction.
40. A semiconductor junction device as recited in claim 34, wherein said second junction comprises an in junction.
41. A semiconductor junction device as recited in claim 34, wherein said second junction comprises a pi junction.
42. A semiconductor junction device as recited in claim 34, wherein said first and second junctions are configured as a bipolar transistor.
43. A semiconductor junction device as recited in claim 42, wherein said bipolar transistor comprises a npn transistor.
44. A semiconductor junction device as recited in claim 42, wherein said bipolar transistor comprises a pnp transistor.
45. A semiconductor junction device as recited in claim 34, wherein said first and second junctions are configured as a pin junction device.
46. A semiconductor junction device as recited in claim 34, wherein said first and second junctions are configured as a pip junction device.
47. A semiconductor junction device, comprising:
a substrate;
a first material extending substantially vertically from said substrate;
said first material comprising a doped semiconductor material;
said first material having a sidewall and an upper surface;
a second material;
said second material comprising a semiconductor material;
said second material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first material; and
a third material;
said third material comprising a doped semiconductor material;
said third material joined to at least a portion of said second material;
wherein a first junction is formed between said first and second materials;
wherein a second junction is formed between said second and third materials; and
wherein said first material is electrically isolated from said third material.
48. A semiconductor junction device as recited in claim 47, further comprising:
a first electrical contact connected to said first material;
a second electrical contact connected to said second material; and
a third electrical contact connected to said third material.
49. A semiconductor junction device as recited in claim 47, wherein said first junction comprises a pn junction.
50. A semiconductor junction device as recited in claim 47, wherein said first junction comprises an in junction.
51. A semiconductor junction device as recited in claim 47, wherein said first junction comprises a pi junction.
52. A semiconductor junction device as recited in claim 47, wherein said second junction comprises a pn junction.
53. A semiconductor junction device as recited in claim 47, wherein said second junction comprises an in junction.
54. A semiconductor junction device as recited in claim 47, wherein said second junction comprises a pi junction.
55. A semiconductor junction device as recited in claim 47, wherein said first and second junctions are configured as a bipolar transistor.
56. A semiconductor junction device as recited in claim 55, wherein said bipolar transistor comprises a npn transistor.
57. A semiconductor junction device as recited in claim 55, wherein said bipolar transistor comprises a pnp transistor.
58. A semiconductor junction device as recited in claim 47, wherein said first and second junctions are configured as a pin junction device.
59. A semiconductor junction device as recited in claim 47, wherein said first and second junctions are configured as a pip junction device.
60. A semiconductor junction device, comprising:
a substrate;
a first doped semiconductor material extending substantially vertically from said substrate;
said first doped semiconductor material having a sidewall and an upper surface;
a second doped semiconductor material;
said second doped semiconductor material joined to at least a portion of said sidewall and to at least a portion of said upper surface of said first doped semiconductor material; and
a third doped semiconductor material;
said third doped semiconductor material joined to at least a portion of said second doped semiconductor material;
wherein a first junction is formed between said first and second materials;
wherein a second junction is formed between said second and third materials; and
wherein said first material is electrically isolated from said third material.
61. A semiconductor junction device as recited in claim 60, further comprising:
a first electrical contact connected to said first material;
a second electrical contact connected to said second material; and
a third electrical contact connected to said third material.
62. A semiconductor junction device as recited in claim 60, wherein said first junction comprises a pn junction.
63. A semiconductor junction device as recited in claim 60, wherein said second junction comprises a pn junction.
64. A semiconductor junction device as recited in claim 60, wherein said first and second junctions are configured as a bipolar transistor.
65. A semiconductor junction device as recited in claim 64, wherein said bipolar transistor comprises a npn transistor.
66. A semiconductor junction device as recited in claim 64, wherein said bipolar transistor comprises a pnp transistor.
67. A method of fabricating a semiconductor junction device, comprising:
forming a region of a first material extending substantially vertically from a substrate;
said first material having a sidewall and an upper surface; and
depositing a second material on at least a portion of said sidewall and on at least a portion of said upper surface of said first material;
wherein a junction is formed between said first and second materials.
68. A method as recited in claim 67, wherein said junction comprises a pn junction.
69. A method as recited in claim 67, wherein said junction comprises an in junction.
70. A method as recited in claim 67, wherein said junction comprises a pi junction.
71. A method as recited in claim 67, wherein at least one of said materials comprises a semiconductor material.
72. A method as recited in claim 67, wherein both of said materials comprise semiconductor materials.
73. A method as recited in claim 67, wherein at least one of said materials comprises a doped semiconductor material.
74. A method as recited in claim 67, wherein both of said materials comprises a doped semiconductor material.
75. A method of fabricating a semiconductor junction device, comprising:
forming a region of a first semiconductor material extending substantially vertically from a substrate;
said first material having a sidewall and an upper surface;
depositing a second semiconductor material on at least a portion of said sidewall and on at least a portion of said upper surface of said first material;
wherein a first junction is formed between said first and second materials;
forming a region of a third semiconductor material joined to at least a portion of said second material;
wherein a second junction is formed between said second and third materials; and
wherein said first material is electrically isolated from said third material.
76. A method as recited in claim 75, wherein said first junction comprises a pn junction.
77. A method as recited in claim 75, wherein said first junction comprises an in junction.
78. A method as recited in claim 75, wherein said first junction comprises a pi junction.
79. A method as recited in claim 75, wherein said second junction comprises a pn junction.
80. A method as recited in claim 75, wherein said second junction comprises an in junction.
81. A method as recited in claim 75, wherein said second junction comprises a pi junction.
82. A method as recited in claim 75, wherein said first and second junctions are configured as a bipolar transistor.
83. A method as recited in claim 82, wherein said bipolar transistor comprises a npn transistor.
84. A method as recited in claim 82, wherein said bipolar transistor comprises a pnp transistor.
85. A method as recited in claim 75, wherein said first and second junctions are configured as a pin junction device.
86. A method as recited in claim 75, wherein said first and second junctions are configured as a pip junction device.
87. A method as recited in claim 75, wherein at least one of said materials comprises a doped semiconductor material.
88. A method as recited in claim 75, where at least two of said materials comprising doped semiconductor materials.
89. A method as recited in claim 75, wherein said first, second and third materials comprise doped semiconductor materials.
90. A method of fabricating a semiconductor junction device, comprising:
forming a region of a first material extending substantially vertically from a substrate;
processing a collector n-doped region on a p-type silicon substrate by high-energy phosphorus ion implantation;
forming an oxide buffer layer over the surface of the substrate by thermal oxidation;
annealing the substrate at high temperature so that the phosphorus atoms are redistributed;
depositing a silicon nitride layer over the oxide layer to form n-hill cap layer;
depositing photoresist over the silicon nitride layer;
patterning said photoresist using a first lithography mask;
selectively removing the nitride-oxide double layer and anisotropically etching the n-doped silicon to reach the p-substrate and an n-hill having a least one sidewall and an upper surface is formed;
implanting boron ions to increase p-type doping in the field around the n-hill;
depositing silicon oxide over said p-substrate and said n-hill;
chemically-mechanically planarizing said silicon-dioxide;
etching back said silicon dioxide to form isolation regions around said n-hill;
depositing and pattering photoresist using a second lithography mask to define intrinsic and extrinsic base regions on said n-hill;
forming a p-region on one side of the n-hill by ion implanting the intrinsic base region; and
extending the p-region over the surface of the n-hill by ion implanting the extrinsic base region.
91. A method as recited in claim 90, further comprising:
removing the photoresist;
forming a doped polysilicon layer over said n-hill and substrate;
depositing undoped polysilicon over said doped polysilicon layer;
chemically-mechanically planarizing the polysilicon layers;
etching back said polysilicon layers selectively to the formed base so that at least a portion of the active sidewall is in contact with the polysilicon;
using a third lithography mask, removing polysilicon from the front and back sides of the n-hill to define emitter and collector active regions;
etching away the nitride layer and depositing passivation oxide;
carrying out annealing and emitter drive-in diffusion; and
forming electrical contacts to said base, emitter and collector regions.
US10/677,643 2001-04-02 2003-10-01 Horizontal current bipolar transistor and fabrication method Expired - Fee Related US7038249B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/677,643 US7038249B2 (en) 2001-04-02 2003-10-01 Horizontal current bipolar transistor and fabrication method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US28100501P 2001-04-02 2001-04-02
PCT/US2002/010402 WO2002080281A1 (en) 2001-04-02 2002-04-01 Horizontal current bipolar transistor
US10/677,643 US7038249B2 (en) 2001-04-02 2003-10-01 Horizontal current bipolar transistor and fabrication method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/010402 Continuation-In-Part WO2002080281A1 (en) 2001-04-02 2002-04-01 Horizontal current bipolar transistor

Publications (2)

Publication Number Publication Date
US20050040495A1 true US20050040495A1 (en) 2005-02-24
US7038249B2 US7038249B2 (en) 2006-05-02

Family

ID=23075552

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/677,643 Expired - Fee Related US7038249B2 (en) 2001-04-02 2003-10-01 Horizontal current bipolar transistor and fabrication method

Country Status (2)

Country Link
US (1) US7038249B2 (en)
WO (1) WO2002080281A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050196931A1 (en) * 2003-11-06 2005-09-08 Chartered Semiconductor Manufacturing, Ltd. Self-aligned lateral heterojunction bipolar transistor
WO2009081867A1 (en) 2007-12-20 2009-07-02 Asahi Kasei Emd Corporation Semiconductor device and method for manufacturing semiconductor devicedispositif à semi-conducteurrs et procédé de fabrication d'un dispositif à semi-conducteurs
US10720517B2 (en) * 2017-10-17 2020-07-21 University Of Zagreb Faculty Of Electrical Engineering And Computing Horizontal current bipolar transistor with floating field regions

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7173320B1 (en) * 2003-04-30 2007-02-06 Altera Corporation High performance lateral bipolar transistor
WO2006077502A1 (en) * 2005-01-18 2006-07-27 Nxp B.V. Bipolar transistor and method of fabricating the same
US9064808B2 (en) 2011-07-25 2015-06-23 Synopsys, Inc. Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same
US8609550B2 (en) 2011-09-08 2013-12-17 Synopsys, Inc. Methods for manufacturing integrated circuit devices having features with reduced edge curvature
US9040929B2 (en) 2012-07-30 2015-05-26 International Business Machines Corporation Charge sensors using inverted lateral bipolar junction transistors
US9842834B2 (en) 2015-12-21 2017-12-12 Marko Koricic Horizontal current bipolar transistors with improved breakdown voltages
US11139402B2 (en) 2018-05-14 2021-10-05 Synopsys, Inc. Crystal orientation engineering to achieve consistent nanowire shapes
US10483368B1 (en) * 2018-05-15 2019-11-19 International Business Machines Corporation Single crystalline extrinsic bases for bipolar junction structures
US11264458B2 (en) 2019-05-20 2022-03-01 Synopsys, Inc. Crystal orientation engineering to achieve consistent nanowire shapes

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4498092A (en) * 1980-09-16 1985-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor photoelectric conversion device
US5508553A (en) * 1993-11-01 1996-04-16 Nec Corporation Transversal bipolar transistor integrated with another transistor commonly provided on a semiconductor substrate
US6187646B1 (en) * 1996-12-20 2001-02-13 Sgs-Thomson Microelectroncis S.A. Method of manufacturing a capacitor as part of an integrated semiconductor circuit
US6429085B1 (en) * 1999-06-25 2002-08-06 Applied Micro Circuits Corporation Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback
US6586298B1 (en) * 2001-06-15 2003-07-01 National Semiconductor Corporation Method of forming high performance bipolar transistor
US6657279B1 (en) * 1997-05-30 2003-12-02 Stmicroelectronics S.R.L. PNP lateral bipolar electronic device and corresponding manufacturing process

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775882A (en) * 1986-11-19 1988-10-04 Rockwell International Corporation Lateral bipolar transistor
US5981985A (en) * 1996-06-24 1999-11-09 The Trustees Of Columbia University In The City Of New York Heterojunction bipolar transistor with buried selective sub-collector layer, and methods of manufacture
US6121633A (en) * 1997-06-12 2000-09-19 Cree Research, Inc. Latch-up free power MOS-bipolar transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4498092A (en) * 1980-09-16 1985-02-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor photoelectric conversion device
US5508553A (en) * 1993-11-01 1996-04-16 Nec Corporation Transversal bipolar transistor integrated with another transistor commonly provided on a semiconductor substrate
US6187646B1 (en) * 1996-12-20 2001-02-13 Sgs-Thomson Microelectroncis S.A. Method of manufacturing a capacitor as part of an integrated semiconductor circuit
US6657279B1 (en) * 1997-05-30 2003-12-02 Stmicroelectronics S.R.L. PNP lateral bipolar electronic device and corresponding manufacturing process
US6429085B1 (en) * 1999-06-25 2002-08-06 Applied Micro Circuits Corporation Self-aligned non-selective thin-epi-base silicon germaniun (SiGe) heterojunction bipolar transistor BiCMOS process using silicon dioxide etchback
US6586298B1 (en) * 2001-06-15 2003-07-01 National Semiconductor Corporation Method of forming high performance bipolar transistor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050196931A1 (en) * 2003-11-06 2005-09-08 Chartered Semiconductor Manufacturing, Ltd. Self-aligned lateral heterojunction bipolar transistor
US7238971B2 (en) * 2003-11-06 2007-07-03 Chartered Semiconductor Manufacturing Ltd. Self-aligned lateral heterojunction bipolar transistor
WO2009081867A1 (en) 2007-12-20 2009-07-02 Asahi Kasei Emd Corporation Semiconductor device and method for manufacturing semiconductor devicedispositif à semi-conducteurrs et procédé de fabrication d'un dispositif à semi-conducteurs
JP2013012782A (en) * 2007-12-20 2013-01-17 Asahi Kasei Electronics Co Ltd Semiconductor device
JP5140092B2 (en) * 2007-12-20 2013-02-06 旭化成エレクトロニクス株式会社 Semiconductor device and manufacturing method of semiconductor device
JP2013038445A (en) * 2007-12-20 2013-02-21 Asahi Kasei Electronics Co Ltd Semiconductor device and semiconductor device manufacturing method
US8569866B2 (en) 2007-12-20 2013-10-29 Asahi Kasei Microdevices Corporation Hybrid-integrated lateral bipolar transistor and CMOS transistor and method for manufacturing the same
US8772837B2 (en) 2007-12-20 2014-07-08 Asahi Kasei Microdevices Corporation Semiconductor device comprising a lateral bipolar transistor
EP2784823A2 (en) 2007-12-20 2014-10-01 Asahi Kasei EMD Corporation Semiconductor device and method for manufacturing the same
EP2784823A3 (en) * 2007-12-20 2015-02-25 Asahi Kasei EMD Corporation Semiconductor device and method for manufacturing the same
EP2897171A2 (en) 2007-12-20 2015-07-22 Asahi Kasei EMD Corporation Semiconductor device and method for manufacturing the same
EP3032588A1 (en) 2007-12-20 2016-06-15 Asahi Kasei EMD Corporation Method for manufacturing semiconductor device
US10720517B2 (en) * 2017-10-17 2020-07-21 University Of Zagreb Faculty Of Electrical Engineering And Computing Horizontal current bipolar transistor with floating field regions

Also Published As

Publication number Publication date
US7038249B2 (en) 2006-05-02
WO2002080281A1 (en) 2002-10-10

Similar Documents

Publication Publication Date Title
US8247300B2 (en) Control of dopant diffusion from buried layers in bipolar integrated circuits
US7462547B2 (en) Method of fabricating a bipolar transistor having reduced collector-base capacitance
US5171702A (en) Method for forming a thick base oxide in a BiCMOS process
US20100055860A1 (en) Semiconductor Process and Integrated Circuit
US6630377B1 (en) Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
US20030082882A1 (en) Control of dopant diffusion from buried layers in bipolar integrated circuits
JP2006080508A (en) Semiconductor device and manufacturing method therefor
US6011297A (en) Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage
US20030057458A1 (en) Bipolar device having shallow junction raised extrinsic base and method for making the same
US7038249B2 (en) Horizontal current bipolar transistor and fabrication method
JP2824263B2 (en) High voltage merged bipolar / CMOS integrated circuit
US20030080394A1 (en) Control of dopant diffusion from polysilicon emitters in bipolar integrated circuits
US6764918B2 (en) Structure and method of making a high performance semiconductor device having a narrow doping profile
US7217609B2 (en) Semiconductor fabrication process, lateral PNP transistor, and integrated circuit
US6767797B2 (en) Method of fabricating complementary self-aligned bipolar transistors
US7572708B1 (en) Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure
US7671447B2 (en) Bipolar transistor and method of manufacturing the same
JP5563340B2 (en) Semiconductor device
JP3732814B2 (en) Semiconductor device
WO1995023432A1 (en) Bicmos structures and methods of fabrication
US5969402A (en) Reduction of depletion spreading sideways utilizing slots
US5912501A (en) Elimination of radius of curvature effects of p-n junction avalanche breakdown using slots
JP2985824B2 (en) Semiconductor device and manufacturing method thereof
EP0409041B1 (en) A method for forming a thick base oxide in a BiCMOS process
JPH10294321A (en) Lateral p-n-p transistor and manufacture thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE, CALI

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SULIGOJ, TOMISLAV;BILJANOVIC, PETAR;WANG, KANG L.;REEL/FRAME:015426/0640

Effective date: 20040225

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20180502