US20040256680A1 - Method of forming a vertical power semiconductor device and structure therefor - Google Patents
Method of forming a vertical power semiconductor device and structure therefor Download PDFInfo
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- US20040256680A1 US20040256680A1 US10/464,971 US46497103A US2004256680A1 US 20040256680 A1 US20040256680 A1 US 20040256680A1 US 46497103 A US46497103 A US 46497103A US 2004256680 A1 US2004256680 A1 US 2004256680A1
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Definitions
- the present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
- the semiconductor industry utilized various structures and methods to form vertical power transistors on the same substrate with lateral low breakdown voltage transistors. Forming both a vertical power transistor and a lateral transistor on the same semiconductor die was highly desirable and offered designers the flexibility to combine various functions on a single semiconductor die.
- the vertical power transistor usually had a higher breakdown voltage than the lateral transistors. In order to obtain the higher breakdown voltage, the vertical transistor was formed in a thick epitaxial layer that had a high resistivity.
- One accepted figure of merit for the resulting on-resistance of the vertical transistor was the on-resistance area product.
- the vertical transistors typically had an on-resistance area product that was no less than one (1.0) milli-ohm-cm 2 .
- the lateral transistor had to be formed in a well in the epitaxial layer. The large thickness of the epitaxial layer provided sufficient depth to form the high resistivity well for the lateral transistor within the epitaxial layer.
- medium or low breakdown voltage vertical power transistors In some applications it would have been advantageous to build medium or low breakdown voltage vertical power transistors on the same die with lateral transistors.
- Medium and low breakdown voltage vertical power transistors generally had a breakdown voltage no greater than about forty volts (40 V).
- medium and low breakdown voltage vertical transistors used a thinner epitaxial layer than the high breakdown voltage vertical transistors.
- a thinner epitaxial layer generally did not allow sufficient room to form the well in which the lateral devices were built. Consequently, it was difficult to combine any lateral transistors on the same semiconductor die with medium or low breakdown voltage vertical power devices.
- FIG. 1 schematically illustrates a cross-sectional portion of an embodiment of semiconductor device in accordance with the present invention
- FIG. 2 schematically illustrates an embodiment of a portion of the semiconductor device of FIG. 1 at a stage of manufacturing in accordance with the present invention
- FIG. 3 schematically illustrates an embodiment of a portion of the semiconductor device of FIG. 1 at another stage of manufacturing in accordance with the present invention.
- FIG. 4 schematically illustrates an embodiment of a portion of the semiconductor device of FIG. 1 at still another stage of manufacturing in accordance with the present invention.
- FIG. 1 schematically illustrates a cross-sectional portion of a semiconductor device 10 that includes a lateral transistor 12 , another lateral transistor 13 , and a high current vertical power transistor 11 that has a low on-resistance.
- Transistor 11 typically has a medium breakdown voltage but may also have a low breakdown voltage.
- Transistor 11 typically has an on-resistance area product that is no greater than about 0.7 milli-ohm-cm 2 .
- the method of forming transistors 11 , 12 , and 13 facilitates forming various types of lateral transistors, other active elements, and passive elements on the same semiconductor die with vertical power transistor 11 .
- Transistors 11 , 12 , and 13 are identified in a generally way by arrows.
- transistors 11 and 12 are N-channel transistors and transistor 13 is a P-channel transistor.
- transistors 11 and 12 are N-channel transistors and transistor 13 is a P-channel transistor.
- transistors 11 and 12 are N-channel transistors and transistor 13 is a P-channel transistor.
- Semiconductor device 10 includes a substrate 14 that has an epitaxial layer 16 formed on a surface of substrate 14 .
- Layer 16 typically is formed as an epitaxial layer that has a lower doping concentration and higher resistivity than substrate 14 .
- Layer 16 is formed to have a thickness 15 and a resistivity that are suitable for forming lateral transistors 12 and 13 .
- the resistivity of layer 16 generally is much higher than the resistivity needed to form a low on-resistance vertical power transistor.
- Thickness 15 generally is no greater than five (5) microns and the resistivity of layer 16 usually is no greater than about 0.8 ohm-centimeter.
- layer 16 is N-type semiconductor material that has a resistivity between about 0.6 and 0.8 ohm-centimeter and has a thickness that is no greater than about four to five microns. Such a resistivity and thickness of layer 16 facilitates forming transistors 12 and 13 in layer 16 . Previously, such a resistivity and thickness were not suitable for forming a low on-resistance high current vertical power transistor.
- Substrate 14 preferably has a resistivity that is no greater than approximately 0.005 ohm-centimeter.
- the method of forming device 10 also facilitates forming transistor 11 within a first doped region or first well 18 that is formed in layer 16 .
- Well 18 is formed to have a conductivity type that is the same as the conductivity type of substrate 14 and a resistivity that is less than the resistivity of layer 16 and that is greater than the resistivity of substrate 14 .
- Lateral transistor 12 is formed to include a source region 31 and a drain region 32 that are formed in a second doped region or second well 19 .
- a gate insulator 33 and a gate conductor 34 of transistor 12 are formed on the surface of layer 16 and interposed between regions 31 and 32 .
- Lateral transistor 13 is formed to include a high voltage drain region 42 , a drain 43 formed within region 42 , and a source region 41 .
- a gate insulator 44 and a gate conductor 46 of transistor 13 are formed on the surface of layer 16 and interposed between regions 41 and 42 .
- Vertical power transistor 11 is formed to also include a plurality of third wells or drift regions 21 that each have a fourth well or body region 22 formed therein.
- a plurality of source regions 23 are formed in drift regions 21 and intersect body regions 22 .
- a gate insulator 24 and gate conductor 26 are formed on the surface of layer 16 adjacent to each source region 23 . It should be noted that regions 21 could also be formed as one continuous region such as stripes that all converge at one end into one common doped region.
- Insulator 24 and conductor 26 are a portion of a gate structure that is overlying a portion of region 21 and adjacent to one of the plurality of gate structures. As is well known in the art that the number of regions 21 and 23 affect the current capacity of transistor 11 , and also that transistor 11 could be formed with a single drift region 21 and source region 23 .
- a drain contact 17 is formed on a surface of substrate 14 opposite to layer 16 .
- transistor 11 is a vertical N-channel power field effect transistor having a breakdown voltage of about fifteen volts (15 V) to forty volts (40 V), and an on-resistance area product that is about 0.5 milli-ohm-cm 2 .
- substrate 14 , layer 16 , well 18 , and regions 23 are N-type semiconductor material while regions 21 and 22 are doped P-type.
- transistor 12 is an N-channel lateral transistor thus well 19 is doped P-type and regions 31 and 32 are N-type.
- Transistor 13 is a P-channel lateral transistor thus drain 43 and regions 41 and 42 are doped P-type.
- FIG. 2 through FIG. 4 schematically illustrate an embodiment of a portion of device 10 at various stages of manufacturing. This explanation will have references to FIG. 1 through FIG. 4.
- a portion of layer 16 is doped to form first doped region or first well 18 .
- well 18 is doped to have a resistivity that is no greater than approximately 0.3 ohm-centimeter and preferably is about 0.15 ohm-centimeter.
- Well 18 typically extends from the surface of layer 16 through layer 16 to electrically contact substrate 14 .
- Well 18 preferably is formed by ion implantation of phosphorus but may be formed by other doping materials and doping techniques.
- second doped region or second well 19 is formed in another portion of layer 16 juxtaposed to well 18 .
- Well 19 is formed to have a doping type that is opposite to the doping type of substrate 14 and a resistivity that is less than the resistivity of well 18 but greater than the resistivity of substrate 14 .
- the resistivity of well 19 is about one thousand (1000) to three thousand (3000) ohms per square, and preferably is about two thousand (2000) ohms per square.
- Well 19 has a thickness or depth into layer 16 that is less than thickness 15 and typically does not electrically contact substrate 14 .
- high voltage drain region 42 of transistor 13 is formed in another portion of layer 16 where transistor 13 is to be formed.
- plurality of third wells or drift regions 21 are formed in well 18 .
- Well 19 , regions 21 , and region 42 are of the same conductivity type and could be formed at the same time thereby saving masking and implantation steps and the associated costs.
- fourth well or body region 22 is formed in each region 21 .
- source region 41 and drain 43 of transistor 13 are formed at the same time as each region 22 in order to lower manufacturing costs since all have the same conductivity type.
- Regions 21 , 41 , and 43 are formed by ion implantation or other well known doping techniques.
- source regions 23 are formed in each region 21 , and source region 31 and drain region 32 are formed in well 19 by well known techniques such as ion implantation.
- transistor 11 may include many regions 21 although only two are illustrated in FIG. 1 through FIG. 4 for simplicity of the illustration. Regions 21 that are adjacent to the edges of well 18 are positioned or formed to intersect the sides of well 18 , as illustrated by dashed lines 25 , to provide a stable breakdown voltage around the edges of well 18 .
- a novel device and method is disclosed. Included, among other features, is forming a vertical power transistor in a well that has a low resistivity and high current capacity and is the same conductivity type as an epitaxial layer that has a thickness and resistivity that are optimized for forming lateral transistors. Doping a portion of the epitaxial layer to form the well facilitates forming the medium breakdown voltage vertical transistor on the same semiconductor die with numbers of lateral transistors and other types of electrical elements.
- the lateral transistors have a higher on-resistance than the power transistor and are formed in the same epitaxial layer.
Abstract
Description
- The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
- In the past, the semiconductor industry utilized various structures and methods to form vertical power transistors on the same substrate with lateral low breakdown voltage transistors. Forming both a vertical power transistor and a lateral transistor on the same semiconductor die was highly desirable and offered designers the flexibility to combine various functions on a single semiconductor die. The vertical power transistor usually had a higher breakdown voltage than the lateral transistors. In order to obtain the higher breakdown voltage, the vertical transistor was formed in a thick epitaxial layer that had a high resistivity. One accepted figure of merit for the resulting on-resistance of the vertical transistor was the on-resistance area product. The vertical transistors typically had an on-resistance area product that was no less than one (1.0) milli-ohm-cm2. The lateral transistor had to be formed in a well in the epitaxial layer. The large thickness of the epitaxial layer provided sufficient depth to form the high resistivity well for the lateral transistor within the epitaxial layer.
- In some applications it would have been advantageous to build medium or low breakdown voltage vertical power transistors on the same die with lateral transistors. Medium and low breakdown voltage vertical power transistors generally had a breakdown voltage no greater than about forty volts (40 V). However, medium and low breakdown voltage vertical transistors used a thinner epitaxial layer than the high breakdown voltage vertical transistors. A thinner epitaxial layer generally did not allow sufficient room to form the well in which the lateral devices were built. Consequently, it was difficult to combine any lateral transistors on the same semiconductor die with medium or low breakdown voltage vertical power devices.
- Accordingly, it is desirable to have a method of forming a medium or low breakdown vertical power transistor and lateral transistors on the same semiconductor die.
- FIG. 1 schematically illustrates a cross-sectional portion of an embodiment of semiconductor device in accordance with the present invention;
- FIG. 2 schematically illustrates an embodiment of a portion of the semiconductor device of FIG. 1 at a stage of manufacturing in accordance with the present invention;
- FIG. 3 schematically illustrates an embodiment of a portion of the semiconductor device of FIG. 1 at another stage of manufacturing in accordance with the present invention; and
- FIG. 4 schematically illustrates an embodiment of a portion of the semiconductor device of FIG. 1 at still another stage of manufacturing in accordance with the present invention.
- For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well known steps and elements are omitted for simplicity of the description.
- FIG. 1 schematically illustrates a cross-sectional portion of a
semiconductor device 10 that includes alateral transistor 12, anotherlateral transistor 13, and a high currentvertical power transistor 11 that has a low on-resistance.Transistor 11 typically has a medium breakdown voltage but may also have a low breakdown voltage.Transistor 11 typically has an on-resistance area product that is no greater than about 0.7 milli-ohm-cm2. The method of formingtransistors vertical power transistor 11.Transistors transistors transistor 13 is a P-channel transistor. However, a person of ordinary skill in the art will appreciate that it is possible to formtransistors transistor 13 as an N-channel device. -
Semiconductor device 10 includes asubstrate 14 that has anepitaxial layer 16 formed on a surface ofsubstrate 14.Layer 16 typically is formed as an epitaxial layer that has a lower doping concentration and higher resistivity thansubstrate 14.Layer 16 is formed to have athickness 15 and a resistivity that are suitable for forminglateral transistors layer 16 generally is much higher than the resistivity needed to form a low on-resistance vertical power transistor.Thickness 15 generally is no greater than five (5) microns and the resistivity oflayer 16 usually is no greater than about 0.8 ohm-centimeter. In the preferred embodiment,layer 16 is N-type semiconductor material that has a resistivity between about 0.6 and 0.8 ohm-centimeter and has a thickness that is no greater than about four to five microns. Such a resistivity and thickness oflayer 16 facilitates formingtransistors layer 16. Previously, such a resistivity and thickness were not suitable for forming a low on-resistance high current vertical power transistor.Substrate 14 preferably has a resistivity that is no greater than approximately 0.005 ohm-centimeter. - As will be seen in more detail hereinafter, the method of forming
device 10 also facilitates formingtransistor 11 within a first doped region or first well 18 that is formed inlayer 16.Well 18 is formed to have a conductivity type that is the same as the conductivity type ofsubstrate 14 and a resistivity that is less than the resistivity oflayer 16 and that is greater than the resistivity ofsubstrate 14.Lateral transistor 12 is formed to include asource region 31 and adrain region 32 that are formed in a second doped region or secondwell 19. Agate insulator 33 and agate conductor 34 oftransistor 12 are formed on the surface oflayer 16 and interposed betweenregions Lateral transistor 13 is formed to include a highvoltage drain region 42, adrain 43 formed withinregion 42, and asource region 41. Agate insulator 44 and agate conductor 46 oftransistor 13 are formed on the surface oflayer 16 and interposed betweenregions Vertical power transistor 11 is formed to also include a plurality of third wells ordrift regions 21 that each have a fourth well orbody region 22 formed therein. A plurality ofsource regions 23 are formed indrift regions 21 andintersect body regions 22. Agate insulator 24 andgate conductor 26 are formed on the surface oflayer 16 adjacent to eachsource region 23. It should be noted thatregions 21 could also be formed as one continuous region such as stripes that all converge at one end into one common doped region.Insulator 24 andconductor 26 are a portion of a gate structure that is overlying a portion ofregion 21 and adjacent to one of the plurality of gate structures. As is well known in the art that the number ofregions transistor 11, and also thattransistor 11 could be formed with asingle drift region 21 andsource region 23. Adrain contact 17 is formed on a surface ofsubstrate 14 opposite tolayer 16. - In the preferred embodiment,
transistor 11 is a vertical N-channel power field effect transistor having a breakdown voltage of about fifteen volts (15 V) to forty volts (40 V), and an on-resistance area product that is about 0.5 milli-ohm-cm2. In this preferred embodiment,substrate 14,layer 16, well 18, andregions 23 are N-type semiconductor material whileregions transistor 12 is an N-channel lateral transistor thus well 19 is doped P-type andregions Transistor 13 is a P-channel lateral transistor thus drain 43 andregions - FIG. 2 through FIG. 4 schematically illustrate an embodiment of a portion of
device 10 at various stages of manufacturing. This explanation will have references to FIG. 1 through FIG. 4. A portion oflayer 16 is doped to form first doped region or first well 18. Typically, well 18 is doped to have a resistivity that is no greater than approximately 0.3 ohm-centimeter and preferably is about 0.15 ohm-centimeter.Well 18 typically extends from the surface oflayer 16 throughlayer 16 to electricallycontact substrate 14. Well 18 preferably is formed by ion implantation of phosphorus but may be formed by other doping materials and doping techniques. - As shown by FIG. 3 after well18 is formed, second doped region or
second well 19 is formed in another portion oflayer 16 juxtaposed to well 18.Well 19 is formed to have a doping type that is opposite to the doping type ofsubstrate 14 and a resistivity that is less than the resistivity of well 18 but greater than the resistivity ofsubstrate 14. Typically the resistivity of well 19 is about one thousand (1000) to three thousand (3000) ohms per square, and preferably is about two thousand (2000) ohms per square. Well 19 has a thickness or depth intolayer 16 that is less thanthickness 15 and typically does not electricallycontact substrate 14. Also, highvoltage drain region 42 oftransistor 13 is formed in another portion oflayer 16 wheretransistor 13 is to be formed. Additionally, plurality of third wells or driftregions 21 are formed inwell 18. Well 19,regions 21, andregion 42 are of the same conductivity type and could be formed at the same time thereby saving masking and implantation steps and the associated costs. - Referring to FIG. 4, fourth well or
body region 22 is formed in eachregion 21. Preferably sourceregion 41 and drain 43 oftransistor 13 are formed at the same time as eachregion 22 in order to lower manufacturing costs since all have the same conductivity type.Regions - Referring back to FIG. 1, subsequently,
source regions 23 are formed in eachregion 21, andsource region 31 and drainregion 32 are formed in well 19 by well known techniques such as ion implantation. As is well know in the art,transistor 11 may includemany regions 21 although only two are illustrated in FIG. 1 through FIG. 4 for simplicity of the illustration.Regions 21 that are adjacent to the edges of well 18 are positioned or formed to intersect the sides of well 18, as illustrated by dashedlines 25, to provide a stable breakdown voltage around the edges ofwell 18. - In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is forming a vertical power transistor in a well that has a low resistivity and high current capacity and is the same conductivity type as an epitaxial layer that has a thickness and resistivity that are optimized for forming lateral transistors. Doping a portion of the epitaxial layer to form the well facilitates forming the medium breakdown voltage vertical transistor on the same semiconductor die with numbers of lateral transistors and other types of electrical elements. The lateral transistors have a higher on-resistance than the power transistor and are formed in the same epitaxial layer.
- While the invention is described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. More specifically the invention has been described for a particular N-channel vertical power transistor structure, although the method is directly applicable to other power devices such as IGBT's and P-channel MOSFETs.
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Cited By (3)
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US20060220140A1 (en) * | 2005-04-01 | 2006-10-05 | Semiconductor Components Industries, Llc. | Method of forming an integrated power device and structure |
US8809961B2 (en) * | 2012-04-23 | 2014-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrostatic discharge (ESD) guard ring protective structure |
CN114883213A (en) * | 2022-07-11 | 2022-08-09 | 广州粤芯半导体技术有限公司 | Integrated monitoring method of semiconductor process |
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US20060220140A1 (en) * | 2005-04-01 | 2006-10-05 | Semiconductor Components Industries, Llc. | Method of forming an integrated power device and structure |
US7714381B2 (en) | 2005-04-01 | 2010-05-11 | Semiconductor Components Industries, Llc | Method of forming an integrated power device and structure |
US20100133610A1 (en) * | 2005-04-01 | 2010-06-03 | Robb Francine Y | Method of forming an integrated power device and structure |
US8207035B2 (en) | 2005-04-01 | 2012-06-26 | Semiconductor Components Industries, Llc | Method of forming an integrated power device and structure |
US8748262B2 (en) | 2005-04-01 | 2014-06-10 | Semiconductor Components Industries, Llc | Method of forming an integrated power device and structure |
US8809961B2 (en) * | 2012-04-23 | 2014-08-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrostatic discharge (ESD) guard ring protective structure |
CN114883213A (en) * | 2022-07-11 | 2022-08-09 | 广州粤芯半导体技术有限公司 | Integrated monitoring method of semiconductor process |
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